1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2009-2012  Realtek Corporation.*/
3 
4 #ifndef __RTL_PCI_H__
5 #define __RTL_PCI_H__
6 
7 #include <linux/pci.h>
8 /* 1: MSDU packet queue,
9  * 2: Rx Command Queue
10  */
11 #define RTL_PCI_RX_MPDU_QUEUE			0
12 #define RTL_PCI_RX_CMD_QUEUE			1
13 #define RTL_PCI_MAX_RX_QUEUE			2
14 
15 #define RTL_PCI_MAX_RX_COUNT			512/*64*/
16 #define RTL_PCI_MAX_TX_QUEUE_COUNT		9
17 
18 #define RT_TXDESC_NUM				128
19 #define TX_DESC_NUM_92E				512
20 #define TX_DESC_NUM_8822B			512
21 #define RT_TXDESC_NUM_BE_QUEUE			256
22 
23 #define BK_QUEUE				0
24 #define BE_QUEUE				1
25 #define VI_QUEUE				2
26 #define VO_QUEUE				3
27 #define BEACON_QUEUE				4
28 #define TXCMD_QUEUE				5
29 #define MGNT_QUEUE				6
30 #define HIGH_QUEUE				7
31 #define HCCA_QUEUE				8
32 #define H2C_QUEUE				TXCMD_QUEUE	/* In 8822B */
33 
34 #define RTL_PCI_DEVICE(vend, dev, cfg)  \
35 	.vendor = (vend), \
36 	.device = (dev), \
37 	.subvendor = PCI_ANY_ID, \
38 	.subdevice = PCI_ANY_ID,\
39 	.driver_data = (kernel_ulong_t)&(cfg)
40 
41 #define INTEL_VENDOR_ID				0x8086
42 #define SIS_VENDOR_ID				0x1039
43 #define ATI_VENDOR_ID				0x1002
44 #define ATI_DEVICE_ID				0x7914
45 #define AMD_VENDOR_ID				0x1022
46 
47 #define PCI_MAX_BRIDGE_NUMBER			255
48 #define PCI_MAX_DEVICES				32
49 #define PCI_MAX_FUNCTION			8
50 
51 #define PCI_CONF_ADDRESS	0x0CF8	/*PCI Configuration Space Address */
52 #define PCI_CONF_DATA		0x0CFC	/*PCI Configuration Space Data */
53 
54 #define PCI_CLASS_BRIDGE_DEV		0x06
55 #define PCI_SUBCLASS_BR_PCI_TO_PCI	0x04
56 #define PCI_CAPABILITY_ID_PCI_EXPRESS	0x10
57 #define PCI_CAP_ID_EXP			0x10
58 
59 #define U1DONTCARE			0xFF
60 #define U2DONTCARE			0xFFFF
61 #define U4DONTCARE			0xFFFFFFFF
62 
63 #define RTL_PCI_8192_DID	0x8192	/*8192 PCI-E */
64 #define RTL_PCI_8192SE_DID	0x8192	/*8192 SE */
65 #define RTL_PCI_8174_DID	0x8174	/*8192 SE */
66 #define RTL_PCI_8173_DID	0x8173	/*8191 SE Crab */
67 #define RTL_PCI_8172_DID	0x8172	/*8191 SE RE */
68 #define RTL_PCI_8171_DID	0x8171	/*8191 SE Unicron */
69 #define RTL_PCI_8723AE_DID	0x8723	/*8723AE */
70 #define RTL_PCI_0045_DID	0x0045	/*8190 PCI for Ceraga */
71 #define RTL_PCI_0046_DID	0x0046	/*8190 Cardbus for Ceraga */
72 #define RTL_PCI_0044_DID	0x0044	/*8192e PCIE for Ceraga */
73 #define RTL_PCI_0047_DID	0x0047	/*8192e Express Card for Ceraga */
74 #define RTL_PCI_700F_DID	0x700F
75 #define RTL_PCI_701F_DID	0x701F
76 #define RTL_PCI_DLINK_DID	0x3304
77 #define RTL_PCI_8723AE_DID	0x8723	/*8723e */
78 #define RTL_PCI_8192CET_DID	0x8191	/*8192ce */
79 #define RTL_PCI_8192CE_DID	0x8178	/*8192ce */
80 #define RTL_PCI_8191CE_DID	0x8177	/*8192ce */
81 #define RTL_PCI_8188CE_DID	0x8176	/*8192ce */
82 #define RTL_PCI_8192CU_DID	0x8191	/*8192ce */
83 #define RTL_PCI_8192DE_DID	0x8193	/*8192de */
84 #define RTL_PCI_8192DE_DID2	0x002B	/*92DE*/
85 #define RTL_PCI_8188EE_DID	0x8179  /*8188ee*/
86 #define RTL_PCI_8723BE_DID	0xB723  /*8723be*/
87 #define RTL_PCI_8192EE_DID	0x818B	/*8192ee*/
88 #define RTL_PCI_8821AE_DID	0x8821	/*8821ae*/
89 #define RTL_PCI_8812AE_DID	0x8812	/*8812ae*/
90 #define RTL_PCI_8822BE_DID	0xB822	/*8822be*/
91 
92 /*8192 support 16 pages of IO registers*/
93 #define RTL_MEM_MAPPED_IO_RANGE_8190PCI		0x1000
94 #define RTL_MEM_MAPPED_IO_RANGE_8192PCIE	0x4000
95 #define RTL_MEM_MAPPED_IO_RANGE_8192SE		0x4000
96 #define RTL_MEM_MAPPED_IO_RANGE_8192CE		0x4000
97 #define RTL_MEM_MAPPED_IO_RANGE_8192DE		0x4000
98 
99 #define RTL_PCI_REVISION_ID_8190PCI		0x00
100 #define RTL_PCI_REVISION_ID_8192PCIE		0x01
101 #define RTL_PCI_REVISION_ID_8192SE		0x10
102 #define RTL_PCI_REVISION_ID_8192CE		0x1
103 #define RTL_PCI_REVISION_ID_8192DE		0x0
104 
105 #define RTL_DEFAULT_HARDWARE_TYPE	HARDWARE_TYPE_RTL8192CE
106 
107 enum pci_bridge_vendor {
108 	PCI_BRIDGE_VENDOR_INTEL = 0x0,	/*0b'0000,0001 */
109 	PCI_BRIDGE_VENDOR_ATI,		/*0b'0000,0010*/
110 	PCI_BRIDGE_VENDOR_AMD,		/*0b'0000,0100*/
111 	PCI_BRIDGE_VENDOR_SIS,		/*0b'0000,1000*/
112 	PCI_BRIDGE_VENDOR_UNKNOWN,	/*0b'0100,0000*/
113 	PCI_BRIDGE_VENDOR_MAX,
114 };
115 
116 struct rtl_pci_capabilities_header {
117 	u8 capability_id;
118 	u8 next;
119 };
120 
121 /* In new TRX flow, Buffer_desc is new concept
122  * But TX wifi info == TX descriptor in old flow
123  * RX wifi info == RX descriptor in old flow
124  */
125 struct rtl_tx_buffer_desc {
126 	u32 dword[4 * (1 << (BUFDESC_SEG_NUM + 1))];
127 } __packed;
128 
129 struct rtl_tx_desc {
130 	u32 dword[16];
131 } __packed;
132 
133 struct rtl_rx_buffer_desc { /*rx buffer desc*/
134 	u32 dword[4];
135 } __packed;
136 
137 struct rtl_rx_desc { /*old: rx desc new: rx wifi info*/
138 	u32 dword[8];
139 } __packed;
140 
141 struct rtl_tx_cmd_desc {
142 	u32 dword[16];
143 } __packed;
144 
145 struct rtl8192_tx_ring {
146 	struct rtl_tx_desc *desc;
147 	dma_addr_t dma;
148 	unsigned int idx;
149 	unsigned int entries;
150 	struct sk_buff_head queue;
151 	/*add for new trx flow*/
152 	struct rtl_tx_buffer_desc *buffer_desc; /*tx buffer descriptor*/
153 	dma_addr_t buffer_desc_dma; /*tx bufferd desc dma memory*/
154 	u16 cur_tx_wp; /* current_tx_write_point */
155 	u16 cur_tx_rp; /* current_tx_read_point */
156 };
157 
158 struct rtl8192_rx_ring {
159 	struct rtl_rx_desc *desc;
160 	dma_addr_t dma;
161 	unsigned int idx;
162 	struct sk_buff *rx_buf[RTL_PCI_MAX_RX_COUNT];
163 	/*add for new trx flow*/
164 	struct rtl_rx_buffer_desc *buffer_desc; /*rx buffer descriptor*/
165 	u16 next_rx_rp; /* next_rx_read_point */
166 };
167 
168 struct rtl_pci {
169 	struct pci_dev *pdev;
170 	bool irq_enabled;
171 
172 	bool driver_is_goingto_unload;
173 	bool up_first_time;
174 	bool first_init;
175 	bool being_init_adapter;
176 	bool init_ready;
177 
178 	/*Tx */
179 	struct rtl8192_tx_ring tx_ring[RTL_PCI_MAX_TX_QUEUE_COUNT];
180 	int txringcount[RTL_PCI_MAX_TX_QUEUE_COUNT];
181 	u32 transmit_config;
182 
183 	/*Rx */
184 	struct rtl8192_rx_ring rx_ring[RTL_PCI_MAX_RX_QUEUE];
185 	int rxringcount;
186 	u16 rxbuffersize;
187 	u32 receive_config;
188 
189 	/*irq */
190 	u8 irq_alloc;
191 	u32 irq_mask[4];	/* 0-1: normal, 2: unused, 3: h2c */
192 	u32 sys_irq_mask;
193 
194 	/*Bcn control register setting */
195 	u32 reg_bcn_ctrl_val;
196 
197 	 /*ASPM*/ u8 const_pci_aspm;
198 	u8 const_amdpci_aspm;
199 	u8 const_hwsw_rfoff_d3;
200 	u8 const_support_pciaspm;
201 	/*pci-e bridge */
202 	u8 const_hostpci_aspm_setting;
203 	/*pci-e device */
204 	u8 const_devicepci_aspm_setting;
205 	/* If it supports ASPM, Offset[560h] = 0x40,
206 	 * otherwise Offset[560h] = 0x00.
207 	 */
208 	bool support_aspm;
209 	bool support_backdoor;
210 
211 	/*QOS & EDCA */
212 	enum acm_method acm_method;
213 
214 	u16 shortretry_limit;
215 	u16 longretry_limit;
216 
217 	/* MSI support */
218 	bool msi_support;
219 	bool using_msi;
220 	/* interrupt clear before set */
221 	bool int_clear;
222 };
223 
224 struct mp_adapter {
225 	u8 linkctrl_reg;
226 
227 	u8 busnumber;
228 	u8 devnumber;
229 	u8 funcnumber;
230 
231 	u8 pcibridge_busnum;
232 	u8 pcibridge_devnum;
233 	u8 pcibridge_funcnum;
234 
235 	u8 pcibridge_vendor;
236 	u16 pcibridge_vendorid;
237 	u16 pcibridge_deviceid;
238 
239 	u8 num4bytes;
240 
241 	u8 pcibridge_pciehdr_offset;
242 	u8 pcibridge_linkctrlreg;
243 
244 	bool amd_l1_patch;
245 };
246 
247 struct rtl_pci_priv {
248 	struct bt_coexist_info bt_coexist;
249 	struct rtl_led_ctl ledctl;
250 	struct rtl_pci dev;
251 	struct mp_adapter ndis_adapter;
252 };
253 
254 #define rtl_pcipriv(hw)		(((struct rtl_pci_priv *)(rtl_priv(hw))->priv))
255 #define rtl_pcidev(pcipriv)	(&((pcipriv)->dev))
256 
257 int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw);
258 
259 extern const struct rtl_intf_ops rtl_pci_ops;
260 
261 int rtl_pci_probe(struct pci_dev *pdev,
262 		  const struct pci_device_id *id);
263 void rtl_pci_disconnect(struct pci_dev *pdev);
264 #ifdef CONFIG_PM_SLEEP
265 int rtl_pci_suspend(struct device *dev);
266 int rtl_pci_resume(struct device *dev);
267 #endif /* CONFIG_PM_SLEEP */
pci_read8_sync(struct rtl_priv * rtlpriv,u32 addr)268 static inline u8 pci_read8_sync(struct rtl_priv *rtlpriv, u32 addr)
269 {
270 	return readb((u8 __iomem *)rtlpriv->io.pci_mem_start + addr);
271 }
272 
pci_read16_sync(struct rtl_priv * rtlpriv,u32 addr)273 static inline u16 pci_read16_sync(struct rtl_priv *rtlpriv, u32 addr)
274 {
275 	return readw((u8 __iomem *)rtlpriv->io.pci_mem_start + addr);
276 }
277 
pci_read32_sync(struct rtl_priv * rtlpriv,u32 addr)278 static inline u32 pci_read32_sync(struct rtl_priv *rtlpriv, u32 addr)
279 {
280 	return readl((u8 __iomem *)rtlpriv->io.pci_mem_start + addr);
281 }
282 
pci_write8_async(struct rtl_priv * rtlpriv,u32 addr,u8 val)283 static inline void pci_write8_async(struct rtl_priv *rtlpriv, u32 addr, u8 val)
284 {
285 	writeb(val, (u8 __iomem *)rtlpriv->io.pci_mem_start + addr);
286 }
287 
pci_write16_async(struct rtl_priv * rtlpriv,u32 addr,u16 val)288 static inline void pci_write16_async(struct rtl_priv *rtlpriv,
289 				     u32 addr, u16 val)
290 {
291 	writew(val, (u8 __iomem *)rtlpriv->io.pci_mem_start + addr);
292 }
293 
pci_write32_async(struct rtl_priv * rtlpriv,u32 addr,u32 val)294 static inline void pci_write32_async(struct rtl_priv *rtlpriv,
295 				     u32 addr, u32 val)
296 {
297 	writel(val, (u8 __iomem *)rtlpriv->io.pci_mem_start + addr);
298 }
299 
calc_fifo_space(u16 rp,u16 wp,u16 size)300 static inline u16 calc_fifo_space(u16 rp, u16 wp, u16 size)
301 {
302 	if (rp <= wp)
303 		return size - 1 + rp - wp;
304 	return rp - wp - 1;
305 }
306 
307 #endif
308