1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Intel Keem Bay PWM driver
4 *
5 * Copyright (C) 2020 Intel Corporation
6 * Authors: Lai Poey Seng <poey.seng.lai@intel.com>
7 * Vineetha G. Jaya Kumaran <vineetha.g.jaya.kumaran@intel.com>
8 *
9 * Limitations:
10 * - Upon disabling a channel, the currently running
11 * period will not be completed. However, upon
12 * reconfiguration of the duty cycle/period, the
13 * currently running period will be completed first.
14 */
15
16 #include <linux/bitfield.h>
17 #include <linux/clk.h>
18 #include <linux/io.h>
19 #include <linux/mod_devicetable.h>
20 #include <linux/module.h>
21 #include <linux/platform_device.h>
22 #include <linux/pwm.h>
23 #include <linux/regmap.h>
24
25 #define KMB_TOTAL_PWM_CHANNELS 6
26 #define KMB_PWM_COUNT_MAX U16_MAX
27 #define KMB_PWM_EN_BIT BIT(31)
28
29 /* Mask */
30 #define KMB_PWM_HIGH_MASK GENMASK(31, 16)
31 #define KMB_PWM_LOW_MASK GENMASK(15, 0)
32 #define KMB_PWM_LEADIN_MASK GENMASK(30, 0)
33
34 /* PWM Register offset */
35 #define KMB_PWM_LEADIN_OFFSET(ch) (0x00 + 4 * (ch))
36 #define KMB_PWM_HIGHLOW_OFFSET(ch) (0x20 + 4 * (ch))
37
38 struct keembay_pwm {
39 struct pwm_chip chip;
40 struct device *dev;
41 struct clk *clk;
42 void __iomem *base;
43 };
44
to_keembay_pwm_dev(struct pwm_chip * chip)45 static inline struct keembay_pwm *to_keembay_pwm_dev(struct pwm_chip *chip)
46 {
47 return container_of(chip, struct keembay_pwm, chip);
48 }
49
keembay_clk_unprepare(void * data)50 static void keembay_clk_unprepare(void *data)
51 {
52 clk_disable_unprepare(data);
53 }
54
keembay_clk_enable(struct device * dev,struct clk * clk)55 static int keembay_clk_enable(struct device *dev, struct clk *clk)
56 {
57 int ret;
58
59 ret = clk_prepare_enable(clk);
60 if (ret)
61 return ret;
62
63 return devm_add_action_or_reset(dev, keembay_clk_unprepare, clk);
64 }
65
66 /*
67 * With gcc 10, CONFIG_CC_OPTIMIZE_FOR_SIZE and only "inline" instead of
68 * "__always_inline" this fails to compile because the compiler doesn't notice
69 * for all valid masks (e.g. KMB_PWM_LEADIN_MASK) that they are ok.
70 */
keembay_pwm_update_bits(struct keembay_pwm * priv,u32 mask,u32 val,u32 offset)71 static __always_inline void keembay_pwm_update_bits(struct keembay_pwm *priv, u32 mask,
72 u32 val, u32 offset)
73 {
74 u32 buff = readl(priv->base + offset);
75
76 buff = u32_replace_bits(buff, val, mask);
77 writel(buff, priv->base + offset);
78 }
79
keembay_pwm_enable(struct keembay_pwm * priv,int ch)80 static void keembay_pwm_enable(struct keembay_pwm *priv, int ch)
81 {
82 keembay_pwm_update_bits(priv, KMB_PWM_EN_BIT, 1,
83 KMB_PWM_LEADIN_OFFSET(ch));
84 }
85
keembay_pwm_disable(struct keembay_pwm * priv,int ch)86 static void keembay_pwm_disable(struct keembay_pwm *priv, int ch)
87 {
88 keembay_pwm_update_bits(priv, KMB_PWM_EN_BIT, 0,
89 KMB_PWM_LEADIN_OFFSET(ch));
90 }
91
keembay_pwm_get_state(struct pwm_chip * chip,struct pwm_device * pwm,struct pwm_state * state)92 static void keembay_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
93 struct pwm_state *state)
94 {
95 struct keembay_pwm *priv = to_keembay_pwm_dev(chip);
96 unsigned long long high, low;
97 unsigned long clk_rate;
98 u32 highlow;
99
100 clk_rate = clk_get_rate(priv->clk);
101
102 /* Read channel enabled status */
103 highlow = readl(priv->base + KMB_PWM_LEADIN_OFFSET(pwm->hwpwm));
104 if (highlow & KMB_PWM_EN_BIT)
105 state->enabled = true;
106 else
107 state->enabled = false;
108
109 /* Read period and duty cycle */
110 highlow = readl(priv->base + KMB_PWM_HIGHLOW_OFFSET(pwm->hwpwm));
111 low = FIELD_GET(KMB_PWM_LOW_MASK, highlow) * NSEC_PER_SEC;
112 high = FIELD_GET(KMB_PWM_HIGH_MASK, highlow) * NSEC_PER_SEC;
113 state->duty_cycle = DIV_ROUND_UP_ULL(high, clk_rate);
114 state->period = DIV_ROUND_UP_ULL(high + low, clk_rate);
115 state->polarity = PWM_POLARITY_NORMAL;
116 }
117
keembay_pwm_apply(struct pwm_chip * chip,struct pwm_device * pwm,const struct pwm_state * state)118 static int keembay_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
119 const struct pwm_state *state)
120 {
121 struct keembay_pwm *priv = to_keembay_pwm_dev(chip);
122 struct pwm_state current_state;
123 unsigned long long div;
124 unsigned long clk_rate;
125 u32 pwm_count = 0;
126 u16 high, low;
127
128 if (state->polarity != PWM_POLARITY_NORMAL)
129 return -EINVAL;
130
131 /*
132 * Configure the pwm repeat count as infinite at (15:0) and leadin
133 * low time as 0 at (30:16), which is in terms of clock cycles.
134 */
135 keembay_pwm_update_bits(priv, KMB_PWM_LEADIN_MASK, 0,
136 KMB_PWM_LEADIN_OFFSET(pwm->hwpwm));
137
138 keembay_pwm_get_state(chip, pwm, ¤t_state);
139
140 if (!state->enabled) {
141 if (current_state.enabled)
142 keembay_pwm_disable(priv, pwm->hwpwm);
143 return 0;
144 }
145
146 /*
147 * The upper 16 bits and lower 16 bits of the KMB_PWM_HIGHLOW_OFFSET
148 * register contain the high time and low time of waveform accordingly.
149 * All the values are in terms of clock cycles.
150 */
151
152 clk_rate = clk_get_rate(priv->clk);
153 div = clk_rate * state->duty_cycle;
154 div = DIV_ROUND_DOWN_ULL(div, NSEC_PER_SEC);
155 if (div > KMB_PWM_COUNT_MAX)
156 return -ERANGE;
157
158 high = div;
159 div = clk_rate * state->period;
160 div = DIV_ROUND_DOWN_ULL(div, NSEC_PER_SEC);
161 div = div - high;
162 if (div > KMB_PWM_COUNT_MAX)
163 return -ERANGE;
164
165 low = div;
166
167 pwm_count = FIELD_PREP(KMB_PWM_HIGH_MASK, high) |
168 FIELD_PREP(KMB_PWM_LOW_MASK, low);
169
170 writel(pwm_count, priv->base + KMB_PWM_HIGHLOW_OFFSET(pwm->hwpwm));
171
172 if (state->enabled && !current_state.enabled)
173 keembay_pwm_enable(priv, pwm->hwpwm);
174
175 return 0;
176 }
177
178 static const struct pwm_ops keembay_pwm_ops = {
179 .owner = THIS_MODULE,
180 .apply = keembay_pwm_apply,
181 .get_state = keembay_pwm_get_state,
182 };
183
keembay_pwm_probe(struct platform_device * pdev)184 static int keembay_pwm_probe(struct platform_device *pdev)
185 {
186 struct device *dev = &pdev->dev;
187 struct keembay_pwm *priv;
188 int ret;
189
190 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
191 if (!priv)
192 return -ENOMEM;
193
194 priv->clk = devm_clk_get(dev, NULL);
195 if (IS_ERR(priv->clk))
196 return dev_err_probe(dev, PTR_ERR(priv->clk), "Failed to get clock\n");
197
198 priv->base = devm_platform_ioremap_resource(pdev, 0);
199 if (IS_ERR(priv->base))
200 return PTR_ERR(priv->base);
201
202 ret = keembay_clk_enable(dev, priv->clk);
203 if (ret)
204 return ret;
205
206 priv->chip.dev = dev;
207 priv->chip.ops = &keembay_pwm_ops;
208 priv->chip.npwm = KMB_TOTAL_PWM_CHANNELS;
209
210 ret = pwmchip_add(&priv->chip);
211 if (ret)
212 return dev_err_probe(dev, ret, "Failed to add PWM chip\n");
213
214 platform_set_drvdata(pdev, priv);
215
216 return 0;
217 }
218
keembay_pwm_remove(struct platform_device * pdev)219 static int keembay_pwm_remove(struct platform_device *pdev)
220 {
221 struct keembay_pwm *priv = platform_get_drvdata(pdev);
222
223 return pwmchip_remove(&priv->chip);
224 }
225
226 static const struct of_device_id keembay_pwm_of_match[] = {
227 { .compatible = "intel,keembay-pwm" },
228 { }
229 };
230 MODULE_DEVICE_TABLE(of, keembay_pwm_of_match);
231
232 static struct platform_driver keembay_pwm_driver = {
233 .probe = keembay_pwm_probe,
234 .remove = keembay_pwm_remove,
235 .driver = {
236 .name = "pwm-keembay",
237 .of_match_table = keembay_pwm_of_match,
238 },
239 };
240 module_platform_driver(keembay_pwm_driver);
241
242 MODULE_ALIAS("platform:pwm-keembay");
243 MODULE_DESCRIPTION("Intel Keem Bay PWM driver");
244 MODULE_LICENSE("GPL v2");
245