1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * drivers/soc/tegra/pmc.c
4 *
5 * Copyright (c) 2010 Google, Inc
6 * Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved.
7 *
8 * Author:
9 * Colin Cross <ccross@google.com>
10 */
11
12 #define pr_fmt(fmt) "tegra-pmc: " fmt
13
14 #include <linux/arm-smccc.h>
15 #include <linux/clk.h>
16 #include <linux/clk-provider.h>
17 #include <linux/clkdev.h>
18 #include <linux/clk/clk-conf.h>
19 #include <linux/clk/tegra.h>
20 #include <linux/debugfs.h>
21 #include <linux/delay.h>
22 #include <linux/device.h>
23 #include <linux/err.h>
24 #include <linux/export.h>
25 #include <linux/init.h>
26 #include <linux/io.h>
27 #include <linux/iopoll.h>
28 #include <linux/irqdomain.h>
29 #include <linux/irq.h>
30 #include <linux/kernel.h>
31 #include <linux/of_address.h>
32 #include <linux/of_clk.h>
33 #include <linux/of.h>
34 #include <linux/of_irq.h>
35 #include <linux/of_platform.h>
36 #include <linux/pinctrl/pinconf-generic.h>
37 #include <linux/pinctrl/pinconf.h>
38 #include <linux/pinctrl/pinctrl.h>
39 #include <linux/platform_device.h>
40 #include <linux/pm_domain.h>
41 #include <linux/reboot.h>
42 #include <linux/regmap.h>
43 #include <linux/reset.h>
44 #include <linux/seq_file.h>
45 #include <linux/slab.h>
46 #include <linux/spinlock.h>
47
48 #include <soc/tegra/common.h>
49 #include <soc/tegra/fuse.h>
50 #include <soc/tegra/pmc.h>
51
52 #include <dt-bindings/interrupt-controller/arm-gic.h>
53 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
54 #include <dt-bindings/gpio/tegra186-gpio.h>
55 #include <dt-bindings/gpio/tegra194-gpio.h>
56 #include <dt-bindings/soc/tegra-pmc.h>
57
58 #define PMC_CNTRL 0x0
59 #define PMC_CNTRL_INTR_POLARITY BIT(17) /* inverts INTR polarity */
60 #define PMC_CNTRL_CPU_PWRREQ_OE BIT(16) /* CPU pwr req enable */
61 #define PMC_CNTRL_CPU_PWRREQ_POLARITY BIT(15) /* CPU pwr req polarity */
62 #define PMC_CNTRL_SIDE_EFFECT_LP0 BIT(14) /* LP0 when CPU pwr gated */
63 #define PMC_CNTRL_SYSCLK_OE BIT(11) /* system clock enable */
64 #define PMC_CNTRL_SYSCLK_POLARITY BIT(10) /* sys clk polarity */
65 #define PMC_CNTRL_PWRREQ_POLARITY BIT(8)
66 #define PMC_CNTRL_BLINK_EN 7
67 #define PMC_CNTRL_MAIN_RST BIT(4)
68
69 #define PMC_WAKE_MASK 0x0c
70 #define PMC_WAKE_LEVEL 0x10
71 #define PMC_WAKE_STATUS 0x14
72 #define PMC_SW_WAKE_STATUS 0x18
73 #define PMC_DPD_PADS_ORIDE 0x1c
74 #define PMC_DPD_PADS_ORIDE_BLINK 20
75
76 #define DPD_SAMPLE 0x020
77 #define DPD_SAMPLE_ENABLE BIT(0)
78 #define DPD_SAMPLE_DISABLE (0 << 0)
79
80 #define PWRGATE_TOGGLE 0x30
81 #define PWRGATE_TOGGLE_START BIT(8)
82
83 #define REMOVE_CLAMPING 0x34
84
85 #define PWRGATE_STATUS 0x38
86
87 #define PMC_BLINK_TIMER 0x40
88 #define PMC_IMPL_E_33V_PWR 0x40
89
90 #define PMC_PWR_DET 0x48
91
92 #define PMC_SCRATCH0_MODE_RECOVERY BIT(31)
93 #define PMC_SCRATCH0_MODE_BOOTLOADER BIT(30)
94 #define PMC_SCRATCH0_MODE_RCM BIT(1)
95 #define PMC_SCRATCH0_MODE_MASK (PMC_SCRATCH0_MODE_RECOVERY | \
96 PMC_SCRATCH0_MODE_BOOTLOADER | \
97 PMC_SCRATCH0_MODE_RCM)
98
99 #define PMC_CPUPWRGOOD_TIMER 0xc8
100 #define PMC_CPUPWROFF_TIMER 0xcc
101 #define PMC_COREPWRGOOD_TIMER 0x3c
102 #define PMC_COREPWROFF_TIMER 0xe0
103
104 #define PMC_PWR_DET_VALUE 0xe4
105
106 #define PMC_USB_DEBOUNCE_DEL 0xec
107 #define PMC_USB_AO 0xf0
108
109 #define PMC_SCRATCH41 0x140
110
111 #define PMC_WAKE2_MASK 0x160
112 #define PMC_WAKE2_LEVEL 0x164
113 #define PMC_WAKE2_STATUS 0x168
114 #define PMC_SW_WAKE2_STATUS 0x16c
115
116 #define PMC_CLK_OUT_CNTRL 0x1a8
117 #define PMC_CLK_OUT_MUX_MASK GENMASK(1, 0)
118 #define PMC_SENSOR_CTRL 0x1b0
119 #define PMC_SENSOR_CTRL_SCRATCH_WRITE BIT(2)
120 #define PMC_SENSOR_CTRL_ENABLE_RST BIT(1)
121
122 #define PMC_RST_STATUS_POR 0
123 #define PMC_RST_STATUS_WATCHDOG 1
124 #define PMC_RST_STATUS_SENSOR 2
125 #define PMC_RST_STATUS_SW_MAIN 3
126 #define PMC_RST_STATUS_LP0 4
127 #define PMC_RST_STATUS_AOTAG 5
128
129 #define IO_DPD_REQ 0x1b8
130 #define IO_DPD_REQ_CODE_IDLE (0U << 30)
131 #define IO_DPD_REQ_CODE_OFF (1U << 30)
132 #define IO_DPD_REQ_CODE_ON (2U << 30)
133 #define IO_DPD_REQ_CODE_MASK (3U << 30)
134
135 #define IO_DPD_STATUS 0x1bc
136 #define IO_DPD2_REQ 0x1c0
137 #define IO_DPD2_STATUS 0x1c4
138 #define SEL_DPD_TIM 0x1c8
139
140 #define PMC_UTMIP_UHSIC_TRIGGERS 0x1ec
141 #define PMC_UTMIP_UHSIC_SAVED_STATE 0x1f0
142
143 #define PMC_UTMIP_TERM_PAD_CFG 0x1f8
144 #define PMC_UTMIP_UHSIC_SLEEP_CFG 0x1fc
145 #define PMC_UTMIP_UHSIC_FAKE 0x218
146
147 #define PMC_SCRATCH54 0x258
148 #define PMC_SCRATCH54_DATA_SHIFT 8
149 #define PMC_SCRATCH54_ADDR_SHIFT 0
150
151 #define PMC_SCRATCH55 0x25c
152 #define PMC_SCRATCH55_RESET_TEGRA BIT(31)
153 #define PMC_SCRATCH55_CNTRL_ID_SHIFT 27
154 #define PMC_SCRATCH55_PINMUX_SHIFT 24
155 #define PMC_SCRATCH55_16BITOP BIT(15)
156 #define PMC_SCRATCH55_CHECKSUM_SHIFT 16
157 #define PMC_SCRATCH55_I2CSLV1_SHIFT 0
158
159 #define PMC_UTMIP_UHSIC_LINE_WAKEUP 0x26c
160
161 #define PMC_UTMIP_BIAS_MASTER_CNTRL 0x270
162 #define PMC_UTMIP_MASTER_CONFIG 0x274
163 #define PMC_UTMIP_UHSIC2_TRIGGERS 0x27c
164 #define PMC_UTMIP_MASTER2_CONFIG 0x29c
165
166 #define GPU_RG_CNTRL 0x2d4
167
168 #define PMC_UTMIP_PAD_CFG0 0x4c0
169 #define PMC_UTMIP_UHSIC_SLEEP_CFG1 0x4d0
170 #define PMC_UTMIP_SLEEPWALK_P3 0x4e0
171 /* Tegra186 and later */
172 #define WAKE_AOWAKE_CNTRL(x) (0x000 + ((x) << 2))
173 #define WAKE_AOWAKE_CNTRL_LEVEL (1 << 3)
174 #define WAKE_AOWAKE_MASK_W(x) (0x180 + ((x) << 2))
175 #define WAKE_AOWAKE_MASK_R(x) (0x300 + ((x) << 2))
176 #define WAKE_AOWAKE_STATUS_W(x) (0x30c + ((x) << 2))
177 #define WAKE_AOWAKE_STATUS_R(x) (0x48c + ((x) << 2))
178 #define WAKE_AOWAKE_TIER0_ROUTING(x) (0x4b4 + ((x) << 2))
179 #define WAKE_AOWAKE_TIER1_ROUTING(x) (0x4c0 + ((x) << 2))
180 #define WAKE_AOWAKE_TIER2_ROUTING(x) (0x4cc + ((x) << 2))
181
182 #define WAKE_AOWAKE_CTRL 0x4f4
183 #define WAKE_AOWAKE_CTRL_INTR_POLARITY BIT(0)
184
185 /* for secure PMC */
186 #define TEGRA_SMC_PMC 0xc2fffe00
187 #define TEGRA_SMC_PMC_READ 0xaa
188 #define TEGRA_SMC_PMC_WRITE 0xbb
189
190 struct pmc_clk {
191 struct clk_hw hw;
192 unsigned long offs;
193 u32 mux_shift;
194 u32 force_en_shift;
195 };
196
197 #define to_pmc_clk(_hw) container_of(_hw, struct pmc_clk, hw)
198
199 struct pmc_clk_gate {
200 struct clk_hw hw;
201 unsigned long offs;
202 u32 shift;
203 };
204
205 #define to_pmc_clk_gate(_hw) container_of(_hw, struct pmc_clk_gate, hw)
206
207 struct pmc_clk_init_data {
208 char *name;
209 const char *const *parents;
210 int num_parents;
211 int clk_id;
212 u8 mux_shift;
213 u8 force_en_shift;
214 };
215
216 static const char * const clk_out1_parents[] = { "osc", "osc_div2",
217 "osc_div4", "extern1",
218 };
219
220 static const char * const clk_out2_parents[] = { "osc", "osc_div2",
221 "osc_div4", "extern2",
222 };
223
224 static const char * const clk_out3_parents[] = { "osc", "osc_div2",
225 "osc_div4", "extern3",
226 };
227
228 static const struct pmc_clk_init_data tegra_pmc_clks_data[] = {
229 {
230 .name = "pmc_clk_out_1",
231 .parents = clk_out1_parents,
232 .num_parents = ARRAY_SIZE(clk_out1_parents),
233 .clk_id = TEGRA_PMC_CLK_OUT_1,
234 .mux_shift = 6,
235 .force_en_shift = 2,
236 },
237 {
238 .name = "pmc_clk_out_2",
239 .parents = clk_out2_parents,
240 .num_parents = ARRAY_SIZE(clk_out2_parents),
241 .clk_id = TEGRA_PMC_CLK_OUT_2,
242 .mux_shift = 14,
243 .force_en_shift = 10,
244 },
245 {
246 .name = "pmc_clk_out_3",
247 .parents = clk_out3_parents,
248 .num_parents = ARRAY_SIZE(clk_out3_parents),
249 .clk_id = TEGRA_PMC_CLK_OUT_3,
250 .mux_shift = 22,
251 .force_en_shift = 18,
252 },
253 };
254
255 struct tegra_powergate {
256 struct generic_pm_domain genpd;
257 struct tegra_pmc *pmc;
258 unsigned int id;
259 struct clk **clks;
260 unsigned int num_clks;
261 unsigned long *clk_rates;
262 struct reset_control *reset;
263 };
264
265 struct tegra_io_pad_soc {
266 enum tegra_io_pad id;
267 unsigned int dpd;
268 unsigned int voltage;
269 const char *name;
270 };
271
272 struct tegra_pmc_regs {
273 unsigned int scratch0;
274 unsigned int dpd_req;
275 unsigned int dpd_status;
276 unsigned int dpd2_req;
277 unsigned int dpd2_status;
278 unsigned int rst_status;
279 unsigned int rst_source_shift;
280 unsigned int rst_source_mask;
281 unsigned int rst_level_shift;
282 unsigned int rst_level_mask;
283 };
284
285 struct tegra_wake_event {
286 const char *name;
287 unsigned int id;
288 unsigned int irq;
289 struct {
290 unsigned int instance;
291 unsigned int pin;
292 } gpio;
293 };
294
295 #define TEGRA_WAKE_IRQ(_name, _id, _irq) \
296 { \
297 .name = _name, \
298 .id = _id, \
299 .irq = _irq, \
300 .gpio = { \
301 .instance = UINT_MAX, \
302 .pin = UINT_MAX, \
303 }, \
304 }
305
306 #define TEGRA_WAKE_GPIO(_name, _id, _instance, _pin) \
307 { \
308 .name = _name, \
309 .id = _id, \
310 .irq = 0, \
311 .gpio = { \
312 .instance = _instance, \
313 .pin = _pin, \
314 }, \
315 }
316
317 struct tegra_pmc_soc {
318 unsigned int num_powergates;
319 const char *const *powergates;
320 unsigned int num_cpu_powergates;
321 const u8 *cpu_powergates;
322
323 bool has_tsense_reset;
324 bool has_gpu_clamps;
325 bool needs_mbist_war;
326 bool has_impl_33v_pwr;
327 bool maybe_tz_only;
328
329 const struct tegra_io_pad_soc *io_pads;
330 unsigned int num_io_pads;
331
332 const struct pinctrl_pin_desc *pin_descs;
333 unsigned int num_pin_descs;
334
335 const struct tegra_pmc_regs *regs;
336 void (*init)(struct tegra_pmc *pmc);
337 void (*setup_irq_polarity)(struct tegra_pmc *pmc,
338 struct device_node *np,
339 bool invert);
340 int (*irq_set_wake)(struct irq_data *data, unsigned int on);
341 int (*irq_set_type)(struct irq_data *data, unsigned int type);
342 int (*powergate_set)(struct tegra_pmc *pmc, unsigned int id,
343 bool new_state);
344
345 const char * const *reset_sources;
346 unsigned int num_reset_sources;
347 const char * const *reset_levels;
348 unsigned int num_reset_levels;
349
350 /*
351 * These describe events that can wake the system from sleep (i.e.
352 * LP0 or SC7). Wakeup from other sleep states (such as LP1 or LP2)
353 * are dealt with in the LIC.
354 */
355 const struct tegra_wake_event *wake_events;
356 unsigned int num_wake_events;
357
358 const struct pmc_clk_init_data *pmc_clks_data;
359 unsigned int num_pmc_clks;
360 bool has_blink_output;
361 bool has_usb_sleepwalk;
362 };
363
364 /**
365 * struct tegra_pmc - NVIDIA Tegra PMC
366 * @dev: pointer to PMC device structure
367 * @base: pointer to I/O remapped register region
368 * @wake: pointer to I/O remapped region for WAKE registers
369 * @aotag: pointer to I/O remapped region for AOTAG registers
370 * @scratch: pointer to I/O remapped region for scratch registers
371 * @clk: pointer to pclk clock
372 * @soc: pointer to SoC data structure
373 * @tz_only: flag specifying if the PMC can only be accessed via TrustZone
374 * @debugfs: pointer to debugfs entry
375 * @rate: currently configured rate of pclk
376 * @suspend_mode: lowest suspend mode available
377 * @cpu_good_time: CPU power good time (in microseconds)
378 * @cpu_off_time: CPU power off time (in microsecends)
379 * @core_osc_time: core power good OSC time (in microseconds)
380 * @core_pmu_time: core power good PMU time (in microseconds)
381 * @core_off_time: core power off time (in microseconds)
382 * @corereq_high: core power request is active-high
383 * @sysclkreq_high: system clock request is active-high
384 * @combined_req: combined power request for CPU & core
385 * @cpu_pwr_good_en: CPU power good signal is enabled
386 * @lp0_vec_phys: physical base address of the LP0 warm boot code
387 * @lp0_vec_size: size of the LP0 warm boot code
388 * @powergates_available: Bitmap of available power gates
389 * @powergates_lock: mutex for power gate register access
390 * @pctl_dev: pin controller exposed by the PMC
391 * @domain: IRQ domain provided by the PMC
392 * @irq: chip implementation for the IRQ domain
393 * @clk_nb: pclk clock changes handler
394 */
395 struct tegra_pmc {
396 struct device *dev;
397 void __iomem *base;
398 void __iomem *wake;
399 void __iomem *aotag;
400 void __iomem *scratch;
401 struct clk *clk;
402 struct dentry *debugfs;
403
404 const struct tegra_pmc_soc *soc;
405 bool tz_only;
406
407 unsigned long rate;
408
409 enum tegra_suspend_mode suspend_mode;
410 u32 cpu_good_time;
411 u32 cpu_off_time;
412 u32 core_osc_time;
413 u32 core_pmu_time;
414 u32 core_off_time;
415 bool corereq_high;
416 bool sysclkreq_high;
417 bool combined_req;
418 bool cpu_pwr_good_en;
419 u32 lp0_vec_phys;
420 u32 lp0_vec_size;
421 DECLARE_BITMAP(powergates_available, TEGRA_POWERGATE_MAX);
422
423 struct mutex powergates_lock;
424
425 struct pinctrl_dev *pctl_dev;
426
427 struct irq_domain *domain;
428 struct irq_chip irq;
429
430 struct notifier_block clk_nb;
431 };
432
433 static struct tegra_pmc *pmc = &(struct tegra_pmc) {
434 .base = NULL,
435 .suspend_mode = TEGRA_SUSPEND_NONE,
436 };
437
438 static inline struct tegra_powergate *
to_powergate(struct generic_pm_domain * domain)439 to_powergate(struct generic_pm_domain *domain)
440 {
441 return container_of(domain, struct tegra_powergate, genpd);
442 }
443
tegra_pmc_readl(struct tegra_pmc * pmc,unsigned long offset)444 static u32 tegra_pmc_readl(struct tegra_pmc *pmc, unsigned long offset)
445 {
446 struct arm_smccc_res res;
447
448 if (pmc->tz_only) {
449 arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_READ, offset, 0, 0,
450 0, 0, 0, &res);
451 if (res.a0) {
452 if (pmc->dev)
453 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n",
454 __func__, res.a0);
455 else
456 pr_warn("%s(): SMC failed: %lu\n", __func__,
457 res.a0);
458 }
459
460 return res.a1;
461 }
462
463 return readl(pmc->base + offset);
464 }
465
tegra_pmc_writel(struct tegra_pmc * pmc,u32 value,unsigned long offset)466 static void tegra_pmc_writel(struct tegra_pmc *pmc, u32 value,
467 unsigned long offset)
468 {
469 struct arm_smccc_res res;
470
471 if (pmc->tz_only) {
472 arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_WRITE, offset,
473 value, 0, 0, 0, 0, &res);
474 if (res.a0) {
475 if (pmc->dev)
476 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n",
477 __func__, res.a0);
478 else
479 pr_warn("%s(): SMC failed: %lu\n", __func__,
480 res.a0);
481 }
482 } else {
483 writel(value, pmc->base + offset);
484 }
485 }
486
tegra_pmc_scratch_readl(struct tegra_pmc * pmc,unsigned long offset)487 static u32 tegra_pmc_scratch_readl(struct tegra_pmc *pmc, unsigned long offset)
488 {
489 if (pmc->tz_only)
490 return tegra_pmc_readl(pmc, offset);
491
492 return readl(pmc->scratch + offset);
493 }
494
tegra_pmc_scratch_writel(struct tegra_pmc * pmc,u32 value,unsigned long offset)495 static void tegra_pmc_scratch_writel(struct tegra_pmc *pmc, u32 value,
496 unsigned long offset)
497 {
498 if (pmc->tz_only)
499 tegra_pmc_writel(pmc, value, offset);
500 else
501 writel(value, pmc->scratch + offset);
502 }
503
504 /*
505 * TODO Figure out a way to call this with the struct tegra_pmc * passed in.
506 * This currently doesn't work because readx_poll_timeout() can only operate
507 * on functions that take a single argument.
508 */
tegra_powergate_state(int id)509 static inline bool tegra_powergate_state(int id)
510 {
511 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps)
512 return (tegra_pmc_readl(pmc, GPU_RG_CNTRL) & 0x1) == 0;
513 else
514 return (tegra_pmc_readl(pmc, PWRGATE_STATUS) & BIT(id)) != 0;
515 }
516
tegra_powergate_is_valid(struct tegra_pmc * pmc,int id)517 static inline bool tegra_powergate_is_valid(struct tegra_pmc *pmc, int id)
518 {
519 return (pmc->soc && pmc->soc->powergates[id]);
520 }
521
tegra_powergate_is_available(struct tegra_pmc * pmc,int id)522 static inline bool tegra_powergate_is_available(struct tegra_pmc *pmc, int id)
523 {
524 return test_bit(id, pmc->powergates_available);
525 }
526
tegra_powergate_lookup(struct tegra_pmc * pmc,const char * name)527 static int tegra_powergate_lookup(struct tegra_pmc *pmc, const char *name)
528 {
529 unsigned int i;
530
531 if (!pmc || !pmc->soc || !name)
532 return -EINVAL;
533
534 for (i = 0; i < pmc->soc->num_powergates; i++) {
535 if (!tegra_powergate_is_valid(pmc, i))
536 continue;
537
538 if (!strcmp(name, pmc->soc->powergates[i]))
539 return i;
540 }
541
542 return -ENODEV;
543 }
544
tegra20_powergate_set(struct tegra_pmc * pmc,unsigned int id,bool new_state)545 static int tegra20_powergate_set(struct tegra_pmc *pmc, unsigned int id,
546 bool new_state)
547 {
548 unsigned int retries = 100;
549 bool status;
550 int ret;
551
552 /*
553 * As per TRM documentation, the toggle command will be dropped by PMC
554 * if there is contention with a HW-initiated toggling (i.e. CPU core
555 * power-gated), the command should be retried in that case.
556 */
557 do {
558 tegra_pmc_writel(pmc, PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
559
560 /* wait for PMC to execute the command */
561 ret = readx_poll_timeout(tegra_powergate_state, id, status,
562 status == new_state, 1, 10);
563 } while (ret == -ETIMEDOUT && retries--);
564
565 return ret;
566 }
567
tegra_powergate_toggle_ready(struct tegra_pmc * pmc)568 static inline bool tegra_powergate_toggle_ready(struct tegra_pmc *pmc)
569 {
570 return !(tegra_pmc_readl(pmc, PWRGATE_TOGGLE) & PWRGATE_TOGGLE_START);
571 }
572
tegra114_powergate_set(struct tegra_pmc * pmc,unsigned int id,bool new_state)573 static int tegra114_powergate_set(struct tegra_pmc *pmc, unsigned int id,
574 bool new_state)
575 {
576 bool status;
577 int err;
578
579 /* wait while PMC power gating is contended */
580 err = readx_poll_timeout(tegra_powergate_toggle_ready, pmc, status,
581 status == true, 1, 100);
582 if (err)
583 return err;
584
585 tegra_pmc_writel(pmc, PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
586
587 /* wait for PMC to accept the command */
588 err = readx_poll_timeout(tegra_powergate_toggle_ready, pmc, status,
589 status == true, 1, 100);
590 if (err)
591 return err;
592
593 /* wait for PMC to execute the command */
594 err = readx_poll_timeout(tegra_powergate_state, id, status,
595 status == new_state, 10, 100000);
596 if (err)
597 return err;
598
599 return 0;
600 }
601
602 /**
603 * tegra_powergate_set() - set the state of a partition
604 * @pmc: power management controller
605 * @id: partition ID
606 * @new_state: new state of the partition
607 */
tegra_powergate_set(struct tegra_pmc * pmc,unsigned int id,bool new_state)608 static int tegra_powergate_set(struct tegra_pmc *pmc, unsigned int id,
609 bool new_state)
610 {
611 int err;
612
613 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps)
614 return -EINVAL;
615
616 mutex_lock(&pmc->powergates_lock);
617
618 if (tegra_powergate_state(id) == new_state) {
619 mutex_unlock(&pmc->powergates_lock);
620 return 0;
621 }
622
623 err = pmc->soc->powergate_set(pmc, id, new_state);
624
625 mutex_unlock(&pmc->powergates_lock);
626
627 return err;
628 }
629
__tegra_powergate_remove_clamping(struct tegra_pmc * pmc,unsigned int id)630 static int __tegra_powergate_remove_clamping(struct tegra_pmc *pmc,
631 unsigned int id)
632 {
633 u32 mask;
634
635 mutex_lock(&pmc->powergates_lock);
636
637 /*
638 * On Tegra124 and later, the clamps for the GPU are controlled by a
639 * separate register (with different semantics).
640 */
641 if (id == TEGRA_POWERGATE_3D) {
642 if (pmc->soc->has_gpu_clamps) {
643 tegra_pmc_writel(pmc, 0, GPU_RG_CNTRL);
644 goto out;
645 }
646 }
647
648 /*
649 * Tegra 2 has a bug where PCIE and VDE clamping masks are
650 * swapped relatively to the partition ids
651 */
652 if (id == TEGRA_POWERGATE_VDEC)
653 mask = (1 << TEGRA_POWERGATE_PCIE);
654 else if (id == TEGRA_POWERGATE_PCIE)
655 mask = (1 << TEGRA_POWERGATE_VDEC);
656 else
657 mask = (1 << id);
658
659 tegra_pmc_writel(pmc, mask, REMOVE_CLAMPING);
660
661 out:
662 mutex_unlock(&pmc->powergates_lock);
663
664 return 0;
665 }
666
tegra_powergate_prepare_clocks(struct tegra_powergate * pg)667 static int tegra_powergate_prepare_clocks(struct tegra_powergate *pg)
668 {
669 unsigned long safe_rate = 100 * 1000 * 1000;
670 unsigned int i;
671 int err;
672
673 for (i = 0; i < pg->num_clks; i++) {
674 pg->clk_rates[i] = clk_get_rate(pg->clks[i]);
675
676 if (!pg->clk_rates[i]) {
677 err = -EINVAL;
678 goto out;
679 }
680
681 if (pg->clk_rates[i] <= safe_rate)
682 continue;
683
684 /*
685 * We don't know whether voltage state is okay for the
686 * current clock rate, hence it's better to temporally
687 * switch clock to a safe rate which is suitable for
688 * all voltages, before enabling the clock.
689 */
690 err = clk_set_rate(pg->clks[i], safe_rate);
691 if (err)
692 goto out;
693 }
694
695 return 0;
696
697 out:
698 while (i--)
699 clk_set_rate(pg->clks[i], pg->clk_rates[i]);
700
701 return err;
702 }
703
tegra_powergate_unprepare_clocks(struct tegra_powergate * pg)704 static int tegra_powergate_unprepare_clocks(struct tegra_powergate *pg)
705 {
706 unsigned int i;
707 int err;
708
709 for (i = 0; i < pg->num_clks; i++) {
710 err = clk_set_rate(pg->clks[i], pg->clk_rates[i]);
711 if (err)
712 return err;
713 }
714
715 return 0;
716 }
717
tegra_powergate_disable_clocks(struct tegra_powergate * pg)718 static void tegra_powergate_disable_clocks(struct tegra_powergate *pg)
719 {
720 unsigned int i;
721
722 for (i = 0; i < pg->num_clks; i++)
723 clk_disable_unprepare(pg->clks[i]);
724 }
725
tegra_powergate_enable_clocks(struct tegra_powergate * pg)726 static int tegra_powergate_enable_clocks(struct tegra_powergate *pg)
727 {
728 unsigned int i;
729 int err;
730
731 for (i = 0; i < pg->num_clks; i++) {
732 err = clk_prepare_enable(pg->clks[i]);
733 if (err)
734 goto out;
735 }
736
737 return 0;
738
739 out:
740 while (i--)
741 clk_disable_unprepare(pg->clks[i]);
742
743 return err;
744 }
745
tegra210_clk_handle_mbist_war(unsigned int id)746 int __weak tegra210_clk_handle_mbist_war(unsigned int id)
747 {
748 return 0;
749 }
750
tegra_powergate_power_up(struct tegra_powergate * pg,bool disable_clocks)751 static int tegra_powergate_power_up(struct tegra_powergate *pg,
752 bool disable_clocks)
753 {
754 int err;
755
756 err = reset_control_assert(pg->reset);
757 if (err)
758 return err;
759
760 usleep_range(10, 20);
761
762 err = tegra_powergate_set(pg->pmc, pg->id, true);
763 if (err < 0)
764 return err;
765
766 usleep_range(10, 20);
767
768 err = tegra_powergate_prepare_clocks(pg);
769 if (err)
770 goto powergate_off;
771
772 err = tegra_powergate_enable_clocks(pg);
773 if (err)
774 goto unprepare_clks;
775
776 usleep_range(10, 20);
777
778 err = __tegra_powergate_remove_clamping(pg->pmc, pg->id);
779 if (err)
780 goto disable_clks;
781
782 usleep_range(10, 20);
783
784 err = reset_control_deassert(pg->reset);
785 if (err)
786 goto powergate_off;
787
788 usleep_range(10, 20);
789
790 if (pg->pmc->soc->needs_mbist_war)
791 err = tegra210_clk_handle_mbist_war(pg->id);
792 if (err)
793 goto disable_clks;
794
795 if (disable_clocks)
796 tegra_powergate_disable_clocks(pg);
797
798 err = tegra_powergate_unprepare_clocks(pg);
799 if (err)
800 return err;
801
802 return 0;
803
804 disable_clks:
805 tegra_powergate_disable_clocks(pg);
806 usleep_range(10, 20);
807
808 unprepare_clks:
809 tegra_powergate_unprepare_clocks(pg);
810
811 powergate_off:
812 tegra_powergate_set(pg->pmc, pg->id, false);
813
814 return err;
815 }
816
tegra_powergate_power_down(struct tegra_powergate * pg)817 static int tegra_powergate_power_down(struct tegra_powergate *pg)
818 {
819 int err;
820
821 err = tegra_powergate_prepare_clocks(pg);
822 if (err)
823 return err;
824
825 err = tegra_powergate_enable_clocks(pg);
826 if (err)
827 goto unprepare_clks;
828
829 usleep_range(10, 20);
830
831 err = reset_control_assert(pg->reset);
832 if (err)
833 goto disable_clks;
834
835 usleep_range(10, 20);
836
837 tegra_powergate_disable_clocks(pg);
838
839 usleep_range(10, 20);
840
841 err = tegra_powergate_set(pg->pmc, pg->id, false);
842 if (err)
843 goto assert_resets;
844
845 err = tegra_powergate_unprepare_clocks(pg);
846 if (err)
847 return err;
848
849 return 0;
850
851 assert_resets:
852 tegra_powergate_enable_clocks(pg);
853 usleep_range(10, 20);
854 reset_control_deassert(pg->reset);
855 usleep_range(10, 20);
856
857 disable_clks:
858 tegra_powergate_disable_clocks(pg);
859
860 unprepare_clks:
861 tegra_powergate_unprepare_clocks(pg);
862
863 return err;
864 }
865
tegra_genpd_power_on(struct generic_pm_domain * domain)866 static int tegra_genpd_power_on(struct generic_pm_domain *domain)
867 {
868 struct tegra_powergate *pg = to_powergate(domain);
869 struct device *dev = pg->pmc->dev;
870 int err;
871
872 err = tegra_powergate_power_up(pg, true);
873 if (err) {
874 dev_err(dev, "failed to turn on PM domain %s: %d\n",
875 pg->genpd.name, err);
876 goto out;
877 }
878
879 reset_control_release(pg->reset);
880
881 out:
882 return err;
883 }
884
tegra_genpd_power_off(struct generic_pm_domain * domain)885 static int tegra_genpd_power_off(struct generic_pm_domain *domain)
886 {
887 struct tegra_powergate *pg = to_powergate(domain);
888 struct device *dev = pg->pmc->dev;
889 int err;
890
891 err = reset_control_acquire(pg->reset);
892 if (err < 0) {
893 dev_err(dev, "failed to acquire resets for PM domain %s: %d\n",
894 pg->genpd.name, err);
895 return err;
896 }
897
898 err = tegra_powergate_power_down(pg);
899 if (err) {
900 dev_err(dev, "failed to turn off PM domain %s: %d\n",
901 pg->genpd.name, err);
902 reset_control_release(pg->reset);
903 }
904
905 return err;
906 }
907
908 /**
909 * tegra_powergate_power_on() - power on partition
910 * @id: partition ID
911 */
tegra_powergate_power_on(unsigned int id)912 int tegra_powergate_power_on(unsigned int id)
913 {
914 if (!tegra_powergate_is_available(pmc, id))
915 return -EINVAL;
916
917 return tegra_powergate_set(pmc, id, true);
918 }
919 EXPORT_SYMBOL(tegra_powergate_power_on);
920
921 /**
922 * tegra_powergate_power_off() - power off partition
923 * @id: partition ID
924 */
tegra_powergate_power_off(unsigned int id)925 int tegra_powergate_power_off(unsigned int id)
926 {
927 if (!tegra_powergate_is_available(pmc, id))
928 return -EINVAL;
929
930 return tegra_powergate_set(pmc, id, false);
931 }
932 EXPORT_SYMBOL(tegra_powergate_power_off);
933
934 /**
935 * tegra_powergate_is_powered() - check if partition is powered
936 * @pmc: power management controller
937 * @id: partition ID
938 */
tegra_powergate_is_powered(struct tegra_pmc * pmc,unsigned int id)939 static int tegra_powergate_is_powered(struct tegra_pmc *pmc, unsigned int id)
940 {
941 if (!tegra_powergate_is_valid(pmc, id))
942 return -EINVAL;
943
944 return tegra_powergate_state(id);
945 }
946
947 /**
948 * tegra_powergate_remove_clamping() - remove power clamps for partition
949 * @id: partition ID
950 */
tegra_powergate_remove_clamping(unsigned int id)951 int tegra_powergate_remove_clamping(unsigned int id)
952 {
953 if (!tegra_powergate_is_available(pmc, id))
954 return -EINVAL;
955
956 return __tegra_powergate_remove_clamping(pmc, id);
957 }
958 EXPORT_SYMBOL(tegra_powergate_remove_clamping);
959
960 /**
961 * tegra_powergate_sequence_power_up() - power up partition
962 * @id: partition ID
963 * @clk: clock for partition
964 * @rst: reset for partition
965 *
966 * Must be called with clk disabled, and returns with clk enabled.
967 */
tegra_powergate_sequence_power_up(unsigned int id,struct clk * clk,struct reset_control * rst)968 int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk,
969 struct reset_control *rst)
970 {
971 struct tegra_powergate *pg;
972 int err;
973
974 if (!tegra_powergate_is_available(pmc, id))
975 return -EINVAL;
976
977 pg = kzalloc(sizeof(*pg), GFP_KERNEL);
978 if (!pg)
979 return -ENOMEM;
980
981 pg->clk_rates = kzalloc(sizeof(*pg->clk_rates), GFP_KERNEL);
982 if (!pg->clk_rates) {
983 kfree(pg->clks);
984 return -ENOMEM;
985 }
986
987 pg->id = id;
988 pg->clks = &clk;
989 pg->num_clks = 1;
990 pg->reset = rst;
991 pg->pmc = pmc;
992
993 err = tegra_powergate_power_up(pg, false);
994 if (err)
995 dev_err(pmc->dev, "failed to turn on partition %d: %d\n", id,
996 err);
997
998 kfree(pg->clk_rates);
999 kfree(pg);
1000
1001 return err;
1002 }
1003 EXPORT_SYMBOL(tegra_powergate_sequence_power_up);
1004
1005 /**
1006 * tegra_get_cpu_powergate_id() - convert from CPU ID to partition ID
1007 * @pmc: power management controller
1008 * @cpuid: CPU partition ID
1009 *
1010 * Returns the partition ID corresponding to the CPU partition ID or a
1011 * negative error code on failure.
1012 */
tegra_get_cpu_powergate_id(struct tegra_pmc * pmc,unsigned int cpuid)1013 static int tegra_get_cpu_powergate_id(struct tegra_pmc *pmc,
1014 unsigned int cpuid)
1015 {
1016 if (pmc->soc && cpuid < pmc->soc->num_cpu_powergates)
1017 return pmc->soc->cpu_powergates[cpuid];
1018
1019 return -EINVAL;
1020 }
1021
1022 /**
1023 * tegra_pmc_cpu_is_powered() - check if CPU partition is powered
1024 * @cpuid: CPU partition ID
1025 */
tegra_pmc_cpu_is_powered(unsigned int cpuid)1026 bool tegra_pmc_cpu_is_powered(unsigned int cpuid)
1027 {
1028 int id;
1029
1030 id = tegra_get_cpu_powergate_id(pmc, cpuid);
1031 if (id < 0)
1032 return false;
1033
1034 return tegra_powergate_is_powered(pmc, id);
1035 }
1036
1037 /**
1038 * tegra_pmc_cpu_power_on() - power on CPU partition
1039 * @cpuid: CPU partition ID
1040 */
tegra_pmc_cpu_power_on(unsigned int cpuid)1041 int tegra_pmc_cpu_power_on(unsigned int cpuid)
1042 {
1043 int id;
1044
1045 id = tegra_get_cpu_powergate_id(pmc, cpuid);
1046 if (id < 0)
1047 return id;
1048
1049 return tegra_powergate_set(pmc, id, true);
1050 }
1051
1052 /**
1053 * tegra_pmc_cpu_remove_clamping() - remove power clamps for CPU partition
1054 * @cpuid: CPU partition ID
1055 */
tegra_pmc_cpu_remove_clamping(unsigned int cpuid)1056 int tegra_pmc_cpu_remove_clamping(unsigned int cpuid)
1057 {
1058 int id;
1059
1060 id = tegra_get_cpu_powergate_id(pmc, cpuid);
1061 if (id < 0)
1062 return id;
1063
1064 return tegra_powergate_remove_clamping(id);
1065 }
1066
tegra_pmc_restart_notify(struct notifier_block * this,unsigned long action,void * data)1067 static int tegra_pmc_restart_notify(struct notifier_block *this,
1068 unsigned long action, void *data)
1069 {
1070 const char *cmd = data;
1071 u32 value;
1072
1073 value = tegra_pmc_scratch_readl(pmc, pmc->soc->regs->scratch0);
1074 value &= ~PMC_SCRATCH0_MODE_MASK;
1075
1076 if (cmd) {
1077 if (strcmp(cmd, "recovery") == 0)
1078 value |= PMC_SCRATCH0_MODE_RECOVERY;
1079
1080 if (strcmp(cmd, "bootloader") == 0)
1081 value |= PMC_SCRATCH0_MODE_BOOTLOADER;
1082
1083 if (strcmp(cmd, "forced-recovery") == 0)
1084 value |= PMC_SCRATCH0_MODE_RCM;
1085 }
1086
1087 tegra_pmc_scratch_writel(pmc, value, pmc->soc->regs->scratch0);
1088
1089 /* reset everything but PMC_SCRATCH0 and PMC_RST_STATUS */
1090 value = tegra_pmc_readl(pmc, PMC_CNTRL);
1091 value |= PMC_CNTRL_MAIN_RST;
1092 tegra_pmc_writel(pmc, value, PMC_CNTRL);
1093
1094 return NOTIFY_DONE;
1095 }
1096
1097 static struct notifier_block tegra_pmc_restart_handler = {
1098 .notifier_call = tegra_pmc_restart_notify,
1099 .priority = 128,
1100 };
1101
powergate_show(struct seq_file * s,void * data)1102 static int powergate_show(struct seq_file *s, void *data)
1103 {
1104 unsigned int i;
1105 int status;
1106
1107 seq_printf(s, " powergate powered\n");
1108 seq_printf(s, "------------------\n");
1109
1110 for (i = 0; i < pmc->soc->num_powergates; i++) {
1111 status = tegra_powergate_is_powered(pmc, i);
1112 if (status < 0)
1113 continue;
1114
1115 seq_printf(s, " %9s %7s\n", pmc->soc->powergates[i],
1116 status ? "yes" : "no");
1117 }
1118
1119 return 0;
1120 }
1121
1122 DEFINE_SHOW_ATTRIBUTE(powergate);
1123
tegra_powergate_debugfs_init(void)1124 static int tegra_powergate_debugfs_init(void)
1125 {
1126 pmc->debugfs = debugfs_create_file("powergate", S_IRUGO, NULL, NULL,
1127 &powergate_fops);
1128 if (!pmc->debugfs)
1129 return -ENOMEM;
1130
1131 return 0;
1132 }
1133
tegra_powergate_of_get_clks(struct tegra_powergate * pg,struct device_node * np)1134 static int tegra_powergate_of_get_clks(struct tegra_powergate *pg,
1135 struct device_node *np)
1136 {
1137 struct clk *clk;
1138 unsigned int i, count;
1139 int err;
1140
1141 count = of_clk_get_parent_count(np);
1142 if (count == 0)
1143 return -ENODEV;
1144
1145 pg->clks = kcalloc(count, sizeof(clk), GFP_KERNEL);
1146 if (!pg->clks)
1147 return -ENOMEM;
1148
1149 pg->clk_rates = kcalloc(count, sizeof(*pg->clk_rates), GFP_KERNEL);
1150 if (!pg->clk_rates) {
1151 kfree(pg->clks);
1152 return -ENOMEM;
1153 }
1154
1155 for (i = 0; i < count; i++) {
1156 pg->clks[i] = of_clk_get(np, i);
1157 if (IS_ERR(pg->clks[i])) {
1158 err = PTR_ERR(pg->clks[i]);
1159 goto err;
1160 }
1161 }
1162
1163 pg->num_clks = count;
1164
1165 return 0;
1166
1167 err:
1168 while (i--)
1169 clk_put(pg->clks[i]);
1170
1171 kfree(pg->clk_rates);
1172 kfree(pg->clks);
1173
1174 return err;
1175 }
1176
tegra_powergate_of_get_resets(struct tegra_powergate * pg,struct device_node * np,bool off)1177 static int tegra_powergate_of_get_resets(struct tegra_powergate *pg,
1178 struct device_node *np, bool off)
1179 {
1180 struct device *dev = pg->pmc->dev;
1181 int err;
1182
1183 pg->reset = of_reset_control_array_get_exclusive_released(np);
1184 if (IS_ERR(pg->reset)) {
1185 err = PTR_ERR(pg->reset);
1186 dev_err(dev, "failed to get device resets: %d\n", err);
1187 return err;
1188 }
1189
1190 err = reset_control_acquire(pg->reset);
1191 if (err < 0) {
1192 pr_err("failed to acquire resets: %d\n", err);
1193 goto out;
1194 }
1195
1196 if (off) {
1197 err = reset_control_assert(pg->reset);
1198 } else {
1199 err = reset_control_deassert(pg->reset);
1200 if (err < 0)
1201 goto out;
1202
1203 reset_control_release(pg->reset);
1204 }
1205
1206 out:
1207 if (err) {
1208 reset_control_release(pg->reset);
1209 reset_control_put(pg->reset);
1210 }
1211
1212 return err;
1213 }
1214
tegra_powergate_add(struct tegra_pmc * pmc,struct device_node * np)1215 static int tegra_powergate_add(struct tegra_pmc *pmc, struct device_node *np)
1216 {
1217 struct device *dev = pmc->dev;
1218 struct tegra_powergate *pg;
1219 int id, err = 0;
1220 bool off;
1221
1222 pg = kzalloc(sizeof(*pg), GFP_KERNEL);
1223 if (!pg)
1224 return -ENOMEM;
1225
1226 id = tegra_powergate_lookup(pmc, np->name);
1227 if (id < 0) {
1228 dev_err(dev, "powergate lookup failed for %pOFn: %d\n", np, id);
1229 err = -ENODEV;
1230 goto free_mem;
1231 }
1232
1233 /*
1234 * Clear the bit for this powergate so it cannot be managed
1235 * directly via the legacy APIs for controlling powergates.
1236 */
1237 clear_bit(id, pmc->powergates_available);
1238
1239 pg->id = id;
1240 pg->genpd.name = np->name;
1241 pg->genpd.power_off = tegra_genpd_power_off;
1242 pg->genpd.power_on = tegra_genpd_power_on;
1243 pg->pmc = pmc;
1244
1245 off = !tegra_powergate_is_powered(pmc, pg->id);
1246
1247 err = tegra_powergate_of_get_clks(pg, np);
1248 if (err < 0) {
1249 dev_err(dev, "failed to get clocks for %pOFn: %d\n", np, err);
1250 goto set_available;
1251 }
1252
1253 err = tegra_powergate_of_get_resets(pg, np, off);
1254 if (err < 0) {
1255 dev_err(dev, "failed to get resets for %pOFn: %d\n", np, err);
1256 goto remove_clks;
1257 }
1258
1259 if (!IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) {
1260 if (off)
1261 WARN_ON(tegra_powergate_power_up(pg, true));
1262
1263 goto remove_resets;
1264 }
1265
1266 err = pm_genpd_init(&pg->genpd, NULL, off);
1267 if (err < 0) {
1268 dev_err(dev, "failed to initialise PM domain %pOFn: %d\n", np,
1269 err);
1270 goto remove_resets;
1271 }
1272
1273 err = of_genpd_add_provider_simple(np, &pg->genpd);
1274 if (err < 0) {
1275 dev_err(dev, "failed to add PM domain provider for %pOFn: %d\n",
1276 np, err);
1277 goto remove_genpd;
1278 }
1279
1280 dev_dbg(dev, "added PM domain %s\n", pg->genpd.name);
1281
1282 return 0;
1283
1284 remove_genpd:
1285 pm_genpd_remove(&pg->genpd);
1286
1287 remove_resets:
1288 reset_control_put(pg->reset);
1289
1290 remove_clks:
1291 while (pg->num_clks--)
1292 clk_put(pg->clks[pg->num_clks]);
1293
1294 kfree(pg->clks);
1295
1296 set_available:
1297 set_bit(id, pmc->powergates_available);
1298
1299 free_mem:
1300 kfree(pg);
1301
1302 return err;
1303 }
1304
tegra_powergate_init(struct tegra_pmc * pmc,struct device_node * parent)1305 static int tegra_powergate_init(struct tegra_pmc *pmc,
1306 struct device_node *parent)
1307 {
1308 struct device_node *np, *child;
1309 int err = 0;
1310
1311 np = of_get_child_by_name(parent, "powergates");
1312 if (!np)
1313 return 0;
1314
1315 for_each_child_of_node(np, child) {
1316 err = tegra_powergate_add(pmc, child);
1317 if (err < 0) {
1318 of_node_put(child);
1319 break;
1320 }
1321 }
1322
1323 of_node_put(np);
1324
1325 return err;
1326 }
1327
tegra_powergate_remove(struct generic_pm_domain * genpd)1328 static void tegra_powergate_remove(struct generic_pm_domain *genpd)
1329 {
1330 struct tegra_powergate *pg = to_powergate(genpd);
1331
1332 reset_control_put(pg->reset);
1333
1334 while (pg->num_clks--)
1335 clk_put(pg->clks[pg->num_clks]);
1336
1337 kfree(pg->clks);
1338
1339 set_bit(pg->id, pmc->powergates_available);
1340
1341 kfree(pg);
1342 }
1343
tegra_powergate_remove_all(struct device_node * parent)1344 static void tegra_powergate_remove_all(struct device_node *parent)
1345 {
1346 struct generic_pm_domain *genpd;
1347 struct device_node *np, *child;
1348
1349 np = of_get_child_by_name(parent, "powergates");
1350 if (!np)
1351 return;
1352
1353 for_each_child_of_node(np, child) {
1354 of_genpd_del_provider(child);
1355
1356 genpd = of_genpd_remove_last(child);
1357 if (IS_ERR(genpd))
1358 continue;
1359
1360 tegra_powergate_remove(genpd);
1361 }
1362
1363 of_node_put(np);
1364 }
1365
1366 static const struct tegra_io_pad_soc *
tegra_io_pad_find(struct tegra_pmc * pmc,enum tegra_io_pad id)1367 tegra_io_pad_find(struct tegra_pmc *pmc, enum tegra_io_pad id)
1368 {
1369 unsigned int i;
1370
1371 for (i = 0; i < pmc->soc->num_io_pads; i++)
1372 if (pmc->soc->io_pads[i].id == id)
1373 return &pmc->soc->io_pads[i];
1374
1375 return NULL;
1376 }
1377
tegra_io_pad_get_dpd_register_bit(struct tegra_pmc * pmc,enum tegra_io_pad id,unsigned long * request,unsigned long * status,u32 * mask)1378 static int tegra_io_pad_get_dpd_register_bit(struct tegra_pmc *pmc,
1379 enum tegra_io_pad id,
1380 unsigned long *request,
1381 unsigned long *status,
1382 u32 *mask)
1383 {
1384 const struct tegra_io_pad_soc *pad;
1385
1386 pad = tegra_io_pad_find(pmc, id);
1387 if (!pad) {
1388 dev_err(pmc->dev, "invalid I/O pad ID %u\n", id);
1389 return -ENOENT;
1390 }
1391
1392 if (pad->dpd == UINT_MAX)
1393 return -ENOTSUPP;
1394
1395 *mask = BIT(pad->dpd % 32);
1396
1397 if (pad->dpd < 32) {
1398 *status = pmc->soc->regs->dpd_status;
1399 *request = pmc->soc->regs->dpd_req;
1400 } else {
1401 *status = pmc->soc->regs->dpd2_status;
1402 *request = pmc->soc->regs->dpd2_req;
1403 }
1404
1405 return 0;
1406 }
1407
tegra_io_pad_prepare(struct tegra_pmc * pmc,enum tegra_io_pad id,unsigned long * request,unsigned long * status,u32 * mask)1408 static int tegra_io_pad_prepare(struct tegra_pmc *pmc, enum tegra_io_pad id,
1409 unsigned long *request, unsigned long *status,
1410 u32 *mask)
1411 {
1412 unsigned long rate, value;
1413 int err;
1414
1415 err = tegra_io_pad_get_dpd_register_bit(pmc, id, request, status, mask);
1416 if (err)
1417 return err;
1418
1419 if (pmc->clk) {
1420 rate = pmc->rate;
1421 if (!rate) {
1422 dev_err(pmc->dev, "failed to get clock rate\n");
1423 return -ENODEV;
1424 }
1425
1426 tegra_pmc_writel(pmc, DPD_SAMPLE_ENABLE, DPD_SAMPLE);
1427
1428 /* must be at least 200 ns, in APB (PCLK) clock cycles */
1429 value = DIV_ROUND_UP(1000000000, rate);
1430 value = DIV_ROUND_UP(200, value);
1431 tegra_pmc_writel(pmc, value, SEL_DPD_TIM);
1432 }
1433
1434 return 0;
1435 }
1436
tegra_io_pad_poll(struct tegra_pmc * pmc,unsigned long offset,u32 mask,u32 val,unsigned long timeout)1437 static int tegra_io_pad_poll(struct tegra_pmc *pmc, unsigned long offset,
1438 u32 mask, u32 val, unsigned long timeout)
1439 {
1440 u32 value;
1441
1442 timeout = jiffies + msecs_to_jiffies(timeout);
1443
1444 while (time_after(timeout, jiffies)) {
1445 value = tegra_pmc_readl(pmc, offset);
1446 if ((value & mask) == val)
1447 return 0;
1448
1449 usleep_range(250, 1000);
1450 }
1451
1452 return -ETIMEDOUT;
1453 }
1454
tegra_io_pad_unprepare(struct tegra_pmc * pmc)1455 static void tegra_io_pad_unprepare(struct tegra_pmc *pmc)
1456 {
1457 if (pmc->clk)
1458 tegra_pmc_writel(pmc, DPD_SAMPLE_DISABLE, DPD_SAMPLE);
1459 }
1460
1461 /**
1462 * tegra_io_pad_power_enable() - enable power to I/O pad
1463 * @id: Tegra I/O pad ID for which to enable power
1464 *
1465 * Returns: 0 on success or a negative error code on failure.
1466 */
tegra_io_pad_power_enable(enum tegra_io_pad id)1467 int tegra_io_pad_power_enable(enum tegra_io_pad id)
1468 {
1469 unsigned long request, status;
1470 u32 mask;
1471 int err;
1472
1473 mutex_lock(&pmc->powergates_lock);
1474
1475 err = tegra_io_pad_prepare(pmc, id, &request, &status, &mask);
1476 if (err < 0) {
1477 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err);
1478 goto unlock;
1479 }
1480
1481 tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_OFF | mask, request);
1482
1483 err = tegra_io_pad_poll(pmc, status, mask, 0, 250);
1484 if (err < 0) {
1485 dev_err(pmc->dev, "failed to enable I/O pad: %d\n", err);
1486 goto unlock;
1487 }
1488
1489 tegra_io_pad_unprepare(pmc);
1490
1491 unlock:
1492 mutex_unlock(&pmc->powergates_lock);
1493 return err;
1494 }
1495 EXPORT_SYMBOL(tegra_io_pad_power_enable);
1496
1497 /**
1498 * tegra_io_pad_power_disable() - disable power to I/O pad
1499 * @id: Tegra I/O pad ID for which to disable power
1500 *
1501 * Returns: 0 on success or a negative error code on failure.
1502 */
tegra_io_pad_power_disable(enum tegra_io_pad id)1503 int tegra_io_pad_power_disable(enum tegra_io_pad id)
1504 {
1505 unsigned long request, status;
1506 u32 mask;
1507 int err;
1508
1509 mutex_lock(&pmc->powergates_lock);
1510
1511 err = tegra_io_pad_prepare(pmc, id, &request, &status, &mask);
1512 if (err < 0) {
1513 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err);
1514 goto unlock;
1515 }
1516
1517 tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_ON | mask, request);
1518
1519 err = tegra_io_pad_poll(pmc, status, mask, mask, 250);
1520 if (err < 0) {
1521 dev_err(pmc->dev, "failed to disable I/O pad: %d\n", err);
1522 goto unlock;
1523 }
1524
1525 tegra_io_pad_unprepare(pmc);
1526
1527 unlock:
1528 mutex_unlock(&pmc->powergates_lock);
1529 return err;
1530 }
1531 EXPORT_SYMBOL(tegra_io_pad_power_disable);
1532
tegra_io_pad_is_powered(struct tegra_pmc * pmc,enum tegra_io_pad id)1533 static int tegra_io_pad_is_powered(struct tegra_pmc *pmc, enum tegra_io_pad id)
1534 {
1535 unsigned long request, status;
1536 u32 mask, value;
1537 int err;
1538
1539 err = tegra_io_pad_get_dpd_register_bit(pmc, id, &request, &status,
1540 &mask);
1541 if (err)
1542 return err;
1543
1544 value = tegra_pmc_readl(pmc, status);
1545
1546 return !(value & mask);
1547 }
1548
tegra_io_pad_set_voltage(struct tegra_pmc * pmc,enum tegra_io_pad id,int voltage)1549 static int tegra_io_pad_set_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id,
1550 int voltage)
1551 {
1552 const struct tegra_io_pad_soc *pad;
1553 u32 value;
1554
1555 pad = tegra_io_pad_find(pmc, id);
1556 if (!pad)
1557 return -ENOENT;
1558
1559 if (pad->voltage == UINT_MAX)
1560 return -ENOTSUPP;
1561
1562 mutex_lock(&pmc->powergates_lock);
1563
1564 if (pmc->soc->has_impl_33v_pwr) {
1565 value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR);
1566
1567 if (voltage == TEGRA_IO_PAD_VOLTAGE_1V8)
1568 value &= ~BIT(pad->voltage);
1569 else
1570 value |= BIT(pad->voltage);
1571
1572 tegra_pmc_writel(pmc, value, PMC_IMPL_E_33V_PWR);
1573 } else {
1574 /* write-enable PMC_PWR_DET_VALUE[pad->voltage] */
1575 value = tegra_pmc_readl(pmc, PMC_PWR_DET);
1576 value |= BIT(pad->voltage);
1577 tegra_pmc_writel(pmc, value, PMC_PWR_DET);
1578
1579 /* update I/O voltage */
1580 value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE);
1581
1582 if (voltage == TEGRA_IO_PAD_VOLTAGE_1V8)
1583 value &= ~BIT(pad->voltage);
1584 else
1585 value |= BIT(pad->voltage);
1586
1587 tegra_pmc_writel(pmc, value, PMC_PWR_DET_VALUE);
1588 }
1589
1590 mutex_unlock(&pmc->powergates_lock);
1591
1592 usleep_range(100, 250);
1593
1594 return 0;
1595 }
1596
tegra_io_pad_get_voltage(struct tegra_pmc * pmc,enum tegra_io_pad id)1597 static int tegra_io_pad_get_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id)
1598 {
1599 const struct tegra_io_pad_soc *pad;
1600 u32 value;
1601
1602 pad = tegra_io_pad_find(pmc, id);
1603 if (!pad)
1604 return -ENOENT;
1605
1606 if (pad->voltage == UINT_MAX)
1607 return -ENOTSUPP;
1608
1609 if (pmc->soc->has_impl_33v_pwr)
1610 value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR);
1611 else
1612 value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE);
1613
1614 if ((value & BIT(pad->voltage)) == 0)
1615 return TEGRA_IO_PAD_VOLTAGE_1V8;
1616
1617 return TEGRA_IO_PAD_VOLTAGE_3V3;
1618 }
1619
1620 /**
1621 * tegra_io_rail_power_on() - enable power to I/O rail
1622 * @id: Tegra I/O pad ID for which to enable power
1623 *
1624 * See also: tegra_io_pad_power_enable()
1625 */
tegra_io_rail_power_on(unsigned int id)1626 int tegra_io_rail_power_on(unsigned int id)
1627 {
1628 return tegra_io_pad_power_enable(id);
1629 }
1630 EXPORT_SYMBOL(tegra_io_rail_power_on);
1631
1632 /**
1633 * tegra_io_rail_power_off() - disable power to I/O rail
1634 * @id: Tegra I/O pad ID for which to disable power
1635 *
1636 * See also: tegra_io_pad_power_disable()
1637 */
tegra_io_rail_power_off(unsigned int id)1638 int tegra_io_rail_power_off(unsigned int id)
1639 {
1640 return tegra_io_pad_power_disable(id);
1641 }
1642 EXPORT_SYMBOL(tegra_io_rail_power_off);
1643
1644 #ifdef CONFIG_PM_SLEEP
tegra_pmc_get_suspend_mode(void)1645 enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void)
1646 {
1647 return pmc->suspend_mode;
1648 }
1649
tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode)1650 void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode)
1651 {
1652 if (mode < TEGRA_SUSPEND_NONE || mode >= TEGRA_MAX_SUSPEND_MODE)
1653 return;
1654
1655 pmc->suspend_mode = mode;
1656 }
1657
tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode)1658 void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode)
1659 {
1660 unsigned long long rate = 0;
1661 u64 ticks;
1662 u32 value;
1663
1664 switch (mode) {
1665 case TEGRA_SUSPEND_LP1:
1666 rate = 32768;
1667 break;
1668
1669 case TEGRA_SUSPEND_LP2:
1670 rate = pmc->rate;
1671 break;
1672
1673 default:
1674 break;
1675 }
1676
1677 if (WARN_ON_ONCE(rate == 0))
1678 rate = 100000000;
1679
1680 ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1;
1681 do_div(ticks, USEC_PER_SEC);
1682 tegra_pmc_writel(pmc, ticks, PMC_CPUPWRGOOD_TIMER);
1683
1684 ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1;
1685 do_div(ticks, USEC_PER_SEC);
1686 tegra_pmc_writel(pmc, ticks, PMC_CPUPWROFF_TIMER);
1687
1688 value = tegra_pmc_readl(pmc, PMC_CNTRL);
1689 value &= ~PMC_CNTRL_SIDE_EFFECT_LP0;
1690 value |= PMC_CNTRL_CPU_PWRREQ_OE;
1691 tegra_pmc_writel(pmc, value, PMC_CNTRL);
1692 }
1693 #endif
1694
tegra_pmc_parse_dt(struct tegra_pmc * pmc,struct device_node * np)1695 static int tegra_pmc_parse_dt(struct tegra_pmc *pmc, struct device_node *np)
1696 {
1697 u32 value, values[2];
1698
1699 if (of_property_read_u32(np, "nvidia,suspend-mode", &value)) {
1700 } else {
1701 switch (value) {
1702 case 0:
1703 pmc->suspend_mode = TEGRA_SUSPEND_LP0;
1704 break;
1705
1706 case 1:
1707 pmc->suspend_mode = TEGRA_SUSPEND_LP1;
1708 break;
1709
1710 case 2:
1711 pmc->suspend_mode = TEGRA_SUSPEND_LP2;
1712 break;
1713
1714 default:
1715 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1716 break;
1717 }
1718 }
1719
1720 pmc->suspend_mode = tegra_pm_validate_suspend_mode(pmc->suspend_mode);
1721
1722 if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &value))
1723 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1724
1725 pmc->cpu_good_time = value;
1726
1727 if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &value))
1728 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1729
1730 pmc->cpu_off_time = value;
1731
1732 if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time",
1733 values, ARRAY_SIZE(values)))
1734 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1735
1736 pmc->core_osc_time = values[0];
1737 pmc->core_pmu_time = values[1];
1738
1739 if (of_property_read_u32(np, "nvidia,core-pwr-off-time", &value))
1740 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1741
1742 pmc->core_off_time = value;
1743
1744 pmc->corereq_high = of_property_read_bool(np,
1745 "nvidia,core-power-req-active-high");
1746
1747 pmc->sysclkreq_high = of_property_read_bool(np,
1748 "nvidia,sys-clock-req-active-high");
1749
1750 pmc->combined_req = of_property_read_bool(np,
1751 "nvidia,combined-power-req");
1752
1753 pmc->cpu_pwr_good_en = of_property_read_bool(np,
1754 "nvidia,cpu-pwr-good-en");
1755
1756 if (of_property_read_u32_array(np, "nvidia,lp0-vec", values,
1757 ARRAY_SIZE(values)))
1758 if (pmc->suspend_mode == TEGRA_SUSPEND_LP0)
1759 pmc->suspend_mode = TEGRA_SUSPEND_LP1;
1760
1761 pmc->lp0_vec_phys = values[0];
1762 pmc->lp0_vec_size = values[1];
1763
1764 return 0;
1765 }
1766
tegra_pmc_init(struct tegra_pmc * pmc)1767 static void tegra_pmc_init(struct tegra_pmc *pmc)
1768 {
1769 if (pmc->soc->init)
1770 pmc->soc->init(pmc);
1771 }
1772
tegra_pmc_init_tsense_reset(struct tegra_pmc * pmc)1773 static void tegra_pmc_init_tsense_reset(struct tegra_pmc *pmc)
1774 {
1775 static const char disabled[] = "emergency thermal reset disabled";
1776 u32 pmu_addr, ctrl_id, reg_addr, reg_data, pinmux;
1777 struct device *dev = pmc->dev;
1778 struct device_node *np;
1779 u32 value, checksum;
1780
1781 if (!pmc->soc->has_tsense_reset)
1782 return;
1783
1784 np = of_get_child_by_name(pmc->dev->of_node, "i2c-thermtrip");
1785 if (!np) {
1786 dev_warn(dev, "i2c-thermtrip node not found, %s.\n", disabled);
1787 return;
1788 }
1789
1790 if (of_property_read_u32(np, "nvidia,i2c-controller-id", &ctrl_id)) {
1791 dev_err(dev, "I2C controller ID missing, %s.\n", disabled);
1792 goto out;
1793 }
1794
1795 if (of_property_read_u32(np, "nvidia,bus-addr", &pmu_addr)) {
1796 dev_err(dev, "nvidia,bus-addr missing, %s.\n", disabled);
1797 goto out;
1798 }
1799
1800 if (of_property_read_u32(np, "nvidia,reg-addr", ®_addr)) {
1801 dev_err(dev, "nvidia,reg-addr missing, %s.\n", disabled);
1802 goto out;
1803 }
1804
1805 if (of_property_read_u32(np, "nvidia,reg-data", ®_data)) {
1806 dev_err(dev, "nvidia,reg-data missing, %s.\n", disabled);
1807 goto out;
1808 }
1809
1810 if (of_property_read_u32(np, "nvidia,pinmux-id", &pinmux))
1811 pinmux = 0;
1812
1813 value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL);
1814 value |= PMC_SENSOR_CTRL_SCRATCH_WRITE;
1815 tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL);
1816
1817 value = (reg_data << PMC_SCRATCH54_DATA_SHIFT) |
1818 (reg_addr << PMC_SCRATCH54_ADDR_SHIFT);
1819 tegra_pmc_writel(pmc, value, PMC_SCRATCH54);
1820
1821 value = PMC_SCRATCH55_RESET_TEGRA;
1822 value |= ctrl_id << PMC_SCRATCH55_CNTRL_ID_SHIFT;
1823 value |= pinmux << PMC_SCRATCH55_PINMUX_SHIFT;
1824 value |= pmu_addr << PMC_SCRATCH55_I2CSLV1_SHIFT;
1825
1826 /*
1827 * Calculate checksum of SCRATCH54, SCRATCH55 fields. Bits 23:16 will
1828 * contain the checksum and are currently zero, so they are not added.
1829 */
1830 checksum = reg_addr + reg_data + (value & 0xff) + ((value >> 8) & 0xff)
1831 + ((value >> 24) & 0xff);
1832 checksum &= 0xff;
1833 checksum = 0x100 - checksum;
1834
1835 value |= checksum << PMC_SCRATCH55_CHECKSUM_SHIFT;
1836
1837 tegra_pmc_writel(pmc, value, PMC_SCRATCH55);
1838
1839 value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL);
1840 value |= PMC_SENSOR_CTRL_ENABLE_RST;
1841 tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL);
1842
1843 dev_info(pmc->dev, "emergency thermal reset enabled\n");
1844
1845 out:
1846 of_node_put(np);
1847 }
1848
tegra_io_pad_pinctrl_get_groups_count(struct pinctrl_dev * pctl_dev)1849 static int tegra_io_pad_pinctrl_get_groups_count(struct pinctrl_dev *pctl_dev)
1850 {
1851 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
1852
1853 return pmc->soc->num_io_pads;
1854 }
1855
tegra_io_pad_pinctrl_get_group_name(struct pinctrl_dev * pctl,unsigned int group)1856 static const char *tegra_io_pad_pinctrl_get_group_name(struct pinctrl_dev *pctl,
1857 unsigned int group)
1858 {
1859 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl);
1860
1861 return pmc->soc->io_pads[group].name;
1862 }
1863
tegra_io_pad_pinctrl_get_group_pins(struct pinctrl_dev * pctl_dev,unsigned int group,const unsigned int ** pins,unsigned int * num_pins)1864 static int tegra_io_pad_pinctrl_get_group_pins(struct pinctrl_dev *pctl_dev,
1865 unsigned int group,
1866 const unsigned int **pins,
1867 unsigned int *num_pins)
1868 {
1869 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
1870
1871 *pins = &pmc->soc->io_pads[group].id;
1872 *num_pins = 1;
1873
1874 return 0;
1875 }
1876
1877 static const struct pinctrl_ops tegra_io_pad_pinctrl_ops = {
1878 .get_groups_count = tegra_io_pad_pinctrl_get_groups_count,
1879 .get_group_name = tegra_io_pad_pinctrl_get_group_name,
1880 .get_group_pins = tegra_io_pad_pinctrl_get_group_pins,
1881 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
1882 .dt_free_map = pinconf_generic_dt_free_map,
1883 };
1884
tegra_io_pad_pinconf_get(struct pinctrl_dev * pctl_dev,unsigned int pin,unsigned long * config)1885 static int tegra_io_pad_pinconf_get(struct pinctrl_dev *pctl_dev,
1886 unsigned int pin, unsigned long *config)
1887 {
1888 enum pin_config_param param = pinconf_to_config_param(*config);
1889 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
1890 const struct tegra_io_pad_soc *pad;
1891 int ret;
1892 u32 arg;
1893
1894 pad = tegra_io_pad_find(pmc, pin);
1895 if (!pad)
1896 return -EINVAL;
1897
1898 switch (param) {
1899 case PIN_CONFIG_POWER_SOURCE:
1900 ret = tegra_io_pad_get_voltage(pmc, pad->id);
1901 if (ret < 0)
1902 return ret;
1903
1904 arg = ret;
1905 break;
1906
1907 case PIN_CONFIG_MODE_LOW_POWER:
1908 ret = tegra_io_pad_is_powered(pmc, pad->id);
1909 if (ret < 0)
1910 return ret;
1911
1912 arg = !ret;
1913 break;
1914
1915 default:
1916 return -EINVAL;
1917 }
1918
1919 *config = pinconf_to_config_packed(param, arg);
1920
1921 return 0;
1922 }
1923
tegra_io_pad_pinconf_set(struct pinctrl_dev * pctl_dev,unsigned int pin,unsigned long * configs,unsigned int num_configs)1924 static int tegra_io_pad_pinconf_set(struct pinctrl_dev *pctl_dev,
1925 unsigned int pin, unsigned long *configs,
1926 unsigned int num_configs)
1927 {
1928 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
1929 const struct tegra_io_pad_soc *pad;
1930 enum pin_config_param param;
1931 unsigned int i;
1932 int err;
1933 u32 arg;
1934
1935 pad = tegra_io_pad_find(pmc, pin);
1936 if (!pad)
1937 return -EINVAL;
1938
1939 for (i = 0; i < num_configs; ++i) {
1940 param = pinconf_to_config_param(configs[i]);
1941 arg = pinconf_to_config_argument(configs[i]);
1942
1943 switch (param) {
1944 case PIN_CONFIG_MODE_LOW_POWER:
1945 if (arg)
1946 err = tegra_io_pad_power_disable(pad->id);
1947 else
1948 err = tegra_io_pad_power_enable(pad->id);
1949 if (err)
1950 return err;
1951 break;
1952 case PIN_CONFIG_POWER_SOURCE:
1953 if (arg != TEGRA_IO_PAD_VOLTAGE_1V8 &&
1954 arg != TEGRA_IO_PAD_VOLTAGE_3V3)
1955 return -EINVAL;
1956 err = tegra_io_pad_set_voltage(pmc, pad->id, arg);
1957 if (err)
1958 return err;
1959 break;
1960 default:
1961 return -EINVAL;
1962 }
1963 }
1964
1965 return 0;
1966 }
1967
1968 static const struct pinconf_ops tegra_io_pad_pinconf_ops = {
1969 .pin_config_get = tegra_io_pad_pinconf_get,
1970 .pin_config_set = tegra_io_pad_pinconf_set,
1971 .is_generic = true,
1972 };
1973
1974 static struct pinctrl_desc tegra_pmc_pctl_desc = {
1975 .pctlops = &tegra_io_pad_pinctrl_ops,
1976 .confops = &tegra_io_pad_pinconf_ops,
1977 };
1978
tegra_pmc_pinctrl_init(struct tegra_pmc * pmc)1979 static int tegra_pmc_pinctrl_init(struct tegra_pmc *pmc)
1980 {
1981 int err;
1982
1983 if (!pmc->soc->num_pin_descs)
1984 return 0;
1985
1986 tegra_pmc_pctl_desc.name = dev_name(pmc->dev);
1987 tegra_pmc_pctl_desc.pins = pmc->soc->pin_descs;
1988 tegra_pmc_pctl_desc.npins = pmc->soc->num_pin_descs;
1989
1990 pmc->pctl_dev = devm_pinctrl_register(pmc->dev, &tegra_pmc_pctl_desc,
1991 pmc);
1992 if (IS_ERR(pmc->pctl_dev)) {
1993 err = PTR_ERR(pmc->pctl_dev);
1994 dev_err(pmc->dev, "failed to register pin controller: %d\n",
1995 err);
1996 return err;
1997 }
1998
1999 return 0;
2000 }
2001
reset_reason_show(struct device * dev,struct device_attribute * attr,char * buf)2002 static ssize_t reset_reason_show(struct device *dev,
2003 struct device_attribute *attr, char *buf)
2004 {
2005 u32 value;
2006
2007 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status);
2008 value &= pmc->soc->regs->rst_source_mask;
2009 value >>= pmc->soc->regs->rst_source_shift;
2010
2011 if (WARN_ON(value >= pmc->soc->num_reset_sources))
2012 return sprintf(buf, "%s\n", "UNKNOWN");
2013
2014 return sprintf(buf, "%s\n", pmc->soc->reset_sources[value]);
2015 }
2016
2017 static DEVICE_ATTR_RO(reset_reason);
2018
reset_level_show(struct device * dev,struct device_attribute * attr,char * buf)2019 static ssize_t reset_level_show(struct device *dev,
2020 struct device_attribute *attr, char *buf)
2021 {
2022 u32 value;
2023
2024 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status);
2025 value &= pmc->soc->regs->rst_level_mask;
2026 value >>= pmc->soc->regs->rst_level_shift;
2027
2028 if (WARN_ON(value >= pmc->soc->num_reset_levels))
2029 return sprintf(buf, "%s\n", "UNKNOWN");
2030
2031 return sprintf(buf, "%s\n", pmc->soc->reset_levels[value]);
2032 }
2033
2034 static DEVICE_ATTR_RO(reset_level);
2035
tegra_pmc_reset_sysfs_init(struct tegra_pmc * pmc)2036 static void tegra_pmc_reset_sysfs_init(struct tegra_pmc *pmc)
2037 {
2038 struct device *dev = pmc->dev;
2039 int err = 0;
2040
2041 if (pmc->soc->reset_sources) {
2042 err = device_create_file(dev, &dev_attr_reset_reason);
2043 if (err < 0)
2044 dev_warn(dev,
2045 "failed to create attr \"reset_reason\": %d\n",
2046 err);
2047 }
2048
2049 if (pmc->soc->reset_levels) {
2050 err = device_create_file(dev, &dev_attr_reset_level);
2051 if (err < 0)
2052 dev_warn(dev,
2053 "failed to create attr \"reset_level\": %d\n",
2054 err);
2055 }
2056 }
2057
tegra_pmc_irq_translate(struct irq_domain * domain,struct irq_fwspec * fwspec,unsigned long * hwirq,unsigned int * type)2058 static int tegra_pmc_irq_translate(struct irq_domain *domain,
2059 struct irq_fwspec *fwspec,
2060 unsigned long *hwirq,
2061 unsigned int *type)
2062 {
2063 if (WARN_ON(fwspec->param_count < 2))
2064 return -EINVAL;
2065
2066 *hwirq = fwspec->param[0];
2067 *type = fwspec->param[1];
2068
2069 return 0;
2070 }
2071
tegra_pmc_irq_alloc(struct irq_domain * domain,unsigned int virq,unsigned int num_irqs,void * data)2072 static int tegra_pmc_irq_alloc(struct irq_domain *domain, unsigned int virq,
2073 unsigned int num_irqs, void *data)
2074 {
2075 struct tegra_pmc *pmc = domain->host_data;
2076 const struct tegra_pmc_soc *soc = pmc->soc;
2077 struct irq_fwspec *fwspec = data;
2078 unsigned int i;
2079 int err = 0;
2080
2081 if (WARN_ON(num_irqs > 1))
2082 return -EINVAL;
2083
2084 for (i = 0; i < soc->num_wake_events; i++) {
2085 const struct tegra_wake_event *event = &soc->wake_events[i];
2086
2087 if (fwspec->param_count == 2) {
2088 struct irq_fwspec spec;
2089
2090 if (event->id != fwspec->param[0])
2091 continue;
2092
2093 err = irq_domain_set_hwirq_and_chip(domain, virq,
2094 event->id,
2095 &pmc->irq, pmc);
2096 if (err < 0)
2097 break;
2098
2099 spec.fwnode = &pmc->dev->of_node->fwnode;
2100 spec.param_count = 3;
2101 spec.param[0] = GIC_SPI;
2102 spec.param[1] = event->irq;
2103 spec.param[2] = fwspec->param[1];
2104
2105 err = irq_domain_alloc_irqs_parent(domain, virq,
2106 num_irqs, &spec);
2107
2108 break;
2109 }
2110
2111 if (fwspec->param_count == 3) {
2112 if (event->gpio.instance != fwspec->param[0] ||
2113 event->gpio.pin != fwspec->param[1])
2114 continue;
2115
2116 err = irq_domain_set_hwirq_and_chip(domain, virq,
2117 event->id,
2118 &pmc->irq, pmc);
2119
2120 /* GPIO hierarchies stop at the PMC level */
2121 if (!err && domain->parent)
2122 err = irq_domain_disconnect_hierarchy(domain->parent,
2123 virq);
2124 break;
2125 }
2126 }
2127
2128 /* If there is no wake-up event, there is no PMC mapping */
2129 if (i == soc->num_wake_events)
2130 err = irq_domain_disconnect_hierarchy(domain, virq);
2131
2132 return err;
2133 }
2134
2135 static const struct irq_domain_ops tegra_pmc_irq_domain_ops = {
2136 .translate = tegra_pmc_irq_translate,
2137 .alloc = tegra_pmc_irq_alloc,
2138 };
2139
tegra210_pmc_irq_set_wake(struct irq_data * data,unsigned int on)2140 static int tegra210_pmc_irq_set_wake(struct irq_data *data, unsigned int on)
2141 {
2142 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
2143 unsigned int offset, bit;
2144 u32 value;
2145
2146 offset = data->hwirq / 32;
2147 bit = data->hwirq % 32;
2148
2149 /* clear wake status */
2150 tegra_pmc_writel(pmc, 0, PMC_SW_WAKE_STATUS);
2151 tegra_pmc_writel(pmc, 0, PMC_SW_WAKE2_STATUS);
2152
2153 tegra_pmc_writel(pmc, 0, PMC_WAKE_STATUS);
2154 tegra_pmc_writel(pmc, 0, PMC_WAKE2_STATUS);
2155
2156 /* enable PMC wake */
2157 if (data->hwirq >= 32)
2158 offset = PMC_WAKE2_MASK;
2159 else
2160 offset = PMC_WAKE_MASK;
2161
2162 value = tegra_pmc_readl(pmc, offset);
2163
2164 if (on)
2165 value |= BIT(bit);
2166 else
2167 value &= ~BIT(bit);
2168
2169 tegra_pmc_writel(pmc, value, offset);
2170
2171 return 0;
2172 }
2173
tegra210_pmc_irq_set_type(struct irq_data * data,unsigned int type)2174 static int tegra210_pmc_irq_set_type(struct irq_data *data, unsigned int type)
2175 {
2176 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
2177 unsigned int offset, bit;
2178 u32 value;
2179
2180 offset = data->hwirq / 32;
2181 bit = data->hwirq % 32;
2182
2183 if (data->hwirq >= 32)
2184 offset = PMC_WAKE2_LEVEL;
2185 else
2186 offset = PMC_WAKE_LEVEL;
2187
2188 value = tegra_pmc_readl(pmc, offset);
2189
2190 switch (type) {
2191 case IRQ_TYPE_EDGE_RISING:
2192 case IRQ_TYPE_LEVEL_HIGH:
2193 value |= BIT(bit);
2194 break;
2195
2196 case IRQ_TYPE_EDGE_FALLING:
2197 case IRQ_TYPE_LEVEL_LOW:
2198 value &= ~BIT(bit);
2199 break;
2200
2201 case IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING:
2202 value ^= BIT(bit);
2203 break;
2204
2205 default:
2206 return -EINVAL;
2207 }
2208
2209 tegra_pmc_writel(pmc, value, offset);
2210
2211 return 0;
2212 }
2213
tegra186_pmc_irq_set_wake(struct irq_data * data,unsigned int on)2214 static int tegra186_pmc_irq_set_wake(struct irq_data *data, unsigned int on)
2215 {
2216 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
2217 unsigned int offset, bit;
2218 u32 value;
2219
2220 offset = data->hwirq / 32;
2221 bit = data->hwirq % 32;
2222
2223 /* clear wake status */
2224 writel(0x1, pmc->wake + WAKE_AOWAKE_STATUS_W(data->hwirq));
2225
2226 /* route wake to tier 2 */
2227 value = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset));
2228
2229 if (!on)
2230 value &= ~(1 << bit);
2231 else
2232 value |= 1 << bit;
2233
2234 writel(value, pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset));
2235
2236 /* enable wakeup event */
2237 writel(!!on, pmc->wake + WAKE_AOWAKE_MASK_W(data->hwirq));
2238
2239 return 0;
2240 }
2241
tegra186_pmc_irq_set_type(struct irq_data * data,unsigned int type)2242 static int tegra186_pmc_irq_set_type(struct irq_data *data, unsigned int type)
2243 {
2244 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
2245 u32 value;
2246
2247 value = readl(pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq));
2248
2249 switch (type) {
2250 case IRQ_TYPE_EDGE_RISING:
2251 case IRQ_TYPE_LEVEL_HIGH:
2252 value |= WAKE_AOWAKE_CNTRL_LEVEL;
2253 break;
2254
2255 case IRQ_TYPE_EDGE_FALLING:
2256 case IRQ_TYPE_LEVEL_LOW:
2257 value &= ~WAKE_AOWAKE_CNTRL_LEVEL;
2258 break;
2259
2260 case IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING:
2261 value ^= WAKE_AOWAKE_CNTRL_LEVEL;
2262 break;
2263
2264 default:
2265 return -EINVAL;
2266 }
2267
2268 writel(value, pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq));
2269
2270 return 0;
2271 }
2272
tegra_irq_mask_parent(struct irq_data * data)2273 static void tegra_irq_mask_parent(struct irq_data *data)
2274 {
2275 if (data->parent_data)
2276 irq_chip_mask_parent(data);
2277 }
2278
tegra_irq_unmask_parent(struct irq_data * data)2279 static void tegra_irq_unmask_parent(struct irq_data *data)
2280 {
2281 if (data->parent_data)
2282 irq_chip_unmask_parent(data);
2283 }
2284
tegra_irq_eoi_parent(struct irq_data * data)2285 static void tegra_irq_eoi_parent(struct irq_data *data)
2286 {
2287 if (data->parent_data)
2288 irq_chip_eoi_parent(data);
2289 }
2290
tegra_irq_set_affinity_parent(struct irq_data * data,const struct cpumask * dest,bool force)2291 static int tegra_irq_set_affinity_parent(struct irq_data *data,
2292 const struct cpumask *dest,
2293 bool force)
2294 {
2295 if (data->parent_data)
2296 return irq_chip_set_affinity_parent(data, dest, force);
2297
2298 return -EINVAL;
2299 }
2300
tegra_pmc_irq_init(struct tegra_pmc * pmc)2301 static int tegra_pmc_irq_init(struct tegra_pmc *pmc)
2302 {
2303 struct irq_domain *parent = NULL;
2304 struct device_node *np;
2305
2306 np = of_irq_find_parent(pmc->dev->of_node);
2307 if (np) {
2308 parent = irq_find_host(np);
2309 of_node_put(np);
2310 }
2311
2312 if (!parent)
2313 return 0;
2314
2315 pmc->irq.name = dev_name(pmc->dev);
2316 pmc->irq.irq_mask = tegra_irq_mask_parent;
2317 pmc->irq.irq_unmask = tegra_irq_unmask_parent;
2318 pmc->irq.irq_eoi = tegra_irq_eoi_parent;
2319 pmc->irq.irq_set_affinity = tegra_irq_set_affinity_parent;
2320 pmc->irq.irq_set_type = pmc->soc->irq_set_type;
2321 pmc->irq.irq_set_wake = pmc->soc->irq_set_wake;
2322
2323 pmc->domain = irq_domain_add_hierarchy(parent, 0, 96, pmc->dev->of_node,
2324 &tegra_pmc_irq_domain_ops, pmc);
2325 if (!pmc->domain) {
2326 dev_err(pmc->dev, "failed to allocate domain\n");
2327 return -ENOMEM;
2328 }
2329
2330 return 0;
2331 }
2332
tegra_pmc_clk_notify_cb(struct notifier_block * nb,unsigned long action,void * ptr)2333 static int tegra_pmc_clk_notify_cb(struct notifier_block *nb,
2334 unsigned long action, void *ptr)
2335 {
2336 struct tegra_pmc *pmc = container_of(nb, struct tegra_pmc, clk_nb);
2337 struct clk_notifier_data *data = ptr;
2338
2339 switch (action) {
2340 case PRE_RATE_CHANGE:
2341 mutex_lock(&pmc->powergates_lock);
2342 break;
2343
2344 case POST_RATE_CHANGE:
2345 pmc->rate = data->new_rate;
2346 fallthrough;
2347
2348 case ABORT_RATE_CHANGE:
2349 mutex_unlock(&pmc->powergates_lock);
2350 break;
2351
2352 default:
2353 WARN_ON_ONCE(1);
2354 return notifier_from_errno(-EINVAL);
2355 }
2356
2357 return NOTIFY_OK;
2358 }
2359
pmc_clk_fence_udelay(u32 offset)2360 static void pmc_clk_fence_udelay(u32 offset)
2361 {
2362 tegra_pmc_readl(pmc, offset);
2363 /* pmc clk propagation delay 2 us */
2364 udelay(2);
2365 }
2366
pmc_clk_mux_get_parent(struct clk_hw * hw)2367 static u8 pmc_clk_mux_get_parent(struct clk_hw *hw)
2368 {
2369 struct pmc_clk *clk = to_pmc_clk(hw);
2370 u32 val;
2371
2372 val = tegra_pmc_readl(pmc, clk->offs) >> clk->mux_shift;
2373 val &= PMC_CLK_OUT_MUX_MASK;
2374
2375 return val;
2376 }
2377
pmc_clk_mux_set_parent(struct clk_hw * hw,u8 index)2378 static int pmc_clk_mux_set_parent(struct clk_hw *hw, u8 index)
2379 {
2380 struct pmc_clk *clk = to_pmc_clk(hw);
2381 u32 val;
2382
2383 val = tegra_pmc_readl(pmc, clk->offs);
2384 val &= ~(PMC_CLK_OUT_MUX_MASK << clk->mux_shift);
2385 val |= index << clk->mux_shift;
2386 tegra_pmc_writel(pmc, val, clk->offs);
2387 pmc_clk_fence_udelay(clk->offs);
2388
2389 return 0;
2390 }
2391
pmc_clk_is_enabled(struct clk_hw * hw)2392 static int pmc_clk_is_enabled(struct clk_hw *hw)
2393 {
2394 struct pmc_clk *clk = to_pmc_clk(hw);
2395 u32 val;
2396
2397 val = tegra_pmc_readl(pmc, clk->offs) & BIT(clk->force_en_shift);
2398
2399 return val ? 1 : 0;
2400 }
2401
pmc_clk_set_state(unsigned long offs,u32 shift,int state)2402 static void pmc_clk_set_state(unsigned long offs, u32 shift, int state)
2403 {
2404 u32 val;
2405
2406 val = tegra_pmc_readl(pmc, offs);
2407 val = state ? (val | BIT(shift)) : (val & ~BIT(shift));
2408 tegra_pmc_writel(pmc, val, offs);
2409 pmc_clk_fence_udelay(offs);
2410 }
2411
pmc_clk_enable(struct clk_hw * hw)2412 static int pmc_clk_enable(struct clk_hw *hw)
2413 {
2414 struct pmc_clk *clk = to_pmc_clk(hw);
2415
2416 pmc_clk_set_state(clk->offs, clk->force_en_shift, 1);
2417
2418 return 0;
2419 }
2420
pmc_clk_disable(struct clk_hw * hw)2421 static void pmc_clk_disable(struct clk_hw *hw)
2422 {
2423 struct pmc_clk *clk = to_pmc_clk(hw);
2424
2425 pmc_clk_set_state(clk->offs, clk->force_en_shift, 0);
2426 }
2427
2428 static const struct clk_ops pmc_clk_ops = {
2429 .get_parent = pmc_clk_mux_get_parent,
2430 .set_parent = pmc_clk_mux_set_parent,
2431 .determine_rate = __clk_mux_determine_rate,
2432 .is_enabled = pmc_clk_is_enabled,
2433 .enable = pmc_clk_enable,
2434 .disable = pmc_clk_disable,
2435 };
2436
2437 static struct clk *
tegra_pmc_clk_out_register(struct tegra_pmc * pmc,const struct pmc_clk_init_data * data,unsigned long offset)2438 tegra_pmc_clk_out_register(struct tegra_pmc *pmc,
2439 const struct pmc_clk_init_data *data,
2440 unsigned long offset)
2441 {
2442 struct clk_init_data init;
2443 struct pmc_clk *pmc_clk;
2444
2445 pmc_clk = devm_kzalloc(pmc->dev, sizeof(*pmc_clk), GFP_KERNEL);
2446 if (!pmc_clk)
2447 return ERR_PTR(-ENOMEM);
2448
2449 init.name = data->name;
2450 init.ops = &pmc_clk_ops;
2451 init.parent_names = data->parents;
2452 init.num_parents = data->num_parents;
2453 init.flags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT |
2454 CLK_SET_PARENT_GATE;
2455
2456 pmc_clk->hw.init = &init;
2457 pmc_clk->offs = offset;
2458 pmc_clk->mux_shift = data->mux_shift;
2459 pmc_clk->force_en_shift = data->force_en_shift;
2460
2461 return clk_register(NULL, &pmc_clk->hw);
2462 }
2463
pmc_clk_gate_is_enabled(struct clk_hw * hw)2464 static int pmc_clk_gate_is_enabled(struct clk_hw *hw)
2465 {
2466 struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
2467
2468 return tegra_pmc_readl(pmc, gate->offs) & BIT(gate->shift) ? 1 : 0;
2469 }
2470
pmc_clk_gate_enable(struct clk_hw * hw)2471 static int pmc_clk_gate_enable(struct clk_hw *hw)
2472 {
2473 struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
2474
2475 pmc_clk_set_state(gate->offs, gate->shift, 1);
2476
2477 return 0;
2478 }
2479
pmc_clk_gate_disable(struct clk_hw * hw)2480 static void pmc_clk_gate_disable(struct clk_hw *hw)
2481 {
2482 struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
2483
2484 pmc_clk_set_state(gate->offs, gate->shift, 0);
2485 }
2486
2487 static const struct clk_ops pmc_clk_gate_ops = {
2488 .is_enabled = pmc_clk_gate_is_enabled,
2489 .enable = pmc_clk_gate_enable,
2490 .disable = pmc_clk_gate_disable,
2491 };
2492
2493 static struct clk *
tegra_pmc_clk_gate_register(struct tegra_pmc * pmc,const char * name,const char * parent_name,unsigned long offset,u32 shift)2494 tegra_pmc_clk_gate_register(struct tegra_pmc *pmc, const char *name,
2495 const char *parent_name, unsigned long offset,
2496 u32 shift)
2497 {
2498 struct clk_init_data init;
2499 struct pmc_clk_gate *gate;
2500
2501 gate = devm_kzalloc(pmc->dev, sizeof(*gate), GFP_KERNEL);
2502 if (!gate)
2503 return ERR_PTR(-ENOMEM);
2504
2505 init.name = name;
2506 init.ops = &pmc_clk_gate_ops;
2507 init.parent_names = &parent_name;
2508 init.num_parents = 1;
2509 init.flags = 0;
2510
2511 gate->hw.init = &init;
2512 gate->offs = offset;
2513 gate->shift = shift;
2514
2515 return clk_register(NULL, &gate->hw);
2516 }
2517
tegra_pmc_clock_register(struct tegra_pmc * pmc,struct device_node * np)2518 static void tegra_pmc_clock_register(struct tegra_pmc *pmc,
2519 struct device_node *np)
2520 {
2521 struct clk *clk;
2522 struct clk_onecell_data *clk_data;
2523 unsigned int num_clks;
2524 int i, err;
2525
2526 num_clks = pmc->soc->num_pmc_clks;
2527 if (pmc->soc->has_blink_output)
2528 num_clks += 1;
2529
2530 if (!num_clks)
2531 return;
2532
2533 clk_data = devm_kmalloc(pmc->dev, sizeof(*clk_data), GFP_KERNEL);
2534 if (!clk_data)
2535 return;
2536
2537 clk_data->clks = devm_kcalloc(pmc->dev, TEGRA_PMC_CLK_MAX,
2538 sizeof(*clk_data->clks), GFP_KERNEL);
2539 if (!clk_data->clks)
2540 return;
2541
2542 clk_data->clk_num = TEGRA_PMC_CLK_MAX;
2543
2544 for (i = 0; i < TEGRA_PMC_CLK_MAX; i++)
2545 clk_data->clks[i] = ERR_PTR(-ENOENT);
2546
2547 for (i = 0; i < pmc->soc->num_pmc_clks; i++) {
2548 const struct pmc_clk_init_data *data;
2549
2550 data = pmc->soc->pmc_clks_data + i;
2551
2552 clk = tegra_pmc_clk_out_register(pmc, data, PMC_CLK_OUT_CNTRL);
2553 if (IS_ERR(clk)) {
2554 dev_warn(pmc->dev, "unable to register clock %s: %d\n",
2555 data->name, PTR_ERR_OR_ZERO(clk));
2556 return;
2557 }
2558
2559 err = clk_register_clkdev(clk, data->name, NULL);
2560 if (err) {
2561 dev_warn(pmc->dev,
2562 "unable to register %s clock lookup: %d\n",
2563 data->name, err);
2564 return;
2565 }
2566
2567 clk_data->clks[data->clk_id] = clk;
2568 }
2569
2570 if (pmc->soc->has_blink_output) {
2571 tegra_pmc_writel(pmc, 0x0, PMC_BLINK_TIMER);
2572 clk = tegra_pmc_clk_gate_register(pmc,
2573 "pmc_blink_override",
2574 "clk_32k",
2575 PMC_DPD_PADS_ORIDE,
2576 PMC_DPD_PADS_ORIDE_BLINK);
2577 if (IS_ERR(clk)) {
2578 dev_warn(pmc->dev,
2579 "unable to register pmc_blink_override: %d\n",
2580 PTR_ERR_OR_ZERO(clk));
2581 return;
2582 }
2583
2584 clk = tegra_pmc_clk_gate_register(pmc, "pmc_blink",
2585 "pmc_blink_override",
2586 PMC_CNTRL,
2587 PMC_CNTRL_BLINK_EN);
2588 if (IS_ERR(clk)) {
2589 dev_warn(pmc->dev,
2590 "unable to register pmc_blink: %d\n",
2591 PTR_ERR_OR_ZERO(clk));
2592 return;
2593 }
2594
2595 err = clk_register_clkdev(clk, "pmc_blink", NULL);
2596 if (err) {
2597 dev_warn(pmc->dev,
2598 "unable to register pmc_blink lookup: %d\n",
2599 err);
2600 return;
2601 }
2602
2603 clk_data->clks[TEGRA_PMC_CLK_BLINK] = clk;
2604 }
2605
2606 err = of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
2607 if (err)
2608 dev_warn(pmc->dev, "failed to add pmc clock provider: %d\n",
2609 err);
2610 }
2611
2612 static const struct regmap_range pmc_usb_sleepwalk_ranges[] = {
2613 regmap_reg_range(PMC_USB_DEBOUNCE_DEL, PMC_USB_AO),
2614 regmap_reg_range(PMC_UTMIP_UHSIC_TRIGGERS, PMC_UTMIP_UHSIC_SAVED_STATE),
2615 regmap_reg_range(PMC_UTMIP_TERM_PAD_CFG, PMC_UTMIP_UHSIC_FAKE),
2616 regmap_reg_range(PMC_UTMIP_UHSIC_LINE_WAKEUP, PMC_UTMIP_UHSIC_LINE_WAKEUP),
2617 regmap_reg_range(PMC_UTMIP_BIAS_MASTER_CNTRL, PMC_UTMIP_MASTER_CONFIG),
2618 regmap_reg_range(PMC_UTMIP_UHSIC2_TRIGGERS, PMC_UTMIP_MASTER2_CONFIG),
2619 regmap_reg_range(PMC_UTMIP_PAD_CFG0, PMC_UTMIP_UHSIC_SLEEP_CFG1),
2620 regmap_reg_range(PMC_UTMIP_SLEEPWALK_P3, PMC_UTMIP_SLEEPWALK_P3),
2621 };
2622
2623 static const struct regmap_access_table pmc_usb_sleepwalk_table = {
2624 .yes_ranges = pmc_usb_sleepwalk_ranges,
2625 .n_yes_ranges = ARRAY_SIZE(pmc_usb_sleepwalk_ranges),
2626 };
2627
tegra_pmc_regmap_readl(void * context,unsigned int offset,unsigned int * value)2628 static int tegra_pmc_regmap_readl(void *context, unsigned int offset, unsigned int *value)
2629 {
2630 struct tegra_pmc *pmc = context;
2631
2632 *value = tegra_pmc_readl(pmc, offset);
2633 return 0;
2634 }
2635
tegra_pmc_regmap_writel(void * context,unsigned int offset,unsigned int value)2636 static int tegra_pmc_regmap_writel(void *context, unsigned int offset, unsigned int value)
2637 {
2638 struct tegra_pmc *pmc = context;
2639
2640 tegra_pmc_writel(pmc, value, offset);
2641 return 0;
2642 }
2643
2644 static const struct regmap_config usb_sleepwalk_regmap_config = {
2645 .name = "usb_sleepwalk",
2646 .reg_bits = 32,
2647 .val_bits = 32,
2648 .reg_stride = 4,
2649 .fast_io = true,
2650 .rd_table = &pmc_usb_sleepwalk_table,
2651 .wr_table = &pmc_usb_sleepwalk_table,
2652 .reg_read = tegra_pmc_regmap_readl,
2653 .reg_write = tegra_pmc_regmap_writel,
2654 };
2655
tegra_pmc_regmap_init(struct tegra_pmc * pmc)2656 static int tegra_pmc_regmap_init(struct tegra_pmc *pmc)
2657 {
2658 struct regmap *regmap;
2659 int err;
2660
2661 if (pmc->soc->has_usb_sleepwalk) {
2662 regmap = devm_regmap_init(pmc->dev, NULL, pmc, &usb_sleepwalk_regmap_config);
2663 if (IS_ERR(regmap)) {
2664 err = PTR_ERR(regmap);
2665 dev_err(pmc->dev, "failed to allocate register map (%d)\n", err);
2666 return err;
2667 }
2668 }
2669
2670 return 0;
2671 }
2672
tegra_pmc_probe(struct platform_device * pdev)2673 static int tegra_pmc_probe(struct platform_device *pdev)
2674 {
2675 void __iomem *base;
2676 struct resource *res;
2677 int err;
2678
2679 /*
2680 * Early initialisation should have configured an initial
2681 * register mapping and setup the soc data pointer. If these
2682 * are not valid then something went badly wrong!
2683 */
2684 if (WARN_ON(!pmc->base || !pmc->soc))
2685 return -ENODEV;
2686
2687 err = tegra_pmc_parse_dt(pmc, pdev->dev.of_node);
2688 if (err < 0)
2689 return err;
2690
2691 /* take over the memory region from the early initialization */
2692 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2693 base = devm_ioremap_resource(&pdev->dev, res);
2694 if (IS_ERR(base))
2695 return PTR_ERR(base);
2696
2697 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "wake");
2698 if (res) {
2699 pmc->wake = devm_ioremap_resource(&pdev->dev, res);
2700 if (IS_ERR(pmc->wake))
2701 return PTR_ERR(pmc->wake);
2702 } else {
2703 pmc->wake = base;
2704 }
2705
2706 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "aotag");
2707 if (res) {
2708 pmc->aotag = devm_ioremap_resource(&pdev->dev, res);
2709 if (IS_ERR(pmc->aotag))
2710 return PTR_ERR(pmc->aotag);
2711 } else {
2712 pmc->aotag = base;
2713 }
2714
2715 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "scratch");
2716 if (res) {
2717 pmc->scratch = devm_ioremap_resource(&pdev->dev, res);
2718 if (IS_ERR(pmc->scratch))
2719 return PTR_ERR(pmc->scratch);
2720 } else {
2721 pmc->scratch = base;
2722 }
2723
2724 pmc->clk = devm_clk_get(&pdev->dev, "pclk");
2725 if (IS_ERR(pmc->clk)) {
2726 err = PTR_ERR(pmc->clk);
2727
2728 if (err != -ENOENT) {
2729 dev_err(&pdev->dev, "failed to get pclk: %d\n", err);
2730 return err;
2731 }
2732
2733 pmc->clk = NULL;
2734 }
2735
2736 /*
2737 * PCLK clock rate can't be retrieved using CLK API because it
2738 * causes lockup if CPU enters LP2 idle state from some other
2739 * CLK notifier, hence we're caching the rate's value locally.
2740 */
2741 if (pmc->clk) {
2742 pmc->clk_nb.notifier_call = tegra_pmc_clk_notify_cb;
2743 err = clk_notifier_register(pmc->clk, &pmc->clk_nb);
2744 if (err) {
2745 dev_err(&pdev->dev,
2746 "failed to register clk notifier\n");
2747 return err;
2748 }
2749
2750 pmc->rate = clk_get_rate(pmc->clk);
2751 }
2752
2753 pmc->dev = &pdev->dev;
2754
2755 tegra_pmc_init(pmc);
2756
2757 tegra_pmc_init_tsense_reset(pmc);
2758
2759 tegra_pmc_reset_sysfs_init(pmc);
2760
2761 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
2762 err = tegra_powergate_debugfs_init();
2763 if (err < 0)
2764 goto cleanup_sysfs;
2765 }
2766
2767 err = register_restart_handler(&tegra_pmc_restart_handler);
2768 if (err) {
2769 dev_err(&pdev->dev, "unable to register restart handler, %d\n",
2770 err);
2771 goto cleanup_debugfs;
2772 }
2773
2774 err = tegra_pmc_pinctrl_init(pmc);
2775 if (err)
2776 goto cleanup_restart_handler;
2777
2778 err = tegra_pmc_regmap_init(pmc);
2779 if (err < 0)
2780 goto cleanup_restart_handler;
2781
2782 err = tegra_powergate_init(pmc, pdev->dev.of_node);
2783 if (err < 0)
2784 goto cleanup_powergates;
2785
2786 err = tegra_pmc_irq_init(pmc);
2787 if (err < 0)
2788 goto cleanup_powergates;
2789
2790 mutex_lock(&pmc->powergates_lock);
2791 iounmap(pmc->base);
2792 pmc->base = base;
2793 mutex_unlock(&pmc->powergates_lock);
2794
2795 tegra_pmc_clock_register(pmc, pdev->dev.of_node);
2796 platform_set_drvdata(pdev, pmc);
2797
2798 return 0;
2799
2800 cleanup_powergates:
2801 tegra_powergate_remove_all(pdev->dev.of_node);
2802 cleanup_restart_handler:
2803 unregister_restart_handler(&tegra_pmc_restart_handler);
2804 cleanup_debugfs:
2805 debugfs_remove(pmc->debugfs);
2806 cleanup_sysfs:
2807 device_remove_file(&pdev->dev, &dev_attr_reset_reason);
2808 device_remove_file(&pdev->dev, &dev_attr_reset_level);
2809 clk_notifier_unregister(pmc->clk, &pmc->clk_nb);
2810
2811 return err;
2812 }
2813
2814 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM)
tegra_pmc_suspend(struct device * dev)2815 static int tegra_pmc_suspend(struct device *dev)
2816 {
2817 struct tegra_pmc *pmc = dev_get_drvdata(dev);
2818
2819 tegra_pmc_writel(pmc, virt_to_phys(tegra_resume), PMC_SCRATCH41);
2820
2821 return 0;
2822 }
2823
tegra_pmc_resume(struct device * dev)2824 static int tegra_pmc_resume(struct device *dev)
2825 {
2826 struct tegra_pmc *pmc = dev_get_drvdata(dev);
2827
2828 tegra_pmc_writel(pmc, 0x0, PMC_SCRATCH41);
2829
2830 return 0;
2831 }
2832
2833 static SIMPLE_DEV_PM_OPS(tegra_pmc_pm_ops, tegra_pmc_suspend, tegra_pmc_resume);
2834
2835 #endif
2836
2837 static const char * const tegra20_powergates[] = {
2838 [TEGRA_POWERGATE_CPU] = "cpu",
2839 [TEGRA_POWERGATE_3D] = "3d",
2840 [TEGRA_POWERGATE_VENC] = "venc",
2841 [TEGRA_POWERGATE_VDEC] = "vdec",
2842 [TEGRA_POWERGATE_PCIE] = "pcie",
2843 [TEGRA_POWERGATE_L2] = "l2",
2844 [TEGRA_POWERGATE_MPE] = "mpe",
2845 };
2846
2847 static const struct tegra_pmc_regs tegra20_pmc_regs = {
2848 .scratch0 = 0x50,
2849 .dpd_req = 0x1b8,
2850 .dpd_status = 0x1bc,
2851 .dpd2_req = 0x1c0,
2852 .dpd2_status = 0x1c4,
2853 .rst_status = 0x1b4,
2854 .rst_source_shift = 0x0,
2855 .rst_source_mask = 0x7,
2856 .rst_level_shift = 0x0,
2857 .rst_level_mask = 0x0,
2858 };
2859
tegra20_pmc_init(struct tegra_pmc * pmc)2860 static void tegra20_pmc_init(struct tegra_pmc *pmc)
2861 {
2862 u32 value, osc, pmu, off;
2863
2864 /* Always enable CPU power request */
2865 value = tegra_pmc_readl(pmc, PMC_CNTRL);
2866 value |= PMC_CNTRL_CPU_PWRREQ_OE;
2867 tegra_pmc_writel(pmc, value, PMC_CNTRL);
2868
2869 value = tegra_pmc_readl(pmc, PMC_CNTRL);
2870
2871 if (pmc->sysclkreq_high)
2872 value &= ~PMC_CNTRL_SYSCLK_POLARITY;
2873 else
2874 value |= PMC_CNTRL_SYSCLK_POLARITY;
2875
2876 if (pmc->corereq_high)
2877 value &= ~PMC_CNTRL_PWRREQ_POLARITY;
2878 else
2879 value |= PMC_CNTRL_PWRREQ_POLARITY;
2880
2881 /* configure the output polarity while the request is tristated */
2882 tegra_pmc_writel(pmc, value, PMC_CNTRL);
2883
2884 /* now enable the request */
2885 value = tegra_pmc_readl(pmc, PMC_CNTRL);
2886 value |= PMC_CNTRL_SYSCLK_OE;
2887 tegra_pmc_writel(pmc, value, PMC_CNTRL);
2888
2889 /* program core timings which are applicable only for suspend state */
2890 if (pmc->suspend_mode != TEGRA_SUSPEND_NONE) {
2891 osc = DIV_ROUND_UP(pmc->core_osc_time * 8192, 1000000);
2892 pmu = DIV_ROUND_UP(pmc->core_pmu_time * 32768, 1000000);
2893 off = DIV_ROUND_UP(pmc->core_off_time * 32768, 1000000);
2894 tegra_pmc_writel(pmc, ((osc << 8) & 0xff00) | (pmu & 0xff),
2895 PMC_COREPWRGOOD_TIMER);
2896 tegra_pmc_writel(pmc, off, PMC_COREPWROFF_TIMER);
2897 }
2898 }
2899
tegra20_pmc_setup_irq_polarity(struct tegra_pmc * pmc,struct device_node * np,bool invert)2900 static void tegra20_pmc_setup_irq_polarity(struct tegra_pmc *pmc,
2901 struct device_node *np,
2902 bool invert)
2903 {
2904 u32 value;
2905
2906 value = tegra_pmc_readl(pmc, PMC_CNTRL);
2907
2908 if (invert)
2909 value |= PMC_CNTRL_INTR_POLARITY;
2910 else
2911 value &= ~PMC_CNTRL_INTR_POLARITY;
2912
2913 tegra_pmc_writel(pmc, value, PMC_CNTRL);
2914 }
2915
2916 static const struct tegra_pmc_soc tegra20_pmc_soc = {
2917 .num_powergates = ARRAY_SIZE(tegra20_powergates),
2918 .powergates = tegra20_powergates,
2919 .num_cpu_powergates = 0,
2920 .cpu_powergates = NULL,
2921 .has_tsense_reset = false,
2922 .has_gpu_clamps = false,
2923 .needs_mbist_war = false,
2924 .has_impl_33v_pwr = false,
2925 .maybe_tz_only = false,
2926 .num_io_pads = 0,
2927 .io_pads = NULL,
2928 .num_pin_descs = 0,
2929 .pin_descs = NULL,
2930 .regs = &tegra20_pmc_regs,
2931 .init = tegra20_pmc_init,
2932 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
2933 .powergate_set = tegra20_powergate_set,
2934 .reset_sources = NULL,
2935 .num_reset_sources = 0,
2936 .reset_levels = NULL,
2937 .num_reset_levels = 0,
2938 .pmc_clks_data = NULL,
2939 .num_pmc_clks = 0,
2940 .has_blink_output = true,
2941 .has_usb_sleepwalk = false,
2942 };
2943
2944 static const char * const tegra30_powergates[] = {
2945 [TEGRA_POWERGATE_CPU] = "cpu0",
2946 [TEGRA_POWERGATE_3D] = "3d0",
2947 [TEGRA_POWERGATE_VENC] = "venc",
2948 [TEGRA_POWERGATE_VDEC] = "vdec",
2949 [TEGRA_POWERGATE_PCIE] = "pcie",
2950 [TEGRA_POWERGATE_L2] = "l2",
2951 [TEGRA_POWERGATE_MPE] = "mpe",
2952 [TEGRA_POWERGATE_HEG] = "heg",
2953 [TEGRA_POWERGATE_SATA] = "sata",
2954 [TEGRA_POWERGATE_CPU1] = "cpu1",
2955 [TEGRA_POWERGATE_CPU2] = "cpu2",
2956 [TEGRA_POWERGATE_CPU3] = "cpu3",
2957 [TEGRA_POWERGATE_CELP] = "celp",
2958 [TEGRA_POWERGATE_3D1] = "3d1",
2959 };
2960
2961 static const u8 tegra30_cpu_powergates[] = {
2962 TEGRA_POWERGATE_CPU,
2963 TEGRA_POWERGATE_CPU1,
2964 TEGRA_POWERGATE_CPU2,
2965 TEGRA_POWERGATE_CPU3,
2966 };
2967
2968 static const char * const tegra30_reset_sources[] = {
2969 "POWER_ON_RESET",
2970 "WATCHDOG",
2971 "SENSOR",
2972 "SW_MAIN",
2973 "LP0"
2974 };
2975
2976 static const struct tegra_pmc_soc tegra30_pmc_soc = {
2977 .num_powergates = ARRAY_SIZE(tegra30_powergates),
2978 .powergates = tegra30_powergates,
2979 .num_cpu_powergates = ARRAY_SIZE(tegra30_cpu_powergates),
2980 .cpu_powergates = tegra30_cpu_powergates,
2981 .has_tsense_reset = true,
2982 .has_gpu_clamps = false,
2983 .needs_mbist_war = false,
2984 .has_impl_33v_pwr = false,
2985 .maybe_tz_only = false,
2986 .num_io_pads = 0,
2987 .io_pads = NULL,
2988 .num_pin_descs = 0,
2989 .pin_descs = NULL,
2990 .regs = &tegra20_pmc_regs,
2991 .init = tegra20_pmc_init,
2992 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
2993 .powergate_set = tegra20_powergate_set,
2994 .reset_sources = tegra30_reset_sources,
2995 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources),
2996 .reset_levels = NULL,
2997 .num_reset_levels = 0,
2998 .pmc_clks_data = tegra_pmc_clks_data,
2999 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
3000 .has_blink_output = true,
3001 .has_usb_sleepwalk = false,
3002 };
3003
3004 static const char * const tegra114_powergates[] = {
3005 [TEGRA_POWERGATE_CPU] = "crail",
3006 [TEGRA_POWERGATE_3D] = "3d",
3007 [TEGRA_POWERGATE_VENC] = "venc",
3008 [TEGRA_POWERGATE_VDEC] = "vdec",
3009 [TEGRA_POWERGATE_MPE] = "mpe",
3010 [TEGRA_POWERGATE_HEG] = "heg",
3011 [TEGRA_POWERGATE_CPU1] = "cpu1",
3012 [TEGRA_POWERGATE_CPU2] = "cpu2",
3013 [TEGRA_POWERGATE_CPU3] = "cpu3",
3014 [TEGRA_POWERGATE_CELP] = "celp",
3015 [TEGRA_POWERGATE_CPU0] = "cpu0",
3016 [TEGRA_POWERGATE_C0NC] = "c0nc",
3017 [TEGRA_POWERGATE_C1NC] = "c1nc",
3018 [TEGRA_POWERGATE_DIS] = "dis",
3019 [TEGRA_POWERGATE_DISB] = "disb",
3020 [TEGRA_POWERGATE_XUSBA] = "xusba",
3021 [TEGRA_POWERGATE_XUSBB] = "xusbb",
3022 [TEGRA_POWERGATE_XUSBC] = "xusbc",
3023 };
3024
3025 static const u8 tegra114_cpu_powergates[] = {
3026 TEGRA_POWERGATE_CPU0,
3027 TEGRA_POWERGATE_CPU1,
3028 TEGRA_POWERGATE_CPU2,
3029 TEGRA_POWERGATE_CPU3,
3030 };
3031
3032 static const struct tegra_pmc_soc tegra114_pmc_soc = {
3033 .num_powergates = ARRAY_SIZE(tegra114_powergates),
3034 .powergates = tegra114_powergates,
3035 .num_cpu_powergates = ARRAY_SIZE(tegra114_cpu_powergates),
3036 .cpu_powergates = tegra114_cpu_powergates,
3037 .has_tsense_reset = true,
3038 .has_gpu_clamps = false,
3039 .needs_mbist_war = false,
3040 .has_impl_33v_pwr = false,
3041 .maybe_tz_only = false,
3042 .num_io_pads = 0,
3043 .io_pads = NULL,
3044 .num_pin_descs = 0,
3045 .pin_descs = NULL,
3046 .regs = &tegra20_pmc_regs,
3047 .init = tegra20_pmc_init,
3048 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
3049 .powergate_set = tegra114_powergate_set,
3050 .reset_sources = tegra30_reset_sources,
3051 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources),
3052 .reset_levels = NULL,
3053 .num_reset_levels = 0,
3054 .pmc_clks_data = tegra_pmc_clks_data,
3055 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
3056 .has_blink_output = true,
3057 .has_usb_sleepwalk = false,
3058 };
3059
3060 static const char * const tegra124_powergates[] = {
3061 [TEGRA_POWERGATE_CPU] = "crail",
3062 [TEGRA_POWERGATE_3D] = "3d",
3063 [TEGRA_POWERGATE_VENC] = "venc",
3064 [TEGRA_POWERGATE_PCIE] = "pcie",
3065 [TEGRA_POWERGATE_VDEC] = "vdec",
3066 [TEGRA_POWERGATE_MPE] = "mpe",
3067 [TEGRA_POWERGATE_HEG] = "heg",
3068 [TEGRA_POWERGATE_SATA] = "sata",
3069 [TEGRA_POWERGATE_CPU1] = "cpu1",
3070 [TEGRA_POWERGATE_CPU2] = "cpu2",
3071 [TEGRA_POWERGATE_CPU3] = "cpu3",
3072 [TEGRA_POWERGATE_CELP] = "celp",
3073 [TEGRA_POWERGATE_CPU0] = "cpu0",
3074 [TEGRA_POWERGATE_C0NC] = "c0nc",
3075 [TEGRA_POWERGATE_C1NC] = "c1nc",
3076 [TEGRA_POWERGATE_SOR] = "sor",
3077 [TEGRA_POWERGATE_DIS] = "dis",
3078 [TEGRA_POWERGATE_DISB] = "disb",
3079 [TEGRA_POWERGATE_XUSBA] = "xusba",
3080 [TEGRA_POWERGATE_XUSBB] = "xusbb",
3081 [TEGRA_POWERGATE_XUSBC] = "xusbc",
3082 [TEGRA_POWERGATE_VIC] = "vic",
3083 [TEGRA_POWERGATE_IRAM] = "iram",
3084 };
3085
3086 static const u8 tegra124_cpu_powergates[] = {
3087 TEGRA_POWERGATE_CPU0,
3088 TEGRA_POWERGATE_CPU1,
3089 TEGRA_POWERGATE_CPU2,
3090 TEGRA_POWERGATE_CPU3,
3091 };
3092
3093 #define TEGRA_IO_PAD(_id, _dpd, _voltage, _name) \
3094 ((struct tegra_io_pad_soc) { \
3095 .id = (_id), \
3096 .dpd = (_dpd), \
3097 .voltage = (_voltage), \
3098 .name = (_name), \
3099 })
3100
3101 #define TEGRA_IO_PIN_DESC(_id, _dpd, _voltage, _name) \
3102 ((struct pinctrl_pin_desc) { \
3103 .number = (_id), \
3104 .name = (_name) \
3105 })
3106
3107 #define TEGRA124_IO_PAD_TABLE(_pad) \
3108 /* .id .dpd .voltage .name */ \
3109 _pad(TEGRA_IO_PAD_AUDIO, 17, UINT_MAX, "audio"), \
3110 _pad(TEGRA_IO_PAD_BB, 15, UINT_MAX, "bb"), \
3111 _pad(TEGRA_IO_PAD_CAM, 36, UINT_MAX, "cam"), \
3112 _pad(TEGRA_IO_PAD_COMP, 22, UINT_MAX, "comp"), \
3113 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \
3114 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csb"), \
3115 _pad(TEGRA_IO_PAD_CSIE, 44, UINT_MAX, "cse"), \
3116 _pad(TEGRA_IO_PAD_DSI, 2, UINT_MAX, "dsi"), \
3117 _pad(TEGRA_IO_PAD_DSIB, 39, UINT_MAX, "dsib"), \
3118 _pad(TEGRA_IO_PAD_DSIC, 40, UINT_MAX, "dsic"), \
3119 _pad(TEGRA_IO_PAD_DSID, 41, UINT_MAX, "dsid"), \
3120 _pad(TEGRA_IO_PAD_HDMI, 28, UINT_MAX, "hdmi"), \
3121 _pad(TEGRA_IO_PAD_HSIC, 19, UINT_MAX, "hsic"), \
3122 _pad(TEGRA_IO_PAD_HV, 38, UINT_MAX, "hv"), \
3123 _pad(TEGRA_IO_PAD_LVDS, 57, UINT_MAX, "lvds"), \
3124 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \
3125 _pad(TEGRA_IO_PAD_NAND, 13, UINT_MAX, "nand"), \
3126 _pad(TEGRA_IO_PAD_PEX_BIAS, 4, UINT_MAX, "pex-bias"), \
3127 _pad(TEGRA_IO_PAD_PEX_CLK1, 5, UINT_MAX, "pex-clk1"), \
3128 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \
3129 _pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \
3130 _pad(TEGRA_IO_PAD_SDMMC1, 33, UINT_MAX, "sdmmc1"), \
3131 _pad(TEGRA_IO_PAD_SDMMC3, 34, UINT_MAX, "sdmmc3"), \
3132 _pad(TEGRA_IO_PAD_SDMMC4, 35, UINT_MAX, "sdmmc4"), \
3133 _pad(TEGRA_IO_PAD_SYS_DDC, 58, UINT_MAX, "sys_ddc"), \
3134 _pad(TEGRA_IO_PAD_UART, 14, UINT_MAX, "uart"), \
3135 _pad(TEGRA_IO_PAD_USB0, 9, UINT_MAX, "usb0"), \
3136 _pad(TEGRA_IO_PAD_USB1, 10, UINT_MAX, "usb1"), \
3137 _pad(TEGRA_IO_PAD_USB2, 11, UINT_MAX, "usb2"), \
3138 _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb_bias")
3139
3140 static const struct tegra_io_pad_soc tegra124_io_pads[] = {
3141 TEGRA124_IO_PAD_TABLE(TEGRA_IO_PAD)
3142 };
3143
3144 static const struct pinctrl_pin_desc tegra124_pin_descs[] = {
3145 TEGRA124_IO_PAD_TABLE(TEGRA_IO_PIN_DESC)
3146 };
3147
3148 static const struct tegra_pmc_soc tegra124_pmc_soc = {
3149 .num_powergates = ARRAY_SIZE(tegra124_powergates),
3150 .powergates = tegra124_powergates,
3151 .num_cpu_powergates = ARRAY_SIZE(tegra124_cpu_powergates),
3152 .cpu_powergates = tegra124_cpu_powergates,
3153 .has_tsense_reset = true,
3154 .has_gpu_clamps = true,
3155 .needs_mbist_war = false,
3156 .has_impl_33v_pwr = false,
3157 .maybe_tz_only = false,
3158 .num_io_pads = ARRAY_SIZE(tegra124_io_pads),
3159 .io_pads = tegra124_io_pads,
3160 .num_pin_descs = ARRAY_SIZE(tegra124_pin_descs),
3161 .pin_descs = tegra124_pin_descs,
3162 .regs = &tegra20_pmc_regs,
3163 .init = tegra20_pmc_init,
3164 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
3165 .powergate_set = tegra114_powergate_set,
3166 .reset_sources = tegra30_reset_sources,
3167 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources),
3168 .reset_levels = NULL,
3169 .num_reset_levels = 0,
3170 .pmc_clks_data = tegra_pmc_clks_data,
3171 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
3172 .has_blink_output = true,
3173 .has_usb_sleepwalk = true,
3174 };
3175
3176 static const char * const tegra210_powergates[] = {
3177 [TEGRA_POWERGATE_CPU] = "crail",
3178 [TEGRA_POWERGATE_3D] = "3d",
3179 [TEGRA_POWERGATE_VENC] = "venc",
3180 [TEGRA_POWERGATE_PCIE] = "pcie",
3181 [TEGRA_POWERGATE_MPE] = "mpe",
3182 [TEGRA_POWERGATE_SATA] = "sata",
3183 [TEGRA_POWERGATE_CPU1] = "cpu1",
3184 [TEGRA_POWERGATE_CPU2] = "cpu2",
3185 [TEGRA_POWERGATE_CPU3] = "cpu3",
3186 [TEGRA_POWERGATE_CPU0] = "cpu0",
3187 [TEGRA_POWERGATE_C0NC] = "c0nc",
3188 [TEGRA_POWERGATE_SOR] = "sor",
3189 [TEGRA_POWERGATE_DIS] = "dis",
3190 [TEGRA_POWERGATE_DISB] = "disb",
3191 [TEGRA_POWERGATE_XUSBA] = "xusba",
3192 [TEGRA_POWERGATE_XUSBB] = "xusbb",
3193 [TEGRA_POWERGATE_XUSBC] = "xusbc",
3194 [TEGRA_POWERGATE_VIC] = "vic",
3195 [TEGRA_POWERGATE_IRAM] = "iram",
3196 [TEGRA_POWERGATE_NVDEC] = "nvdec",
3197 [TEGRA_POWERGATE_NVJPG] = "nvjpg",
3198 [TEGRA_POWERGATE_AUD] = "aud",
3199 [TEGRA_POWERGATE_DFD] = "dfd",
3200 [TEGRA_POWERGATE_VE2] = "ve2",
3201 };
3202
3203 static const u8 tegra210_cpu_powergates[] = {
3204 TEGRA_POWERGATE_CPU0,
3205 TEGRA_POWERGATE_CPU1,
3206 TEGRA_POWERGATE_CPU2,
3207 TEGRA_POWERGATE_CPU3,
3208 };
3209
3210 #define TEGRA210_IO_PAD_TABLE(_pad) \
3211 /* .id .dpd .voltage .name */ \
3212 _pad(TEGRA_IO_PAD_AUDIO, 17, 5, "audio"), \
3213 _pad(TEGRA_IO_PAD_AUDIO_HV, 61, 18, "audio-hv"), \
3214 _pad(TEGRA_IO_PAD_CAM, 36, 10, "cam"), \
3215 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \
3216 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csib"), \
3217 _pad(TEGRA_IO_PAD_CSIC, 42, UINT_MAX, "csic"), \
3218 _pad(TEGRA_IO_PAD_CSID, 43, UINT_MAX, "csid"), \
3219 _pad(TEGRA_IO_PAD_CSIE, 44, UINT_MAX, "csie"), \
3220 _pad(TEGRA_IO_PAD_CSIF, 45, UINT_MAX, "csif"), \
3221 _pad(TEGRA_IO_PAD_DBG, 25, 19, "dbg"), \
3222 _pad(TEGRA_IO_PAD_DEBUG_NONAO, 26, UINT_MAX, "debug-nonao"), \
3223 _pad(TEGRA_IO_PAD_DMIC, 50, 20, "dmic"), \
3224 _pad(TEGRA_IO_PAD_DP, 51, UINT_MAX, "dp"), \
3225 _pad(TEGRA_IO_PAD_DSI, 2, UINT_MAX, "dsi"), \
3226 _pad(TEGRA_IO_PAD_DSIB, 39, UINT_MAX, "dsib"), \
3227 _pad(TEGRA_IO_PAD_DSIC, 40, UINT_MAX, "dsic"), \
3228 _pad(TEGRA_IO_PAD_DSID, 41, UINT_MAX, "dsid"), \
3229 _pad(TEGRA_IO_PAD_EMMC, 35, UINT_MAX, "emmc"), \
3230 _pad(TEGRA_IO_PAD_EMMC2, 37, UINT_MAX, "emmc2"), \
3231 _pad(TEGRA_IO_PAD_GPIO, 27, 21, "gpio"), \
3232 _pad(TEGRA_IO_PAD_HDMI, 28, UINT_MAX, "hdmi"), \
3233 _pad(TEGRA_IO_PAD_HSIC, 19, UINT_MAX, "hsic"), \
3234 _pad(TEGRA_IO_PAD_LVDS, 57, UINT_MAX, "lvds"), \
3235 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \
3236 _pad(TEGRA_IO_PAD_PEX_BIAS, 4, UINT_MAX, "pex-bias"), \
3237 _pad(TEGRA_IO_PAD_PEX_CLK1, 5, UINT_MAX, "pex-clk1"), \
3238 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \
3239 _pad(TEGRA_IO_PAD_PEX_CNTRL, UINT_MAX, 11, "pex-cntrl"), \
3240 _pad(TEGRA_IO_PAD_SDMMC1, 33, 12, "sdmmc1"), \
3241 _pad(TEGRA_IO_PAD_SDMMC3, 34, 13, "sdmmc3"), \
3242 _pad(TEGRA_IO_PAD_SPI, 46, 22, "spi"), \
3243 _pad(TEGRA_IO_PAD_SPI_HV, 47, 23, "spi-hv"), \
3244 _pad(TEGRA_IO_PAD_UART, 14, 2, "uart"), \
3245 _pad(TEGRA_IO_PAD_USB0, 9, UINT_MAX, "usb0"), \
3246 _pad(TEGRA_IO_PAD_USB1, 10, UINT_MAX, "usb1"), \
3247 _pad(TEGRA_IO_PAD_USB2, 11, UINT_MAX, "usb2"), \
3248 _pad(TEGRA_IO_PAD_USB3, 18, UINT_MAX, "usb3"), \
3249 _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb-bias")
3250
3251 static const struct tegra_io_pad_soc tegra210_io_pads[] = {
3252 TEGRA210_IO_PAD_TABLE(TEGRA_IO_PAD)
3253 };
3254
3255 static const struct pinctrl_pin_desc tegra210_pin_descs[] = {
3256 TEGRA210_IO_PAD_TABLE(TEGRA_IO_PIN_DESC)
3257 };
3258
3259 static const char * const tegra210_reset_sources[] = {
3260 "POWER_ON_RESET",
3261 "WATCHDOG",
3262 "SENSOR",
3263 "SW_MAIN",
3264 "LP0",
3265 "AOTAG"
3266 };
3267
3268 static const struct tegra_wake_event tegra210_wake_events[] = {
3269 TEGRA_WAKE_IRQ("rtc", 16, 2),
3270 TEGRA_WAKE_IRQ("pmu", 51, 86),
3271 };
3272
3273 static const struct tegra_pmc_soc tegra210_pmc_soc = {
3274 .num_powergates = ARRAY_SIZE(tegra210_powergates),
3275 .powergates = tegra210_powergates,
3276 .num_cpu_powergates = ARRAY_SIZE(tegra210_cpu_powergates),
3277 .cpu_powergates = tegra210_cpu_powergates,
3278 .has_tsense_reset = true,
3279 .has_gpu_clamps = true,
3280 .needs_mbist_war = true,
3281 .has_impl_33v_pwr = false,
3282 .maybe_tz_only = true,
3283 .num_io_pads = ARRAY_SIZE(tegra210_io_pads),
3284 .io_pads = tegra210_io_pads,
3285 .num_pin_descs = ARRAY_SIZE(tegra210_pin_descs),
3286 .pin_descs = tegra210_pin_descs,
3287 .regs = &tegra20_pmc_regs,
3288 .init = tegra20_pmc_init,
3289 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
3290 .powergate_set = tegra114_powergate_set,
3291 .irq_set_wake = tegra210_pmc_irq_set_wake,
3292 .irq_set_type = tegra210_pmc_irq_set_type,
3293 .reset_sources = tegra210_reset_sources,
3294 .num_reset_sources = ARRAY_SIZE(tegra210_reset_sources),
3295 .reset_levels = NULL,
3296 .num_reset_levels = 0,
3297 .num_wake_events = ARRAY_SIZE(tegra210_wake_events),
3298 .wake_events = tegra210_wake_events,
3299 .pmc_clks_data = tegra_pmc_clks_data,
3300 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
3301 .has_blink_output = true,
3302 .has_usb_sleepwalk = true,
3303 };
3304
3305 #define TEGRA186_IO_PAD_TABLE(_pad) \
3306 /* .id .dpd .voltage .name */ \
3307 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \
3308 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csib"), \
3309 _pad(TEGRA_IO_PAD_DSI, 2, UINT_MAX, "dsi"), \
3310 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \
3311 _pad(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, UINT_MAX, "pex-clk-bias"), \
3312 _pad(TEGRA_IO_PAD_PEX_CLK3, 5, UINT_MAX, "pex-clk3"), \
3313 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \
3314 _pad(TEGRA_IO_PAD_PEX_CLK1, 7, UINT_MAX, "pex-clk1"), \
3315 _pad(TEGRA_IO_PAD_USB0, 9, UINT_MAX, "usb0"), \
3316 _pad(TEGRA_IO_PAD_USB1, 10, UINT_MAX, "usb1"), \
3317 _pad(TEGRA_IO_PAD_USB2, 11, UINT_MAX, "usb2"), \
3318 _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb-bias"), \
3319 _pad(TEGRA_IO_PAD_UART, 14, UINT_MAX, "uart"), \
3320 _pad(TEGRA_IO_PAD_AUDIO, 17, UINT_MAX, "audio"), \
3321 _pad(TEGRA_IO_PAD_HSIC, 19, UINT_MAX, "hsic"), \
3322 _pad(TEGRA_IO_PAD_DBG, 25, UINT_MAX, "dbg"), \
3323 _pad(TEGRA_IO_PAD_HDMI_DP0, 28, UINT_MAX, "hdmi-dp0"), \
3324 _pad(TEGRA_IO_PAD_HDMI_DP1, 29, UINT_MAX, "hdmi-dp1"), \
3325 _pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \
3326 _pad(TEGRA_IO_PAD_SDMMC2_HV, 34, 5, "sdmmc2-hv"), \
3327 _pad(TEGRA_IO_PAD_SDMMC4, 36, UINT_MAX, "sdmmc4"), \
3328 _pad(TEGRA_IO_PAD_CAM, 38, UINT_MAX, "cam"), \
3329 _pad(TEGRA_IO_PAD_DSIB, 40, UINT_MAX, "dsib"), \
3330 _pad(TEGRA_IO_PAD_DSIC, 41, UINT_MAX, "dsic"), \
3331 _pad(TEGRA_IO_PAD_DSID, 42, UINT_MAX, "dsid"), \
3332 _pad(TEGRA_IO_PAD_CSIC, 43, UINT_MAX, "csic"), \
3333 _pad(TEGRA_IO_PAD_CSID, 44, UINT_MAX, "csid"), \
3334 _pad(TEGRA_IO_PAD_CSIE, 45, UINT_MAX, "csie"), \
3335 _pad(TEGRA_IO_PAD_CSIF, 46, UINT_MAX, "csif"), \
3336 _pad(TEGRA_IO_PAD_SPI, 47, UINT_MAX, "spi"), \
3337 _pad(TEGRA_IO_PAD_UFS, 49, UINT_MAX, "ufs"), \
3338 _pad(TEGRA_IO_PAD_DMIC_HV, 52, 2, "dmic-hv"), \
3339 _pad(TEGRA_IO_PAD_EDP, 53, UINT_MAX, "edp"), \
3340 _pad(TEGRA_IO_PAD_SDMMC1_HV, 55, 4, "sdmmc1-hv"), \
3341 _pad(TEGRA_IO_PAD_SDMMC3_HV, 56, 6, "sdmmc3-hv"), \
3342 _pad(TEGRA_IO_PAD_CONN, 60, UINT_MAX, "conn"), \
3343 _pad(TEGRA_IO_PAD_AUDIO_HV, 61, 1, "audio-hv"), \
3344 _pad(TEGRA_IO_PAD_AO_HV, UINT_MAX, 0, "ao-hv")
3345
3346 static const struct tegra_io_pad_soc tegra186_io_pads[] = {
3347 TEGRA186_IO_PAD_TABLE(TEGRA_IO_PAD)
3348 };
3349
3350 static const struct pinctrl_pin_desc tegra186_pin_descs[] = {
3351 TEGRA186_IO_PAD_TABLE(TEGRA_IO_PIN_DESC)
3352 };
3353
3354 static const struct tegra_pmc_regs tegra186_pmc_regs = {
3355 .scratch0 = 0x2000,
3356 .dpd_req = 0x74,
3357 .dpd_status = 0x78,
3358 .dpd2_req = 0x7c,
3359 .dpd2_status = 0x80,
3360 .rst_status = 0x70,
3361 .rst_source_shift = 0x2,
3362 .rst_source_mask = 0x3c,
3363 .rst_level_shift = 0x0,
3364 .rst_level_mask = 0x3,
3365 };
3366
tegra186_pmc_setup_irq_polarity(struct tegra_pmc * pmc,struct device_node * np,bool invert)3367 static void tegra186_pmc_setup_irq_polarity(struct tegra_pmc *pmc,
3368 struct device_node *np,
3369 bool invert)
3370 {
3371 struct resource regs;
3372 void __iomem *wake;
3373 u32 value;
3374 int index;
3375
3376 index = of_property_match_string(np, "reg-names", "wake");
3377 if (index < 0) {
3378 dev_err(pmc->dev, "failed to find PMC wake registers\n");
3379 return;
3380 }
3381
3382 of_address_to_resource(np, index, ®s);
3383
3384 wake = ioremap(regs.start, resource_size(®s));
3385 if (!wake) {
3386 dev_err(pmc->dev, "failed to map PMC wake registers\n");
3387 return;
3388 }
3389
3390 value = readl(wake + WAKE_AOWAKE_CTRL);
3391
3392 if (invert)
3393 value |= WAKE_AOWAKE_CTRL_INTR_POLARITY;
3394 else
3395 value &= ~WAKE_AOWAKE_CTRL_INTR_POLARITY;
3396
3397 writel(value, wake + WAKE_AOWAKE_CTRL);
3398
3399 iounmap(wake);
3400 }
3401
3402 static const char * const tegra186_reset_sources[] = {
3403 "SYS_RESET",
3404 "AOWDT",
3405 "MCCPLEXWDT",
3406 "BPMPWDT",
3407 "SCEWDT",
3408 "SPEWDT",
3409 "APEWDT",
3410 "BCCPLEXWDT",
3411 "SENSOR",
3412 "AOTAG",
3413 "VFSENSOR",
3414 "SWREST",
3415 "SC7",
3416 "HSM",
3417 "CORESIGHT"
3418 };
3419
3420 static const char * const tegra186_reset_levels[] = {
3421 "L0", "L1", "L2", "WARM"
3422 };
3423
3424 static const struct tegra_wake_event tegra186_wake_events[] = {
3425 TEGRA_WAKE_IRQ("pmu", 24, 209),
3426 TEGRA_WAKE_GPIO("power", 29, 1, TEGRA186_AON_GPIO(FF, 0)),
3427 TEGRA_WAKE_IRQ("rtc", 73, 10),
3428 };
3429
3430 static const struct tegra_pmc_soc tegra186_pmc_soc = {
3431 .num_powergates = 0,
3432 .powergates = NULL,
3433 .num_cpu_powergates = 0,
3434 .cpu_powergates = NULL,
3435 .has_tsense_reset = false,
3436 .has_gpu_clamps = false,
3437 .needs_mbist_war = false,
3438 .has_impl_33v_pwr = true,
3439 .maybe_tz_only = false,
3440 .num_io_pads = ARRAY_SIZE(tegra186_io_pads),
3441 .io_pads = tegra186_io_pads,
3442 .num_pin_descs = ARRAY_SIZE(tegra186_pin_descs),
3443 .pin_descs = tegra186_pin_descs,
3444 .regs = &tegra186_pmc_regs,
3445 .init = NULL,
3446 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity,
3447 .irq_set_wake = tegra186_pmc_irq_set_wake,
3448 .irq_set_type = tegra186_pmc_irq_set_type,
3449 .reset_sources = tegra186_reset_sources,
3450 .num_reset_sources = ARRAY_SIZE(tegra186_reset_sources),
3451 .reset_levels = tegra186_reset_levels,
3452 .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels),
3453 .num_wake_events = ARRAY_SIZE(tegra186_wake_events),
3454 .wake_events = tegra186_wake_events,
3455 .pmc_clks_data = NULL,
3456 .num_pmc_clks = 0,
3457 .has_blink_output = false,
3458 .has_usb_sleepwalk = false,
3459 };
3460
3461 #define TEGRA194_IO_PAD_TABLE(_pad) \
3462 /* .id .dpd .voltage .name */ \
3463 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \
3464 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csib"), \
3465 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \
3466 _pad(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, UINT_MAX, "pex-clk-bias"), \
3467 _pad(TEGRA_IO_PAD_PEX_CLK3, 5, UINT_MAX, "pex-clk3"), \
3468 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \
3469 _pad(TEGRA_IO_PAD_PEX_CLK1, 7, UINT_MAX, "pex-clk1"), \
3470 _pad(TEGRA_IO_PAD_EQOS, 8, UINT_MAX, "eqos"), \
3471 _pad(TEGRA_IO_PAD_PEX_CLK_2_BIAS, 9, UINT_MAX, "pex-clk-2-bias"), \
3472 _pad(TEGRA_IO_PAD_PEX_CLK_2, 10, UINT_MAX, "pex-clk-2"), \
3473 _pad(TEGRA_IO_PAD_DAP3, 11, UINT_MAX, "dap3"), \
3474 _pad(TEGRA_IO_PAD_DAP5, 12, UINT_MAX, "dap5"), \
3475 _pad(TEGRA_IO_PAD_UART, 14, UINT_MAX, "uart"), \
3476 _pad(TEGRA_IO_PAD_PWR_CTL, 15, UINT_MAX, "pwr-ctl"), \
3477 _pad(TEGRA_IO_PAD_SOC_GPIO53, 16, UINT_MAX, "soc-gpio53"), \
3478 _pad(TEGRA_IO_PAD_AUDIO, 17, UINT_MAX, "audio"), \
3479 _pad(TEGRA_IO_PAD_GP_PWM2, 18, UINT_MAX, "gp-pwm2"), \
3480 _pad(TEGRA_IO_PAD_GP_PWM3, 19, UINT_MAX, "gp-pwm3"), \
3481 _pad(TEGRA_IO_PAD_SOC_GPIO12, 20, UINT_MAX, "soc-gpio12"), \
3482 _pad(TEGRA_IO_PAD_SOC_GPIO13, 21, UINT_MAX, "soc-gpio13"), \
3483 _pad(TEGRA_IO_PAD_SOC_GPIO10, 22, UINT_MAX, "soc-gpio10"), \
3484 _pad(TEGRA_IO_PAD_UART4, 23, UINT_MAX, "uart4"), \
3485 _pad(TEGRA_IO_PAD_UART5, 24, UINT_MAX, "uart5"), \
3486 _pad(TEGRA_IO_PAD_DBG, 25, UINT_MAX, "dbg"), \
3487 _pad(TEGRA_IO_PAD_HDMI_DP3, 26, UINT_MAX, "hdmi-dp3"), \
3488 _pad(TEGRA_IO_PAD_HDMI_DP2, 27, UINT_MAX, "hdmi-dp2"), \
3489 _pad(TEGRA_IO_PAD_HDMI_DP0, 28, UINT_MAX, "hdmi-dp0"), \
3490 _pad(TEGRA_IO_PAD_HDMI_DP1, 29, UINT_MAX, "hdmi-dp1"), \
3491 _pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \
3492 _pad(TEGRA_IO_PAD_PEX_CTL2, 33, UINT_MAX, "pex-ctl2"), \
3493 _pad(TEGRA_IO_PAD_PEX_L0_RST_N, 34, UINT_MAX, "pex-l0-rst"), \
3494 _pad(TEGRA_IO_PAD_PEX_L1_RST_N, 35, UINT_MAX, "pex-l1-rst"), \
3495 _pad(TEGRA_IO_PAD_SDMMC4, 36, UINT_MAX, "sdmmc4"), \
3496 _pad(TEGRA_IO_PAD_PEX_L5_RST_N, 37, UINT_MAX, "pex-l5-rst"), \
3497 _pad(TEGRA_IO_PAD_CAM, 38, UINT_MAX, "cam"), \
3498 _pad(TEGRA_IO_PAD_CSIC, 43, UINT_MAX, "csic"), \
3499 _pad(TEGRA_IO_PAD_CSID, 44, UINT_MAX, "csid"), \
3500 _pad(TEGRA_IO_PAD_CSIE, 45, UINT_MAX, "csie"), \
3501 _pad(TEGRA_IO_PAD_CSIF, 46, UINT_MAX, "csif"), \
3502 _pad(TEGRA_IO_PAD_SPI, 47, UINT_MAX, "spi"), \
3503 _pad(TEGRA_IO_PAD_UFS, 49, UINT_MAX, "ufs"), \
3504 _pad(TEGRA_IO_PAD_CSIG, 50, UINT_MAX, "csig"), \
3505 _pad(TEGRA_IO_PAD_CSIH, 51, UINT_MAX, "csih"), \
3506 _pad(TEGRA_IO_PAD_EDP, 53, UINT_MAX, "edp"), \
3507 _pad(TEGRA_IO_PAD_SDMMC1_HV, 55, 4, "sdmmc1-hv"), \
3508 _pad(TEGRA_IO_PAD_SDMMC3_HV, 56, 6, "sdmmc3-hv"), \
3509 _pad(TEGRA_IO_PAD_CONN, 60, UINT_MAX, "conn"), \
3510 _pad(TEGRA_IO_PAD_AUDIO_HV, 61, 1, "audio-hv"), \
3511 _pad(TEGRA_IO_PAD_AO_HV, UINT_MAX, 0, "ao-hv")
3512
3513 static const struct tegra_io_pad_soc tegra194_io_pads[] = {
3514 TEGRA194_IO_PAD_TABLE(TEGRA_IO_PAD)
3515 };
3516
3517 static const struct pinctrl_pin_desc tegra194_pin_descs[] = {
3518 TEGRA194_IO_PAD_TABLE(TEGRA_IO_PIN_DESC)
3519 };
3520
3521 static const struct tegra_pmc_regs tegra194_pmc_regs = {
3522 .scratch0 = 0x2000,
3523 .dpd_req = 0x74,
3524 .dpd_status = 0x78,
3525 .dpd2_req = 0x7c,
3526 .dpd2_status = 0x80,
3527 .rst_status = 0x70,
3528 .rst_source_shift = 0x2,
3529 .rst_source_mask = 0x7c,
3530 .rst_level_shift = 0x0,
3531 .rst_level_mask = 0x3,
3532 };
3533
3534 static const char * const tegra194_reset_sources[] = {
3535 "SYS_RESET_N",
3536 "AOWDT",
3537 "BCCPLEXWDT",
3538 "BPMPWDT",
3539 "SCEWDT",
3540 "SPEWDT",
3541 "APEWDT",
3542 "LCCPLEXWDT",
3543 "SENSOR",
3544 "AOTAG",
3545 "VFSENSOR",
3546 "MAINSWRST",
3547 "SC7",
3548 "HSM",
3549 "CSITE",
3550 "RCEWDT",
3551 "PVA0WDT",
3552 "PVA1WDT",
3553 "L1A_ASYNC",
3554 "BPMPBOOT",
3555 "FUSECRC",
3556 };
3557
3558 static const struct tegra_wake_event tegra194_wake_events[] = {
3559 TEGRA_WAKE_IRQ("pmu", 24, 209),
3560 TEGRA_WAKE_GPIO("power", 29, 1, TEGRA194_AON_GPIO(EE, 4)),
3561 TEGRA_WAKE_IRQ("rtc", 73, 10),
3562 };
3563
3564 static const struct tegra_pmc_soc tegra194_pmc_soc = {
3565 .num_powergates = 0,
3566 .powergates = NULL,
3567 .num_cpu_powergates = 0,
3568 .cpu_powergates = NULL,
3569 .has_tsense_reset = false,
3570 .has_gpu_clamps = false,
3571 .needs_mbist_war = false,
3572 .has_impl_33v_pwr = true,
3573 .maybe_tz_only = false,
3574 .num_io_pads = ARRAY_SIZE(tegra194_io_pads),
3575 .io_pads = tegra194_io_pads,
3576 .num_pin_descs = ARRAY_SIZE(tegra194_pin_descs),
3577 .pin_descs = tegra194_pin_descs,
3578 .regs = &tegra194_pmc_regs,
3579 .init = NULL,
3580 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity,
3581 .irq_set_wake = tegra186_pmc_irq_set_wake,
3582 .irq_set_type = tegra186_pmc_irq_set_type,
3583 .reset_sources = tegra194_reset_sources,
3584 .num_reset_sources = ARRAY_SIZE(tegra194_reset_sources),
3585 .reset_levels = tegra186_reset_levels,
3586 .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels),
3587 .num_wake_events = ARRAY_SIZE(tegra194_wake_events),
3588 .wake_events = tegra194_wake_events,
3589 .pmc_clks_data = NULL,
3590 .num_pmc_clks = 0,
3591 .has_blink_output = false,
3592 .has_usb_sleepwalk = false,
3593 };
3594
3595 static const struct tegra_pmc_regs tegra234_pmc_regs = {
3596 .scratch0 = 0x2000,
3597 .dpd_req = 0,
3598 .dpd_status = 0,
3599 .dpd2_req = 0,
3600 .dpd2_status = 0,
3601 .rst_status = 0x70,
3602 .rst_source_shift = 0x2,
3603 .rst_source_mask = 0xfc,
3604 .rst_level_shift = 0x0,
3605 .rst_level_mask = 0x3,
3606 };
3607
3608 static const char * const tegra234_reset_sources[] = {
3609 "SYS_RESET_N",
3610 "AOWDT",
3611 "BCCPLEXWDT",
3612 "BPMPWDT",
3613 "SCEWDT",
3614 "SPEWDT",
3615 "APEWDT",
3616 "LCCPLEXWDT",
3617 "SENSOR",
3618 "AOTAG",
3619 "VFSENSOR",
3620 "MAINSWRST",
3621 "SC7",
3622 "HSM",
3623 "CSITE",
3624 "RCEWDT",
3625 "PVA0WDT",
3626 "PVA1WDT",
3627 "L1A_ASYNC",
3628 "BPMPBOOT",
3629 "FUSECRC",
3630 };
3631
3632 static const struct tegra_pmc_soc tegra234_pmc_soc = {
3633 .num_powergates = 0,
3634 .powergates = NULL,
3635 .num_cpu_powergates = 0,
3636 .cpu_powergates = NULL,
3637 .has_tsense_reset = false,
3638 .has_gpu_clamps = false,
3639 .needs_mbist_war = false,
3640 .has_impl_33v_pwr = true,
3641 .maybe_tz_only = false,
3642 .num_io_pads = 0,
3643 .io_pads = NULL,
3644 .num_pin_descs = 0,
3645 .pin_descs = NULL,
3646 .regs = &tegra234_pmc_regs,
3647 .init = NULL,
3648 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity,
3649 .irq_set_wake = tegra186_pmc_irq_set_wake,
3650 .irq_set_type = tegra186_pmc_irq_set_type,
3651 .reset_sources = tegra234_reset_sources,
3652 .num_reset_sources = ARRAY_SIZE(tegra234_reset_sources),
3653 .reset_levels = tegra186_reset_levels,
3654 .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels),
3655 .num_wake_events = 0,
3656 .wake_events = NULL,
3657 .pmc_clks_data = NULL,
3658 .num_pmc_clks = 0,
3659 .has_blink_output = false,
3660 };
3661
3662 static const struct of_device_id tegra_pmc_match[] = {
3663 { .compatible = "nvidia,tegra234-pmc", .data = &tegra234_pmc_soc },
3664 { .compatible = "nvidia,tegra194-pmc", .data = &tegra194_pmc_soc },
3665 { .compatible = "nvidia,tegra186-pmc", .data = &tegra186_pmc_soc },
3666 { .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc },
3667 { .compatible = "nvidia,tegra132-pmc", .data = &tegra124_pmc_soc },
3668 { .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc },
3669 { .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc },
3670 { .compatible = "nvidia,tegra30-pmc", .data = &tegra30_pmc_soc },
3671 { .compatible = "nvidia,tegra20-pmc", .data = &tegra20_pmc_soc },
3672 { }
3673 };
3674
3675 static struct platform_driver tegra_pmc_driver = {
3676 .driver = {
3677 .name = "tegra-pmc",
3678 .suppress_bind_attrs = true,
3679 .of_match_table = tegra_pmc_match,
3680 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM)
3681 .pm = &tegra_pmc_pm_ops,
3682 #endif
3683 },
3684 .probe = tegra_pmc_probe,
3685 };
3686 builtin_platform_driver(tegra_pmc_driver);
3687
tegra_pmc_detect_tz_only(struct tegra_pmc * pmc)3688 static bool __init tegra_pmc_detect_tz_only(struct tegra_pmc *pmc)
3689 {
3690 u32 value, saved;
3691
3692 saved = readl(pmc->base + pmc->soc->regs->scratch0);
3693 value = saved ^ 0xffffffff;
3694
3695 if (value == 0xffffffff)
3696 value = 0xdeadbeef;
3697
3698 /* write pattern and read it back */
3699 writel(value, pmc->base + pmc->soc->regs->scratch0);
3700 value = readl(pmc->base + pmc->soc->regs->scratch0);
3701
3702 /* if we read all-zeroes, access is restricted to TZ only */
3703 if (value == 0) {
3704 pr_info("access to PMC is restricted to TZ\n");
3705 return true;
3706 }
3707
3708 /* restore original value */
3709 writel(saved, pmc->base + pmc->soc->regs->scratch0);
3710
3711 return false;
3712 }
3713
3714 /*
3715 * Early initialization to allow access to registers in the very early boot
3716 * process.
3717 */
tegra_pmc_early_init(void)3718 static int __init tegra_pmc_early_init(void)
3719 {
3720 const struct of_device_id *match;
3721 struct device_node *np;
3722 struct resource regs;
3723 unsigned int i;
3724 bool invert;
3725
3726 mutex_init(&pmc->powergates_lock);
3727
3728 np = of_find_matching_node_and_match(NULL, tegra_pmc_match, &match);
3729 if (!np) {
3730 /*
3731 * Fall back to legacy initialization for 32-bit ARM only. All
3732 * 64-bit ARM device tree files for Tegra are required to have
3733 * a PMC node.
3734 *
3735 * This is for backwards-compatibility with old device trees
3736 * that didn't contain a PMC node. Note that in this case the
3737 * SoC data can't be matched and therefore powergating is
3738 * disabled.
3739 */
3740 if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) {
3741 pr_warn("DT node not found, powergating disabled\n");
3742
3743 regs.start = 0x7000e400;
3744 regs.end = 0x7000e7ff;
3745 regs.flags = IORESOURCE_MEM;
3746
3747 pr_warn("Using memory region %pR\n", ®s);
3748 } else {
3749 /*
3750 * At this point we're not running on Tegra, so play
3751 * nice with multi-platform kernels.
3752 */
3753 return 0;
3754 }
3755 } else {
3756 /*
3757 * Extract information from the device tree if we've found a
3758 * matching node.
3759 */
3760 if (of_address_to_resource(np, 0, ®s) < 0) {
3761 pr_err("failed to get PMC registers\n");
3762 of_node_put(np);
3763 return -ENXIO;
3764 }
3765 }
3766
3767 pmc->base = ioremap(regs.start, resource_size(®s));
3768 if (!pmc->base) {
3769 pr_err("failed to map PMC registers\n");
3770 of_node_put(np);
3771 return -ENXIO;
3772 }
3773
3774 if (np) {
3775 pmc->soc = match->data;
3776
3777 if (pmc->soc->maybe_tz_only)
3778 pmc->tz_only = tegra_pmc_detect_tz_only(pmc);
3779
3780 /* Create a bitmap of the available and valid partitions */
3781 for (i = 0; i < pmc->soc->num_powergates; i++)
3782 if (pmc->soc->powergates[i])
3783 set_bit(i, pmc->powergates_available);
3784
3785 /*
3786 * Invert the interrupt polarity if a PMC device tree node
3787 * exists and contains the nvidia,invert-interrupt property.
3788 */
3789 invert = of_property_read_bool(np, "nvidia,invert-interrupt");
3790
3791 pmc->soc->setup_irq_polarity(pmc, np, invert);
3792
3793 of_node_put(np);
3794 }
3795
3796 return 0;
3797 }
3798 early_initcall(tegra_pmc_early_init);
3799