1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2019, Linaro Limited
3
4 #include <linux/clk.h>
5 #include <linux/clk-provider.h>
6 #include <linux/interrupt.h>
7 #include <linux/kernel.h>
8 #include <linux/mfd/wcd934x/registers.h>
9 #include <linux/mfd/wcd934x/wcd934x.h>
10 #include <linux/module.h>
11 #include <linux/mutex.h>
12 #include <linux/of_clk.h>
13 #include <linux/of.h>
14 #include <linux/platform_device.h>
15 #include <linux/regmap.h>
16 #include <linux/regulator/consumer.h>
17 #include <linux/slab.h>
18 #include <linux/slimbus.h>
19 #include <sound/pcm_params.h>
20 #include <sound/soc.h>
21 #include <sound/soc-dapm.h>
22 #include <sound/tlv.h>
23 #include "wcd-clsh-v2.h"
24
25 #define WCD934X_RATES_MASK (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
26 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
27 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
28 /* Fractional Rates */
29 #define WCD934X_FRAC_RATES_MASK (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
30 SNDRV_PCM_RATE_176400)
31 #define WCD934X_FORMATS_S16_S24_LE (SNDRV_PCM_FMTBIT_S16_LE | \
32 SNDRV_PCM_FMTBIT_S24_LE)
33
34 /* slave port water mark level
35 * (0: 6bytes, 1: 9bytes, 2: 12 bytes, 3: 15 bytes)
36 */
37 #define SLAVE_PORT_WATER_MARK_6BYTES 0
38 #define SLAVE_PORT_WATER_MARK_9BYTES 1
39 #define SLAVE_PORT_WATER_MARK_12BYTES 2
40 #define SLAVE_PORT_WATER_MARK_15BYTES 3
41 #define SLAVE_PORT_WATER_MARK_SHIFT 1
42 #define SLAVE_PORT_ENABLE 1
43 #define SLAVE_PORT_DISABLE 0
44 #define WCD934X_SLIM_WATER_MARK_VAL \
45 ((SLAVE_PORT_WATER_MARK_12BYTES << SLAVE_PORT_WATER_MARK_SHIFT) | \
46 (SLAVE_PORT_ENABLE))
47
48 #define WCD934X_SLIM_NUM_PORT_REG 3
49 #define WCD934X_SLIM_PGD_PORT_INT_TX_EN0 (WCD934X_SLIM_PGD_PORT_INT_EN0 + 2)
50 #define WCD934X_SLIM_IRQ_OVERFLOW BIT(0)
51 #define WCD934X_SLIM_IRQ_UNDERFLOW BIT(1)
52 #define WCD934X_SLIM_IRQ_PORT_CLOSED BIT(2)
53
54 #define WCD934X_MCLK_CLK_12P288MHZ 12288000
55 #define WCD934X_MCLK_CLK_9P6MHZ 9600000
56
57 /* Only valid for 9.6 MHz mclk */
58 #define WCD9XXX_DMIC_SAMPLE_RATE_2P4MHZ 2400000
59 #define WCD9XXX_DMIC_SAMPLE_RATE_4P8MHZ 4800000
60
61 /* Only valid for 12.288 MHz mclk */
62 #define WCD9XXX_DMIC_SAMPLE_RATE_4P096MHZ 4096000
63
64 #define WCD934X_DMIC_CLK_DIV_2 0x0
65 #define WCD934X_DMIC_CLK_DIV_3 0x1
66 #define WCD934X_DMIC_CLK_DIV_4 0x2
67 #define WCD934X_DMIC_CLK_DIV_6 0x3
68 #define WCD934X_DMIC_CLK_DIV_8 0x4
69 #define WCD934X_DMIC_CLK_DIV_16 0x5
70 #define WCD934X_DMIC_CLK_DRIVE_DEFAULT 0x02
71
72 #define TX_HPF_CUT_OFF_FREQ_MASK 0x60
73 #define CF_MIN_3DB_4HZ 0x0
74 #define CF_MIN_3DB_75HZ 0x1
75 #define CF_MIN_3DB_150HZ 0x2
76
77 #define WCD934X_RX_START 16
78 #define WCD934X_NUM_INTERPOLATORS 9
79 #define WCD934X_RX_PATH_CTL_OFFSET 20
80 #define WCD934X_MAX_VALID_ADC_MUX 13
81 #define WCD934X_INVALID_ADC_MUX 9
82
83 #define WCD934X_SLIM_RX_CH(p) \
84 {.port = p + WCD934X_RX_START, .shift = p,}
85
86 #define WCD934X_SLIM_TX_CH(p) \
87 {.port = p, .shift = p,}
88
89 /* Feature masks to distinguish codec version */
90 #define DSD_DISABLED_MASK 0
91 #define SLNQ_DISABLED_MASK 1
92
93 #define DSD_DISABLED BIT(DSD_DISABLED_MASK)
94 #define SLNQ_DISABLED BIT(SLNQ_DISABLED_MASK)
95
96 /* As fine version info cannot be retrieved before wcd probe.
97 * Define three coarse versions for possible future use before wcd probe.
98 */
99 #define WCD_VERSION_WCD9340_1_0 0x400
100 #define WCD_VERSION_WCD9341_1_0 0x410
101 #define WCD_VERSION_WCD9340_1_1 0x401
102 #define WCD_VERSION_WCD9341_1_1 0x411
103 #define WCD934X_AMIC_PWR_LEVEL_LP 0
104 #define WCD934X_AMIC_PWR_LEVEL_DEFAULT 1
105 #define WCD934X_AMIC_PWR_LEVEL_HP 2
106 #define WCD934X_AMIC_PWR_LEVEL_HYBRID 3
107 #define WCD934X_AMIC_PWR_LVL_MASK 0x60
108 #define WCD934X_AMIC_PWR_LVL_SHIFT 0x5
109
110 #define WCD934X_DEC_PWR_LVL_MASK 0x06
111 #define WCD934X_DEC_PWR_LVL_LP 0x02
112 #define WCD934X_DEC_PWR_LVL_HP 0x04
113 #define WCD934X_DEC_PWR_LVL_DF 0x00
114 #define WCD934X_DEC_PWR_LVL_HYBRID WCD934X_DEC_PWR_LVL_DF
115
116 #define WCD934X_DEF_MICBIAS_MV 1800
117 #define WCD934X_MAX_MICBIAS_MV 2850
118
119 #define WCD_IIR_FILTER_SIZE (sizeof(u32) * BAND_MAX)
120
121 #define WCD_IIR_FILTER_CTL(xname, iidx, bidx) \
122 { \
123 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
124 .info = wcd934x_iir_filter_info, \
125 .get = wcd934x_get_iir_band_audio_mixer, \
126 .put = wcd934x_put_iir_band_audio_mixer, \
127 .private_value = (unsigned long)&(struct wcd_iir_filter_ctl) { \
128 .iir_idx = iidx, \
129 .band_idx = bidx, \
130 .bytes_ext = {.max = WCD_IIR_FILTER_SIZE, }, \
131 } \
132 }
133
134 #define WCD934X_INTERPOLATOR_PATH(id) \
135 {"RX INT" #id "_1 MIX1 INP0", "RX0", "SLIM RX0"}, \
136 {"RX INT" #id "_1 MIX1 INP0", "RX1", "SLIM RX1"}, \
137 {"RX INT" #id "_1 MIX1 INP0", "RX2", "SLIM RX2"}, \
138 {"RX INT" #id "_1 MIX1 INP0", "RX3", "SLIM RX3"}, \
139 {"RX INT" #id "_1 MIX1 INP0", "RX4", "SLIM RX4"}, \
140 {"RX INT" #id "_1 MIX1 INP0", "RX5", "SLIM RX5"}, \
141 {"RX INT" #id "_1 MIX1 INP0", "RX6", "SLIM RX6"}, \
142 {"RX INT" #id "_1 MIX1 INP0", "RX7", "SLIM RX7"}, \
143 {"RX INT" #id "_1 MIX1 INP0", "IIR0", "IIR0"}, \
144 {"RX INT" #id "_1 MIX1 INP0", "IIR1", "IIR1"}, \
145 {"RX INT" #id "_1 MIX1 INP1", "RX0", "SLIM RX0"}, \
146 {"RX INT" #id "_1 MIX1 INP1", "RX1", "SLIM RX1"}, \
147 {"RX INT" #id "_1 MIX1 INP1", "RX2", "SLIM RX2"}, \
148 {"RX INT" #id "_1 MIX1 INP1", "RX3", "SLIM RX3"}, \
149 {"RX INT" #id "_1 MIX1 INP1", "RX4", "SLIM RX4"}, \
150 {"RX INT" #id "_1 MIX1 INP1", "RX5", "SLIM RX5"}, \
151 {"RX INT" #id "_1 MIX1 INP1", "RX6", "SLIM RX6"}, \
152 {"RX INT" #id "_1 MIX1 INP1", "RX7", "SLIM RX7"}, \
153 {"RX INT" #id "_1 MIX1 INP1", "IIR0", "IIR0"}, \
154 {"RX INT" #id "_1 MIX1 INP1", "IIR1", "IIR1"}, \
155 {"RX INT" #id "_1 MIX1 INP2", "RX0", "SLIM RX0"}, \
156 {"RX INT" #id "_1 MIX1 INP2", "RX1", "SLIM RX1"}, \
157 {"RX INT" #id "_1 MIX1 INP2", "RX2", "SLIM RX2"}, \
158 {"RX INT" #id "_1 MIX1 INP2", "RX3", "SLIM RX3"}, \
159 {"RX INT" #id "_1 MIX1 INP2", "RX4", "SLIM RX4"}, \
160 {"RX INT" #id "_1 MIX1 INP2", "RX5", "SLIM RX5"}, \
161 {"RX INT" #id "_1 MIX1 INP2", "RX6", "SLIM RX6"}, \
162 {"RX INT" #id "_1 MIX1 INP2", "RX7", "SLIM RX7"}, \
163 {"RX INT" #id "_1 MIX1 INP2", "IIR0", "IIR0"}, \
164 {"RX INT" #id "_1 MIX1 INP2", "IIR1", "IIR1"}, \
165 {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP0"}, \
166 {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP1"}, \
167 {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP2"}, \
168 {"RX INT" #id "_2 MUX", "RX0", "SLIM RX0"}, \
169 {"RX INT" #id "_2 MUX", "RX1", "SLIM RX1"}, \
170 {"RX INT" #id "_2 MUX", "RX2", "SLIM RX2"}, \
171 {"RX INT" #id "_2 MUX", "RX3", "SLIM RX3"}, \
172 {"RX INT" #id "_2 MUX", "RX4", "SLIM RX4"}, \
173 {"RX INT" #id "_2 MUX", "RX5", "SLIM RX5"}, \
174 {"RX INT" #id "_2 MUX", "RX6", "SLIM RX6"}, \
175 {"RX INT" #id "_2 MUX", "RX7", "SLIM RX7"}, \
176 {"RX INT" #id "_2 MUX", NULL, "INT" #id "_CLK"}, \
177 {"RX INT" #id "_2 MUX", NULL, "DSMDEM" #id "_CLK"}, \
178 {"RX INT" #id "_2 INTERP", NULL, "RX INT" #id "_2 MUX"}, \
179 {"RX INT" #id " SEC MIX", NULL, "RX INT" #id "_2 INTERP"}, \
180 {"RX INT" #id "_1 INTERP", NULL, "RX INT" #id "_1 MIX1"}, \
181 {"RX INT" #id "_1 INTERP", NULL, "INT" #id "_CLK"}, \
182 {"RX INT" #id "_1 INTERP", NULL, "DSMDEM" #id "_CLK"}, \
183 {"RX INT" #id " SEC MIX", NULL, "RX INT" #id "_1 INTERP"}
184
185 #define WCD934X_INTERPOLATOR_MIX2(id) \
186 {"RX INT" #id " MIX2", NULL, "RX INT" #id " SEC MIX"}, \
187 {"RX INT" #id " MIX2", NULL, "RX INT" #id " MIX2 INP"}
188
189 #define WCD934X_SLIM_RX_AIF_PATH(id) \
190 {"SLIM RX"#id" MUX", "AIF1_PB", "AIF1 PB"}, \
191 {"SLIM RX"#id" MUX", "AIF2_PB", "AIF2 PB"}, \
192 {"SLIM RX"#id" MUX", "AIF3_PB", "AIF3 PB"}, \
193 {"SLIM RX"#id" MUX", "AIF4_PB", "AIF4 PB"}, \
194 {"SLIM RX"#id, NULL, "SLIM RX"#id" MUX"}
195
196 #define WCD934X_ADC_MUX(id) \
197 {"ADC MUX" #id, "DMIC", "DMIC MUX" #id }, \
198 {"ADC MUX" #id, "AMIC", "AMIC MUX" #id }, \
199 {"DMIC MUX" #id, "DMIC0", "DMIC0"}, \
200 {"DMIC MUX" #id, "DMIC1", "DMIC1"}, \
201 {"DMIC MUX" #id, "DMIC2", "DMIC2"}, \
202 {"DMIC MUX" #id, "DMIC3", "DMIC3"}, \
203 {"DMIC MUX" #id, "DMIC4", "DMIC4"}, \
204 {"DMIC MUX" #id, "DMIC5", "DMIC5"}, \
205 {"AMIC MUX" #id, "ADC1", "ADC1"}, \
206 {"AMIC MUX" #id, "ADC2", "ADC2"}, \
207 {"AMIC MUX" #id, "ADC3", "ADC3"}, \
208 {"AMIC MUX" #id, "ADC4", "ADC4"}
209
210 #define WCD934X_IIR_INP_MUX(id) \
211 {"IIR" #id, NULL, "IIR" #id " INP0 MUX"}, \
212 {"IIR" #id " INP0 MUX", "DEC0", "ADC MUX0"}, \
213 {"IIR" #id " INP0 MUX", "DEC1", "ADC MUX1"}, \
214 {"IIR" #id " INP0 MUX", "DEC2", "ADC MUX2"}, \
215 {"IIR" #id " INP0 MUX", "DEC3", "ADC MUX3"}, \
216 {"IIR" #id " INP0 MUX", "DEC4", "ADC MUX4"}, \
217 {"IIR" #id " INP0 MUX", "DEC5", "ADC MUX5"}, \
218 {"IIR" #id " INP0 MUX", "DEC6", "ADC MUX6"}, \
219 {"IIR" #id " INP0 MUX", "DEC7", "ADC MUX7"}, \
220 {"IIR" #id " INP0 MUX", "DEC8", "ADC MUX8"}, \
221 {"IIR" #id " INP0 MUX", "RX0", "SLIM RX0"}, \
222 {"IIR" #id " INP0 MUX", "RX1", "SLIM RX1"}, \
223 {"IIR" #id " INP0 MUX", "RX2", "SLIM RX2"}, \
224 {"IIR" #id " INP0 MUX", "RX3", "SLIM RX3"}, \
225 {"IIR" #id " INP0 MUX", "RX4", "SLIM RX4"}, \
226 {"IIR" #id " INP0 MUX", "RX5", "SLIM RX5"}, \
227 {"IIR" #id " INP0 MUX", "RX6", "SLIM RX6"}, \
228 {"IIR" #id " INP0 MUX", "RX7", "SLIM RX7"}, \
229 {"IIR" #id, NULL, "IIR" #id " INP1 MUX"}, \
230 {"IIR" #id " INP1 MUX", "DEC0", "ADC MUX0"}, \
231 {"IIR" #id " INP1 MUX", "DEC1", "ADC MUX1"}, \
232 {"IIR" #id " INP1 MUX", "DEC2", "ADC MUX2"}, \
233 {"IIR" #id " INP1 MUX", "DEC3", "ADC MUX3"}, \
234 {"IIR" #id " INP1 MUX", "DEC4", "ADC MUX4"}, \
235 {"IIR" #id " INP1 MUX", "DEC5", "ADC MUX5"}, \
236 {"IIR" #id " INP1 MUX", "DEC6", "ADC MUX6"}, \
237 {"IIR" #id " INP1 MUX", "DEC7", "ADC MUX7"}, \
238 {"IIR" #id " INP1 MUX", "DEC8", "ADC MUX8"}, \
239 {"IIR" #id " INP1 MUX", "RX0", "SLIM RX0"}, \
240 {"IIR" #id " INP1 MUX", "RX1", "SLIM RX1"}, \
241 {"IIR" #id " INP1 MUX", "RX2", "SLIM RX2"}, \
242 {"IIR" #id " INP1 MUX", "RX3", "SLIM RX3"}, \
243 {"IIR" #id " INP1 MUX", "RX4", "SLIM RX4"}, \
244 {"IIR" #id " INP1 MUX", "RX5", "SLIM RX5"}, \
245 {"IIR" #id " INP1 MUX", "RX6", "SLIM RX6"}, \
246 {"IIR" #id " INP1 MUX", "RX7", "SLIM RX7"}, \
247 {"IIR" #id, NULL, "IIR" #id " INP2 MUX"}, \
248 {"IIR" #id " INP2 MUX", "DEC0", "ADC MUX0"}, \
249 {"IIR" #id " INP2 MUX", "DEC1", "ADC MUX1"}, \
250 {"IIR" #id " INP2 MUX", "DEC2", "ADC MUX2"}, \
251 {"IIR" #id " INP2 MUX", "DEC3", "ADC MUX3"}, \
252 {"IIR" #id " INP2 MUX", "DEC4", "ADC MUX4"}, \
253 {"IIR" #id " INP2 MUX", "DEC5", "ADC MUX5"}, \
254 {"IIR" #id " INP2 MUX", "DEC6", "ADC MUX6"}, \
255 {"IIR" #id " INP2 MUX", "DEC7", "ADC MUX7"}, \
256 {"IIR" #id " INP2 MUX", "DEC8", "ADC MUX8"}, \
257 {"IIR" #id " INP2 MUX", "RX0", "SLIM RX0"}, \
258 {"IIR" #id " INP2 MUX", "RX1", "SLIM RX1"}, \
259 {"IIR" #id " INP2 MUX", "RX2", "SLIM RX2"}, \
260 {"IIR" #id " INP2 MUX", "RX3", "SLIM RX3"}, \
261 {"IIR" #id " INP2 MUX", "RX4", "SLIM RX4"}, \
262 {"IIR" #id " INP2 MUX", "RX5", "SLIM RX5"}, \
263 {"IIR" #id " INP2 MUX", "RX6", "SLIM RX6"}, \
264 {"IIR" #id " INP2 MUX", "RX7", "SLIM RX7"}, \
265 {"IIR" #id, NULL, "IIR" #id " INP3 MUX"}, \
266 {"IIR" #id " INP3 MUX", "DEC0", "ADC MUX0"}, \
267 {"IIR" #id " INP3 MUX", "DEC1", "ADC MUX1"}, \
268 {"IIR" #id " INP3 MUX", "DEC2", "ADC MUX2"}, \
269 {"IIR" #id " INP3 MUX", "DEC3", "ADC MUX3"}, \
270 {"IIR" #id " INP3 MUX", "DEC4", "ADC MUX4"}, \
271 {"IIR" #id " INP3 MUX", "DEC5", "ADC MUX5"}, \
272 {"IIR" #id " INP3 MUX", "DEC6", "ADC MUX6"}, \
273 {"IIR" #id " INP3 MUX", "DEC7", "ADC MUX7"}, \
274 {"IIR" #id " INP3 MUX", "DEC8", "ADC MUX8"}, \
275 {"IIR" #id " INP3 MUX", "RX0", "SLIM RX0"}, \
276 {"IIR" #id " INP3 MUX", "RX1", "SLIM RX1"}, \
277 {"IIR" #id " INP3 MUX", "RX2", "SLIM RX2"}, \
278 {"IIR" #id " INP3 MUX", "RX3", "SLIM RX3"}, \
279 {"IIR" #id " INP3 MUX", "RX4", "SLIM RX4"}, \
280 {"IIR" #id " INP3 MUX", "RX5", "SLIM RX5"}, \
281 {"IIR" #id " INP3 MUX", "RX6", "SLIM RX6"}, \
282 {"IIR" #id " INP3 MUX", "RX7", "SLIM RX7"}
283
284 #define WCD934X_SLIM_TX_AIF_PATH(id) \
285 {"AIF1_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id }, \
286 {"AIF2_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id }, \
287 {"AIF3_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id }, \
288 {"SLIM TX" #id, NULL, "CDC_IF TX" #id " MUX"}
289
290 enum {
291 MIC_BIAS_1 = 1,
292 MIC_BIAS_2,
293 MIC_BIAS_3,
294 MIC_BIAS_4
295 };
296
297 enum {
298 SIDO_SOURCE_INTERNAL,
299 SIDO_SOURCE_RCO_BG,
300 };
301
302 enum {
303 INTERP_EAR = 0,
304 INTERP_HPHL,
305 INTERP_HPHR,
306 INTERP_LO1,
307 INTERP_LO2,
308 INTERP_LO3_NA, /* LO3 not avalible in Tavil */
309 INTERP_LO4_NA,
310 INTERP_SPKR1, /*INT7 WSA Speakers via soundwire */
311 INTERP_SPKR2, /*INT8 WSA Speakers via soundwire */
312 INTERP_MAX,
313 };
314
315 enum {
316 WCD934X_RX0 = 0,
317 WCD934X_RX1,
318 WCD934X_RX2,
319 WCD934X_RX3,
320 WCD934X_RX4,
321 WCD934X_RX5,
322 WCD934X_RX6,
323 WCD934X_RX7,
324 WCD934X_RX8,
325 WCD934X_RX9,
326 WCD934X_RX10,
327 WCD934X_RX11,
328 WCD934X_RX12,
329 WCD934X_RX_MAX,
330 };
331
332 enum {
333 WCD934X_TX0 = 0,
334 WCD934X_TX1,
335 WCD934X_TX2,
336 WCD934X_TX3,
337 WCD934X_TX4,
338 WCD934X_TX5,
339 WCD934X_TX6,
340 WCD934X_TX7,
341 WCD934X_TX8,
342 WCD934X_TX9,
343 WCD934X_TX10,
344 WCD934X_TX11,
345 WCD934X_TX12,
346 WCD934X_TX13,
347 WCD934X_TX14,
348 WCD934X_TX15,
349 WCD934X_TX_MAX,
350 };
351
352 struct wcd934x_slim_ch {
353 u32 ch_num;
354 u16 port;
355 u16 shift;
356 struct list_head list;
357 };
358
359 static const struct wcd934x_slim_ch wcd934x_tx_chs[WCD934X_TX_MAX] = {
360 WCD934X_SLIM_TX_CH(0),
361 WCD934X_SLIM_TX_CH(1),
362 WCD934X_SLIM_TX_CH(2),
363 WCD934X_SLIM_TX_CH(3),
364 WCD934X_SLIM_TX_CH(4),
365 WCD934X_SLIM_TX_CH(5),
366 WCD934X_SLIM_TX_CH(6),
367 WCD934X_SLIM_TX_CH(7),
368 WCD934X_SLIM_TX_CH(8),
369 WCD934X_SLIM_TX_CH(9),
370 WCD934X_SLIM_TX_CH(10),
371 WCD934X_SLIM_TX_CH(11),
372 WCD934X_SLIM_TX_CH(12),
373 WCD934X_SLIM_TX_CH(13),
374 WCD934X_SLIM_TX_CH(14),
375 WCD934X_SLIM_TX_CH(15),
376 };
377
378 static const struct wcd934x_slim_ch wcd934x_rx_chs[WCD934X_RX_MAX] = {
379 WCD934X_SLIM_RX_CH(0), /* 16 */
380 WCD934X_SLIM_RX_CH(1), /* 17 */
381 WCD934X_SLIM_RX_CH(2),
382 WCD934X_SLIM_RX_CH(3),
383 WCD934X_SLIM_RX_CH(4),
384 WCD934X_SLIM_RX_CH(5),
385 WCD934X_SLIM_RX_CH(6),
386 WCD934X_SLIM_RX_CH(7),
387 WCD934X_SLIM_RX_CH(8),
388 WCD934X_SLIM_RX_CH(9),
389 WCD934X_SLIM_RX_CH(10),
390 WCD934X_SLIM_RX_CH(11),
391 WCD934X_SLIM_RX_CH(12),
392 };
393
394 /* Codec supports 2 IIR filters */
395 enum {
396 IIR0 = 0,
397 IIR1,
398 IIR_MAX,
399 };
400
401 /* Each IIR has 5 Filter Stages */
402 enum {
403 BAND1 = 0,
404 BAND2,
405 BAND3,
406 BAND4,
407 BAND5,
408 BAND_MAX,
409 };
410
411 enum {
412 COMPANDER_1, /* HPH_L */
413 COMPANDER_2, /* HPH_R */
414 COMPANDER_3, /* LO1_DIFF */
415 COMPANDER_4, /* LO2_DIFF */
416 COMPANDER_5, /* LO3_SE - not used in Tavil */
417 COMPANDER_6, /* LO4_SE - not used in Tavil */
418 COMPANDER_7, /* SWR SPK CH1 */
419 COMPANDER_8, /* SWR SPK CH2 */
420 COMPANDER_MAX,
421 };
422
423 enum {
424 AIF1_PB = 0,
425 AIF1_CAP,
426 AIF2_PB,
427 AIF2_CAP,
428 AIF3_PB,
429 AIF3_CAP,
430 AIF4_PB,
431 AIF4_VIFEED,
432 AIF4_MAD_TX,
433 NUM_CODEC_DAIS,
434 };
435
436 enum {
437 INTn_1_INP_SEL_ZERO = 0,
438 INTn_1_INP_SEL_DEC0,
439 INTn_1_INP_SEL_DEC1,
440 INTn_1_INP_SEL_IIR0,
441 INTn_1_INP_SEL_IIR1,
442 INTn_1_INP_SEL_RX0,
443 INTn_1_INP_SEL_RX1,
444 INTn_1_INP_SEL_RX2,
445 INTn_1_INP_SEL_RX3,
446 INTn_1_INP_SEL_RX4,
447 INTn_1_INP_SEL_RX5,
448 INTn_1_INP_SEL_RX6,
449 INTn_1_INP_SEL_RX7,
450 };
451
452 enum {
453 INTn_2_INP_SEL_ZERO = 0,
454 INTn_2_INP_SEL_RX0,
455 INTn_2_INP_SEL_RX1,
456 INTn_2_INP_SEL_RX2,
457 INTn_2_INP_SEL_RX3,
458 INTn_2_INP_SEL_RX4,
459 INTn_2_INP_SEL_RX5,
460 INTn_2_INP_SEL_RX6,
461 INTn_2_INP_SEL_RX7,
462 INTn_2_INP_SEL_PROXIMITY,
463 };
464
465 enum {
466 INTERP_MAIN_PATH,
467 INTERP_MIX_PATH,
468 };
469
470 struct interp_sample_rate {
471 int sample_rate;
472 int rate_val;
473 };
474
475 static struct interp_sample_rate sr_val_tbl[] = {
476 {8000, 0x0},
477 {16000, 0x1},
478 {32000, 0x3},
479 {48000, 0x4},
480 {96000, 0x5},
481 {192000, 0x6},
482 {384000, 0x7},
483 {44100, 0x9},
484 {88200, 0xA},
485 {176400, 0xB},
486 {352800, 0xC},
487 };
488
489 struct wcd_slim_codec_dai_data {
490 struct list_head slim_ch_list;
491 struct slim_stream_config sconfig;
492 struct slim_stream_runtime *sruntime;
493 };
494
495 static const struct regmap_range_cfg wcd934x_ifc_ranges[] = {
496 {
497 .name = "WCD9335-IFC-DEV",
498 .range_min = 0x0,
499 .range_max = 0xffff,
500 .selector_reg = 0x800,
501 .selector_mask = 0xfff,
502 .selector_shift = 0,
503 .window_start = 0x800,
504 .window_len = 0x400,
505 },
506 };
507
508 static struct regmap_config wcd934x_ifc_regmap_config = {
509 .reg_bits = 16,
510 .val_bits = 8,
511 .max_register = 0xffff,
512 .ranges = wcd934x_ifc_ranges,
513 .num_ranges = ARRAY_SIZE(wcd934x_ifc_ranges),
514 };
515
516 struct wcd934x_codec {
517 struct device *dev;
518 struct clk_hw hw;
519 struct clk *extclk;
520 struct regmap *regmap;
521 struct regmap *if_regmap;
522 struct slim_device *sdev;
523 struct slim_device *sidev;
524 struct wcd_clsh_ctrl *clsh_ctrl;
525 struct snd_soc_component *component;
526 struct wcd934x_slim_ch rx_chs[WCD934X_RX_MAX];
527 struct wcd934x_slim_ch tx_chs[WCD934X_TX_MAX];
528 struct wcd_slim_codec_dai_data dai[NUM_CODEC_DAIS];
529 int rate;
530 u32 version;
531 u32 hph_mode;
532 int num_rx_port;
533 int num_tx_port;
534 u32 tx_port_value[WCD934X_TX_MAX];
535 u32 rx_port_value[WCD934X_RX_MAX];
536 int sido_input_src;
537 int dmic_0_1_clk_cnt;
538 int dmic_2_3_clk_cnt;
539 int dmic_4_5_clk_cnt;
540 int dmic_sample_rate;
541 int comp_enabled[COMPANDER_MAX];
542 int sysclk_users;
543 struct mutex sysclk_mutex;
544 };
545
546 #define to_wcd934x_codec(_hw) container_of(_hw, struct wcd934x_codec, hw)
547
548 struct wcd_iir_filter_ctl {
549 unsigned int iir_idx;
550 unsigned int band_idx;
551 struct soc_bytes_ext bytes_ext;
552 };
553
554 static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400);
555 static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
556 static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
557 static const DECLARE_TLV_DB_SCALE(ear_pa_gain, 0, 150, 0);
558
559 /* Cutoff frequency for high pass filter */
560 static const char * const cf_text[] = {
561 "CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ"
562 };
563
564 static const char * const rx_cf_text[] = {
565 "CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ",
566 "CF_NEG_3DB_0P48HZ"
567 };
568
569 static const char * const rx_hph_mode_mux_text[] = {
570 "Class H Invalid", "Class-H Hi-Fi", "Class-H Low Power", "Class-AB",
571 "Class-H Hi-Fi Low Power"
572 };
573
574 static const char *const slim_rx_mux_text[] = {
575 "ZERO", "AIF1_PB", "AIF2_PB", "AIF3_PB", "AIF4_PB",
576 };
577
578 static const char * const rx_int0_7_mix_mux_text[] = {
579 "ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5",
580 "RX6", "RX7", "PROXIMITY"
581 };
582
583 static const char * const rx_int_mix_mux_text[] = {
584 "ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5",
585 "RX6", "RX7"
586 };
587
588 static const char * const rx_prim_mix_text[] = {
589 "ZERO", "DEC0", "DEC1", "IIR0", "IIR1", "RX0", "RX1", "RX2",
590 "RX3", "RX4", "RX5", "RX6", "RX7"
591 };
592
593 static const char * const rx_sidetone_mix_text[] = {
594 "ZERO", "SRC0", "SRC1", "SRC_SUM"
595 };
596
597 static const char * const iir_inp_mux_text[] = {
598 "ZERO", "DEC0", "DEC1", "DEC2", "DEC3", "DEC4", "DEC5", "DEC6",
599 "DEC7", "DEC8", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5", "RX6", "RX7"
600 };
601
602 static const char * const rx_int_dem_inp_mux_text[] = {
603 "NORMAL_DSM_OUT", "CLSH_DSM_OUT",
604 };
605
606 static const char * const rx_int0_1_interp_mux_text[] = {
607 "ZERO", "RX INT0_1 MIX1",
608 };
609
610 static const char * const rx_int1_1_interp_mux_text[] = {
611 "ZERO", "RX INT1_1 MIX1",
612 };
613
614 static const char * const rx_int2_1_interp_mux_text[] = {
615 "ZERO", "RX INT2_1 MIX1",
616 };
617
618 static const char * const rx_int3_1_interp_mux_text[] = {
619 "ZERO", "RX INT3_1 MIX1",
620 };
621
622 static const char * const rx_int4_1_interp_mux_text[] = {
623 "ZERO", "RX INT4_1 MIX1",
624 };
625
626 static const char * const rx_int7_1_interp_mux_text[] = {
627 "ZERO", "RX INT7_1 MIX1",
628 };
629
630 static const char * const rx_int8_1_interp_mux_text[] = {
631 "ZERO", "RX INT8_1 MIX1",
632 };
633
634 static const char * const rx_int0_2_interp_mux_text[] = {
635 "ZERO", "RX INT0_2 MUX",
636 };
637
638 static const char * const rx_int1_2_interp_mux_text[] = {
639 "ZERO", "RX INT1_2 MUX",
640 };
641
642 static const char * const rx_int2_2_interp_mux_text[] = {
643 "ZERO", "RX INT2_2 MUX",
644 };
645
646 static const char * const rx_int3_2_interp_mux_text[] = {
647 "ZERO", "RX INT3_2 MUX",
648 };
649
650 static const char * const rx_int4_2_interp_mux_text[] = {
651 "ZERO", "RX INT4_2 MUX",
652 };
653
654 static const char * const rx_int7_2_interp_mux_text[] = {
655 "ZERO", "RX INT7_2 MUX",
656 };
657
658 static const char * const rx_int8_2_interp_mux_text[] = {
659 "ZERO", "RX INT8_2 MUX",
660 };
661
662 static const char * const dmic_mux_text[] = {
663 "ZERO", "DMIC0", "DMIC1", "DMIC2", "DMIC3", "DMIC4", "DMIC5"
664 };
665
666 static const char * const amic_mux_text[] = {
667 "ZERO", "ADC1", "ADC2", "ADC3", "ADC4"
668 };
669
670 static const char * const amic4_5_sel_text[] = {
671 "AMIC4", "AMIC5"
672 };
673
674 static const char * const adc_mux_text[] = {
675 "DMIC", "AMIC", "ANC_FB_TUNE1", "ANC_FB_TUNE2"
676 };
677
678 static const char * const cdc_if_tx0_mux_text[] = {
679 "ZERO", "RX_MIX_TX0", "DEC0", "DEC0_192"
680 };
681
682 static const char * const cdc_if_tx1_mux_text[] = {
683 "ZERO", "RX_MIX_TX1", "DEC1", "DEC1_192"
684 };
685
686 static const char * const cdc_if_tx2_mux_text[] = {
687 "ZERO", "RX_MIX_TX2", "DEC2", "DEC2_192"
688 };
689
690 static const char * const cdc_if_tx3_mux_text[] = {
691 "ZERO", "RX_MIX_TX3", "DEC3", "DEC3_192"
692 };
693
694 static const char * const cdc_if_tx4_mux_text[] = {
695 "ZERO", "RX_MIX_TX4", "DEC4", "DEC4_192"
696 };
697
698 static const char * const cdc_if_tx5_mux_text[] = {
699 "ZERO", "RX_MIX_TX5", "DEC5", "DEC5_192"
700 };
701
702 static const char * const cdc_if_tx6_mux_text[] = {
703 "ZERO", "RX_MIX_TX6", "DEC6", "DEC6_192"
704 };
705
706 static const char * const cdc_if_tx7_mux_text[] = {
707 "ZERO", "RX_MIX_TX7", "DEC7", "DEC7_192"
708 };
709
710 static const char * const cdc_if_tx8_mux_text[] = {
711 "ZERO", "RX_MIX_TX8", "DEC8", "DEC8_192"
712 };
713
714 static const char * const cdc_if_tx9_mux_text[] = {
715 "ZERO", "DEC7", "DEC7_192"
716 };
717
718 static const char * const cdc_if_tx10_mux_text[] = {
719 "ZERO", "DEC6", "DEC6_192"
720 };
721
722 static const char * const cdc_if_tx11_mux_text[] = {
723 "DEC_0_5", "DEC_9_12", "MAD_AUDIO", "MAD_BRDCST"
724 };
725
726 static const char * const cdc_if_tx11_inp1_mux_text[] = {
727 "ZERO", "DEC0", "DEC1", "DEC2", "DEC3", "DEC4",
728 "DEC5", "RX_MIX_TX5", "DEC9_10", "DEC11_12"
729 };
730
731 static const char * const cdc_if_tx13_mux_text[] = {
732 "CDC_DEC_5", "MAD_BRDCST"
733 };
734
735 static const char * const cdc_if_tx13_inp1_mux_text[] = {
736 "ZERO", "DEC5", "DEC5_192"
737 };
738
739 static const struct soc_enum cf_dec0_enum =
740 SOC_ENUM_SINGLE(WCD934X_CDC_TX0_TX_PATH_CFG0, 5, 3, cf_text);
741
742 static const struct soc_enum cf_dec1_enum =
743 SOC_ENUM_SINGLE(WCD934X_CDC_TX1_TX_PATH_CFG0, 5, 3, cf_text);
744
745 static const struct soc_enum cf_dec2_enum =
746 SOC_ENUM_SINGLE(WCD934X_CDC_TX2_TX_PATH_CFG0, 5, 3, cf_text);
747
748 static const struct soc_enum cf_dec3_enum =
749 SOC_ENUM_SINGLE(WCD934X_CDC_TX3_TX_PATH_CFG0, 5, 3, cf_text);
750
751 static const struct soc_enum cf_dec4_enum =
752 SOC_ENUM_SINGLE(WCD934X_CDC_TX4_TX_PATH_CFG0, 5, 3, cf_text);
753
754 static const struct soc_enum cf_dec5_enum =
755 SOC_ENUM_SINGLE(WCD934X_CDC_TX5_TX_PATH_CFG0, 5, 3, cf_text);
756
757 static const struct soc_enum cf_dec6_enum =
758 SOC_ENUM_SINGLE(WCD934X_CDC_TX6_TX_PATH_CFG0, 5, 3, cf_text);
759
760 static const struct soc_enum cf_dec7_enum =
761 SOC_ENUM_SINGLE(WCD934X_CDC_TX7_TX_PATH_CFG0, 5, 3, cf_text);
762
763 static const struct soc_enum cf_dec8_enum =
764 SOC_ENUM_SINGLE(WCD934X_CDC_TX8_TX_PATH_CFG0, 5, 3, cf_text);
765
766 static const struct soc_enum cf_int0_1_enum =
767 SOC_ENUM_SINGLE(WCD934X_CDC_RX0_RX_PATH_CFG2, 0, 4, rx_cf_text);
768
769 static SOC_ENUM_SINGLE_DECL(cf_int0_2_enum, WCD934X_CDC_RX0_RX_PATH_MIX_CFG, 2,
770 rx_cf_text);
771
772 static const struct soc_enum cf_int1_1_enum =
773 SOC_ENUM_SINGLE(WCD934X_CDC_RX1_RX_PATH_CFG2, 0, 4, rx_cf_text);
774
775 static SOC_ENUM_SINGLE_DECL(cf_int1_2_enum, WCD934X_CDC_RX1_RX_PATH_MIX_CFG, 2,
776 rx_cf_text);
777
778 static const struct soc_enum cf_int2_1_enum =
779 SOC_ENUM_SINGLE(WCD934X_CDC_RX2_RX_PATH_CFG2, 0, 4, rx_cf_text);
780
781 static SOC_ENUM_SINGLE_DECL(cf_int2_2_enum, WCD934X_CDC_RX2_RX_PATH_MIX_CFG, 2,
782 rx_cf_text);
783
784 static const struct soc_enum cf_int3_1_enum =
785 SOC_ENUM_SINGLE(WCD934X_CDC_RX3_RX_PATH_CFG2, 0, 4, rx_cf_text);
786
787 static SOC_ENUM_SINGLE_DECL(cf_int3_2_enum, WCD934X_CDC_RX3_RX_PATH_MIX_CFG, 2,
788 rx_cf_text);
789
790 static const struct soc_enum cf_int4_1_enum =
791 SOC_ENUM_SINGLE(WCD934X_CDC_RX4_RX_PATH_CFG2, 0, 4, rx_cf_text);
792
793 static SOC_ENUM_SINGLE_DECL(cf_int4_2_enum, WCD934X_CDC_RX4_RX_PATH_MIX_CFG, 2,
794 rx_cf_text);
795
796 static const struct soc_enum cf_int7_1_enum =
797 SOC_ENUM_SINGLE(WCD934X_CDC_RX7_RX_PATH_CFG2, 0, 4, rx_cf_text);
798
799 static SOC_ENUM_SINGLE_DECL(cf_int7_2_enum, WCD934X_CDC_RX7_RX_PATH_MIX_CFG, 2,
800 rx_cf_text);
801
802 static const struct soc_enum cf_int8_1_enum =
803 SOC_ENUM_SINGLE(WCD934X_CDC_RX8_RX_PATH_CFG2, 0, 4, rx_cf_text);
804
805 static SOC_ENUM_SINGLE_DECL(cf_int8_2_enum, WCD934X_CDC_RX8_RX_PATH_MIX_CFG, 2,
806 rx_cf_text);
807
808 static const struct soc_enum rx_hph_mode_mux_enum =
809 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
810 rx_hph_mode_mux_text);
811
812 static const struct soc_enum slim_rx_mux_enum =
813 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(slim_rx_mux_text), slim_rx_mux_text);
814
815 static const struct soc_enum rx_int0_2_mux_chain_enum =
816 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG1, 0, 10,
817 rx_int0_7_mix_mux_text);
818
819 static const struct soc_enum rx_int1_2_mux_chain_enum =
820 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG1, 0, 9,
821 rx_int_mix_mux_text);
822
823 static const struct soc_enum rx_int2_2_mux_chain_enum =
824 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG1, 0, 9,
825 rx_int_mix_mux_text);
826
827 static const struct soc_enum rx_int3_2_mux_chain_enum =
828 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG1, 0, 9,
829 rx_int_mix_mux_text);
830
831 static const struct soc_enum rx_int4_2_mux_chain_enum =
832 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG1, 0, 9,
833 rx_int_mix_mux_text);
834
835 static const struct soc_enum rx_int7_2_mux_chain_enum =
836 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG1, 0, 10,
837 rx_int0_7_mix_mux_text);
838
839 static const struct soc_enum rx_int8_2_mux_chain_enum =
840 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG1, 0, 9,
841 rx_int_mix_mux_text);
842
843 static const struct soc_enum rx_int0_1_mix_inp0_chain_enum =
844 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG0, 0, 13,
845 rx_prim_mix_text);
846
847 static const struct soc_enum rx_int0_1_mix_inp1_chain_enum =
848 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG0, 4, 13,
849 rx_prim_mix_text);
850
851 static const struct soc_enum rx_int0_1_mix_inp2_chain_enum =
852 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG1, 4, 13,
853 rx_prim_mix_text);
854
855 static const struct soc_enum rx_int1_1_mix_inp0_chain_enum =
856 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG0, 0, 13,
857 rx_prim_mix_text);
858
859 static const struct soc_enum rx_int1_1_mix_inp1_chain_enum =
860 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG0, 4, 13,
861 rx_prim_mix_text);
862
863 static const struct soc_enum rx_int1_1_mix_inp2_chain_enum =
864 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG1, 4, 13,
865 rx_prim_mix_text);
866
867 static const struct soc_enum rx_int2_1_mix_inp0_chain_enum =
868 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG0, 0, 13,
869 rx_prim_mix_text);
870
871 static const struct soc_enum rx_int2_1_mix_inp1_chain_enum =
872 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG0, 4, 13,
873 rx_prim_mix_text);
874
875 static const struct soc_enum rx_int2_1_mix_inp2_chain_enum =
876 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG1, 4, 13,
877 rx_prim_mix_text);
878
879 static const struct soc_enum rx_int3_1_mix_inp0_chain_enum =
880 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG0, 0, 13,
881 rx_prim_mix_text);
882
883 static const struct soc_enum rx_int3_1_mix_inp1_chain_enum =
884 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG0, 4, 13,
885 rx_prim_mix_text);
886
887 static const struct soc_enum rx_int3_1_mix_inp2_chain_enum =
888 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG1, 4, 13,
889 rx_prim_mix_text);
890
891 static const struct soc_enum rx_int4_1_mix_inp0_chain_enum =
892 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG0, 0, 13,
893 rx_prim_mix_text);
894
895 static const struct soc_enum rx_int4_1_mix_inp1_chain_enum =
896 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG0, 4, 13,
897 rx_prim_mix_text);
898
899 static const struct soc_enum rx_int4_1_mix_inp2_chain_enum =
900 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG1, 4, 13,
901 rx_prim_mix_text);
902
903 static const struct soc_enum rx_int7_1_mix_inp0_chain_enum =
904 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG0, 0, 13,
905 rx_prim_mix_text);
906
907 static const struct soc_enum rx_int7_1_mix_inp1_chain_enum =
908 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG0, 4, 13,
909 rx_prim_mix_text);
910
911 static const struct soc_enum rx_int7_1_mix_inp2_chain_enum =
912 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG1, 4, 13,
913 rx_prim_mix_text);
914
915 static const struct soc_enum rx_int8_1_mix_inp0_chain_enum =
916 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG0, 0, 13,
917 rx_prim_mix_text);
918
919 static const struct soc_enum rx_int8_1_mix_inp1_chain_enum =
920 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG0, 4, 13,
921 rx_prim_mix_text);
922
923 static const struct soc_enum rx_int8_1_mix_inp2_chain_enum =
924 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG1, 4, 13,
925 rx_prim_mix_text);
926
927 static const struct soc_enum rx_int0_mix2_inp_mux_enum =
928 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 0, 4,
929 rx_sidetone_mix_text);
930
931 static const struct soc_enum rx_int1_mix2_inp_mux_enum =
932 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 2, 4,
933 rx_sidetone_mix_text);
934
935 static const struct soc_enum rx_int2_mix2_inp_mux_enum =
936 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 4, 4,
937 rx_sidetone_mix_text);
938
939 static const struct soc_enum rx_int3_mix2_inp_mux_enum =
940 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 6, 4,
941 rx_sidetone_mix_text);
942
943 static const struct soc_enum rx_int4_mix2_inp_mux_enum =
944 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG1, 0, 4,
945 rx_sidetone_mix_text);
946
947 static const struct soc_enum rx_int7_mix2_inp_mux_enum =
948 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG1, 2, 4,
949 rx_sidetone_mix_text);
950
951 static const struct soc_enum iir0_inp0_mux_enum =
952 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG0,
953 0, 18, iir_inp_mux_text);
954
955 static const struct soc_enum iir0_inp1_mux_enum =
956 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG1,
957 0, 18, iir_inp_mux_text);
958
959 static const struct soc_enum iir0_inp2_mux_enum =
960 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG2,
961 0, 18, iir_inp_mux_text);
962
963 static const struct soc_enum iir0_inp3_mux_enum =
964 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG3,
965 0, 18, iir_inp_mux_text);
966
967 static const struct soc_enum iir1_inp0_mux_enum =
968 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG0,
969 0, 18, iir_inp_mux_text);
970
971 static const struct soc_enum iir1_inp1_mux_enum =
972 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG1,
973 0, 18, iir_inp_mux_text);
974
975 static const struct soc_enum iir1_inp2_mux_enum =
976 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG2,
977 0, 18, iir_inp_mux_text);
978
979 static const struct soc_enum iir1_inp3_mux_enum =
980 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG3,
981 0, 18, iir_inp_mux_text);
982
983 static const struct soc_enum rx_int0_dem_inp_mux_enum =
984 SOC_ENUM_SINGLE(WCD934X_CDC_RX0_RX_PATH_SEC0, 0,
985 ARRAY_SIZE(rx_int_dem_inp_mux_text),
986 rx_int_dem_inp_mux_text);
987
988 static const struct soc_enum rx_int1_dem_inp_mux_enum =
989 SOC_ENUM_SINGLE(WCD934X_CDC_RX1_RX_PATH_SEC0, 0,
990 ARRAY_SIZE(rx_int_dem_inp_mux_text),
991 rx_int_dem_inp_mux_text);
992
993 static const struct soc_enum rx_int2_dem_inp_mux_enum =
994 SOC_ENUM_SINGLE(WCD934X_CDC_RX2_RX_PATH_SEC0, 0,
995 ARRAY_SIZE(rx_int_dem_inp_mux_text),
996 rx_int_dem_inp_mux_text);
997
998 static const struct soc_enum tx_adc_mux0_enum =
999 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1, 0,
1000 ARRAY_SIZE(adc_mux_text), adc_mux_text);
1001 static const struct soc_enum tx_adc_mux1_enum =
1002 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 0,
1003 ARRAY_SIZE(adc_mux_text), adc_mux_text);
1004 static const struct soc_enum tx_adc_mux2_enum =
1005 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG1, 0,
1006 ARRAY_SIZE(adc_mux_text), adc_mux_text);
1007 static const struct soc_enum tx_adc_mux3_enum =
1008 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1, 0,
1009 ARRAY_SIZE(adc_mux_text), adc_mux_text);
1010 static const struct soc_enum tx_adc_mux4_enum =
1011 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1, 2,
1012 ARRAY_SIZE(adc_mux_text), adc_mux_text);
1013 static const struct soc_enum tx_adc_mux5_enum =
1014 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 2,
1015 ARRAY_SIZE(adc_mux_text), adc_mux_text);
1016 static const struct soc_enum tx_adc_mux6_enum =
1017 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG1, 2,
1018 ARRAY_SIZE(adc_mux_text), adc_mux_text);
1019 static const struct soc_enum tx_adc_mux7_enum =
1020 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1, 2,
1021 ARRAY_SIZE(adc_mux_text), adc_mux_text);
1022 static const struct soc_enum tx_adc_mux8_enum =
1023 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 4,
1024 ARRAY_SIZE(adc_mux_text), adc_mux_text);
1025
1026 static const struct soc_enum rx_int0_1_interp_mux_enum =
1027 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2,
1028 rx_int0_1_interp_mux_text);
1029
1030 static const struct soc_enum rx_int1_1_interp_mux_enum =
1031 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2,
1032 rx_int1_1_interp_mux_text);
1033
1034 static const struct soc_enum rx_int2_1_interp_mux_enum =
1035 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2,
1036 rx_int2_1_interp_mux_text);
1037
1038 static const struct soc_enum rx_int3_1_interp_mux_enum =
1039 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int3_1_interp_mux_text);
1040
1041 static const struct soc_enum rx_int4_1_interp_mux_enum =
1042 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int4_1_interp_mux_text);
1043
1044 static const struct soc_enum rx_int7_1_interp_mux_enum =
1045 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int7_1_interp_mux_text);
1046
1047 static const struct soc_enum rx_int8_1_interp_mux_enum =
1048 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int8_1_interp_mux_text);
1049
1050 static const struct soc_enum rx_int0_2_interp_mux_enum =
1051 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int0_2_interp_mux_text);
1052
1053 static const struct soc_enum rx_int1_2_interp_mux_enum =
1054 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int1_2_interp_mux_text);
1055
1056 static const struct soc_enum rx_int2_2_interp_mux_enum =
1057 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int2_2_interp_mux_text);
1058
1059 static const struct soc_enum rx_int3_2_interp_mux_enum =
1060 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int3_2_interp_mux_text);
1061
1062 static const struct soc_enum rx_int4_2_interp_mux_enum =
1063 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int4_2_interp_mux_text);
1064
1065 static const struct soc_enum rx_int7_2_interp_mux_enum =
1066 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int7_2_interp_mux_text);
1067
1068 static const struct soc_enum rx_int8_2_interp_mux_enum =
1069 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int8_2_interp_mux_text);
1070
1071 static const struct soc_enum tx_dmic_mux0_enum =
1072 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 3, 7,
1073 dmic_mux_text);
1074
1075 static const struct soc_enum tx_dmic_mux1_enum =
1076 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 3, 7,
1077 dmic_mux_text);
1078
1079 static const struct soc_enum tx_dmic_mux2_enum =
1080 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 3, 7,
1081 dmic_mux_text);
1082
1083 static const struct soc_enum tx_dmic_mux3_enum =
1084 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 3, 7,
1085 dmic_mux_text);
1086
1087 static const struct soc_enum tx_dmic_mux4_enum =
1088 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 3, 7,
1089 dmic_mux_text);
1090
1091 static const struct soc_enum tx_dmic_mux5_enum =
1092 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 3, 7,
1093 dmic_mux_text);
1094
1095 static const struct soc_enum tx_dmic_mux6_enum =
1096 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 3, 7,
1097 dmic_mux_text);
1098
1099 static const struct soc_enum tx_dmic_mux7_enum =
1100 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 3, 7,
1101 dmic_mux_text);
1102
1103 static const struct soc_enum tx_dmic_mux8_enum =
1104 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 3, 7,
1105 dmic_mux_text);
1106
1107 static const struct soc_enum tx_amic_mux0_enum =
1108 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 0, 5,
1109 amic_mux_text);
1110 static const struct soc_enum tx_amic_mux1_enum =
1111 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 0, 5,
1112 amic_mux_text);
1113 static const struct soc_enum tx_amic_mux2_enum =
1114 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 0, 5,
1115 amic_mux_text);
1116 static const struct soc_enum tx_amic_mux3_enum =
1117 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 0, 5,
1118 amic_mux_text);
1119 static const struct soc_enum tx_amic_mux4_enum =
1120 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 0, 5,
1121 amic_mux_text);
1122 static const struct soc_enum tx_amic_mux5_enum =
1123 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 0, 5,
1124 amic_mux_text);
1125 static const struct soc_enum tx_amic_mux6_enum =
1126 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 0, 5,
1127 amic_mux_text);
1128 static const struct soc_enum tx_amic_mux7_enum =
1129 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 0, 5,
1130 amic_mux_text);
1131 static const struct soc_enum tx_amic_mux8_enum =
1132 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 0, 5,
1133 amic_mux_text);
1134
1135 static const struct soc_enum tx_amic4_5_enum =
1136 SOC_ENUM_SINGLE(WCD934X_TX_NEW_AMIC_4_5_SEL, 7, 2, amic4_5_sel_text);
1137
1138 static const struct soc_enum cdc_if_tx0_mux_enum =
1139 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0, 0,
1140 ARRAY_SIZE(cdc_if_tx0_mux_text), cdc_if_tx0_mux_text);
1141 static const struct soc_enum cdc_if_tx1_mux_enum =
1142 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0, 2,
1143 ARRAY_SIZE(cdc_if_tx1_mux_text), cdc_if_tx1_mux_text);
1144 static const struct soc_enum cdc_if_tx2_mux_enum =
1145 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0, 4,
1146 ARRAY_SIZE(cdc_if_tx2_mux_text), cdc_if_tx2_mux_text);
1147 static const struct soc_enum cdc_if_tx3_mux_enum =
1148 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0, 6,
1149 ARRAY_SIZE(cdc_if_tx3_mux_text), cdc_if_tx3_mux_text);
1150 static const struct soc_enum cdc_if_tx4_mux_enum =
1151 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1, 0,
1152 ARRAY_SIZE(cdc_if_tx4_mux_text), cdc_if_tx4_mux_text);
1153 static const struct soc_enum cdc_if_tx5_mux_enum =
1154 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1, 2,
1155 ARRAY_SIZE(cdc_if_tx5_mux_text), cdc_if_tx5_mux_text);
1156 static const struct soc_enum cdc_if_tx6_mux_enum =
1157 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1, 4,
1158 ARRAY_SIZE(cdc_if_tx6_mux_text), cdc_if_tx6_mux_text);
1159 static const struct soc_enum cdc_if_tx7_mux_enum =
1160 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1, 6,
1161 ARRAY_SIZE(cdc_if_tx7_mux_text), cdc_if_tx7_mux_text);
1162 static const struct soc_enum cdc_if_tx8_mux_enum =
1163 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2, 0,
1164 ARRAY_SIZE(cdc_if_tx8_mux_text), cdc_if_tx8_mux_text);
1165 static const struct soc_enum cdc_if_tx9_mux_enum =
1166 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2, 2,
1167 ARRAY_SIZE(cdc_if_tx9_mux_text), cdc_if_tx9_mux_text);
1168 static const struct soc_enum cdc_if_tx10_mux_enum =
1169 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2, 4,
1170 ARRAY_SIZE(cdc_if_tx10_mux_text), cdc_if_tx10_mux_text);
1171 static const struct soc_enum cdc_if_tx11_inp1_mux_enum =
1172 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3, 0,
1173 ARRAY_SIZE(cdc_if_tx11_inp1_mux_text),
1174 cdc_if_tx11_inp1_mux_text);
1175 static const struct soc_enum cdc_if_tx11_mux_enum =
1176 SOC_ENUM_SINGLE(WCD934X_DATA_HUB_SB_TX11_INP_CFG, 0,
1177 ARRAY_SIZE(cdc_if_tx11_mux_text), cdc_if_tx11_mux_text);
1178 static const struct soc_enum cdc_if_tx13_inp1_mux_enum =
1179 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3, 4,
1180 ARRAY_SIZE(cdc_if_tx13_inp1_mux_text),
1181 cdc_if_tx13_inp1_mux_text);
1182 static const struct soc_enum cdc_if_tx13_mux_enum =
1183 SOC_ENUM_SINGLE(WCD934X_DATA_HUB_SB_TX13_INP_CFG, 0,
1184 ARRAY_SIZE(cdc_if_tx13_mux_text), cdc_if_tx13_mux_text);
1185
wcd934x_set_sido_input_src(struct wcd934x_codec * wcd,int sido_src)1186 static int wcd934x_set_sido_input_src(struct wcd934x_codec *wcd, int sido_src)
1187 {
1188 if (sido_src == wcd->sido_input_src)
1189 return 0;
1190
1191 if (sido_src == SIDO_SOURCE_INTERNAL) {
1192 regmap_update_bits(wcd->regmap, WCD934X_ANA_BUCK_CTL,
1193 WCD934X_ANA_BUCK_HI_ACCU_EN_MASK, 0);
1194 usleep_range(100, 110);
1195 regmap_update_bits(wcd->regmap, WCD934X_ANA_BUCK_CTL,
1196 WCD934X_ANA_BUCK_HI_ACCU_PRE_ENX_MASK, 0x0);
1197 usleep_range(100, 110);
1198 regmap_update_bits(wcd->regmap, WCD934X_ANA_RCO,
1199 WCD934X_ANA_RCO_BG_EN_MASK, 0);
1200 usleep_range(100, 110);
1201 regmap_update_bits(wcd->regmap, WCD934X_ANA_BUCK_CTL,
1202 WCD934X_ANA_BUCK_PRE_EN1_MASK,
1203 WCD934X_ANA_BUCK_PRE_EN1_ENABLE);
1204 usleep_range(100, 110);
1205 regmap_update_bits(wcd->regmap, WCD934X_ANA_BUCK_CTL,
1206 WCD934X_ANA_BUCK_PRE_EN2_MASK,
1207 WCD934X_ANA_BUCK_PRE_EN2_ENABLE);
1208 usleep_range(100, 110);
1209 regmap_update_bits(wcd->regmap, WCD934X_ANA_BUCK_CTL,
1210 WCD934X_ANA_BUCK_HI_ACCU_EN_MASK,
1211 WCD934X_ANA_BUCK_HI_ACCU_ENABLE);
1212 usleep_range(100, 110);
1213 } else if (sido_src == SIDO_SOURCE_RCO_BG) {
1214 regmap_update_bits(wcd->regmap, WCD934X_ANA_RCO,
1215 WCD934X_ANA_RCO_BG_EN_MASK,
1216 WCD934X_ANA_RCO_BG_ENABLE);
1217 usleep_range(100, 110);
1218 }
1219 wcd->sido_input_src = sido_src;
1220
1221 return 0;
1222 }
1223
wcd934x_enable_ana_bias_and_sysclk(struct wcd934x_codec * wcd)1224 static int wcd934x_enable_ana_bias_and_sysclk(struct wcd934x_codec *wcd)
1225 {
1226 mutex_lock(&wcd->sysclk_mutex);
1227
1228 if (++wcd->sysclk_users != 1) {
1229 mutex_unlock(&wcd->sysclk_mutex);
1230 return 0;
1231 }
1232 mutex_unlock(&wcd->sysclk_mutex);
1233
1234 regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
1235 WCD934X_ANA_BIAS_EN_MASK,
1236 WCD934X_ANA_BIAS_EN);
1237 regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
1238 WCD934X_ANA_PRECHRG_EN_MASK,
1239 WCD934X_ANA_PRECHRG_EN);
1240 /*
1241 * 1ms delay is required after pre-charge is enabled
1242 * as per HW requirement
1243 */
1244 usleep_range(1000, 1100);
1245 regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
1246 WCD934X_ANA_PRECHRG_EN_MASK, 0);
1247 regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
1248 WCD934X_ANA_PRECHRG_MODE_MASK, 0);
1249
1250 /*
1251 * In data clock contrl register is changed
1252 * to CLK_SYS_MCLK_PRG
1253 */
1254
1255 regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG,
1256 WCD934X_EXT_CLK_BUF_EN_MASK,
1257 WCD934X_EXT_CLK_BUF_EN);
1258 regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG,
1259 WCD934X_EXT_CLK_DIV_RATIO_MASK,
1260 WCD934X_EXT_CLK_DIV_BY_2);
1261 regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG,
1262 WCD934X_MCLK_SRC_MASK,
1263 WCD934X_MCLK_SRC_EXT_CLK);
1264 regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG,
1265 WCD934X_MCLK_EN_MASK, WCD934X_MCLK_EN);
1266 regmap_update_bits(wcd->regmap,
1267 WCD934X_CDC_CLK_RST_CTRL_FS_CNT_CONTROL,
1268 WCD934X_CDC_FS_MCLK_CNT_EN_MASK,
1269 WCD934X_CDC_FS_MCLK_CNT_ENABLE);
1270 regmap_update_bits(wcd->regmap,
1271 WCD934X_CDC_CLK_RST_CTRL_MCLK_CONTROL,
1272 WCD934X_MCLK_EN_MASK,
1273 WCD934X_MCLK_EN);
1274 regmap_update_bits(wcd->regmap, WCD934X_CODEC_RPM_CLK_GATE,
1275 WCD934X_CODEC_RPM_CLK_GATE_MASK, 0x0);
1276 /*
1277 * 10us sleep is required after clock is enabled
1278 * as per HW requirement
1279 */
1280 usleep_range(10, 15);
1281
1282 wcd934x_set_sido_input_src(wcd, SIDO_SOURCE_RCO_BG);
1283
1284 return 0;
1285 }
1286
wcd934x_disable_ana_bias_and_syclk(struct wcd934x_codec * wcd)1287 static int wcd934x_disable_ana_bias_and_syclk(struct wcd934x_codec *wcd)
1288 {
1289 mutex_lock(&wcd->sysclk_mutex);
1290 if (--wcd->sysclk_users != 0) {
1291 mutex_unlock(&wcd->sysclk_mutex);
1292 return 0;
1293 }
1294 mutex_unlock(&wcd->sysclk_mutex);
1295
1296 regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG,
1297 WCD934X_EXT_CLK_BUF_EN_MASK |
1298 WCD934X_MCLK_EN_MASK, 0x0);
1299 wcd934x_set_sido_input_src(wcd, SIDO_SOURCE_INTERNAL);
1300
1301 regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
1302 WCD934X_ANA_BIAS_EN_MASK, 0);
1303 regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
1304 WCD934X_ANA_PRECHRG_EN_MASK, 0);
1305
1306 return 0;
1307 }
1308
__wcd934x_cdc_mclk_enable(struct wcd934x_codec * wcd,bool enable)1309 static int __wcd934x_cdc_mclk_enable(struct wcd934x_codec *wcd, bool enable)
1310 {
1311 int ret = 0;
1312
1313 if (enable) {
1314 ret = clk_prepare_enable(wcd->extclk);
1315
1316 if (ret) {
1317 dev_err(wcd->dev, "%s: ext clk enable failed\n",
1318 __func__);
1319 return ret;
1320 }
1321 ret = wcd934x_enable_ana_bias_and_sysclk(wcd);
1322 } else {
1323 int val;
1324
1325 regmap_read(wcd->regmap, WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL,
1326 &val);
1327
1328 /* Don't disable clock if soundwire using it.*/
1329 if (val & WCD934X_CDC_SWR_CLK_EN_MASK)
1330 return 0;
1331
1332 wcd934x_disable_ana_bias_and_syclk(wcd);
1333 clk_disable_unprepare(wcd->extclk);
1334 }
1335
1336 return ret;
1337 }
1338
wcd934x_codec_enable_mclk(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)1339 static int wcd934x_codec_enable_mclk(struct snd_soc_dapm_widget *w,
1340 struct snd_kcontrol *kc, int event)
1341 {
1342 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
1343 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
1344
1345 switch (event) {
1346 case SND_SOC_DAPM_PRE_PMU:
1347 return __wcd934x_cdc_mclk_enable(wcd, true);
1348 case SND_SOC_DAPM_POST_PMD:
1349 return __wcd934x_cdc_mclk_enable(wcd, false);
1350 }
1351
1352 return 0;
1353 }
1354
wcd934x_get_version(struct wcd934x_codec * wcd)1355 static int wcd934x_get_version(struct wcd934x_codec *wcd)
1356 {
1357 int val1, val2, ver, ret;
1358 struct regmap *regmap;
1359 u16 id_minor;
1360 u32 version_mask = 0;
1361
1362 regmap = wcd->regmap;
1363 ver = 0;
1364
1365 ret = regmap_bulk_read(regmap, WCD934X_CHIP_TIER_CTRL_CHIP_ID_BYTE0,
1366 (u8 *)&id_minor, sizeof(u16));
1367
1368 if (ret)
1369 return ret;
1370
1371 regmap_read(regmap, WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT14, &val1);
1372 regmap_read(regmap, WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT15, &val2);
1373
1374 version_mask |= (!!((u8)val1 & 0x80)) << DSD_DISABLED_MASK;
1375 version_mask |= (!!((u8)val2 & 0x01)) << SLNQ_DISABLED_MASK;
1376
1377 switch (version_mask) {
1378 case DSD_DISABLED | SLNQ_DISABLED:
1379 if (id_minor == 0)
1380 ver = WCD_VERSION_WCD9340_1_0;
1381 else if (id_minor == 0x01)
1382 ver = WCD_VERSION_WCD9340_1_1;
1383 break;
1384 case SLNQ_DISABLED:
1385 if (id_minor == 0)
1386 ver = WCD_VERSION_WCD9341_1_0;
1387 else if (id_minor == 0x01)
1388 ver = WCD_VERSION_WCD9341_1_1;
1389 break;
1390 }
1391
1392 wcd->version = ver;
1393 dev_info(wcd->dev, "WCD934X Minor:0x%x Version:0x%x\n", id_minor, ver);
1394
1395 return 0;
1396 }
1397
wcd934x_enable_efuse_sensing(struct wcd934x_codec * wcd)1398 static void wcd934x_enable_efuse_sensing(struct wcd934x_codec *wcd)
1399 {
1400 int rc, val;
1401
1402 __wcd934x_cdc_mclk_enable(wcd, true);
1403
1404 regmap_update_bits(wcd->regmap,
1405 WCD934X_CHIP_TIER_CTRL_EFUSE_CTL,
1406 WCD934X_EFUSE_SENSE_STATE_MASK,
1407 WCD934X_EFUSE_SENSE_STATE_DEF);
1408 regmap_update_bits(wcd->regmap,
1409 WCD934X_CHIP_TIER_CTRL_EFUSE_CTL,
1410 WCD934X_EFUSE_SENSE_EN_MASK,
1411 WCD934X_EFUSE_SENSE_ENABLE);
1412 /*
1413 * 5ms sleep required after enabling efuse control
1414 * before checking the status.
1415 */
1416 usleep_range(5000, 5500);
1417 wcd934x_set_sido_input_src(wcd, SIDO_SOURCE_RCO_BG);
1418
1419 rc = regmap_read(wcd->regmap,
1420 WCD934X_CHIP_TIER_CTRL_EFUSE_STATUS, &val);
1421 if (rc || (!(val & 0x01)))
1422 WARN(1, "%s: Efuse sense is not complete val=%x, ret=%d\n",
1423 __func__, val, rc);
1424
1425 __wcd934x_cdc_mclk_enable(wcd, false);
1426 }
1427
wcd934x_swrm_clock(struct wcd934x_codec * wcd,bool enable)1428 static int wcd934x_swrm_clock(struct wcd934x_codec *wcd, bool enable)
1429 {
1430 if (enable) {
1431 __wcd934x_cdc_mclk_enable(wcd, true);
1432 regmap_update_bits(wcd->regmap,
1433 WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL,
1434 WCD934X_CDC_SWR_CLK_EN_MASK,
1435 WCD934X_CDC_SWR_CLK_ENABLE);
1436 } else {
1437 regmap_update_bits(wcd->regmap,
1438 WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL,
1439 WCD934X_CDC_SWR_CLK_EN_MASK, 0);
1440 __wcd934x_cdc_mclk_enable(wcd, false);
1441 }
1442
1443 return 0;
1444 }
1445
wcd934x_set_prim_interpolator_rate(struct snd_soc_dai * dai,u8 rate_val,u32 rate)1446 static int wcd934x_set_prim_interpolator_rate(struct snd_soc_dai *dai,
1447 u8 rate_val, u32 rate)
1448 {
1449 struct snd_soc_component *comp = dai->component;
1450 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
1451 struct wcd934x_slim_ch *ch;
1452 u8 cfg0, cfg1, inp0_sel, inp1_sel, inp2_sel;
1453 int inp, j;
1454
1455 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) {
1456 inp = ch->shift + INTn_1_INP_SEL_RX0;
1457 /*
1458 * Loop through all interpolator MUX inputs and find out
1459 * to which interpolator input, the slim rx port
1460 * is connected
1461 */
1462 for (j = 0; j < WCD934X_NUM_INTERPOLATORS; j++) {
1463 /* Interpolators 5 and 6 are not aviliable in Tavil */
1464 if (j == INTERP_LO3_NA || j == INTERP_LO4_NA)
1465 continue;
1466
1467 cfg0 = snd_soc_component_read(comp,
1468 WCD934X_CDC_RX_INP_MUX_RX_INT_CFG0(j));
1469 cfg1 = snd_soc_component_read(comp,
1470 WCD934X_CDC_RX_INP_MUX_RX_INT_CFG1(j));
1471
1472 inp0_sel = cfg0 &
1473 WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
1474 inp1_sel = (cfg0 >> 4) &
1475 WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
1476 inp2_sel = (cfg1 >> 4) &
1477 WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
1478
1479 if ((inp0_sel == inp) || (inp1_sel == inp) ||
1480 (inp2_sel == inp)) {
1481 /* rate is in Hz */
1482 /*
1483 * Ear and speaker primary path does not support
1484 * native sample rates
1485 */
1486 if ((j == INTERP_EAR || j == INTERP_SPKR1 ||
1487 j == INTERP_SPKR2) && rate == 44100)
1488 dev_err(wcd->dev,
1489 "Cannot set 44.1KHz on INT%d\n",
1490 j);
1491 else
1492 snd_soc_component_update_bits(comp,
1493 WCD934X_CDC_RX_PATH_CTL(j),
1494 WCD934X_CDC_MIX_PCM_RATE_MASK,
1495 rate_val);
1496 }
1497 }
1498 }
1499
1500 return 0;
1501 }
1502
wcd934x_set_mix_interpolator_rate(struct snd_soc_dai * dai,int rate_val,u32 rate)1503 static int wcd934x_set_mix_interpolator_rate(struct snd_soc_dai *dai,
1504 int rate_val, u32 rate)
1505 {
1506 struct snd_soc_component *component = dai->component;
1507 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
1508 struct wcd934x_slim_ch *ch;
1509 int val, j;
1510
1511 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) {
1512 for (j = 0; j < WCD934X_NUM_INTERPOLATORS; j++) {
1513 /* Interpolators 5 and 6 are not aviliable in Tavil */
1514 if (j == INTERP_LO3_NA || j == INTERP_LO4_NA)
1515 continue;
1516 val = snd_soc_component_read(component,
1517 WCD934X_CDC_RX_INP_MUX_RX_INT_CFG1(j)) &
1518 WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
1519
1520 if (val == (ch->shift + INTn_2_INP_SEL_RX0)) {
1521 /*
1522 * Ear mix path supports only 48, 96, 192,
1523 * 384KHz only
1524 */
1525 if ((j == INTERP_EAR) &&
1526 (rate_val < 0x4 ||
1527 rate_val > 0x7)) {
1528 dev_err(component->dev,
1529 "Invalid rate for AIF_PB DAI(%d)\n",
1530 dai->id);
1531 return -EINVAL;
1532 }
1533
1534 snd_soc_component_update_bits(component,
1535 WCD934X_CDC_RX_PATH_MIX_CTL(j),
1536 WCD934X_CDC_MIX_PCM_RATE_MASK,
1537 rate_val);
1538 }
1539 }
1540 }
1541
1542 return 0;
1543 }
1544
wcd934x_set_interpolator_rate(struct snd_soc_dai * dai,u32 sample_rate)1545 static int wcd934x_set_interpolator_rate(struct snd_soc_dai *dai,
1546 u32 sample_rate)
1547 {
1548 int rate_val = 0;
1549 int i, ret;
1550
1551 for (i = 0; i < ARRAY_SIZE(sr_val_tbl); i++) {
1552 if (sample_rate == sr_val_tbl[i].sample_rate) {
1553 rate_val = sr_val_tbl[i].rate_val;
1554 break;
1555 }
1556 }
1557 if ((i == ARRAY_SIZE(sr_val_tbl)) || (rate_val < 0)) {
1558 dev_err(dai->dev, "Unsupported sample rate: %d\n", sample_rate);
1559 return -EINVAL;
1560 }
1561
1562 ret = wcd934x_set_prim_interpolator_rate(dai, (u8)rate_val,
1563 sample_rate);
1564 if (ret)
1565 return ret;
1566 ret = wcd934x_set_mix_interpolator_rate(dai, (u8)rate_val,
1567 sample_rate);
1568
1569 return ret;
1570 }
1571
wcd934x_set_decimator_rate(struct snd_soc_dai * dai,u8 rate_val,u32 rate)1572 static int wcd934x_set_decimator_rate(struct snd_soc_dai *dai,
1573 u8 rate_val, u32 rate)
1574 {
1575 struct snd_soc_component *comp = dai->component;
1576 struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(comp);
1577 u8 shift = 0, shift_val = 0, tx_mux_sel;
1578 struct wcd934x_slim_ch *ch;
1579 int tx_port, tx_port_reg;
1580 int decimator = -1;
1581
1582 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) {
1583 tx_port = ch->port;
1584 /* Find the SB TX MUX input - which decimator is connected */
1585 switch (tx_port) {
1586 case 0 ... 3:
1587 tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0;
1588 shift = (tx_port << 1);
1589 shift_val = 0x03;
1590 break;
1591 case 4 ... 7:
1592 tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1;
1593 shift = ((tx_port - 4) << 1);
1594 shift_val = 0x03;
1595 break;
1596 case 8 ... 10:
1597 tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2;
1598 shift = ((tx_port - 8) << 1);
1599 shift_val = 0x03;
1600 break;
1601 case 11:
1602 tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3;
1603 shift = 0;
1604 shift_val = 0x0F;
1605 break;
1606 case 13:
1607 tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3;
1608 shift = 4;
1609 shift_val = 0x03;
1610 break;
1611 default:
1612 dev_err(wcd->dev, "Invalid SLIM TX%u port DAI ID:%d\n",
1613 tx_port, dai->id);
1614 return -EINVAL;
1615 }
1616
1617 tx_mux_sel = snd_soc_component_read(comp, tx_port_reg) &
1618 (shift_val << shift);
1619
1620 tx_mux_sel = tx_mux_sel >> shift;
1621 switch (tx_port) {
1622 case 0 ... 8:
1623 if ((tx_mux_sel == 0x2) || (tx_mux_sel == 0x3))
1624 decimator = tx_port;
1625 break;
1626 case 9 ... 10:
1627 if ((tx_mux_sel == 0x1) || (tx_mux_sel == 0x2))
1628 decimator = ((tx_port == 9) ? 7 : 6);
1629 break;
1630 case 11:
1631 if ((tx_mux_sel >= 1) && (tx_mux_sel < 7))
1632 decimator = tx_mux_sel - 1;
1633 break;
1634 case 13:
1635 if ((tx_mux_sel == 0x1) || (tx_mux_sel == 0x2))
1636 decimator = 5;
1637 break;
1638 default:
1639 dev_err(wcd->dev, "ERROR: Invalid tx_port: %d\n",
1640 tx_port);
1641 return -EINVAL;
1642 }
1643
1644 snd_soc_component_update_bits(comp,
1645 WCD934X_CDC_TX_PATH_CTL(decimator),
1646 WCD934X_CDC_TX_PATH_CTL_PCM_RATE_MASK,
1647 rate_val);
1648 }
1649
1650 return 0;
1651 }
1652
wcd934x_slim_set_hw_params(struct wcd934x_codec * wcd,struct wcd_slim_codec_dai_data * dai_data,int direction)1653 static int wcd934x_slim_set_hw_params(struct wcd934x_codec *wcd,
1654 struct wcd_slim_codec_dai_data *dai_data,
1655 int direction)
1656 {
1657 struct list_head *slim_ch_list = &dai_data->slim_ch_list;
1658 struct slim_stream_config *cfg = &dai_data->sconfig;
1659 struct wcd934x_slim_ch *ch;
1660 u16 payload = 0;
1661 int ret, i;
1662
1663 cfg->ch_count = 0;
1664 cfg->direction = direction;
1665 cfg->port_mask = 0;
1666
1667 /* Configure slave interface device */
1668 list_for_each_entry(ch, slim_ch_list, list) {
1669 cfg->ch_count++;
1670 payload |= 1 << ch->shift;
1671 cfg->port_mask |= BIT(ch->port);
1672 }
1673
1674 cfg->chs = kcalloc(cfg->ch_count, sizeof(unsigned int), GFP_KERNEL);
1675 if (!cfg->chs)
1676 return -ENOMEM;
1677
1678 i = 0;
1679 list_for_each_entry(ch, slim_ch_list, list) {
1680 cfg->chs[i++] = ch->ch_num;
1681 if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
1682 /* write to interface device */
1683 ret = regmap_write(wcd->if_regmap,
1684 WCD934X_SLIM_PGD_RX_PORT_MULTI_CHNL_0(ch->port),
1685 payload);
1686
1687 if (ret < 0)
1688 goto err;
1689
1690 /* configure the slave port for water mark and enable*/
1691 ret = regmap_write(wcd->if_regmap,
1692 WCD934X_SLIM_PGD_RX_PORT_CFG(ch->port),
1693 WCD934X_SLIM_WATER_MARK_VAL);
1694 if (ret < 0)
1695 goto err;
1696 } else {
1697 ret = regmap_write(wcd->if_regmap,
1698 WCD934X_SLIM_PGD_TX_PORT_MULTI_CHNL_0(ch->port),
1699 payload & 0x00FF);
1700 if (ret < 0)
1701 goto err;
1702
1703 /* ports 8,9 */
1704 ret = regmap_write(wcd->if_regmap,
1705 WCD934X_SLIM_PGD_TX_PORT_MULTI_CHNL_1(ch->port),
1706 (payload & 0xFF00) >> 8);
1707 if (ret < 0)
1708 goto err;
1709
1710 /* configure the slave port for water mark and enable*/
1711 ret = regmap_write(wcd->if_regmap,
1712 WCD934X_SLIM_PGD_TX_PORT_CFG(ch->port),
1713 WCD934X_SLIM_WATER_MARK_VAL);
1714
1715 if (ret < 0)
1716 goto err;
1717 }
1718 }
1719
1720 dai_data->sruntime = slim_stream_allocate(wcd->sdev, "WCD934x-SLIM");
1721
1722 return 0;
1723
1724 err:
1725 dev_err(wcd->dev, "Error Setting slim hw params\n");
1726 kfree(cfg->chs);
1727 cfg->chs = NULL;
1728
1729 return ret;
1730 }
1731
wcd934x_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)1732 static int wcd934x_hw_params(struct snd_pcm_substream *substream,
1733 struct snd_pcm_hw_params *params,
1734 struct snd_soc_dai *dai)
1735 {
1736 struct wcd934x_codec *wcd;
1737 int ret, tx_fs_rate = 0;
1738
1739 wcd = snd_soc_component_get_drvdata(dai->component);
1740
1741 switch (substream->stream) {
1742 case SNDRV_PCM_STREAM_PLAYBACK:
1743 ret = wcd934x_set_interpolator_rate(dai, params_rate(params));
1744 if (ret) {
1745 dev_err(wcd->dev, "cannot set sample rate: %u\n",
1746 params_rate(params));
1747 return ret;
1748 }
1749 switch (params_width(params)) {
1750 case 16 ... 24:
1751 wcd->dai[dai->id].sconfig.bps = params_width(params);
1752 break;
1753 default:
1754 dev_err(wcd->dev, "Invalid format 0x%x\n",
1755 params_width(params));
1756 return -EINVAL;
1757 }
1758 break;
1759
1760 case SNDRV_PCM_STREAM_CAPTURE:
1761 switch (params_rate(params)) {
1762 case 8000:
1763 tx_fs_rate = 0;
1764 break;
1765 case 16000:
1766 tx_fs_rate = 1;
1767 break;
1768 case 32000:
1769 tx_fs_rate = 3;
1770 break;
1771 case 48000:
1772 tx_fs_rate = 4;
1773 break;
1774 case 96000:
1775 tx_fs_rate = 5;
1776 break;
1777 case 192000:
1778 tx_fs_rate = 6;
1779 break;
1780 case 384000:
1781 tx_fs_rate = 7;
1782 break;
1783 default:
1784 dev_err(wcd->dev, "Invalid TX sample rate: %d\n",
1785 params_rate(params));
1786 return -EINVAL;
1787
1788 }
1789
1790 ret = wcd934x_set_decimator_rate(dai, tx_fs_rate,
1791 params_rate(params));
1792 if (ret < 0) {
1793 dev_err(wcd->dev, "Cannot set TX Decimator rate\n");
1794 return ret;
1795 }
1796 switch (params_width(params)) {
1797 case 16 ... 32:
1798 wcd->dai[dai->id].sconfig.bps = params_width(params);
1799 break;
1800 default:
1801 dev_err(wcd->dev, "Invalid format 0x%x\n",
1802 params_width(params));
1803 return -EINVAL;
1804 }
1805 break;
1806 default:
1807 dev_err(wcd->dev, "Invalid stream type %d\n",
1808 substream->stream);
1809 return -EINVAL;
1810 }
1811
1812 wcd->dai[dai->id].sconfig.rate = params_rate(params);
1813 wcd934x_slim_set_hw_params(wcd, &wcd->dai[dai->id], substream->stream);
1814
1815 return 0;
1816 }
1817
wcd934x_hw_free(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)1818 static int wcd934x_hw_free(struct snd_pcm_substream *substream,
1819 struct snd_soc_dai *dai)
1820 {
1821 struct wcd_slim_codec_dai_data *dai_data;
1822 struct wcd934x_codec *wcd;
1823
1824 wcd = snd_soc_component_get_drvdata(dai->component);
1825
1826 dai_data = &wcd->dai[dai->id];
1827
1828 kfree(dai_data->sconfig.chs);
1829
1830 return 0;
1831 }
1832
wcd934x_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)1833 static int wcd934x_trigger(struct snd_pcm_substream *substream, int cmd,
1834 struct snd_soc_dai *dai)
1835 {
1836 struct wcd_slim_codec_dai_data *dai_data;
1837 struct wcd934x_codec *wcd;
1838 struct slim_stream_config *cfg;
1839
1840 wcd = snd_soc_component_get_drvdata(dai->component);
1841
1842 dai_data = &wcd->dai[dai->id];
1843
1844 switch (cmd) {
1845 case SNDRV_PCM_TRIGGER_START:
1846 case SNDRV_PCM_TRIGGER_RESUME:
1847 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1848 cfg = &dai_data->sconfig;
1849 slim_stream_prepare(dai_data->sruntime, cfg);
1850 slim_stream_enable(dai_data->sruntime);
1851 break;
1852 case SNDRV_PCM_TRIGGER_STOP:
1853 case SNDRV_PCM_TRIGGER_SUSPEND:
1854 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1855 slim_stream_unprepare(dai_data->sruntime);
1856 slim_stream_disable(dai_data->sruntime);
1857 break;
1858 default:
1859 break;
1860 }
1861
1862 return 0;
1863 }
1864
wcd934x_set_channel_map(struct snd_soc_dai * dai,unsigned int tx_num,unsigned int * tx_slot,unsigned int rx_num,unsigned int * rx_slot)1865 static int wcd934x_set_channel_map(struct snd_soc_dai *dai,
1866 unsigned int tx_num, unsigned int *tx_slot,
1867 unsigned int rx_num, unsigned int *rx_slot)
1868 {
1869 struct wcd934x_codec *wcd;
1870 int i;
1871
1872 wcd = snd_soc_component_get_drvdata(dai->component);
1873
1874 if (tx_num > WCD934X_TX_MAX || rx_num > WCD934X_RX_MAX) {
1875 dev_err(wcd->dev, "Invalid tx %d or rx %d channel count\n",
1876 tx_num, rx_num);
1877 return -EINVAL;
1878 }
1879
1880 if (!tx_slot || !rx_slot) {
1881 dev_err(wcd->dev, "Invalid tx_slot=%p, rx_slot=%p\n",
1882 tx_slot, rx_slot);
1883 return -EINVAL;
1884 }
1885
1886 wcd->num_rx_port = rx_num;
1887 for (i = 0; i < rx_num; i++) {
1888 wcd->rx_chs[i].ch_num = rx_slot[i];
1889 INIT_LIST_HEAD(&wcd->rx_chs[i].list);
1890 }
1891
1892 wcd->num_tx_port = tx_num;
1893 for (i = 0; i < tx_num; i++) {
1894 wcd->tx_chs[i].ch_num = tx_slot[i];
1895 INIT_LIST_HEAD(&wcd->tx_chs[i].list);
1896 }
1897
1898 return 0;
1899 }
1900
wcd934x_get_channel_map(struct snd_soc_dai * dai,unsigned int * tx_num,unsigned int * tx_slot,unsigned int * rx_num,unsigned int * rx_slot)1901 static int wcd934x_get_channel_map(struct snd_soc_dai *dai,
1902 unsigned int *tx_num, unsigned int *tx_slot,
1903 unsigned int *rx_num, unsigned int *rx_slot)
1904 {
1905 struct wcd934x_slim_ch *ch;
1906 struct wcd934x_codec *wcd;
1907 int i = 0;
1908
1909 wcd = snd_soc_component_get_drvdata(dai->component);
1910
1911 switch (dai->id) {
1912 case AIF1_PB:
1913 case AIF2_PB:
1914 case AIF3_PB:
1915 case AIF4_PB:
1916 if (!rx_slot || !rx_num) {
1917 dev_err(wcd->dev, "Invalid rx_slot %p or rx_num %p\n",
1918 rx_slot, rx_num);
1919 return -EINVAL;
1920 }
1921
1922 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list)
1923 rx_slot[i++] = ch->ch_num;
1924
1925 *rx_num = i;
1926 break;
1927 case AIF1_CAP:
1928 case AIF2_CAP:
1929 case AIF3_CAP:
1930 if (!tx_slot || !tx_num) {
1931 dev_err(wcd->dev, "Invalid tx_slot %p or tx_num %p\n",
1932 tx_slot, tx_num);
1933 return -EINVAL;
1934 }
1935
1936 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list)
1937 tx_slot[i++] = ch->ch_num;
1938
1939 *tx_num = i;
1940 break;
1941 default:
1942 dev_err(wcd->dev, "Invalid DAI ID %x\n", dai->id);
1943 break;
1944 }
1945
1946 return 0;
1947 }
1948
1949 static const struct snd_soc_dai_ops wcd934x_dai_ops = {
1950 .hw_params = wcd934x_hw_params,
1951 .hw_free = wcd934x_hw_free,
1952 .trigger = wcd934x_trigger,
1953 .set_channel_map = wcd934x_set_channel_map,
1954 .get_channel_map = wcd934x_get_channel_map,
1955 };
1956
1957 static struct snd_soc_dai_driver wcd934x_slim_dais[] = {
1958 [0] = {
1959 .name = "wcd934x_rx1",
1960 .id = AIF1_PB,
1961 .playback = {
1962 .stream_name = "AIF1 Playback",
1963 .rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK,
1964 .formats = WCD934X_FORMATS_S16_S24_LE,
1965 .rate_max = 192000,
1966 .rate_min = 8000,
1967 .channels_min = 1,
1968 .channels_max = 2,
1969 },
1970 .ops = &wcd934x_dai_ops,
1971 },
1972 [1] = {
1973 .name = "wcd934x_tx1",
1974 .id = AIF1_CAP,
1975 .capture = {
1976 .stream_name = "AIF1 Capture",
1977 .rates = WCD934X_RATES_MASK,
1978 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1979 .rate_min = 8000,
1980 .rate_max = 192000,
1981 .channels_min = 1,
1982 .channels_max = 4,
1983 },
1984 .ops = &wcd934x_dai_ops,
1985 },
1986 [2] = {
1987 .name = "wcd934x_rx2",
1988 .id = AIF2_PB,
1989 .playback = {
1990 .stream_name = "AIF2 Playback",
1991 .rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK,
1992 .formats = WCD934X_FORMATS_S16_S24_LE,
1993 .rate_min = 8000,
1994 .rate_max = 192000,
1995 .channels_min = 1,
1996 .channels_max = 2,
1997 },
1998 .ops = &wcd934x_dai_ops,
1999 },
2000 [3] = {
2001 .name = "wcd934x_tx2",
2002 .id = AIF2_CAP,
2003 .capture = {
2004 .stream_name = "AIF2 Capture",
2005 .rates = WCD934X_RATES_MASK,
2006 .formats = SNDRV_PCM_FMTBIT_S16_LE,
2007 .rate_min = 8000,
2008 .rate_max = 192000,
2009 .channels_min = 1,
2010 .channels_max = 4,
2011 },
2012 .ops = &wcd934x_dai_ops,
2013 },
2014 [4] = {
2015 .name = "wcd934x_rx3",
2016 .id = AIF3_PB,
2017 .playback = {
2018 .stream_name = "AIF3 Playback",
2019 .rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK,
2020 .formats = WCD934X_FORMATS_S16_S24_LE,
2021 .rate_min = 8000,
2022 .rate_max = 192000,
2023 .channels_min = 1,
2024 .channels_max = 2,
2025 },
2026 .ops = &wcd934x_dai_ops,
2027 },
2028 [5] = {
2029 .name = "wcd934x_tx3",
2030 .id = AIF3_CAP,
2031 .capture = {
2032 .stream_name = "AIF3 Capture",
2033 .rates = WCD934X_RATES_MASK,
2034 .formats = SNDRV_PCM_FMTBIT_S16_LE,
2035 .rate_min = 8000,
2036 .rate_max = 192000,
2037 .channels_min = 1,
2038 .channels_max = 4,
2039 },
2040 .ops = &wcd934x_dai_ops,
2041 },
2042 [6] = {
2043 .name = "wcd934x_rx4",
2044 .id = AIF4_PB,
2045 .playback = {
2046 .stream_name = "AIF4 Playback",
2047 .rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK,
2048 .formats = WCD934X_FORMATS_S16_S24_LE,
2049 .rate_min = 8000,
2050 .rate_max = 192000,
2051 .channels_min = 1,
2052 .channels_max = 2,
2053 },
2054 .ops = &wcd934x_dai_ops,
2055 },
2056 };
2057
swclk_gate_enable(struct clk_hw * hw)2058 static int swclk_gate_enable(struct clk_hw *hw)
2059 {
2060 return wcd934x_swrm_clock(to_wcd934x_codec(hw), true);
2061 }
2062
swclk_gate_disable(struct clk_hw * hw)2063 static void swclk_gate_disable(struct clk_hw *hw)
2064 {
2065 wcd934x_swrm_clock(to_wcd934x_codec(hw), false);
2066 }
2067
swclk_gate_is_enabled(struct clk_hw * hw)2068 static int swclk_gate_is_enabled(struct clk_hw *hw)
2069 {
2070 struct wcd934x_codec *wcd = to_wcd934x_codec(hw);
2071 int ret, val;
2072
2073 regmap_read(wcd->regmap, WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL, &val);
2074 ret = val & WCD934X_CDC_SWR_CLK_EN_MASK;
2075
2076 return ret;
2077 }
2078
swclk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)2079 static unsigned long swclk_recalc_rate(struct clk_hw *hw,
2080 unsigned long parent_rate)
2081 {
2082 return parent_rate / 2;
2083 }
2084
2085 static const struct clk_ops swclk_gate_ops = {
2086 .prepare = swclk_gate_enable,
2087 .unprepare = swclk_gate_disable,
2088 .is_enabled = swclk_gate_is_enabled,
2089 .recalc_rate = swclk_recalc_rate,
2090
2091 };
2092
wcd934x_register_mclk_output(struct wcd934x_codec * wcd)2093 static struct clk *wcd934x_register_mclk_output(struct wcd934x_codec *wcd)
2094 {
2095 struct clk *parent = wcd->extclk;
2096 struct device *dev = wcd->dev;
2097 struct device_node *np = dev->parent->of_node;
2098 const char *parent_clk_name = NULL;
2099 const char *clk_name = "mclk";
2100 struct clk_hw *hw;
2101 struct clk_init_data init;
2102 int ret;
2103
2104 if (of_property_read_u32(np, "clock-frequency", &wcd->rate))
2105 return NULL;
2106
2107 parent_clk_name = __clk_get_name(parent);
2108
2109 of_property_read_string(np, "clock-output-names", &clk_name);
2110
2111 init.name = clk_name;
2112 init.ops = &swclk_gate_ops;
2113 init.flags = 0;
2114 init.parent_names = &parent_clk_name;
2115 init.num_parents = 1;
2116 wcd->hw.init = &init;
2117
2118 hw = &wcd->hw;
2119 ret = devm_clk_hw_register(wcd->dev->parent, hw);
2120 if (ret)
2121 return ERR_PTR(ret);
2122
2123 ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw);
2124 if (ret)
2125 return ERR_PTR(ret);
2126
2127 return NULL;
2128 }
2129
wcd934x_get_micbias_val(struct device * dev,const char * micbias)2130 static int wcd934x_get_micbias_val(struct device *dev, const char *micbias)
2131 {
2132 int mv;
2133
2134 if (of_property_read_u32(dev->parent->of_node, micbias, &mv)) {
2135 dev_err(dev, "%s value not found, using default\n", micbias);
2136 mv = WCD934X_DEF_MICBIAS_MV;
2137 } else {
2138 /* convert it to milli volts */
2139 mv = mv/1000;
2140 }
2141
2142 if (mv < 1000 || mv > 2850) {
2143 dev_err(dev, "%s value not in valid range, using default\n",
2144 micbias);
2145 mv = WCD934X_DEF_MICBIAS_MV;
2146 }
2147
2148 return (mv - 1000) / 50;
2149 }
2150
wcd934x_init_dmic(struct snd_soc_component * comp)2151 static int wcd934x_init_dmic(struct snd_soc_component *comp)
2152 {
2153 int vout_ctl_1, vout_ctl_2, vout_ctl_3, vout_ctl_4;
2154 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
2155 u32 def_dmic_rate, dmic_clk_drv;
2156
2157 vout_ctl_1 = wcd934x_get_micbias_val(comp->dev,
2158 "qcom,micbias1-microvolt");
2159 vout_ctl_2 = wcd934x_get_micbias_val(comp->dev,
2160 "qcom,micbias2-microvolt");
2161 vout_ctl_3 = wcd934x_get_micbias_val(comp->dev,
2162 "qcom,micbias3-microvolt");
2163 vout_ctl_4 = wcd934x_get_micbias_val(comp->dev,
2164 "qcom,micbias4-microvolt");
2165
2166 snd_soc_component_update_bits(comp, WCD934X_ANA_MICB1,
2167 WCD934X_MICB_VAL_MASK, vout_ctl_1);
2168 snd_soc_component_update_bits(comp, WCD934X_ANA_MICB2,
2169 WCD934X_MICB_VAL_MASK, vout_ctl_2);
2170 snd_soc_component_update_bits(comp, WCD934X_ANA_MICB3,
2171 WCD934X_MICB_VAL_MASK, vout_ctl_3);
2172 snd_soc_component_update_bits(comp, WCD934X_ANA_MICB4,
2173 WCD934X_MICB_VAL_MASK, vout_ctl_4);
2174
2175 if (wcd->rate == WCD934X_MCLK_CLK_9P6MHZ)
2176 def_dmic_rate = WCD9XXX_DMIC_SAMPLE_RATE_4P8MHZ;
2177 else
2178 def_dmic_rate = WCD9XXX_DMIC_SAMPLE_RATE_4P096MHZ;
2179
2180 wcd->dmic_sample_rate = def_dmic_rate;
2181
2182 dmic_clk_drv = 0;
2183 snd_soc_component_update_bits(comp, WCD934X_TEST_DEBUG_PAD_DRVCTL_0,
2184 0x0C, dmic_clk_drv << 2);
2185
2186 return 0;
2187 }
2188
wcd934x_hw_init(struct wcd934x_codec * wcd)2189 static void wcd934x_hw_init(struct wcd934x_codec *wcd)
2190 {
2191 struct regmap *rm = wcd->regmap;
2192
2193 /* set SPKR rate to FS_2P4_3P072 */
2194 regmap_update_bits(rm, WCD934X_CDC_RX7_RX_PATH_CFG1, 0x08, 0x08);
2195 regmap_update_bits(rm, WCD934X_CDC_RX8_RX_PATH_CFG1, 0x08, 0x08);
2196
2197 /* Take DMICs out of reset */
2198 regmap_update_bits(rm, WCD934X_CPE_SS_DMIC_CFG, 0x80, 0x00);
2199 }
2200
wcd934x_comp_init(struct snd_soc_component * component)2201 static int wcd934x_comp_init(struct snd_soc_component *component)
2202 {
2203 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
2204
2205 wcd934x_hw_init(wcd);
2206 wcd934x_enable_efuse_sensing(wcd);
2207 wcd934x_get_version(wcd);
2208
2209 return 0;
2210 }
2211
wcd934x_slim_irq_handler(int irq,void * data)2212 static irqreturn_t wcd934x_slim_irq_handler(int irq, void *data)
2213 {
2214 struct wcd934x_codec *wcd = data;
2215 unsigned long status = 0;
2216 int i, j, port_id;
2217 unsigned int val, int_val = 0;
2218 irqreturn_t ret = IRQ_NONE;
2219 bool tx;
2220 unsigned short reg = 0;
2221
2222 for (i = WCD934X_SLIM_PGD_PORT_INT_STATUS_RX_0, j = 0;
2223 i <= WCD934X_SLIM_PGD_PORT_INT_STATUS_TX_1; i++, j++) {
2224 regmap_read(wcd->if_regmap, i, &val);
2225 status |= ((u32)val << (8 * j));
2226 }
2227
2228 for_each_set_bit(j, &status, 32) {
2229 tx = false;
2230 port_id = j;
2231
2232 if (j >= 16) {
2233 tx = true;
2234 port_id = j - 16;
2235 }
2236
2237 regmap_read(wcd->if_regmap,
2238 WCD934X_SLIM_PGD_PORT_INT_RX_SOURCE0 + j, &val);
2239 if (val) {
2240 if (!tx)
2241 reg = WCD934X_SLIM_PGD_PORT_INT_EN0 +
2242 (port_id / 8);
2243 else
2244 reg = WCD934X_SLIM_PGD_PORT_INT_TX_EN0 +
2245 (port_id / 8);
2246 regmap_read(wcd->if_regmap, reg, &int_val);
2247 }
2248
2249 if (val & WCD934X_SLIM_IRQ_OVERFLOW)
2250 dev_err_ratelimited(wcd->dev,
2251 "overflow error on %s port %d, value %x\n",
2252 (tx ? "TX" : "RX"), port_id, val);
2253
2254 if (val & WCD934X_SLIM_IRQ_UNDERFLOW)
2255 dev_err_ratelimited(wcd->dev,
2256 "underflow error on %s port %d, value %x\n",
2257 (tx ? "TX" : "RX"), port_id, val);
2258
2259 if ((val & WCD934X_SLIM_IRQ_OVERFLOW) ||
2260 (val & WCD934X_SLIM_IRQ_UNDERFLOW)) {
2261 if (!tx)
2262 reg = WCD934X_SLIM_PGD_PORT_INT_EN0 +
2263 (port_id / 8);
2264 else
2265 reg = WCD934X_SLIM_PGD_PORT_INT_TX_EN0 +
2266 (port_id / 8);
2267 regmap_read(
2268 wcd->if_regmap, reg, &int_val);
2269 if (int_val & (1 << (port_id % 8))) {
2270 int_val = int_val ^ (1 << (port_id % 8));
2271 regmap_write(wcd->if_regmap,
2272 reg, int_val);
2273 }
2274 }
2275
2276 if (val & WCD934X_SLIM_IRQ_PORT_CLOSED)
2277 dev_err_ratelimited(wcd->dev,
2278 "Port Closed %s port %d, value %x\n",
2279 (tx ? "TX" : "RX"), port_id, val);
2280
2281 regmap_write(wcd->if_regmap,
2282 WCD934X_SLIM_PGD_PORT_INT_CLR_RX_0 + (j / 8),
2283 BIT(j % 8));
2284 ret = IRQ_HANDLED;
2285 }
2286
2287 return ret;
2288 }
2289
wcd934x_comp_probe(struct snd_soc_component * component)2290 static int wcd934x_comp_probe(struct snd_soc_component *component)
2291 {
2292 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
2293 int i;
2294
2295 snd_soc_component_init_regmap(component, wcd->regmap);
2296 wcd->component = component;
2297
2298 /* Class-H Init*/
2299 wcd->clsh_ctrl = wcd_clsh_ctrl_alloc(component, wcd->version);
2300 if (IS_ERR(wcd->clsh_ctrl))
2301 return PTR_ERR(wcd->clsh_ctrl);
2302
2303 /* Default HPH Mode to Class-H Low HiFi */
2304 wcd->hph_mode = CLS_H_LOHIFI;
2305
2306 wcd934x_comp_init(component);
2307
2308 for (i = 0; i < NUM_CODEC_DAIS; i++)
2309 INIT_LIST_HEAD(&wcd->dai[i].slim_ch_list);
2310
2311 wcd934x_init_dmic(component);
2312 return 0;
2313 }
2314
wcd934x_comp_remove(struct snd_soc_component * comp)2315 static void wcd934x_comp_remove(struct snd_soc_component *comp)
2316 {
2317 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
2318
2319 wcd_clsh_ctrl_free(wcd->clsh_ctrl);
2320 }
2321
wcd934x_comp_set_sysclk(struct snd_soc_component * comp,int clk_id,int source,unsigned int freq,int dir)2322 static int wcd934x_comp_set_sysclk(struct snd_soc_component *comp,
2323 int clk_id, int source,
2324 unsigned int freq, int dir)
2325 {
2326 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
2327 int val = WCD934X_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ;
2328
2329 wcd->rate = freq;
2330
2331 if (wcd->rate == WCD934X_MCLK_CLK_12P288MHZ)
2332 val = WCD934X_CODEC_RPM_CLK_MCLK_CFG_12P288MHZ;
2333
2334 snd_soc_component_update_bits(comp, WCD934X_CODEC_RPM_CLK_MCLK_CFG,
2335 WCD934X_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK,
2336 val);
2337
2338 return clk_set_rate(wcd->extclk, freq);
2339 }
2340
get_iir_band_coeff(struct snd_soc_component * component,int iir_idx,int band_idx,int coeff_idx)2341 static uint32_t get_iir_band_coeff(struct snd_soc_component *component,
2342 int iir_idx, int band_idx, int coeff_idx)
2343 {
2344 u32 value = 0;
2345 int reg, b2_reg;
2346
2347 /* Address does not automatically update if reading */
2348 reg = WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B1_CTL + 16 * iir_idx;
2349 b2_reg = WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B2_CTL + 16 * iir_idx;
2350
2351 snd_soc_component_write(component, reg,
2352 ((band_idx * BAND_MAX + coeff_idx) *
2353 sizeof(uint32_t)) & 0x7F);
2354
2355 value |= snd_soc_component_read(component, b2_reg);
2356 snd_soc_component_write(component, reg,
2357 ((band_idx * BAND_MAX + coeff_idx)
2358 * sizeof(uint32_t) + 1) & 0x7F);
2359
2360 value |= (snd_soc_component_read(component, b2_reg) << 8);
2361 snd_soc_component_write(component, reg,
2362 ((band_idx * BAND_MAX + coeff_idx)
2363 * sizeof(uint32_t) + 2) & 0x7F);
2364
2365 value |= (snd_soc_component_read(component, b2_reg) << 16);
2366 snd_soc_component_write(component, reg,
2367 ((band_idx * BAND_MAX + coeff_idx)
2368 * sizeof(uint32_t) + 3) & 0x7F);
2369
2370 /* Mask bits top 2 bits since they are reserved */
2371 value |= (snd_soc_component_read(component, b2_reg) << 24);
2372 return value;
2373 }
2374
set_iir_band_coeff(struct snd_soc_component * component,int iir_idx,int band_idx,uint32_t value)2375 static void set_iir_band_coeff(struct snd_soc_component *component,
2376 int iir_idx, int band_idx, uint32_t value)
2377 {
2378 int reg = WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B2_CTL + 16 * iir_idx;
2379
2380 snd_soc_component_write(component, reg, (value & 0xFF));
2381 snd_soc_component_write(component, reg, (value >> 8) & 0xFF);
2382 snd_soc_component_write(component, reg, (value >> 16) & 0xFF);
2383 /* Mask top 2 bits, 7-8 are reserved */
2384 snd_soc_component_write(component, reg, (value >> 24) & 0x3F);
2385 }
2386
wcd934x_put_iir_band_audio_mixer(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2387 static int wcd934x_put_iir_band_audio_mixer(
2388 struct snd_kcontrol *kcontrol,
2389 struct snd_ctl_elem_value *ucontrol)
2390 {
2391 struct snd_soc_component *component =
2392 snd_soc_kcontrol_component(kcontrol);
2393 struct wcd_iir_filter_ctl *ctl =
2394 (struct wcd_iir_filter_ctl *)kcontrol->private_value;
2395 struct soc_bytes_ext *params = &ctl->bytes_ext;
2396 int iir_idx = ctl->iir_idx;
2397 int band_idx = ctl->band_idx;
2398 u32 coeff[BAND_MAX];
2399 int reg = WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B1_CTL + 16 * iir_idx;
2400
2401 memcpy(&coeff[0], ucontrol->value.bytes.data, params->max);
2402
2403 /* Mask top bit it is reserved */
2404 /* Updates addr automatically for each B2 write */
2405 snd_soc_component_write(component, reg, (band_idx * BAND_MAX *
2406 sizeof(uint32_t)) & 0x7F);
2407
2408 set_iir_band_coeff(component, iir_idx, band_idx, coeff[0]);
2409 set_iir_band_coeff(component, iir_idx, band_idx, coeff[1]);
2410 set_iir_band_coeff(component, iir_idx, band_idx, coeff[2]);
2411 set_iir_band_coeff(component, iir_idx, band_idx, coeff[3]);
2412 set_iir_band_coeff(component, iir_idx, band_idx, coeff[4]);
2413
2414 return 0;
2415 }
2416
wcd934x_get_iir_band_audio_mixer(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2417 static int wcd934x_get_iir_band_audio_mixer(struct snd_kcontrol *kcontrol,
2418 struct snd_ctl_elem_value *ucontrol)
2419 {
2420 struct snd_soc_component *component =
2421 snd_soc_kcontrol_component(kcontrol);
2422 struct wcd_iir_filter_ctl *ctl =
2423 (struct wcd_iir_filter_ctl *)kcontrol->private_value;
2424 struct soc_bytes_ext *params = &ctl->bytes_ext;
2425 int iir_idx = ctl->iir_idx;
2426 int band_idx = ctl->band_idx;
2427 u32 coeff[BAND_MAX];
2428
2429 coeff[0] = get_iir_band_coeff(component, iir_idx, band_idx, 0);
2430 coeff[1] = get_iir_band_coeff(component, iir_idx, band_idx, 1);
2431 coeff[2] = get_iir_band_coeff(component, iir_idx, band_idx, 2);
2432 coeff[3] = get_iir_band_coeff(component, iir_idx, band_idx, 3);
2433 coeff[4] = get_iir_band_coeff(component, iir_idx, band_idx, 4);
2434
2435 memcpy(ucontrol->value.bytes.data, &coeff[0], params->max);
2436
2437 return 0;
2438 }
2439
wcd934x_iir_filter_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * ucontrol)2440 static int wcd934x_iir_filter_info(struct snd_kcontrol *kcontrol,
2441 struct snd_ctl_elem_info *ucontrol)
2442 {
2443 struct wcd_iir_filter_ctl *ctl =
2444 (struct wcd_iir_filter_ctl *)kcontrol->private_value;
2445 struct soc_bytes_ext *params = &ctl->bytes_ext;
2446
2447 ucontrol->type = SNDRV_CTL_ELEM_TYPE_BYTES;
2448 ucontrol->count = params->max;
2449
2450 return 0;
2451 }
2452
wcd934x_compander_get(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)2453 static int wcd934x_compander_get(struct snd_kcontrol *kc,
2454 struct snd_ctl_elem_value *ucontrol)
2455 {
2456 struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
2457 int comp = ((struct soc_mixer_control *)kc->private_value)->shift;
2458 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
2459
2460 ucontrol->value.integer.value[0] = wcd->comp_enabled[comp];
2461
2462 return 0;
2463 }
2464
wcd934x_compander_set(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)2465 static int wcd934x_compander_set(struct snd_kcontrol *kc,
2466 struct snd_ctl_elem_value *ucontrol)
2467 {
2468 struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
2469 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
2470 int comp = ((struct soc_mixer_control *)kc->private_value)->shift;
2471 int value = ucontrol->value.integer.value[0];
2472 int sel;
2473
2474 wcd->comp_enabled[comp] = value;
2475 sel = value ? WCD934X_HPH_GAIN_SRC_SEL_COMPANDER :
2476 WCD934X_HPH_GAIN_SRC_SEL_REGISTER;
2477
2478 /* Any specific register configuration for compander */
2479 switch (comp) {
2480 case COMPANDER_1:
2481 /* Set Gain Source Select based on compander enable/disable */
2482 snd_soc_component_update_bits(component, WCD934X_HPH_L_EN,
2483 WCD934X_HPH_GAIN_SRC_SEL_MASK,
2484 sel);
2485 break;
2486 case COMPANDER_2:
2487 snd_soc_component_update_bits(component, WCD934X_HPH_R_EN,
2488 WCD934X_HPH_GAIN_SRC_SEL_MASK,
2489 sel);
2490 break;
2491 case COMPANDER_3:
2492 case COMPANDER_4:
2493 case COMPANDER_7:
2494 case COMPANDER_8:
2495 break;
2496 default:
2497 break;
2498 }
2499
2500 return 0;
2501 }
2502
wcd934x_rx_hph_mode_get(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)2503 static int wcd934x_rx_hph_mode_get(struct snd_kcontrol *kc,
2504 struct snd_ctl_elem_value *ucontrol)
2505 {
2506 struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
2507 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
2508
2509 ucontrol->value.enumerated.item[0] = wcd->hph_mode;
2510
2511 return 0;
2512 }
2513
wcd934x_rx_hph_mode_put(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)2514 static int wcd934x_rx_hph_mode_put(struct snd_kcontrol *kc,
2515 struct snd_ctl_elem_value *ucontrol)
2516 {
2517 struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
2518 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
2519 u32 mode_val;
2520
2521 mode_val = ucontrol->value.enumerated.item[0];
2522
2523 if (mode_val == 0) {
2524 dev_err(wcd->dev, "Invalid HPH Mode, default to ClSH HiFi\n");
2525 mode_val = CLS_H_LOHIFI;
2526 }
2527 wcd->hph_mode = mode_val;
2528
2529 return 0;
2530 }
2531
slim_rx_mux_get(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)2532 static int slim_rx_mux_get(struct snd_kcontrol *kc,
2533 struct snd_ctl_elem_value *ucontrol)
2534 {
2535 struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kc);
2536 struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kc);
2537 struct wcd934x_codec *wcd = dev_get_drvdata(dapm->dev);
2538
2539 ucontrol->value.enumerated.item[0] = wcd->rx_port_value[w->shift];
2540
2541 return 0;
2542 }
2543
slim_rx_mux_put(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)2544 static int slim_rx_mux_put(struct snd_kcontrol *kc,
2545 struct snd_ctl_elem_value *ucontrol)
2546 {
2547 struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kc);
2548 struct wcd934x_codec *wcd = dev_get_drvdata(w->dapm->dev);
2549 struct soc_enum *e = (struct soc_enum *)kc->private_value;
2550 struct snd_soc_dapm_update *update = NULL;
2551 u32 port_id = w->shift;
2552
2553 if (wcd->rx_port_value[port_id] == ucontrol->value.enumerated.item[0])
2554 return 0;
2555
2556 wcd->rx_port_value[port_id] = ucontrol->value.enumerated.item[0];
2557
2558 switch (wcd->rx_port_value[port_id]) {
2559 case 0:
2560 list_del_init(&wcd->rx_chs[port_id].list);
2561 break;
2562 case 1:
2563 list_add_tail(&wcd->rx_chs[port_id].list,
2564 &wcd->dai[AIF1_PB].slim_ch_list);
2565 break;
2566 case 2:
2567 list_add_tail(&wcd->rx_chs[port_id].list,
2568 &wcd->dai[AIF2_PB].slim_ch_list);
2569 break;
2570 case 3:
2571 list_add_tail(&wcd->rx_chs[port_id].list,
2572 &wcd->dai[AIF3_PB].slim_ch_list);
2573 break;
2574 case 4:
2575 list_add_tail(&wcd->rx_chs[port_id].list,
2576 &wcd->dai[AIF4_PB].slim_ch_list);
2577 break;
2578 default:
2579 dev_err(wcd->dev, "Unknown AIF %d\n",
2580 wcd->rx_port_value[port_id]);
2581 goto err;
2582 }
2583
2584 snd_soc_dapm_mux_update_power(w->dapm, kc, wcd->rx_port_value[port_id],
2585 e, update);
2586
2587 return 0;
2588 err:
2589 return -EINVAL;
2590 }
2591
wcd934x_int_dem_inp_mux_put(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)2592 static int wcd934x_int_dem_inp_mux_put(struct snd_kcontrol *kc,
2593 struct snd_ctl_elem_value *ucontrol)
2594 {
2595 struct soc_enum *e = (struct soc_enum *)kc->private_value;
2596 struct snd_soc_component *component;
2597 int reg, val, ret;
2598
2599 component = snd_soc_dapm_kcontrol_component(kc);
2600 val = ucontrol->value.enumerated.item[0];
2601 if (e->reg == WCD934X_CDC_RX0_RX_PATH_SEC0)
2602 reg = WCD934X_CDC_RX0_RX_PATH_CFG0;
2603 else if (e->reg == WCD934X_CDC_RX1_RX_PATH_SEC0)
2604 reg = WCD934X_CDC_RX1_RX_PATH_CFG0;
2605 else if (e->reg == WCD934X_CDC_RX2_RX_PATH_SEC0)
2606 reg = WCD934X_CDC_RX2_RX_PATH_CFG0;
2607 else
2608 return -EINVAL;
2609
2610 /* Set Look Ahead Delay */
2611 if (val)
2612 snd_soc_component_update_bits(component, reg,
2613 WCD934X_RX_DLY_ZN_EN_MASK,
2614 WCD934X_RX_DLY_ZN_ENABLE);
2615 else
2616 snd_soc_component_update_bits(component, reg,
2617 WCD934X_RX_DLY_ZN_EN_MASK,
2618 WCD934X_RX_DLY_ZN_DISABLE);
2619
2620 ret = snd_soc_dapm_put_enum_double(kc, ucontrol);
2621
2622 return ret;
2623 }
2624
wcd934x_dec_enum_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2625 static int wcd934x_dec_enum_put(struct snd_kcontrol *kcontrol,
2626 struct snd_ctl_elem_value *ucontrol)
2627 {
2628 struct snd_soc_component *comp;
2629 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
2630 unsigned int val;
2631 u16 mic_sel_reg = 0;
2632 u8 mic_sel;
2633
2634 comp = snd_soc_dapm_kcontrol_component(kcontrol);
2635
2636 val = ucontrol->value.enumerated.item[0];
2637 if (val > e->items - 1)
2638 return -EINVAL;
2639
2640 switch (e->reg) {
2641 case WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1:
2642 if (e->shift_l == 0)
2643 mic_sel_reg = WCD934X_CDC_TX0_TX_PATH_CFG0;
2644 else if (e->shift_l == 2)
2645 mic_sel_reg = WCD934X_CDC_TX4_TX_PATH_CFG0;
2646 else if (e->shift_l == 4)
2647 mic_sel_reg = WCD934X_CDC_TX8_TX_PATH_CFG0;
2648 break;
2649 case WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1:
2650 if (e->shift_l == 0)
2651 mic_sel_reg = WCD934X_CDC_TX1_TX_PATH_CFG0;
2652 else if (e->shift_l == 2)
2653 mic_sel_reg = WCD934X_CDC_TX5_TX_PATH_CFG0;
2654 break;
2655 case WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG1:
2656 if (e->shift_l == 0)
2657 mic_sel_reg = WCD934X_CDC_TX2_TX_PATH_CFG0;
2658 else if (e->shift_l == 2)
2659 mic_sel_reg = WCD934X_CDC_TX6_TX_PATH_CFG0;
2660 break;
2661 case WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1:
2662 if (e->shift_l == 0)
2663 mic_sel_reg = WCD934X_CDC_TX3_TX_PATH_CFG0;
2664 else if (e->shift_l == 2)
2665 mic_sel_reg = WCD934X_CDC_TX7_TX_PATH_CFG0;
2666 break;
2667 default:
2668 dev_err(comp->dev, "%s: e->reg: 0x%x not expected\n",
2669 __func__, e->reg);
2670 return -EINVAL;
2671 }
2672
2673 /* ADC: 0, DMIC: 1 */
2674 mic_sel = val ? 0x0 : 0x1;
2675 if (mic_sel_reg)
2676 snd_soc_component_update_bits(comp, mic_sel_reg, BIT(7),
2677 mic_sel << 7);
2678
2679 return snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
2680 }
2681
2682 static const struct snd_kcontrol_new rx_int0_2_mux =
2683 SOC_DAPM_ENUM("RX INT0_2 MUX Mux", rx_int0_2_mux_chain_enum);
2684
2685 static const struct snd_kcontrol_new rx_int1_2_mux =
2686 SOC_DAPM_ENUM("RX INT1_2 MUX Mux", rx_int1_2_mux_chain_enum);
2687
2688 static const struct snd_kcontrol_new rx_int2_2_mux =
2689 SOC_DAPM_ENUM("RX INT2_2 MUX Mux", rx_int2_2_mux_chain_enum);
2690
2691 static const struct snd_kcontrol_new rx_int3_2_mux =
2692 SOC_DAPM_ENUM("RX INT3_2 MUX Mux", rx_int3_2_mux_chain_enum);
2693
2694 static const struct snd_kcontrol_new rx_int4_2_mux =
2695 SOC_DAPM_ENUM("RX INT4_2 MUX Mux", rx_int4_2_mux_chain_enum);
2696
2697 static const struct snd_kcontrol_new rx_int7_2_mux =
2698 SOC_DAPM_ENUM("RX INT7_2 MUX Mux", rx_int7_2_mux_chain_enum);
2699
2700 static const struct snd_kcontrol_new rx_int8_2_mux =
2701 SOC_DAPM_ENUM("RX INT8_2 MUX Mux", rx_int8_2_mux_chain_enum);
2702
2703 static const struct snd_kcontrol_new rx_int0_1_mix_inp0_mux =
2704 SOC_DAPM_ENUM("RX INT0_1 MIX1 INP0 Mux", rx_int0_1_mix_inp0_chain_enum);
2705
2706 static const struct snd_kcontrol_new rx_int0_1_mix_inp1_mux =
2707 SOC_DAPM_ENUM("RX INT0_1 MIX1 INP1 Mux", rx_int0_1_mix_inp1_chain_enum);
2708
2709 static const struct snd_kcontrol_new rx_int0_1_mix_inp2_mux =
2710 SOC_DAPM_ENUM("RX INT0_1 MIX1 INP2 Mux", rx_int0_1_mix_inp2_chain_enum);
2711
2712 static const struct snd_kcontrol_new rx_int1_1_mix_inp0_mux =
2713 SOC_DAPM_ENUM("RX INT1_1 MIX1 INP0 Mux", rx_int1_1_mix_inp0_chain_enum);
2714
2715 static const struct snd_kcontrol_new rx_int1_1_mix_inp1_mux =
2716 SOC_DAPM_ENUM("RX INT1_1 MIX1 INP1 Mux", rx_int1_1_mix_inp1_chain_enum);
2717
2718 static const struct snd_kcontrol_new rx_int1_1_mix_inp2_mux =
2719 SOC_DAPM_ENUM("RX INT1_1 MIX1 INP2 Mux", rx_int1_1_mix_inp2_chain_enum);
2720
2721 static const struct snd_kcontrol_new rx_int2_1_mix_inp0_mux =
2722 SOC_DAPM_ENUM("RX INT2_1 MIX1 INP0 Mux", rx_int2_1_mix_inp0_chain_enum);
2723
2724 static const struct snd_kcontrol_new rx_int2_1_mix_inp1_mux =
2725 SOC_DAPM_ENUM("RX INT2_1 MIX1 INP1 Mux", rx_int2_1_mix_inp1_chain_enum);
2726
2727 static const struct snd_kcontrol_new rx_int2_1_mix_inp2_mux =
2728 SOC_DAPM_ENUM("RX INT2_1 MIX1 INP2 Mux", rx_int2_1_mix_inp2_chain_enum);
2729
2730 static const struct snd_kcontrol_new rx_int3_1_mix_inp0_mux =
2731 SOC_DAPM_ENUM("RX INT3_1 MIX1 INP0 Mux", rx_int3_1_mix_inp0_chain_enum);
2732
2733 static const struct snd_kcontrol_new rx_int3_1_mix_inp1_mux =
2734 SOC_DAPM_ENUM("RX INT3_1 MIX1 INP1 Mux", rx_int3_1_mix_inp1_chain_enum);
2735
2736 static const struct snd_kcontrol_new rx_int3_1_mix_inp2_mux =
2737 SOC_DAPM_ENUM("RX INT3_1 MIX1 INP2 Mux", rx_int3_1_mix_inp2_chain_enum);
2738
2739 static const struct snd_kcontrol_new rx_int4_1_mix_inp0_mux =
2740 SOC_DAPM_ENUM("RX INT4_1 MIX1 INP0 Mux", rx_int4_1_mix_inp0_chain_enum);
2741
2742 static const struct snd_kcontrol_new rx_int4_1_mix_inp1_mux =
2743 SOC_DAPM_ENUM("RX INT4_1 MIX1 INP1 Mux", rx_int4_1_mix_inp1_chain_enum);
2744
2745 static const struct snd_kcontrol_new rx_int4_1_mix_inp2_mux =
2746 SOC_DAPM_ENUM("RX INT4_1 MIX1 INP2 Mux", rx_int4_1_mix_inp2_chain_enum);
2747
2748 static const struct snd_kcontrol_new rx_int7_1_mix_inp0_mux =
2749 SOC_DAPM_ENUM("RX INT7_1 MIX1 INP0 Mux", rx_int7_1_mix_inp0_chain_enum);
2750
2751 static const struct snd_kcontrol_new rx_int7_1_mix_inp1_mux =
2752 SOC_DAPM_ENUM("RX INT7_1 MIX1 INP1 Mux", rx_int7_1_mix_inp1_chain_enum);
2753
2754 static const struct snd_kcontrol_new rx_int7_1_mix_inp2_mux =
2755 SOC_DAPM_ENUM("RX INT7_1 MIX1 INP2 Mux", rx_int7_1_mix_inp2_chain_enum);
2756
2757 static const struct snd_kcontrol_new rx_int8_1_mix_inp0_mux =
2758 SOC_DAPM_ENUM("RX INT8_1 MIX1 INP0 Mux", rx_int8_1_mix_inp0_chain_enum);
2759
2760 static const struct snd_kcontrol_new rx_int8_1_mix_inp1_mux =
2761 SOC_DAPM_ENUM("RX INT8_1 MIX1 INP1 Mux", rx_int8_1_mix_inp1_chain_enum);
2762
2763 static const struct snd_kcontrol_new rx_int8_1_mix_inp2_mux =
2764 SOC_DAPM_ENUM("RX INT8_1 MIX1 INP2 Mux", rx_int8_1_mix_inp2_chain_enum);
2765
2766 static const struct snd_kcontrol_new rx_int0_mix2_inp_mux =
2767 SOC_DAPM_ENUM("RX INT0 MIX2 INP Mux", rx_int0_mix2_inp_mux_enum);
2768
2769 static const struct snd_kcontrol_new rx_int1_mix2_inp_mux =
2770 SOC_DAPM_ENUM("RX INT1 MIX2 INP Mux", rx_int1_mix2_inp_mux_enum);
2771
2772 static const struct snd_kcontrol_new rx_int2_mix2_inp_mux =
2773 SOC_DAPM_ENUM("RX INT2 MIX2 INP Mux", rx_int2_mix2_inp_mux_enum);
2774
2775 static const struct snd_kcontrol_new rx_int3_mix2_inp_mux =
2776 SOC_DAPM_ENUM("RX INT3 MIX2 INP Mux", rx_int3_mix2_inp_mux_enum);
2777
2778 static const struct snd_kcontrol_new rx_int4_mix2_inp_mux =
2779 SOC_DAPM_ENUM("RX INT4 MIX2 INP Mux", rx_int4_mix2_inp_mux_enum);
2780
2781 static const struct snd_kcontrol_new rx_int7_mix2_inp_mux =
2782 SOC_DAPM_ENUM("RX INT7 MIX2 INP Mux", rx_int7_mix2_inp_mux_enum);
2783
2784 static const struct snd_kcontrol_new iir0_inp0_mux =
2785 SOC_DAPM_ENUM("IIR0 INP0 Mux", iir0_inp0_mux_enum);
2786 static const struct snd_kcontrol_new iir0_inp1_mux =
2787 SOC_DAPM_ENUM("IIR0 INP1 Mux", iir0_inp1_mux_enum);
2788 static const struct snd_kcontrol_new iir0_inp2_mux =
2789 SOC_DAPM_ENUM("IIR0 INP2 Mux", iir0_inp2_mux_enum);
2790 static const struct snd_kcontrol_new iir0_inp3_mux =
2791 SOC_DAPM_ENUM("IIR0 INP3 Mux", iir0_inp3_mux_enum);
2792
2793 static const struct snd_kcontrol_new iir1_inp0_mux =
2794 SOC_DAPM_ENUM("IIR1 INP0 Mux", iir1_inp0_mux_enum);
2795 static const struct snd_kcontrol_new iir1_inp1_mux =
2796 SOC_DAPM_ENUM("IIR1 INP1 Mux", iir1_inp1_mux_enum);
2797 static const struct snd_kcontrol_new iir1_inp2_mux =
2798 SOC_DAPM_ENUM("IIR1 INP2 Mux", iir1_inp2_mux_enum);
2799 static const struct snd_kcontrol_new iir1_inp3_mux =
2800 SOC_DAPM_ENUM("IIR1 INP3 Mux", iir1_inp3_mux_enum);
2801
2802 static const struct snd_kcontrol_new slim_rx_mux[WCD934X_RX_MAX] = {
2803 SOC_DAPM_ENUM_EXT("SLIM RX0 Mux", slim_rx_mux_enum,
2804 slim_rx_mux_get, slim_rx_mux_put),
2805 SOC_DAPM_ENUM_EXT("SLIM RX1 Mux", slim_rx_mux_enum,
2806 slim_rx_mux_get, slim_rx_mux_put),
2807 SOC_DAPM_ENUM_EXT("SLIM RX2 Mux", slim_rx_mux_enum,
2808 slim_rx_mux_get, slim_rx_mux_put),
2809 SOC_DAPM_ENUM_EXT("SLIM RX3 Mux", slim_rx_mux_enum,
2810 slim_rx_mux_get, slim_rx_mux_put),
2811 SOC_DAPM_ENUM_EXT("SLIM RX4 Mux", slim_rx_mux_enum,
2812 slim_rx_mux_get, slim_rx_mux_put),
2813 SOC_DAPM_ENUM_EXT("SLIM RX5 Mux", slim_rx_mux_enum,
2814 slim_rx_mux_get, slim_rx_mux_put),
2815 SOC_DAPM_ENUM_EXT("SLIM RX6 Mux", slim_rx_mux_enum,
2816 slim_rx_mux_get, slim_rx_mux_put),
2817 SOC_DAPM_ENUM_EXT("SLIM RX7 Mux", slim_rx_mux_enum,
2818 slim_rx_mux_get, slim_rx_mux_put),
2819 };
2820
2821 static const struct snd_kcontrol_new rx_int1_asrc_switch[] = {
2822 SOC_DAPM_SINGLE("HPHL Switch", SND_SOC_NOPM, 0, 1, 0),
2823 };
2824
2825 static const struct snd_kcontrol_new rx_int2_asrc_switch[] = {
2826 SOC_DAPM_SINGLE("HPHR Switch", SND_SOC_NOPM, 0, 1, 0),
2827 };
2828
2829 static const struct snd_kcontrol_new rx_int3_asrc_switch[] = {
2830 SOC_DAPM_SINGLE("LO1 Switch", SND_SOC_NOPM, 0, 1, 0),
2831 };
2832
2833 static const struct snd_kcontrol_new rx_int4_asrc_switch[] = {
2834 SOC_DAPM_SINGLE("LO2 Switch", SND_SOC_NOPM, 0, 1, 0),
2835 };
2836
2837 static const struct snd_kcontrol_new rx_int0_dem_inp_mux =
2838 SOC_DAPM_ENUM_EXT("RX INT0 DEM MUX Mux", rx_int0_dem_inp_mux_enum,
2839 snd_soc_dapm_get_enum_double,
2840 wcd934x_int_dem_inp_mux_put);
2841
2842 static const struct snd_kcontrol_new rx_int1_dem_inp_mux =
2843 SOC_DAPM_ENUM_EXT("RX INT1 DEM MUX Mux", rx_int1_dem_inp_mux_enum,
2844 snd_soc_dapm_get_enum_double,
2845 wcd934x_int_dem_inp_mux_put);
2846
2847 static const struct snd_kcontrol_new rx_int2_dem_inp_mux =
2848 SOC_DAPM_ENUM_EXT("RX INT2 DEM MUX Mux", rx_int2_dem_inp_mux_enum,
2849 snd_soc_dapm_get_enum_double,
2850 wcd934x_int_dem_inp_mux_put);
2851
2852 static const struct snd_kcontrol_new rx_int0_1_interp_mux =
2853 SOC_DAPM_ENUM("RX INT0_1 INTERP Mux", rx_int0_1_interp_mux_enum);
2854
2855 static const struct snd_kcontrol_new rx_int1_1_interp_mux =
2856 SOC_DAPM_ENUM("RX INT1_1 INTERP Mux", rx_int1_1_interp_mux_enum);
2857
2858 static const struct snd_kcontrol_new rx_int2_1_interp_mux =
2859 SOC_DAPM_ENUM("RX INT2_1 INTERP Mux", rx_int2_1_interp_mux_enum);
2860
2861 static const struct snd_kcontrol_new rx_int3_1_interp_mux =
2862 SOC_DAPM_ENUM("RX INT3_1 INTERP Mux", rx_int3_1_interp_mux_enum);
2863
2864 static const struct snd_kcontrol_new rx_int4_1_interp_mux =
2865 SOC_DAPM_ENUM("RX INT4_1 INTERP Mux", rx_int4_1_interp_mux_enum);
2866
2867 static const struct snd_kcontrol_new rx_int7_1_interp_mux =
2868 SOC_DAPM_ENUM("RX INT7_1 INTERP Mux", rx_int7_1_interp_mux_enum);
2869
2870 static const struct snd_kcontrol_new rx_int8_1_interp_mux =
2871 SOC_DAPM_ENUM("RX INT8_1 INTERP Mux", rx_int8_1_interp_mux_enum);
2872
2873 static const struct snd_kcontrol_new rx_int0_2_interp_mux =
2874 SOC_DAPM_ENUM("RX INT0_2 INTERP Mux", rx_int0_2_interp_mux_enum);
2875
2876 static const struct snd_kcontrol_new rx_int1_2_interp_mux =
2877 SOC_DAPM_ENUM("RX INT1_2 INTERP Mux", rx_int1_2_interp_mux_enum);
2878
2879 static const struct snd_kcontrol_new rx_int2_2_interp_mux =
2880 SOC_DAPM_ENUM("RX INT2_2 INTERP Mux", rx_int2_2_interp_mux_enum);
2881
2882 static const struct snd_kcontrol_new rx_int3_2_interp_mux =
2883 SOC_DAPM_ENUM("RX INT3_2 INTERP Mux", rx_int3_2_interp_mux_enum);
2884
2885 static const struct snd_kcontrol_new rx_int4_2_interp_mux =
2886 SOC_DAPM_ENUM("RX INT4_2 INTERP Mux", rx_int4_2_interp_mux_enum);
2887
2888 static const struct snd_kcontrol_new rx_int7_2_interp_mux =
2889 SOC_DAPM_ENUM("RX INT7_2 INTERP Mux", rx_int7_2_interp_mux_enum);
2890
2891 static const struct snd_kcontrol_new rx_int8_2_interp_mux =
2892 SOC_DAPM_ENUM("RX INT8_2 INTERP Mux", rx_int8_2_interp_mux_enum);
2893
2894 static const struct snd_kcontrol_new tx_dmic_mux0 =
2895 SOC_DAPM_ENUM("DMIC MUX0 Mux", tx_dmic_mux0_enum);
2896
2897 static const struct snd_kcontrol_new tx_dmic_mux1 =
2898 SOC_DAPM_ENUM("DMIC MUX1 Mux", tx_dmic_mux1_enum);
2899
2900 static const struct snd_kcontrol_new tx_dmic_mux2 =
2901 SOC_DAPM_ENUM("DMIC MUX2 Mux", tx_dmic_mux2_enum);
2902
2903 static const struct snd_kcontrol_new tx_dmic_mux3 =
2904 SOC_DAPM_ENUM("DMIC MUX3 Mux", tx_dmic_mux3_enum);
2905
2906 static const struct snd_kcontrol_new tx_dmic_mux4 =
2907 SOC_DAPM_ENUM("DMIC MUX4 Mux", tx_dmic_mux4_enum);
2908
2909 static const struct snd_kcontrol_new tx_dmic_mux5 =
2910 SOC_DAPM_ENUM("DMIC MUX5 Mux", tx_dmic_mux5_enum);
2911
2912 static const struct snd_kcontrol_new tx_dmic_mux6 =
2913 SOC_DAPM_ENUM("DMIC MUX6 Mux", tx_dmic_mux6_enum);
2914
2915 static const struct snd_kcontrol_new tx_dmic_mux7 =
2916 SOC_DAPM_ENUM("DMIC MUX7 Mux", tx_dmic_mux7_enum);
2917
2918 static const struct snd_kcontrol_new tx_dmic_mux8 =
2919 SOC_DAPM_ENUM("DMIC MUX8 Mux", tx_dmic_mux8_enum);
2920
2921 static const struct snd_kcontrol_new tx_amic_mux0 =
2922 SOC_DAPM_ENUM("AMIC MUX0 Mux", tx_amic_mux0_enum);
2923
2924 static const struct snd_kcontrol_new tx_amic_mux1 =
2925 SOC_DAPM_ENUM("AMIC MUX1 Mux", tx_amic_mux1_enum);
2926
2927 static const struct snd_kcontrol_new tx_amic_mux2 =
2928 SOC_DAPM_ENUM("AMIC MUX2 Mux", tx_amic_mux2_enum);
2929
2930 static const struct snd_kcontrol_new tx_amic_mux3 =
2931 SOC_DAPM_ENUM("AMIC MUX3 Mux", tx_amic_mux3_enum);
2932
2933 static const struct snd_kcontrol_new tx_amic_mux4 =
2934 SOC_DAPM_ENUM("AMIC MUX4 Mux", tx_amic_mux4_enum);
2935
2936 static const struct snd_kcontrol_new tx_amic_mux5 =
2937 SOC_DAPM_ENUM("AMIC MUX5 Mux", tx_amic_mux5_enum);
2938
2939 static const struct snd_kcontrol_new tx_amic_mux6 =
2940 SOC_DAPM_ENUM("AMIC MUX6 Mux", tx_amic_mux6_enum);
2941
2942 static const struct snd_kcontrol_new tx_amic_mux7 =
2943 SOC_DAPM_ENUM("AMIC MUX7 Mux", tx_amic_mux7_enum);
2944
2945 static const struct snd_kcontrol_new tx_amic_mux8 =
2946 SOC_DAPM_ENUM("AMIC MUX8 Mux", tx_amic_mux8_enum);
2947
2948 static const struct snd_kcontrol_new tx_amic4_5 =
2949 SOC_DAPM_ENUM("AMIC4_5 SEL Mux", tx_amic4_5_enum);
2950
2951 static const struct snd_kcontrol_new tx_adc_mux0_mux =
2952 SOC_DAPM_ENUM_EXT("ADC MUX0 Mux", tx_adc_mux0_enum,
2953 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
2954 static const struct snd_kcontrol_new tx_adc_mux1_mux =
2955 SOC_DAPM_ENUM_EXT("ADC MUX1 Mux", tx_adc_mux1_enum,
2956 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
2957 static const struct snd_kcontrol_new tx_adc_mux2_mux =
2958 SOC_DAPM_ENUM_EXT("ADC MUX2 Mux", tx_adc_mux2_enum,
2959 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
2960 static const struct snd_kcontrol_new tx_adc_mux3_mux =
2961 SOC_DAPM_ENUM_EXT("ADC MUX3 Mux", tx_adc_mux3_enum,
2962 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
2963 static const struct snd_kcontrol_new tx_adc_mux4_mux =
2964 SOC_DAPM_ENUM_EXT("ADC MUX4 Mux", tx_adc_mux4_enum,
2965 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
2966 static const struct snd_kcontrol_new tx_adc_mux5_mux =
2967 SOC_DAPM_ENUM_EXT("ADC MUX5 Mux", tx_adc_mux5_enum,
2968 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
2969 static const struct snd_kcontrol_new tx_adc_mux6_mux =
2970 SOC_DAPM_ENUM_EXT("ADC MUX6 Mux", tx_adc_mux6_enum,
2971 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
2972 static const struct snd_kcontrol_new tx_adc_mux7_mux =
2973 SOC_DAPM_ENUM_EXT("ADC MUX7 Mux", tx_adc_mux7_enum,
2974 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
2975 static const struct snd_kcontrol_new tx_adc_mux8_mux =
2976 SOC_DAPM_ENUM_EXT("ADC MUX8 Mux", tx_adc_mux8_enum,
2977 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
2978
2979 static const struct snd_kcontrol_new cdc_if_tx0_mux =
2980 SOC_DAPM_ENUM("CDC_IF TX0 MUX Mux", cdc_if_tx0_mux_enum);
2981 static const struct snd_kcontrol_new cdc_if_tx1_mux =
2982 SOC_DAPM_ENUM("CDC_IF TX1 MUX Mux", cdc_if_tx1_mux_enum);
2983 static const struct snd_kcontrol_new cdc_if_tx2_mux =
2984 SOC_DAPM_ENUM("CDC_IF TX2 MUX Mux", cdc_if_tx2_mux_enum);
2985 static const struct snd_kcontrol_new cdc_if_tx3_mux =
2986 SOC_DAPM_ENUM("CDC_IF TX3 MUX Mux", cdc_if_tx3_mux_enum);
2987 static const struct snd_kcontrol_new cdc_if_tx4_mux =
2988 SOC_DAPM_ENUM("CDC_IF TX4 MUX Mux", cdc_if_tx4_mux_enum);
2989 static const struct snd_kcontrol_new cdc_if_tx5_mux =
2990 SOC_DAPM_ENUM("CDC_IF TX5 MUX Mux", cdc_if_tx5_mux_enum);
2991 static const struct snd_kcontrol_new cdc_if_tx6_mux =
2992 SOC_DAPM_ENUM("CDC_IF TX6 MUX Mux", cdc_if_tx6_mux_enum);
2993 static const struct snd_kcontrol_new cdc_if_tx7_mux =
2994 SOC_DAPM_ENUM("CDC_IF TX7 MUX Mux", cdc_if_tx7_mux_enum);
2995 static const struct snd_kcontrol_new cdc_if_tx8_mux =
2996 SOC_DAPM_ENUM("CDC_IF TX8 MUX Mux", cdc_if_tx8_mux_enum);
2997 static const struct snd_kcontrol_new cdc_if_tx9_mux =
2998 SOC_DAPM_ENUM("CDC_IF TX9 MUX Mux", cdc_if_tx9_mux_enum);
2999 static const struct snd_kcontrol_new cdc_if_tx10_mux =
3000 SOC_DAPM_ENUM("CDC_IF TX10 MUX Mux", cdc_if_tx10_mux_enum);
3001 static const struct snd_kcontrol_new cdc_if_tx11_mux =
3002 SOC_DAPM_ENUM("CDC_IF TX11 MUX Mux", cdc_if_tx11_mux_enum);
3003 static const struct snd_kcontrol_new cdc_if_tx11_inp1_mux =
3004 SOC_DAPM_ENUM("CDC_IF TX11 INP1 MUX Mux", cdc_if_tx11_inp1_mux_enum);
3005 static const struct snd_kcontrol_new cdc_if_tx13_mux =
3006 SOC_DAPM_ENUM("CDC_IF TX13 MUX Mux", cdc_if_tx13_mux_enum);
3007 static const struct snd_kcontrol_new cdc_if_tx13_inp1_mux =
3008 SOC_DAPM_ENUM("CDC_IF TX13 INP1 MUX Mux", cdc_if_tx13_inp1_mux_enum);
3009
slim_tx_mixer_get(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)3010 static int slim_tx_mixer_get(struct snd_kcontrol *kc,
3011 struct snd_ctl_elem_value *ucontrol)
3012 {
3013 struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kc);
3014 struct wcd934x_codec *wcd = dev_get_drvdata(dapm->dev);
3015 struct soc_mixer_control *mixer =
3016 (struct soc_mixer_control *)kc->private_value;
3017 int port_id = mixer->shift;
3018
3019 ucontrol->value.integer.value[0] = wcd->tx_port_value[port_id];
3020
3021 return 0;
3022 }
3023
slim_tx_mixer_put(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)3024 static int slim_tx_mixer_put(struct snd_kcontrol *kc,
3025 struct snd_ctl_elem_value *ucontrol)
3026 {
3027 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kc);
3028 struct wcd934x_codec *wcd = dev_get_drvdata(widget->dapm->dev);
3029 struct snd_soc_dapm_update *update = NULL;
3030 struct soc_mixer_control *mixer =
3031 (struct soc_mixer_control *)kc->private_value;
3032 int enable = ucontrol->value.integer.value[0];
3033 int dai_id = widget->shift;
3034 int port_id = mixer->shift;
3035
3036 /* only add to the list if value not set */
3037 if (enable == wcd->tx_port_value[port_id])
3038 return 0;
3039
3040 wcd->tx_port_value[port_id] = enable;
3041
3042 if (enable)
3043 list_add_tail(&wcd->tx_chs[port_id].list,
3044 &wcd->dai[dai_id].slim_ch_list);
3045 else
3046 list_del_init(&wcd->tx_chs[port_id].list);
3047
3048 snd_soc_dapm_mixer_update_power(widget->dapm, kc, enable, update);
3049
3050 return 0;
3051 }
3052
3053 static const struct snd_kcontrol_new aif1_slim_cap_mixer[] = {
3054 SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD934X_TX0, 1, 0,
3055 slim_tx_mixer_get, slim_tx_mixer_put),
3056 SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD934X_TX1, 1, 0,
3057 slim_tx_mixer_get, slim_tx_mixer_put),
3058 SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD934X_TX2, 1, 0,
3059 slim_tx_mixer_get, slim_tx_mixer_put),
3060 SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD934X_TX3, 1, 0,
3061 slim_tx_mixer_get, slim_tx_mixer_put),
3062 SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD934X_TX4, 1, 0,
3063 slim_tx_mixer_get, slim_tx_mixer_put),
3064 SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD934X_TX5, 1, 0,
3065 slim_tx_mixer_get, slim_tx_mixer_put),
3066 SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD934X_TX6, 1, 0,
3067 slim_tx_mixer_get, slim_tx_mixer_put),
3068 SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD934X_TX7, 1, 0,
3069 slim_tx_mixer_get, slim_tx_mixer_put),
3070 SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD934X_TX8, 1, 0,
3071 slim_tx_mixer_get, slim_tx_mixer_put),
3072 SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD934X_TX9, 1, 0,
3073 slim_tx_mixer_get, slim_tx_mixer_put),
3074 SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD934X_TX10, 1, 0,
3075 slim_tx_mixer_get, slim_tx_mixer_put),
3076 SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD934X_TX11, 1, 0,
3077 slim_tx_mixer_get, slim_tx_mixer_put),
3078 SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD934X_TX13, 1, 0,
3079 slim_tx_mixer_get, slim_tx_mixer_put),
3080 };
3081
3082 static const struct snd_kcontrol_new aif2_slim_cap_mixer[] = {
3083 SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD934X_TX0, 1, 0,
3084 slim_tx_mixer_get, slim_tx_mixer_put),
3085 SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD934X_TX1, 1, 0,
3086 slim_tx_mixer_get, slim_tx_mixer_put),
3087 SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD934X_TX2, 1, 0,
3088 slim_tx_mixer_get, slim_tx_mixer_put),
3089 SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD934X_TX3, 1, 0,
3090 slim_tx_mixer_get, slim_tx_mixer_put),
3091 SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD934X_TX4, 1, 0,
3092 slim_tx_mixer_get, slim_tx_mixer_put),
3093 SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD934X_TX5, 1, 0,
3094 slim_tx_mixer_get, slim_tx_mixer_put),
3095 SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD934X_TX6, 1, 0,
3096 slim_tx_mixer_get, slim_tx_mixer_put),
3097 SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD934X_TX7, 1, 0,
3098 slim_tx_mixer_get, slim_tx_mixer_put),
3099 SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD934X_TX8, 1, 0,
3100 slim_tx_mixer_get, slim_tx_mixer_put),
3101 SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD934X_TX9, 1, 0,
3102 slim_tx_mixer_get, slim_tx_mixer_put),
3103 SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD934X_TX10, 1, 0,
3104 slim_tx_mixer_get, slim_tx_mixer_put),
3105 SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD934X_TX11, 1, 0,
3106 slim_tx_mixer_get, slim_tx_mixer_put),
3107 SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD934X_TX13, 1, 0,
3108 slim_tx_mixer_get, slim_tx_mixer_put),
3109 };
3110
3111 static const struct snd_kcontrol_new aif3_slim_cap_mixer[] = {
3112 SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD934X_TX0, 1, 0,
3113 slim_tx_mixer_get, slim_tx_mixer_put),
3114 SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD934X_TX1, 1, 0,
3115 slim_tx_mixer_get, slim_tx_mixer_put),
3116 SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD934X_TX2, 1, 0,
3117 slim_tx_mixer_get, slim_tx_mixer_put),
3118 SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD934X_TX3, 1, 0,
3119 slim_tx_mixer_get, slim_tx_mixer_put),
3120 SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD934X_TX4, 1, 0,
3121 slim_tx_mixer_get, slim_tx_mixer_put),
3122 SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD934X_TX5, 1, 0,
3123 slim_tx_mixer_get, slim_tx_mixer_put),
3124 SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD934X_TX6, 1, 0,
3125 slim_tx_mixer_get, slim_tx_mixer_put),
3126 SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD934X_TX7, 1, 0,
3127 slim_tx_mixer_get, slim_tx_mixer_put),
3128 SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD934X_TX8, 1, 0,
3129 slim_tx_mixer_get, slim_tx_mixer_put),
3130 SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD934X_TX9, 1, 0,
3131 slim_tx_mixer_get, slim_tx_mixer_put),
3132 SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD934X_TX10, 1, 0,
3133 slim_tx_mixer_get, slim_tx_mixer_put),
3134 SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD934X_TX11, 1, 0,
3135 slim_tx_mixer_get, slim_tx_mixer_put),
3136 SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD934X_TX13, 1, 0,
3137 slim_tx_mixer_get, slim_tx_mixer_put),
3138 };
3139
3140 static const struct snd_kcontrol_new wcd934x_snd_controls[] = {
3141 /* Gain Controls */
3142 SOC_SINGLE_TLV("EAR PA Volume", WCD934X_ANA_EAR, 4, 4, 1, ear_pa_gain),
3143 SOC_SINGLE_TLV("HPHL Volume", WCD934X_HPH_L_EN, 0, 24, 1, line_gain),
3144 SOC_SINGLE_TLV("HPHR Volume", WCD934X_HPH_R_EN, 0, 24, 1, line_gain),
3145 SOC_SINGLE_TLV("LINEOUT1 Volume", WCD934X_DIFF_LO_LO1_COMPANDER,
3146 3, 16, 1, line_gain),
3147 SOC_SINGLE_TLV("LINEOUT2 Volume", WCD934X_DIFF_LO_LO2_COMPANDER,
3148 3, 16, 1, line_gain),
3149
3150 SOC_SINGLE_TLV("ADC1 Volume", WCD934X_ANA_AMIC1, 0, 20, 0, analog_gain),
3151 SOC_SINGLE_TLV("ADC2 Volume", WCD934X_ANA_AMIC2, 0, 20, 0, analog_gain),
3152 SOC_SINGLE_TLV("ADC3 Volume", WCD934X_ANA_AMIC3, 0, 20, 0, analog_gain),
3153 SOC_SINGLE_TLV("ADC4 Volume", WCD934X_ANA_AMIC4, 0, 20, 0, analog_gain),
3154
3155 SOC_SINGLE_S8_TLV("RX0 Digital Volume", WCD934X_CDC_RX0_RX_VOL_CTL,
3156 -84, 40, digital_gain), /* -84dB min - 40dB max */
3157 SOC_SINGLE_S8_TLV("RX1 Digital Volume", WCD934X_CDC_RX1_RX_VOL_CTL,
3158 -84, 40, digital_gain),
3159 SOC_SINGLE_S8_TLV("RX2 Digital Volume", WCD934X_CDC_RX2_RX_VOL_CTL,
3160 -84, 40, digital_gain),
3161 SOC_SINGLE_S8_TLV("RX3 Digital Volume", WCD934X_CDC_RX3_RX_VOL_CTL,
3162 -84, 40, digital_gain),
3163 SOC_SINGLE_S8_TLV("RX4 Digital Volume", WCD934X_CDC_RX4_RX_VOL_CTL,
3164 -84, 40, digital_gain),
3165 SOC_SINGLE_S8_TLV("RX7 Digital Volume", WCD934X_CDC_RX7_RX_VOL_CTL,
3166 -84, 40, digital_gain),
3167 SOC_SINGLE_S8_TLV("RX8 Digital Volume", WCD934X_CDC_RX8_RX_VOL_CTL,
3168 -84, 40, digital_gain),
3169 SOC_SINGLE_S8_TLV("RX0 Mix Digital Volume",
3170 WCD934X_CDC_RX0_RX_VOL_MIX_CTL,
3171 -84, 40, digital_gain),
3172 SOC_SINGLE_S8_TLV("RX1 Mix Digital Volume",
3173 WCD934X_CDC_RX1_RX_VOL_MIX_CTL,
3174 -84, 40, digital_gain),
3175 SOC_SINGLE_S8_TLV("RX2 Mix Digital Volume",
3176 WCD934X_CDC_RX2_RX_VOL_MIX_CTL,
3177 -84, 40, digital_gain),
3178 SOC_SINGLE_S8_TLV("RX3 Mix Digital Volume",
3179 WCD934X_CDC_RX3_RX_VOL_MIX_CTL,
3180 -84, 40, digital_gain),
3181 SOC_SINGLE_S8_TLV("RX4 Mix Digital Volume",
3182 WCD934X_CDC_RX4_RX_VOL_MIX_CTL,
3183 -84, 40, digital_gain),
3184 SOC_SINGLE_S8_TLV("RX7 Mix Digital Volume",
3185 WCD934X_CDC_RX7_RX_VOL_MIX_CTL,
3186 -84, 40, digital_gain),
3187 SOC_SINGLE_S8_TLV("RX8 Mix Digital Volume",
3188 WCD934X_CDC_RX8_RX_VOL_MIX_CTL,
3189 -84, 40, digital_gain),
3190
3191 SOC_SINGLE_S8_TLV("DEC0 Volume", WCD934X_CDC_TX0_TX_VOL_CTL,
3192 -84, 40, digital_gain),
3193 SOC_SINGLE_S8_TLV("DEC1 Volume", WCD934X_CDC_TX1_TX_VOL_CTL,
3194 -84, 40, digital_gain),
3195 SOC_SINGLE_S8_TLV("DEC2 Volume", WCD934X_CDC_TX2_TX_VOL_CTL,
3196 -84, 40, digital_gain),
3197 SOC_SINGLE_S8_TLV("DEC3 Volume", WCD934X_CDC_TX3_TX_VOL_CTL,
3198 -84, 40, digital_gain),
3199 SOC_SINGLE_S8_TLV("DEC4 Volume", WCD934X_CDC_TX4_TX_VOL_CTL,
3200 -84, 40, digital_gain),
3201 SOC_SINGLE_S8_TLV("DEC5 Volume", WCD934X_CDC_TX5_TX_VOL_CTL,
3202 -84, 40, digital_gain),
3203 SOC_SINGLE_S8_TLV("DEC6 Volume", WCD934X_CDC_TX6_TX_VOL_CTL,
3204 -84, 40, digital_gain),
3205 SOC_SINGLE_S8_TLV("DEC7 Volume", WCD934X_CDC_TX7_TX_VOL_CTL,
3206 -84, 40, digital_gain),
3207 SOC_SINGLE_S8_TLV("DEC8 Volume", WCD934X_CDC_TX8_TX_VOL_CTL,
3208 -84, 40, digital_gain),
3209
3210 SOC_SINGLE_S8_TLV("IIR0 INP0 Volume",
3211 WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B1_CTL, -84, 40,
3212 digital_gain),
3213 SOC_SINGLE_S8_TLV("IIR0 INP1 Volume",
3214 WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B2_CTL, -84, 40,
3215 digital_gain),
3216 SOC_SINGLE_S8_TLV("IIR0 INP2 Volume",
3217 WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B3_CTL, -84, 40,
3218 digital_gain),
3219 SOC_SINGLE_S8_TLV("IIR0 INP3 Volume",
3220 WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B4_CTL, -84, 40,
3221 digital_gain),
3222 SOC_SINGLE_S8_TLV("IIR1 INP0 Volume",
3223 WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B1_CTL, -84, 40,
3224 digital_gain),
3225 SOC_SINGLE_S8_TLV("IIR1 INP1 Volume",
3226 WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B2_CTL, -84, 40,
3227 digital_gain),
3228 SOC_SINGLE_S8_TLV("IIR1 INP2 Volume",
3229 WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B3_CTL, -84, 40,
3230 digital_gain),
3231 SOC_SINGLE_S8_TLV("IIR1 INP3 Volume",
3232 WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B4_CTL, -84, 40,
3233 digital_gain),
3234
3235 SOC_ENUM("TX0 HPF cut off", cf_dec0_enum),
3236 SOC_ENUM("TX1 HPF cut off", cf_dec1_enum),
3237 SOC_ENUM("TX2 HPF cut off", cf_dec2_enum),
3238 SOC_ENUM("TX3 HPF cut off", cf_dec3_enum),
3239 SOC_ENUM("TX4 HPF cut off", cf_dec4_enum),
3240 SOC_ENUM("TX5 HPF cut off", cf_dec5_enum),
3241 SOC_ENUM("TX6 HPF cut off", cf_dec6_enum),
3242 SOC_ENUM("TX7 HPF cut off", cf_dec7_enum),
3243 SOC_ENUM("TX8 HPF cut off", cf_dec8_enum),
3244
3245 SOC_ENUM("RX INT0_1 HPF cut off", cf_int0_1_enum),
3246 SOC_ENUM("RX INT0_2 HPF cut off", cf_int0_2_enum),
3247 SOC_ENUM("RX INT1_1 HPF cut off", cf_int1_1_enum),
3248 SOC_ENUM("RX INT1_2 HPF cut off", cf_int1_2_enum),
3249 SOC_ENUM("RX INT2_1 HPF cut off", cf_int2_1_enum),
3250 SOC_ENUM("RX INT2_2 HPF cut off", cf_int2_2_enum),
3251 SOC_ENUM("RX INT3_1 HPF cut off", cf_int3_1_enum),
3252 SOC_ENUM("RX INT3_2 HPF cut off", cf_int3_2_enum),
3253 SOC_ENUM("RX INT4_1 HPF cut off", cf_int4_1_enum),
3254 SOC_ENUM("RX INT4_2 HPF cut off", cf_int4_2_enum),
3255 SOC_ENUM("RX INT7_1 HPF cut off", cf_int7_1_enum),
3256 SOC_ENUM("RX INT7_2 HPF cut off", cf_int7_2_enum),
3257 SOC_ENUM("RX INT8_1 HPF cut off", cf_int8_1_enum),
3258 SOC_ENUM("RX INT8_2 HPF cut off", cf_int8_2_enum),
3259
3260 SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
3261 wcd934x_rx_hph_mode_get, wcd934x_rx_hph_mode_put),
3262
3263 SOC_SINGLE("IIR1 Band1 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL,
3264 0, 1, 0),
3265 SOC_SINGLE("IIR1 Band2 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL,
3266 1, 1, 0),
3267 SOC_SINGLE("IIR1 Band3 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL,
3268 2, 1, 0),
3269 SOC_SINGLE("IIR1 Band4 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL,
3270 3, 1, 0),
3271 SOC_SINGLE("IIR1 Band5 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL,
3272 4, 1, 0),
3273 SOC_SINGLE("IIR2 Band1 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL,
3274 0, 1, 0),
3275 SOC_SINGLE("IIR2 Band2 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL,
3276 1, 1, 0),
3277 SOC_SINGLE("IIR2 Band3 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL,
3278 2, 1, 0),
3279 SOC_SINGLE("IIR2 Band4 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL,
3280 3, 1, 0),
3281 SOC_SINGLE("IIR2 Band5 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL,
3282 4, 1, 0),
3283 WCD_IIR_FILTER_CTL("IIR0 Band1", IIR0, BAND1),
3284 WCD_IIR_FILTER_CTL("IIR0 Band2", IIR0, BAND2),
3285 WCD_IIR_FILTER_CTL("IIR0 Band3", IIR0, BAND3),
3286 WCD_IIR_FILTER_CTL("IIR0 Band4", IIR0, BAND4),
3287 WCD_IIR_FILTER_CTL("IIR0 Band5", IIR0, BAND5),
3288
3289 WCD_IIR_FILTER_CTL("IIR1 Band1", IIR1, BAND1),
3290 WCD_IIR_FILTER_CTL("IIR1 Band2", IIR1, BAND2),
3291 WCD_IIR_FILTER_CTL("IIR1 Band3", IIR1, BAND3),
3292 WCD_IIR_FILTER_CTL("IIR1 Band4", IIR1, BAND4),
3293 WCD_IIR_FILTER_CTL("IIR1 Band5", IIR1, BAND5),
3294
3295 SOC_SINGLE_EXT("COMP1 Switch", SND_SOC_NOPM, COMPANDER_1, 1, 0,
3296 wcd934x_compander_get, wcd934x_compander_set),
3297 SOC_SINGLE_EXT("COMP2 Switch", SND_SOC_NOPM, COMPANDER_2, 1, 0,
3298 wcd934x_compander_get, wcd934x_compander_set),
3299 SOC_SINGLE_EXT("COMP3 Switch", SND_SOC_NOPM, COMPANDER_3, 1, 0,
3300 wcd934x_compander_get, wcd934x_compander_set),
3301 SOC_SINGLE_EXT("COMP4 Switch", SND_SOC_NOPM, COMPANDER_4, 1, 0,
3302 wcd934x_compander_get, wcd934x_compander_set),
3303 SOC_SINGLE_EXT("COMP7 Switch", SND_SOC_NOPM, COMPANDER_7, 1, 0,
3304 wcd934x_compander_get, wcd934x_compander_set),
3305 SOC_SINGLE_EXT("COMP8 Switch", SND_SOC_NOPM, COMPANDER_8, 1, 0,
3306 wcd934x_compander_get, wcd934x_compander_set),
3307 };
3308
wcd934x_codec_enable_int_port(struct wcd_slim_codec_dai_data * dai,struct snd_soc_component * component)3309 static void wcd934x_codec_enable_int_port(struct wcd_slim_codec_dai_data *dai,
3310 struct snd_soc_component *component)
3311 {
3312 int port_num = 0;
3313 unsigned short reg = 0;
3314 unsigned int val = 0;
3315 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
3316 struct wcd934x_slim_ch *ch;
3317
3318 list_for_each_entry(ch, &dai->slim_ch_list, list) {
3319 if (ch->port >= WCD934X_RX_START) {
3320 port_num = ch->port - WCD934X_RX_START;
3321 reg = WCD934X_SLIM_PGD_PORT_INT_EN0 + (port_num / 8);
3322 } else {
3323 port_num = ch->port;
3324 reg = WCD934X_SLIM_PGD_PORT_INT_TX_EN0 + (port_num / 8);
3325 }
3326
3327 regmap_read(wcd->if_regmap, reg, &val);
3328 if (!(val & BIT(port_num % 8)))
3329 regmap_write(wcd->if_regmap, reg,
3330 val | BIT(port_num % 8));
3331 }
3332 }
3333
wcd934x_codec_enable_slim(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)3334 static int wcd934x_codec_enable_slim(struct snd_soc_dapm_widget *w,
3335 struct snd_kcontrol *kc, int event)
3336 {
3337 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3338 struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(comp);
3339 struct wcd_slim_codec_dai_data *dai = &wcd->dai[w->shift];
3340
3341 switch (event) {
3342 case SND_SOC_DAPM_POST_PMU:
3343 wcd934x_codec_enable_int_port(dai, comp);
3344 break;
3345 }
3346
3347 return 0;
3348 }
3349
wcd934x_codec_hd2_control(struct snd_soc_component * component,u16 interp_idx,int event)3350 static void wcd934x_codec_hd2_control(struct snd_soc_component *component,
3351 u16 interp_idx, int event)
3352 {
3353 u16 hd2_scale_reg;
3354 u16 hd2_enable_reg = 0;
3355
3356 switch (interp_idx) {
3357 case INTERP_HPHL:
3358 hd2_scale_reg = WCD934X_CDC_RX1_RX_PATH_SEC3;
3359 hd2_enable_reg = WCD934X_CDC_RX1_RX_PATH_CFG0;
3360 break;
3361 case INTERP_HPHR:
3362 hd2_scale_reg = WCD934X_CDC_RX2_RX_PATH_SEC3;
3363 hd2_enable_reg = WCD934X_CDC_RX2_RX_PATH_CFG0;
3364 break;
3365 default:
3366 return;
3367 }
3368
3369 if (SND_SOC_DAPM_EVENT_ON(event)) {
3370 snd_soc_component_update_bits(component, hd2_scale_reg,
3371 WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_MASK,
3372 WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_0P3125);
3373 snd_soc_component_update_bits(component, hd2_enable_reg,
3374 WCD934X_CDC_RX_PATH_CFG_HD2_EN_MASK,
3375 WCD934X_CDC_RX_PATH_CFG_HD2_ENABLE);
3376 }
3377
3378 if (SND_SOC_DAPM_EVENT_OFF(event)) {
3379 snd_soc_component_update_bits(component, hd2_enable_reg,
3380 WCD934X_CDC_RX_PATH_CFG_HD2_EN_MASK,
3381 WCD934X_CDC_RX_PATH_CFG_HD2_DISABLE);
3382 snd_soc_component_update_bits(component, hd2_scale_reg,
3383 WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_MASK,
3384 WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_0P0000);
3385 }
3386 }
3387
wcd934x_codec_hphdelay_lutbypass(struct snd_soc_component * comp,u16 interp_idx,int event)3388 static void wcd934x_codec_hphdelay_lutbypass(struct snd_soc_component *comp,
3389 u16 interp_idx, int event)
3390 {
3391 u8 hph_dly_mask;
3392 u16 hph_lut_bypass_reg = 0;
3393
3394 switch (interp_idx) {
3395 case INTERP_HPHL:
3396 hph_dly_mask = 1;
3397 hph_lut_bypass_reg = WCD934X_CDC_TOP_HPHL_COMP_LUT;
3398 break;
3399 case INTERP_HPHR:
3400 hph_dly_mask = 2;
3401 hph_lut_bypass_reg = WCD934X_CDC_TOP_HPHR_COMP_LUT;
3402 break;
3403 default:
3404 return;
3405 }
3406
3407 if (SND_SOC_DAPM_EVENT_ON(event)) {
3408 snd_soc_component_update_bits(comp, WCD934X_CDC_CLSH_TEST0,
3409 hph_dly_mask, 0x0);
3410 snd_soc_component_update_bits(comp, hph_lut_bypass_reg,
3411 WCD934X_HPH_LUT_BYPASS_MASK,
3412 WCD934X_HPH_LUT_BYPASS_ENABLE);
3413 }
3414
3415 if (SND_SOC_DAPM_EVENT_OFF(event)) {
3416 snd_soc_component_update_bits(comp, WCD934X_CDC_CLSH_TEST0,
3417 hph_dly_mask, hph_dly_mask);
3418 snd_soc_component_update_bits(comp, hph_lut_bypass_reg,
3419 WCD934X_HPH_LUT_BYPASS_MASK,
3420 WCD934X_HPH_LUT_BYPASS_DISABLE);
3421 }
3422 }
3423
wcd934x_config_compander(struct snd_soc_component * comp,int interp_n,int event)3424 static int wcd934x_config_compander(struct snd_soc_component *comp,
3425 int interp_n, int event)
3426 {
3427 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
3428 int compander;
3429 u16 comp_ctl0_reg, rx_path_cfg0_reg;
3430
3431 /* EAR does not have compander */
3432 if (!interp_n)
3433 return 0;
3434
3435 compander = interp_n - 1;
3436 if (!wcd->comp_enabled[compander])
3437 return 0;
3438
3439 comp_ctl0_reg = WCD934X_CDC_COMPANDER1_CTL0 + (compander * 8);
3440 rx_path_cfg0_reg = WCD934X_CDC_RX1_RX_PATH_CFG0 + (compander * 20);
3441
3442 switch (event) {
3443 case SND_SOC_DAPM_PRE_PMU:
3444 /* Enable Compander Clock */
3445 snd_soc_component_update_bits(comp, comp_ctl0_reg,
3446 WCD934X_COMP_CLK_EN_MASK,
3447 WCD934X_COMP_CLK_ENABLE);
3448 snd_soc_component_update_bits(comp, comp_ctl0_reg,
3449 WCD934X_COMP_SOFT_RST_MASK,
3450 WCD934X_COMP_SOFT_RST_ENABLE);
3451 snd_soc_component_update_bits(comp, comp_ctl0_reg,
3452 WCD934X_COMP_SOFT_RST_MASK,
3453 WCD934X_COMP_SOFT_RST_DISABLE);
3454 snd_soc_component_update_bits(comp, rx_path_cfg0_reg,
3455 WCD934X_HPH_CMP_EN_MASK,
3456 WCD934X_HPH_CMP_ENABLE);
3457 break;
3458 case SND_SOC_DAPM_POST_PMD:
3459 snd_soc_component_update_bits(comp, rx_path_cfg0_reg,
3460 WCD934X_HPH_CMP_EN_MASK,
3461 WCD934X_HPH_CMP_DISABLE);
3462 snd_soc_component_update_bits(comp, comp_ctl0_reg,
3463 WCD934X_COMP_HALT_MASK,
3464 WCD934X_COMP_HALT);
3465 snd_soc_component_update_bits(comp, comp_ctl0_reg,
3466 WCD934X_COMP_SOFT_RST_MASK,
3467 WCD934X_COMP_SOFT_RST_ENABLE);
3468 snd_soc_component_update_bits(comp, comp_ctl0_reg,
3469 WCD934X_COMP_SOFT_RST_MASK,
3470 WCD934X_COMP_SOFT_RST_DISABLE);
3471 snd_soc_component_update_bits(comp, comp_ctl0_reg,
3472 WCD934X_COMP_CLK_EN_MASK, 0x0);
3473 snd_soc_component_update_bits(comp, comp_ctl0_reg,
3474 WCD934X_COMP_SOFT_RST_MASK, 0x0);
3475 break;
3476 }
3477
3478 return 0;
3479 }
3480
wcd934x_codec_enable_interp_clk(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)3481 static int wcd934x_codec_enable_interp_clk(struct snd_soc_dapm_widget *w,
3482 struct snd_kcontrol *kc, int event)
3483 {
3484 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3485 int interp_idx = w->shift;
3486 u16 main_reg = WCD934X_CDC_RX0_RX_PATH_CTL + (interp_idx * 20);
3487
3488 switch (event) {
3489 case SND_SOC_DAPM_PRE_PMU:
3490 /* Clk enable */
3491 snd_soc_component_update_bits(comp, main_reg,
3492 WCD934X_RX_CLK_EN_MASK,
3493 WCD934X_RX_CLK_ENABLE);
3494 wcd934x_codec_hd2_control(comp, interp_idx, event);
3495 wcd934x_codec_hphdelay_lutbypass(comp, interp_idx, event);
3496 wcd934x_config_compander(comp, interp_idx, event);
3497 break;
3498 case SND_SOC_DAPM_POST_PMD:
3499 wcd934x_config_compander(comp, interp_idx, event);
3500 wcd934x_codec_hphdelay_lutbypass(comp, interp_idx, event);
3501 wcd934x_codec_hd2_control(comp, interp_idx, event);
3502 /* Clk Disable */
3503 snd_soc_component_update_bits(comp, main_reg,
3504 WCD934X_RX_CLK_EN_MASK, 0);
3505 /* Reset enable and disable */
3506 snd_soc_component_update_bits(comp, main_reg,
3507 WCD934X_RX_RESET_MASK,
3508 WCD934X_RX_RESET_ENABLE);
3509 snd_soc_component_update_bits(comp, main_reg,
3510 WCD934X_RX_RESET_MASK,
3511 WCD934X_RX_RESET_DISABLE);
3512 /* Reset rate to 48K*/
3513 snd_soc_component_update_bits(comp, main_reg,
3514 WCD934X_RX_PCM_RATE_MASK,
3515 WCD934X_RX_PCM_RATE_F_48K);
3516 break;
3517 }
3518
3519 return 0;
3520 }
3521
wcd934x_codec_enable_mix_path(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)3522 static int wcd934x_codec_enable_mix_path(struct snd_soc_dapm_widget *w,
3523 struct snd_kcontrol *kc, int event)
3524 {
3525 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3526 int offset_val = 0;
3527 u16 gain_reg, mix_reg;
3528 int val = 0;
3529
3530 gain_reg = WCD934X_CDC_RX0_RX_VOL_MIX_CTL +
3531 (w->shift * WCD934X_RX_PATH_CTL_OFFSET);
3532 mix_reg = WCD934X_CDC_RX0_RX_PATH_MIX_CTL +
3533 (w->shift * WCD934X_RX_PATH_CTL_OFFSET);
3534
3535 switch (event) {
3536 case SND_SOC_DAPM_PRE_PMU:
3537 /* Clk enable */
3538 snd_soc_component_update_bits(comp, mix_reg,
3539 WCD934X_CDC_RX_MIX_CLK_EN_MASK,
3540 WCD934X_CDC_RX_MIX_CLK_ENABLE);
3541 break;
3542
3543 case SND_SOC_DAPM_POST_PMU:
3544 val = snd_soc_component_read(comp, gain_reg);
3545 val += offset_val;
3546 snd_soc_component_write(comp, gain_reg, val);
3547 break;
3548 }
3549
3550 return 0;
3551 }
3552
wcd934x_codec_set_iir_gain(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)3553 static int wcd934x_codec_set_iir_gain(struct snd_soc_dapm_widget *w,
3554 struct snd_kcontrol *kcontrol, int event)
3555 {
3556 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3557 int reg = w->reg;
3558
3559 switch (event) {
3560 case SND_SOC_DAPM_POST_PMU:
3561 /* B1 GAIN */
3562 snd_soc_component_write(comp, reg,
3563 snd_soc_component_read(comp, reg));
3564 /* B2 GAIN */
3565 reg++;
3566 snd_soc_component_write(comp, reg,
3567 snd_soc_component_read(comp, reg));
3568 /* B3 GAIN */
3569 reg++;
3570 snd_soc_component_write(comp, reg,
3571 snd_soc_component_read(comp, reg));
3572 /* B4 GAIN */
3573 reg++;
3574 snd_soc_component_write(comp, reg,
3575 snd_soc_component_read(comp, reg));
3576 /* B5 GAIN */
3577 reg++;
3578 snd_soc_component_write(comp, reg,
3579 snd_soc_component_read(comp, reg));
3580 break;
3581 default:
3582 break;
3583 }
3584 return 0;
3585 }
3586
wcd934x_codec_enable_main_path(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)3587 static int wcd934x_codec_enable_main_path(struct snd_soc_dapm_widget *w,
3588 struct snd_kcontrol *kcontrol,
3589 int event)
3590 {
3591 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3592 u16 gain_reg;
3593
3594 gain_reg = WCD934X_CDC_RX0_RX_VOL_CTL + (w->shift *
3595 WCD934X_RX_PATH_CTL_OFFSET);
3596
3597 switch (event) {
3598 case SND_SOC_DAPM_POST_PMU:
3599 snd_soc_component_write(comp, gain_reg,
3600 snd_soc_component_read(comp, gain_reg));
3601 break;
3602 }
3603
3604 return 0;
3605 }
3606
wcd934x_codec_ear_dac_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)3607 static int wcd934x_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
3608 struct snd_kcontrol *kc, int event)
3609 {
3610 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3611 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
3612
3613 switch (event) {
3614 case SND_SOC_DAPM_PRE_PMU:
3615 /* Disable AutoChop timer during power up */
3616 snd_soc_component_update_bits(comp,
3617 WCD934X_HPH_NEW_INT_HPH_TIMER1,
3618 WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK, 0x0);
3619 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
3620 WCD_CLSH_STATE_EAR, CLS_H_NORMAL);
3621
3622 break;
3623 case SND_SOC_DAPM_POST_PMD:
3624 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
3625 WCD_CLSH_STATE_EAR, CLS_H_NORMAL);
3626 break;
3627 }
3628
3629 return 0;
3630 }
3631
wcd934x_codec_hphl_dac_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)3632 static int wcd934x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
3633 struct snd_kcontrol *kcontrol,
3634 int event)
3635 {
3636 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3637 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
3638 int hph_mode = wcd->hph_mode;
3639 u8 dem_inp;
3640
3641 switch (event) {
3642 case SND_SOC_DAPM_PRE_PMU:
3643 /* Read DEM INP Select */
3644 dem_inp = snd_soc_component_read(comp,
3645 WCD934X_CDC_RX1_RX_PATH_SEC0) & 0x03;
3646
3647 if (((hph_mode == CLS_H_HIFI) || (hph_mode == CLS_H_LOHIFI) ||
3648 (hph_mode == CLS_H_LP)) && (dem_inp != 0x01)) {
3649 return -EINVAL;
3650 }
3651 if (hph_mode != CLS_H_LP)
3652 /* Ripple freq control enable */
3653 snd_soc_component_update_bits(comp,
3654 WCD934X_SIDO_NEW_VOUT_D_FREQ2,
3655 WCD934X_SIDO_RIPPLE_FREQ_EN_MASK,
3656 WCD934X_SIDO_RIPPLE_FREQ_ENABLE);
3657 /* Disable AutoChop timer during power up */
3658 snd_soc_component_update_bits(comp,
3659 WCD934X_HPH_NEW_INT_HPH_TIMER1,
3660 WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK, 0x0);
3661 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
3662 WCD_CLSH_STATE_HPHL, hph_mode);
3663
3664 break;
3665 case SND_SOC_DAPM_POST_PMD:
3666 /* 1000us required as per HW requirement */
3667 usleep_range(1000, 1100);
3668 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
3669 WCD_CLSH_STATE_HPHL, hph_mode);
3670 if (hph_mode != CLS_H_LP)
3671 /* Ripple freq control disable */
3672 snd_soc_component_update_bits(comp,
3673 WCD934X_SIDO_NEW_VOUT_D_FREQ2,
3674 WCD934X_SIDO_RIPPLE_FREQ_EN_MASK, 0x0);
3675
3676 break;
3677 default:
3678 break;
3679 }
3680
3681 return 0;
3682 }
3683
wcd934x_codec_hphr_dac_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)3684 static int wcd934x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
3685 struct snd_kcontrol *kcontrol,
3686 int event)
3687 {
3688 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3689 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
3690 int hph_mode = wcd->hph_mode;
3691 u8 dem_inp;
3692
3693 switch (event) {
3694 case SND_SOC_DAPM_PRE_PMU:
3695 dem_inp = snd_soc_component_read(comp,
3696 WCD934X_CDC_RX2_RX_PATH_SEC0) & 0x03;
3697 if (((hph_mode == CLS_H_HIFI) || (hph_mode == CLS_H_LOHIFI) ||
3698 (hph_mode == CLS_H_LP)) && (dem_inp != 0x01)) {
3699 return -EINVAL;
3700 }
3701 if (hph_mode != CLS_H_LP)
3702 /* Ripple freq control enable */
3703 snd_soc_component_update_bits(comp,
3704 WCD934X_SIDO_NEW_VOUT_D_FREQ2,
3705 WCD934X_SIDO_RIPPLE_FREQ_EN_MASK,
3706 WCD934X_SIDO_RIPPLE_FREQ_ENABLE);
3707 /* Disable AutoChop timer during power up */
3708 snd_soc_component_update_bits(comp,
3709 WCD934X_HPH_NEW_INT_HPH_TIMER1,
3710 WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK, 0x0);
3711 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
3712 WCD_CLSH_STATE_HPHR,
3713 hph_mode);
3714 break;
3715 case SND_SOC_DAPM_POST_PMD:
3716 /* 1000us required as per HW requirement */
3717 usleep_range(1000, 1100);
3718
3719 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
3720 WCD_CLSH_STATE_HPHR, hph_mode);
3721 if (hph_mode != CLS_H_LP)
3722 /* Ripple freq control disable */
3723 snd_soc_component_update_bits(comp,
3724 WCD934X_SIDO_NEW_VOUT_D_FREQ2,
3725 WCD934X_SIDO_RIPPLE_FREQ_EN_MASK, 0x0);
3726 break;
3727 default:
3728 break;
3729 }
3730
3731 return 0;
3732 }
3733
wcd934x_codec_lineout_dac_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)3734 static int wcd934x_codec_lineout_dac_event(struct snd_soc_dapm_widget *w,
3735 struct snd_kcontrol *kc, int event)
3736 {
3737 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3738 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
3739
3740 switch (event) {
3741 case SND_SOC_DAPM_PRE_PMU:
3742 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
3743 WCD_CLSH_STATE_LO, CLS_AB);
3744 break;
3745 case SND_SOC_DAPM_POST_PMD:
3746 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
3747 WCD_CLSH_STATE_LO, CLS_AB);
3748 break;
3749 }
3750
3751 return 0;
3752 }
3753
wcd934x_codec_enable_hphl_pa(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)3754 static int wcd934x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
3755 struct snd_kcontrol *kcontrol,
3756 int event)
3757 {
3758 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3759
3760 switch (event) {
3761 case SND_SOC_DAPM_POST_PMU:
3762 /*
3763 * 7ms sleep is required after PA is enabled as per
3764 * HW requirement. If compander is disabled, then
3765 * 20ms delay is needed.
3766 */
3767 usleep_range(20000, 20100);
3768
3769 snd_soc_component_update_bits(comp, WCD934X_HPH_L_TEST,
3770 WCD934X_HPH_OCP_DET_MASK,
3771 WCD934X_HPH_OCP_DET_ENABLE);
3772 /* Remove Mute on primary path */
3773 snd_soc_component_update_bits(comp, WCD934X_CDC_RX1_RX_PATH_CTL,
3774 WCD934X_RX_PATH_PGA_MUTE_EN_MASK,
3775 0);
3776 /* Enable GM3 boost */
3777 snd_soc_component_update_bits(comp, WCD934X_HPH_CNP_WG_CTL,
3778 WCD934X_HPH_GM3_BOOST_EN_MASK,
3779 WCD934X_HPH_GM3_BOOST_ENABLE);
3780 /* Enable AutoChop timer at the end of power up */
3781 snd_soc_component_update_bits(comp,
3782 WCD934X_HPH_NEW_INT_HPH_TIMER1,
3783 WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK,
3784 WCD934X_HPH_AUTOCHOP_TIMER_ENABLE);
3785 /* Remove mix path mute */
3786 snd_soc_component_update_bits(comp,
3787 WCD934X_CDC_RX1_RX_PATH_MIX_CTL,
3788 WCD934X_CDC_RX_PGA_MUTE_EN_MASK, 0x00);
3789 break;
3790 case SND_SOC_DAPM_PRE_PMD:
3791 /* Enable DSD Mute before PA disable */
3792 snd_soc_component_update_bits(comp, WCD934X_HPH_L_TEST,
3793 WCD934X_HPH_OCP_DET_MASK,
3794 WCD934X_HPH_OCP_DET_DISABLE);
3795 snd_soc_component_update_bits(comp, WCD934X_CDC_RX1_RX_PATH_CTL,
3796 WCD934X_RX_PATH_PGA_MUTE_EN_MASK,
3797 WCD934X_RX_PATH_PGA_MUTE_ENABLE);
3798 snd_soc_component_update_bits(comp,
3799 WCD934X_CDC_RX1_RX_PATH_MIX_CTL,
3800 WCD934X_RX_PATH_PGA_MUTE_EN_MASK,
3801 WCD934X_RX_PATH_PGA_MUTE_ENABLE);
3802 break;
3803 case SND_SOC_DAPM_POST_PMD:
3804 /*
3805 * 5ms sleep is required after PA disable. If compander is
3806 * disabled, then 20ms delay is needed after PA disable.
3807 */
3808 usleep_range(20000, 20100);
3809 break;
3810 }
3811
3812 return 0;
3813 }
3814
wcd934x_codec_enable_hphr_pa(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)3815 static int wcd934x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
3816 struct snd_kcontrol *kcontrol,
3817 int event)
3818 {
3819 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3820
3821 switch (event) {
3822 case SND_SOC_DAPM_POST_PMU:
3823 /*
3824 * 7ms sleep is required after PA is enabled as per
3825 * HW requirement. If compander is disabled, then
3826 * 20ms delay is needed.
3827 */
3828 usleep_range(20000, 20100);
3829 snd_soc_component_update_bits(comp, WCD934X_HPH_R_TEST,
3830 WCD934X_HPH_OCP_DET_MASK,
3831 WCD934X_HPH_OCP_DET_ENABLE);
3832 /* Remove mute */
3833 snd_soc_component_update_bits(comp, WCD934X_CDC_RX2_RX_PATH_CTL,
3834 WCD934X_RX_PATH_PGA_MUTE_EN_MASK,
3835 0);
3836 /* Enable GM3 boost */
3837 snd_soc_component_update_bits(comp, WCD934X_HPH_CNP_WG_CTL,
3838 WCD934X_HPH_GM3_BOOST_EN_MASK,
3839 WCD934X_HPH_GM3_BOOST_ENABLE);
3840 /* Enable AutoChop timer at the end of power up */
3841 snd_soc_component_update_bits(comp,
3842 WCD934X_HPH_NEW_INT_HPH_TIMER1,
3843 WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK,
3844 WCD934X_HPH_AUTOCHOP_TIMER_ENABLE);
3845 /* Remove mix path mute if it is enabled */
3846 if ((snd_soc_component_read(comp,
3847 WCD934X_CDC_RX2_RX_PATH_MIX_CTL)) & 0x10)
3848 snd_soc_component_update_bits(comp,
3849 WCD934X_CDC_RX2_RX_PATH_MIX_CTL,
3850 WCD934X_CDC_RX_PGA_MUTE_EN_MASK,
3851 WCD934X_CDC_RX_PGA_MUTE_DISABLE);
3852 break;
3853 case SND_SOC_DAPM_PRE_PMD:
3854 snd_soc_component_update_bits(comp, WCD934X_HPH_R_TEST,
3855 WCD934X_HPH_OCP_DET_MASK,
3856 WCD934X_HPH_OCP_DET_DISABLE);
3857 snd_soc_component_update_bits(comp, WCD934X_CDC_RX2_RX_PATH_CTL,
3858 WCD934X_RX_PATH_PGA_MUTE_EN_MASK,
3859 WCD934X_RX_PATH_PGA_MUTE_ENABLE);
3860 snd_soc_component_update_bits(comp,
3861 WCD934X_CDC_RX2_RX_PATH_MIX_CTL,
3862 WCD934X_CDC_RX_PGA_MUTE_EN_MASK,
3863 WCD934X_CDC_RX_PGA_MUTE_ENABLE);
3864 break;
3865 case SND_SOC_DAPM_POST_PMD:
3866 /*
3867 * 5ms sleep is required after PA disable. If compander is
3868 * disabled, then 20ms delay is needed after PA disable.
3869 */
3870 usleep_range(20000, 20100);
3871 break;
3872 }
3873
3874 return 0;
3875 }
3876
wcd934x_get_dmic_sample_rate(struct snd_soc_component * comp,unsigned int dmic,struct wcd934x_codec * wcd)3877 static u32 wcd934x_get_dmic_sample_rate(struct snd_soc_component *comp,
3878 unsigned int dmic,
3879 struct wcd934x_codec *wcd)
3880 {
3881 u8 tx_stream_fs;
3882 u8 adc_mux_index = 0, adc_mux_sel = 0;
3883 bool dec_found = false;
3884 u16 adc_mux_ctl_reg, tx_fs_reg;
3885 u32 dmic_fs;
3886
3887 while (!dec_found && adc_mux_index < WCD934X_MAX_VALID_ADC_MUX) {
3888 if (adc_mux_index < 4) {
3889 adc_mux_ctl_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0 +
3890 (adc_mux_index * 2);
3891 } else if (adc_mux_index < WCD934X_INVALID_ADC_MUX) {
3892 adc_mux_ctl_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 +
3893 adc_mux_index - 4;
3894 } else if (adc_mux_index == WCD934X_INVALID_ADC_MUX) {
3895 ++adc_mux_index;
3896 continue;
3897 }
3898 adc_mux_sel = ((snd_soc_component_read(comp, adc_mux_ctl_reg)
3899 & 0xF8) >> 3) - 1;
3900
3901 if (adc_mux_sel == dmic) {
3902 dec_found = true;
3903 break;
3904 }
3905
3906 ++adc_mux_index;
3907 }
3908
3909 if (dec_found && adc_mux_index <= 8) {
3910 tx_fs_reg = WCD934X_CDC_TX0_TX_PATH_CTL + (16 * adc_mux_index);
3911 tx_stream_fs = snd_soc_component_read(comp, tx_fs_reg) & 0x0F;
3912 if (tx_stream_fs <= 4) {
3913 if (wcd->dmic_sample_rate <=
3914 WCD9XXX_DMIC_SAMPLE_RATE_2P4MHZ)
3915 dmic_fs = wcd->dmic_sample_rate;
3916 else
3917 dmic_fs = WCD9XXX_DMIC_SAMPLE_RATE_2P4MHZ;
3918 } else
3919 dmic_fs = WCD9XXX_DMIC_SAMPLE_RATE_4P8MHZ;
3920 } else {
3921 dmic_fs = wcd->dmic_sample_rate;
3922 }
3923
3924 return dmic_fs;
3925 }
3926
wcd934x_get_dmic_clk_val(struct snd_soc_component * comp,u32 mclk_rate,u32 dmic_clk_rate)3927 static u8 wcd934x_get_dmic_clk_val(struct snd_soc_component *comp,
3928 u32 mclk_rate, u32 dmic_clk_rate)
3929 {
3930 u32 div_factor;
3931 u8 dmic_ctl_val;
3932
3933 /* Default value to return in case of error */
3934 if (mclk_rate == WCD934X_MCLK_CLK_9P6MHZ)
3935 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_2;
3936 else
3937 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_3;
3938
3939 if (dmic_clk_rate == 0) {
3940 dev_err(comp->dev,
3941 "%s: dmic_sample_rate cannot be 0\n",
3942 __func__);
3943 goto done;
3944 }
3945
3946 div_factor = mclk_rate / dmic_clk_rate;
3947 switch (div_factor) {
3948 case 2:
3949 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_2;
3950 break;
3951 case 3:
3952 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_3;
3953 break;
3954 case 4:
3955 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_4;
3956 break;
3957 case 6:
3958 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_6;
3959 break;
3960 case 8:
3961 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_8;
3962 break;
3963 case 16:
3964 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_16;
3965 break;
3966 default:
3967 dev_err(comp->dev,
3968 "%s: Invalid div_factor %u, clk_rate(%u), dmic_rate(%u)\n",
3969 __func__, div_factor, mclk_rate, dmic_clk_rate);
3970 break;
3971 }
3972
3973 done:
3974 return dmic_ctl_val;
3975 }
3976
wcd934x_codec_enable_dmic(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)3977 static int wcd934x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
3978 struct snd_kcontrol *kcontrol, int event)
3979 {
3980 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3981 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
3982 u8 dmic_clk_en = 0x01;
3983 u16 dmic_clk_reg;
3984 s32 *dmic_clk_cnt;
3985 u8 dmic_rate_val, dmic_rate_shift = 1;
3986 unsigned int dmic;
3987 u32 dmic_sample_rate;
3988 int ret;
3989 char *wname;
3990
3991 wname = strpbrk(w->name, "012345");
3992 if (!wname) {
3993 dev_err(comp->dev, "%s: widget not found\n", __func__);
3994 return -EINVAL;
3995 }
3996
3997 ret = kstrtouint(wname, 10, &dmic);
3998 if (ret < 0) {
3999 dev_err(comp->dev, "%s: Invalid DMIC line on the codec\n",
4000 __func__);
4001 return -EINVAL;
4002 }
4003
4004 switch (dmic) {
4005 case 0:
4006 case 1:
4007 dmic_clk_cnt = &wcd->dmic_0_1_clk_cnt;
4008 dmic_clk_reg = WCD934X_CPE_SS_DMIC0_CTL;
4009 break;
4010 case 2:
4011 case 3:
4012 dmic_clk_cnt = &wcd->dmic_2_3_clk_cnt;
4013 dmic_clk_reg = WCD934X_CPE_SS_DMIC1_CTL;
4014 break;
4015 case 4:
4016 case 5:
4017 dmic_clk_cnt = &wcd->dmic_4_5_clk_cnt;
4018 dmic_clk_reg = WCD934X_CPE_SS_DMIC2_CTL;
4019 break;
4020 default:
4021 dev_err(comp->dev, "%s: Invalid DMIC Selection\n",
4022 __func__);
4023 return -EINVAL;
4024 }
4025
4026 switch (event) {
4027 case SND_SOC_DAPM_PRE_PMU:
4028 dmic_sample_rate = wcd934x_get_dmic_sample_rate(comp, dmic,
4029 wcd);
4030 dmic_rate_val = wcd934x_get_dmic_clk_val(comp, wcd->rate,
4031 dmic_sample_rate);
4032 (*dmic_clk_cnt)++;
4033 if (*dmic_clk_cnt == 1) {
4034 dmic_rate_val = dmic_rate_val << dmic_rate_shift;
4035 snd_soc_component_update_bits(comp, dmic_clk_reg,
4036 WCD934X_DMIC_RATE_MASK,
4037 dmic_rate_val);
4038 snd_soc_component_update_bits(comp, dmic_clk_reg,
4039 dmic_clk_en, dmic_clk_en);
4040 }
4041
4042 break;
4043 case SND_SOC_DAPM_POST_PMD:
4044 (*dmic_clk_cnt)--;
4045 if (*dmic_clk_cnt == 0)
4046 snd_soc_component_update_bits(comp, dmic_clk_reg,
4047 dmic_clk_en, 0);
4048 break;
4049 }
4050
4051 return 0;
4052 }
4053
wcd934x_codec_find_amic_input(struct snd_soc_component * comp,int adc_mux_n)4054 static int wcd934x_codec_find_amic_input(struct snd_soc_component *comp,
4055 int adc_mux_n)
4056 {
4057 u16 mask, shift, adc_mux_in_reg;
4058 u16 amic_mux_sel_reg;
4059 bool is_amic;
4060
4061 if (adc_mux_n < 0 || adc_mux_n > WCD934X_MAX_VALID_ADC_MUX ||
4062 adc_mux_n == WCD934X_INVALID_ADC_MUX)
4063 return 0;
4064
4065 if (adc_mux_n < 3) {
4066 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1 +
4067 adc_mux_n;
4068 mask = 0x03;
4069 shift = 0;
4070 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0 +
4071 2 * adc_mux_n;
4072 } else if (adc_mux_n < 4) {
4073 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1;
4074 mask = 0x03;
4075 shift = 0;
4076 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0 +
4077 2 * adc_mux_n;
4078 } else if (adc_mux_n < 7) {
4079 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1 +
4080 (adc_mux_n - 4);
4081 mask = 0x0C;
4082 shift = 2;
4083 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 +
4084 adc_mux_n - 4;
4085 } else if (adc_mux_n < 8) {
4086 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1;
4087 mask = 0x0C;
4088 shift = 2;
4089 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 +
4090 adc_mux_n - 4;
4091 } else if (adc_mux_n < 12) {
4092 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1 +
4093 ((adc_mux_n == 8) ? (adc_mux_n - 8) :
4094 (adc_mux_n - 9));
4095 mask = 0x30;
4096 shift = 4;
4097 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 +
4098 adc_mux_n - 4;
4099 } else if (adc_mux_n < 13) {
4100 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1;
4101 mask = 0x30;
4102 shift = 4;
4103 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 +
4104 adc_mux_n - 4;
4105 } else {
4106 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1;
4107 mask = 0xC0;
4108 shift = 6;
4109 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 +
4110 adc_mux_n - 4;
4111 }
4112
4113 is_amic = (((snd_soc_component_read(comp, adc_mux_in_reg)
4114 & mask) >> shift) == 1);
4115 if (!is_amic)
4116 return 0;
4117
4118 return snd_soc_component_read(comp, amic_mux_sel_reg) & 0x07;
4119 }
4120
wcd934x_codec_get_amic_pwlvl_reg(struct snd_soc_component * comp,int amic)4121 static u16 wcd934x_codec_get_amic_pwlvl_reg(struct snd_soc_component *comp,
4122 int amic)
4123 {
4124 u16 pwr_level_reg = 0;
4125
4126 switch (amic) {
4127 case 1:
4128 case 2:
4129 pwr_level_reg = WCD934X_ANA_AMIC1;
4130 break;
4131
4132 case 3:
4133 case 4:
4134 pwr_level_reg = WCD934X_ANA_AMIC3;
4135 break;
4136 default:
4137 break;
4138 }
4139
4140 return pwr_level_reg;
4141 }
4142
wcd934x_codec_enable_dec(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)4143 static int wcd934x_codec_enable_dec(struct snd_soc_dapm_widget *w,
4144 struct snd_kcontrol *kcontrol, int event)
4145 {
4146 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4147 unsigned int decimator;
4148 char *dec_adc_mux_name = NULL;
4149 char *widget_name = NULL;
4150 char *wname;
4151 int ret = 0, amic_n;
4152 u16 tx_vol_ctl_reg, pwr_level_reg = 0, dec_cfg_reg, hpf_gate_reg;
4153 u16 tx_gain_ctl_reg;
4154 char *dec;
4155 u8 hpf_coff_freq;
4156
4157 widget_name = kstrndup(w->name, 15, GFP_KERNEL);
4158 if (!widget_name)
4159 return -ENOMEM;
4160
4161 wname = widget_name;
4162 dec_adc_mux_name = strsep(&widget_name, " ");
4163 if (!dec_adc_mux_name) {
4164 dev_err(comp->dev, "%s: Invalid decimator = %s\n",
4165 __func__, w->name);
4166 ret = -EINVAL;
4167 goto out;
4168 }
4169 dec_adc_mux_name = widget_name;
4170
4171 dec = strpbrk(dec_adc_mux_name, "012345678");
4172 if (!dec) {
4173 dev_err(comp->dev, "%s: decimator index not found\n",
4174 __func__);
4175 ret = -EINVAL;
4176 goto out;
4177 }
4178
4179 ret = kstrtouint(dec, 10, &decimator);
4180 if (ret < 0) {
4181 dev_err(comp->dev, "%s: Invalid decimator = %s\n",
4182 __func__, wname);
4183 ret = -EINVAL;
4184 goto out;
4185 }
4186
4187 tx_vol_ctl_reg = WCD934X_CDC_TX0_TX_PATH_CTL + 16 * decimator;
4188 hpf_gate_reg = WCD934X_CDC_TX0_TX_PATH_SEC2 + 16 * decimator;
4189 dec_cfg_reg = WCD934X_CDC_TX0_TX_PATH_CFG0 + 16 * decimator;
4190 tx_gain_ctl_reg = WCD934X_CDC_TX0_TX_VOL_CTL + 16 * decimator;
4191
4192 switch (event) {
4193 case SND_SOC_DAPM_PRE_PMU:
4194 amic_n = wcd934x_codec_find_amic_input(comp, decimator);
4195 if (amic_n)
4196 pwr_level_reg = wcd934x_codec_get_amic_pwlvl_reg(comp,
4197 amic_n);
4198
4199 if (!pwr_level_reg)
4200 break;
4201
4202 switch ((snd_soc_component_read(comp, pwr_level_reg) &
4203 WCD934X_AMIC_PWR_LVL_MASK) >>
4204 WCD934X_AMIC_PWR_LVL_SHIFT) {
4205 case WCD934X_AMIC_PWR_LEVEL_LP:
4206 snd_soc_component_update_bits(comp, dec_cfg_reg,
4207 WCD934X_DEC_PWR_LVL_MASK,
4208 WCD934X_DEC_PWR_LVL_LP);
4209 break;
4210 case WCD934X_AMIC_PWR_LEVEL_HP:
4211 snd_soc_component_update_bits(comp, dec_cfg_reg,
4212 WCD934X_DEC_PWR_LVL_MASK,
4213 WCD934X_DEC_PWR_LVL_HP);
4214 break;
4215 case WCD934X_AMIC_PWR_LEVEL_DEFAULT:
4216 case WCD934X_AMIC_PWR_LEVEL_HYBRID:
4217 default:
4218 snd_soc_component_update_bits(comp, dec_cfg_reg,
4219 WCD934X_DEC_PWR_LVL_MASK,
4220 WCD934X_DEC_PWR_LVL_DF);
4221 break;
4222 }
4223 break;
4224 case SND_SOC_DAPM_POST_PMU:
4225 hpf_coff_freq = (snd_soc_component_read(comp, dec_cfg_reg) &
4226 TX_HPF_CUT_OFF_FREQ_MASK) >> 5;
4227 if (hpf_coff_freq != CF_MIN_3DB_150HZ) {
4228 snd_soc_component_update_bits(comp, dec_cfg_reg,
4229 TX_HPF_CUT_OFF_FREQ_MASK,
4230 CF_MIN_3DB_150HZ << 5);
4231 snd_soc_component_update_bits(comp, hpf_gate_reg,
4232 WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ_MASK,
4233 WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ);
4234 /*
4235 * Minimum 1 clk cycle delay is required as per
4236 * HW spec.
4237 */
4238 usleep_range(1000, 1010);
4239 snd_soc_component_update_bits(comp, hpf_gate_reg,
4240 WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ_MASK,
4241 0);
4242 }
4243 /* apply gain after decimator is enabled */
4244 snd_soc_component_write(comp, tx_gain_ctl_reg,
4245 snd_soc_component_read(comp,
4246 tx_gain_ctl_reg));
4247 break;
4248 case SND_SOC_DAPM_PRE_PMD:
4249 hpf_coff_freq = (snd_soc_component_read(comp, dec_cfg_reg) &
4250 TX_HPF_CUT_OFF_FREQ_MASK) >> 5;
4251
4252 if (hpf_coff_freq != CF_MIN_3DB_150HZ) {
4253 snd_soc_component_update_bits(comp, dec_cfg_reg,
4254 TX_HPF_CUT_OFF_FREQ_MASK,
4255 hpf_coff_freq << 5);
4256 snd_soc_component_update_bits(comp, hpf_gate_reg,
4257 WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ_MASK,
4258 WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ);
4259 /*
4260 * Minimum 1 clk cycle delay is required as per
4261 * HW spec.
4262 */
4263 usleep_range(1000, 1010);
4264 snd_soc_component_update_bits(comp, hpf_gate_reg,
4265 WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ_MASK,
4266 0);
4267 }
4268 break;
4269 case SND_SOC_DAPM_POST_PMD:
4270 snd_soc_component_update_bits(comp, tx_vol_ctl_reg,
4271 0x10, 0x00);
4272 snd_soc_component_update_bits(comp, dec_cfg_reg,
4273 WCD934X_DEC_PWR_LVL_MASK,
4274 WCD934X_DEC_PWR_LVL_DF);
4275 break;
4276 }
4277 out:
4278 kfree(wname);
4279 return ret;
4280 }
4281
wcd934x_codec_set_tx_hold(struct snd_soc_component * comp,u16 amic_reg,bool set)4282 static void wcd934x_codec_set_tx_hold(struct snd_soc_component *comp,
4283 u16 amic_reg, bool set)
4284 {
4285 u8 mask = 0x20;
4286 u8 val;
4287
4288 if (amic_reg == WCD934X_ANA_AMIC1 ||
4289 amic_reg == WCD934X_ANA_AMIC3)
4290 mask = 0x40;
4291
4292 val = set ? mask : 0x00;
4293
4294 switch (amic_reg) {
4295 case WCD934X_ANA_AMIC1:
4296 case WCD934X_ANA_AMIC2:
4297 snd_soc_component_update_bits(comp, WCD934X_ANA_AMIC2,
4298 mask, val);
4299 break;
4300 case WCD934X_ANA_AMIC3:
4301 case WCD934X_ANA_AMIC4:
4302 snd_soc_component_update_bits(comp, WCD934X_ANA_AMIC4,
4303 mask, val);
4304 break;
4305 default:
4306 break;
4307 }
4308 }
4309
wcd934x_codec_enable_adc(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)4310 static int wcd934x_codec_enable_adc(struct snd_soc_dapm_widget *w,
4311 struct snd_kcontrol *kcontrol, int event)
4312 {
4313 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4314
4315 switch (event) {
4316 case SND_SOC_DAPM_PRE_PMU:
4317 wcd934x_codec_set_tx_hold(comp, w->reg, true);
4318 break;
4319 default:
4320 break;
4321 }
4322
4323 return 0;
4324 }
4325
4326 static const struct snd_soc_dapm_widget wcd934x_dapm_widgets[] = {
4327 /* Analog Outputs */
4328 SND_SOC_DAPM_OUTPUT("EAR"),
4329 SND_SOC_DAPM_OUTPUT("HPHL"),
4330 SND_SOC_DAPM_OUTPUT("HPHR"),
4331 SND_SOC_DAPM_OUTPUT("LINEOUT1"),
4332 SND_SOC_DAPM_OUTPUT("LINEOUT2"),
4333 SND_SOC_DAPM_OUTPUT("SPK1 OUT"),
4334 SND_SOC_DAPM_OUTPUT("SPK2 OUT"),
4335 SND_SOC_DAPM_OUTPUT("ANC EAR"),
4336 SND_SOC_DAPM_OUTPUT("ANC HPHL"),
4337 SND_SOC_DAPM_OUTPUT("ANC HPHR"),
4338 SND_SOC_DAPM_OUTPUT("WDMA3_OUT"),
4339 SND_SOC_DAPM_OUTPUT("MAD_CPE_OUT1"),
4340 SND_SOC_DAPM_OUTPUT("MAD_CPE_OUT2"),
4341 SND_SOC_DAPM_AIF_IN_E("AIF1 PB", "AIF1 Playback", 0, SND_SOC_NOPM,
4342 AIF1_PB, 0, wcd934x_codec_enable_slim,
4343 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4344 SND_SOC_DAPM_AIF_IN_E("AIF2 PB", "AIF2 Playback", 0, SND_SOC_NOPM,
4345 AIF2_PB, 0, wcd934x_codec_enable_slim,
4346 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4347 SND_SOC_DAPM_AIF_IN_E("AIF3 PB", "AIF3 Playback", 0, SND_SOC_NOPM,
4348 AIF3_PB, 0, wcd934x_codec_enable_slim,
4349 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4350 SND_SOC_DAPM_AIF_IN_E("AIF4 PB", "AIF4 Playback", 0, SND_SOC_NOPM,
4351 AIF4_PB, 0, wcd934x_codec_enable_slim,
4352 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4353
4354 SND_SOC_DAPM_MUX("SLIM RX0 MUX", SND_SOC_NOPM, WCD934X_RX0, 0,
4355 &slim_rx_mux[WCD934X_RX0]),
4356 SND_SOC_DAPM_MUX("SLIM RX1 MUX", SND_SOC_NOPM, WCD934X_RX1, 0,
4357 &slim_rx_mux[WCD934X_RX1]),
4358 SND_SOC_DAPM_MUX("SLIM RX2 MUX", SND_SOC_NOPM, WCD934X_RX2, 0,
4359 &slim_rx_mux[WCD934X_RX2]),
4360 SND_SOC_DAPM_MUX("SLIM RX3 MUX", SND_SOC_NOPM, WCD934X_RX3, 0,
4361 &slim_rx_mux[WCD934X_RX3]),
4362 SND_SOC_DAPM_MUX("SLIM RX4 MUX", SND_SOC_NOPM, WCD934X_RX4, 0,
4363 &slim_rx_mux[WCD934X_RX4]),
4364 SND_SOC_DAPM_MUX("SLIM RX5 MUX", SND_SOC_NOPM, WCD934X_RX5, 0,
4365 &slim_rx_mux[WCD934X_RX5]),
4366 SND_SOC_DAPM_MUX("SLIM RX6 MUX", SND_SOC_NOPM, WCD934X_RX6, 0,
4367 &slim_rx_mux[WCD934X_RX6]),
4368 SND_SOC_DAPM_MUX("SLIM RX7 MUX", SND_SOC_NOPM, WCD934X_RX7, 0,
4369 &slim_rx_mux[WCD934X_RX7]),
4370
4371 SND_SOC_DAPM_MIXER("SLIM RX0", SND_SOC_NOPM, 0, 0, NULL, 0),
4372 SND_SOC_DAPM_MIXER("SLIM RX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4373 SND_SOC_DAPM_MIXER("SLIM RX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4374 SND_SOC_DAPM_MIXER("SLIM RX3", SND_SOC_NOPM, 0, 0, NULL, 0),
4375 SND_SOC_DAPM_MIXER("SLIM RX4", SND_SOC_NOPM, 0, 0, NULL, 0),
4376 SND_SOC_DAPM_MIXER("SLIM RX5", SND_SOC_NOPM, 0, 0, NULL, 0),
4377 SND_SOC_DAPM_MIXER("SLIM RX6", SND_SOC_NOPM, 0, 0, NULL, 0),
4378 SND_SOC_DAPM_MIXER("SLIM RX7", SND_SOC_NOPM, 0, 0, NULL, 0),
4379
4380 SND_SOC_DAPM_MUX_E("RX INT0_2 MUX", SND_SOC_NOPM, INTERP_EAR, 0,
4381 &rx_int0_2_mux, wcd934x_codec_enable_mix_path,
4382 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4383 SND_SOC_DAPM_POST_PMD),
4384 SND_SOC_DAPM_MUX_E("RX INT1_2 MUX", SND_SOC_NOPM, INTERP_HPHL, 0,
4385 &rx_int1_2_mux, wcd934x_codec_enable_mix_path,
4386 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4387 SND_SOC_DAPM_POST_PMD),
4388 SND_SOC_DAPM_MUX_E("RX INT2_2 MUX", SND_SOC_NOPM, INTERP_HPHR, 0,
4389 &rx_int2_2_mux, wcd934x_codec_enable_mix_path,
4390 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4391 SND_SOC_DAPM_POST_PMD),
4392 SND_SOC_DAPM_MUX_E("RX INT3_2 MUX", SND_SOC_NOPM, INTERP_LO1, 0,
4393 &rx_int3_2_mux, wcd934x_codec_enable_mix_path,
4394 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4395 SND_SOC_DAPM_POST_PMD),
4396 SND_SOC_DAPM_MUX_E("RX INT4_2 MUX", SND_SOC_NOPM, INTERP_LO2, 0,
4397 &rx_int4_2_mux, wcd934x_codec_enable_mix_path,
4398 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4399 SND_SOC_DAPM_POST_PMD),
4400 SND_SOC_DAPM_MUX_E("RX INT7_2 MUX", SND_SOC_NOPM, INTERP_SPKR1, 0,
4401 &rx_int7_2_mux, wcd934x_codec_enable_mix_path,
4402 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4403 SND_SOC_DAPM_POST_PMD),
4404 SND_SOC_DAPM_MUX_E("RX INT8_2 MUX", SND_SOC_NOPM, INTERP_SPKR2, 0,
4405 &rx_int8_2_mux, wcd934x_codec_enable_mix_path,
4406 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4407 SND_SOC_DAPM_POST_PMD),
4408
4409 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4410 &rx_int0_1_mix_inp0_mux),
4411 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4412 &rx_int0_1_mix_inp1_mux),
4413 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4414 &rx_int0_1_mix_inp2_mux),
4415 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4416 &rx_int1_1_mix_inp0_mux),
4417 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4418 &rx_int1_1_mix_inp1_mux),
4419 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4420 &rx_int1_1_mix_inp2_mux),
4421 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4422 &rx_int2_1_mix_inp0_mux),
4423 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4424 &rx_int2_1_mix_inp1_mux),
4425 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4426 &rx_int2_1_mix_inp2_mux),
4427 SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4428 &rx_int3_1_mix_inp0_mux),
4429 SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4430 &rx_int3_1_mix_inp1_mux),
4431 SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4432 &rx_int3_1_mix_inp2_mux),
4433 SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4434 &rx_int4_1_mix_inp0_mux),
4435 SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4436 &rx_int4_1_mix_inp1_mux),
4437 SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4438 &rx_int4_1_mix_inp2_mux),
4439 SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4440 &rx_int7_1_mix_inp0_mux),
4441 SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4442 &rx_int7_1_mix_inp1_mux),
4443 SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4444 &rx_int7_1_mix_inp2_mux),
4445 SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4446 &rx_int8_1_mix_inp0_mux),
4447 SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4448 &rx_int8_1_mix_inp1_mux),
4449 SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4450 &rx_int8_1_mix_inp2_mux),
4451 SND_SOC_DAPM_MIXER("RX INT0_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4452 SND_SOC_DAPM_MIXER("RX INT0 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4453 SND_SOC_DAPM_MIXER("RX INT1_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4454 SND_SOC_DAPM_MIXER("RX INT1 SEC MIX", SND_SOC_NOPM, 0, 0,
4455 rx_int1_asrc_switch,
4456 ARRAY_SIZE(rx_int1_asrc_switch)),
4457 SND_SOC_DAPM_MIXER("RX INT2_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4458 SND_SOC_DAPM_MIXER("RX INT2 SEC MIX", SND_SOC_NOPM, 0, 0,
4459 rx_int2_asrc_switch,
4460 ARRAY_SIZE(rx_int2_asrc_switch)),
4461 SND_SOC_DAPM_MIXER("RX INT3_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4462 SND_SOC_DAPM_MIXER("RX INT3 SEC MIX", SND_SOC_NOPM, 0, 0,
4463 rx_int3_asrc_switch,
4464 ARRAY_SIZE(rx_int3_asrc_switch)),
4465 SND_SOC_DAPM_MIXER("RX INT4_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4466 SND_SOC_DAPM_MIXER("RX INT4 SEC MIX", SND_SOC_NOPM, 0, 0,
4467 rx_int4_asrc_switch,
4468 ARRAY_SIZE(rx_int4_asrc_switch)),
4469 SND_SOC_DAPM_MIXER("RX INT7_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4470 SND_SOC_DAPM_MIXER("RX INT7 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4471 SND_SOC_DAPM_MIXER("RX INT8_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4472 SND_SOC_DAPM_MIXER("RX INT8 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4473 SND_SOC_DAPM_MIXER("RX INT0 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4474 SND_SOC_DAPM_MIXER("RX INT1 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4475 SND_SOC_DAPM_MIXER("RX INT1 MIX3", SND_SOC_NOPM, 0, 0, NULL, 0),
4476 SND_SOC_DAPM_MIXER("RX INT2 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4477 SND_SOC_DAPM_MIXER("RX INT2 MIX3", SND_SOC_NOPM, 0, 0, NULL, 0),
4478 SND_SOC_DAPM_MIXER("RX INT3 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4479 SND_SOC_DAPM_MIXER("RX INT3 MIX3", SND_SOC_NOPM, 0, 0, NULL, 0),
4480 SND_SOC_DAPM_MIXER("RX INT4 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4481 SND_SOC_DAPM_MIXER("RX INT4 MIX3", SND_SOC_NOPM, 0, 0, NULL, 0),
4482
4483 SND_SOC_DAPM_MIXER("RX INT7 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4484 SND_SOC_DAPM_MIXER_E("RX INT7 CHAIN", SND_SOC_NOPM, 0, 0,
4485 NULL, 0, NULL, 0),
4486 SND_SOC_DAPM_MIXER_E("RX INT8 CHAIN", SND_SOC_NOPM, 0, 0,
4487 NULL, 0, NULL, 0),
4488 SND_SOC_DAPM_MUX_E("RX INT0 MIX2 INP", WCD934X_CDC_RX0_RX_PATH_CFG0, 4,
4489 0, &rx_int0_mix2_inp_mux, NULL,
4490 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4491 SND_SOC_DAPM_MUX_E("RX INT1 MIX2 INP", WCD934X_CDC_RX1_RX_PATH_CFG0, 4,
4492 0, &rx_int1_mix2_inp_mux, NULL,
4493 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4494 SND_SOC_DAPM_MUX_E("RX INT2 MIX2 INP", WCD934X_CDC_RX2_RX_PATH_CFG0, 4,
4495 0, &rx_int2_mix2_inp_mux, NULL,
4496 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4497 SND_SOC_DAPM_MUX_E("RX INT3 MIX2 INP", WCD934X_CDC_RX3_RX_PATH_CFG0, 4,
4498 0, &rx_int3_mix2_inp_mux, NULL,
4499 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4500 SND_SOC_DAPM_MUX_E("RX INT4 MIX2 INP", WCD934X_CDC_RX4_RX_PATH_CFG0, 4,
4501 0, &rx_int4_mix2_inp_mux, NULL,
4502 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4503 SND_SOC_DAPM_MUX_E("RX INT7 MIX2 INP", WCD934X_CDC_RX7_RX_PATH_CFG0, 4,
4504 0, &rx_int7_mix2_inp_mux, NULL,
4505 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4506
4507 SND_SOC_DAPM_MUX("IIR0 INP0 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp0_mux),
4508 SND_SOC_DAPM_MUX("IIR0 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp1_mux),
4509 SND_SOC_DAPM_MUX("IIR0 INP2 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp2_mux),
4510 SND_SOC_DAPM_MUX("IIR0 INP3 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp3_mux),
4511 SND_SOC_DAPM_MUX("IIR1 INP0 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp0_mux),
4512 SND_SOC_DAPM_MUX("IIR1 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp1_mux),
4513 SND_SOC_DAPM_MUX("IIR1 INP2 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp2_mux),
4514 SND_SOC_DAPM_MUX("IIR1 INP3 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp3_mux),
4515
4516 SND_SOC_DAPM_PGA_E("IIR0", WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B1_CTL,
4517 0, 0, NULL, 0, wcd934x_codec_set_iir_gain,
4518 SND_SOC_DAPM_POST_PMU),
4519 SND_SOC_DAPM_PGA_E("IIR1", WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B1_CTL,
4520 1, 0, NULL, 0, wcd934x_codec_set_iir_gain,
4521 SND_SOC_DAPM_POST_PMU),
4522 SND_SOC_DAPM_MIXER("SRC0", WCD934X_CDC_SIDETONE_SRC0_ST_SRC_PATH_CTL,
4523 4, 0, NULL, 0),
4524 SND_SOC_DAPM_MIXER("SRC1", WCD934X_CDC_SIDETONE_SRC1_ST_SRC_PATH_CTL,
4525 4, 0, NULL, 0),
4526 SND_SOC_DAPM_MUX("RX INT0 DEM MUX", SND_SOC_NOPM, 0, 0,
4527 &rx_int0_dem_inp_mux),
4528 SND_SOC_DAPM_MUX("RX INT1 DEM MUX", SND_SOC_NOPM, 0, 0,
4529 &rx_int1_dem_inp_mux),
4530 SND_SOC_DAPM_MUX("RX INT2 DEM MUX", SND_SOC_NOPM, 0, 0,
4531 &rx_int2_dem_inp_mux),
4532
4533 SND_SOC_DAPM_MUX_E("RX INT0_1 INTERP", SND_SOC_NOPM, INTERP_EAR, 0,
4534 &rx_int0_1_interp_mux,
4535 wcd934x_codec_enable_main_path,
4536 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4537 SND_SOC_DAPM_POST_PMD),
4538 SND_SOC_DAPM_MUX_E("RX INT1_1 INTERP", SND_SOC_NOPM, INTERP_HPHL, 0,
4539 &rx_int1_1_interp_mux,
4540 wcd934x_codec_enable_main_path,
4541 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4542 SND_SOC_DAPM_POST_PMD),
4543 SND_SOC_DAPM_MUX_E("RX INT2_1 INTERP", SND_SOC_NOPM, INTERP_HPHR, 0,
4544 &rx_int2_1_interp_mux,
4545 wcd934x_codec_enable_main_path,
4546 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4547 SND_SOC_DAPM_POST_PMD),
4548 SND_SOC_DAPM_MUX_E("RX INT3_1 INTERP", SND_SOC_NOPM, INTERP_LO1, 0,
4549 &rx_int3_1_interp_mux,
4550 wcd934x_codec_enable_main_path,
4551 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4552 SND_SOC_DAPM_POST_PMD),
4553 SND_SOC_DAPM_MUX_E("RX INT4_1 INTERP", SND_SOC_NOPM, INTERP_LO2, 0,
4554 &rx_int4_1_interp_mux,
4555 wcd934x_codec_enable_main_path,
4556 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4557 SND_SOC_DAPM_POST_PMD),
4558 SND_SOC_DAPM_MUX_E("RX INT7_1 INTERP", SND_SOC_NOPM, INTERP_SPKR1, 0,
4559 &rx_int7_1_interp_mux,
4560 wcd934x_codec_enable_main_path,
4561 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4562 SND_SOC_DAPM_POST_PMD),
4563 SND_SOC_DAPM_MUX_E("RX INT8_1 INTERP", SND_SOC_NOPM, INTERP_SPKR2, 0,
4564 &rx_int8_1_interp_mux,
4565 wcd934x_codec_enable_main_path,
4566 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4567 SND_SOC_DAPM_POST_PMD),
4568
4569 SND_SOC_DAPM_MUX("RX INT0_2 INTERP", SND_SOC_NOPM, 0, 0,
4570 &rx_int0_2_interp_mux),
4571 SND_SOC_DAPM_MUX("RX INT1_2 INTERP", SND_SOC_NOPM, 0, 0,
4572 &rx_int1_2_interp_mux),
4573 SND_SOC_DAPM_MUX("RX INT2_2 INTERP", SND_SOC_NOPM, 0, 0,
4574 &rx_int2_2_interp_mux),
4575 SND_SOC_DAPM_MUX("RX INT3_2 INTERP", SND_SOC_NOPM, 0, 0,
4576 &rx_int3_2_interp_mux),
4577 SND_SOC_DAPM_MUX("RX INT4_2 INTERP", SND_SOC_NOPM, 0, 0,
4578 &rx_int4_2_interp_mux),
4579 SND_SOC_DAPM_MUX("RX INT7_2 INTERP", SND_SOC_NOPM, 0, 0,
4580 &rx_int7_2_interp_mux),
4581 SND_SOC_DAPM_MUX("RX INT8_2 INTERP", SND_SOC_NOPM, 0, 0,
4582 &rx_int8_2_interp_mux),
4583 SND_SOC_DAPM_DAC_E("RX INT0 DAC", NULL, SND_SOC_NOPM,
4584 0, 0, wcd934x_codec_ear_dac_event,
4585 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4586 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4587 SND_SOC_DAPM_DAC_E("RX INT1 DAC", NULL, WCD934X_ANA_HPH,
4588 5, 0, wcd934x_codec_hphl_dac_event,
4589 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4590 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4591 SND_SOC_DAPM_DAC_E("RX INT2 DAC", NULL, WCD934X_ANA_HPH,
4592 4, 0, wcd934x_codec_hphr_dac_event,
4593 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4594 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4595 SND_SOC_DAPM_DAC_E("RX INT3 DAC", NULL, SND_SOC_NOPM,
4596 0, 0, wcd934x_codec_lineout_dac_event,
4597 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4598 SND_SOC_DAPM_DAC_E("RX INT4 DAC", NULL, SND_SOC_NOPM,
4599 0, 0, wcd934x_codec_lineout_dac_event,
4600 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4601 SND_SOC_DAPM_PGA_E("EAR PA", WCD934X_ANA_EAR, 7, 0, NULL, 0, NULL, 0),
4602 SND_SOC_DAPM_PGA_E("HPHL PA", WCD934X_ANA_HPH, 7, 0, NULL, 0,
4603 wcd934x_codec_enable_hphl_pa,
4604 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4605 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4606 SND_SOC_DAPM_PGA_E("HPHR PA", WCD934X_ANA_HPH, 6, 0, NULL, 0,
4607 wcd934x_codec_enable_hphr_pa,
4608 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4609 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4610 SND_SOC_DAPM_PGA_E("LINEOUT1 PA", WCD934X_ANA_LO_1_2, 7, 0, NULL, 0,
4611 NULL, 0),
4612 SND_SOC_DAPM_PGA_E("LINEOUT2 PA", WCD934X_ANA_LO_1_2, 6, 0, NULL, 0,
4613 NULL, 0),
4614 SND_SOC_DAPM_SUPPLY("RX_BIAS", WCD934X_ANA_RX_SUPPLIES, 0, 0, NULL,
4615 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4616 SND_SOC_DAPM_SUPPLY("SBOOST0", WCD934X_CDC_RX7_RX_PATH_CFG1,
4617 0, 0, NULL, 0),
4618 SND_SOC_DAPM_SUPPLY("SBOOST0_CLK", WCD934X_CDC_BOOST0_BOOST_PATH_CTL,
4619 0, 0, NULL, 0),
4620 SND_SOC_DAPM_SUPPLY("SBOOST1", WCD934X_CDC_RX8_RX_PATH_CFG1,
4621 0, 0, NULL, 0),
4622 SND_SOC_DAPM_SUPPLY("SBOOST1_CLK", WCD934X_CDC_BOOST1_BOOST_PATH_CTL,
4623 0, 0, NULL, 0),
4624 SND_SOC_DAPM_SUPPLY("INT0_CLK", SND_SOC_NOPM, INTERP_EAR, 0,
4625 wcd934x_codec_enable_interp_clk,
4626 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4627 SND_SOC_DAPM_SUPPLY("INT1_CLK", SND_SOC_NOPM, INTERP_HPHL, 0,
4628 wcd934x_codec_enable_interp_clk,
4629 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4630 SND_SOC_DAPM_SUPPLY("INT2_CLK", SND_SOC_NOPM, INTERP_HPHR, 0,
4631 wcd934x_codec_enable_interp_clk,
4632 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4633 SND_SOC_DAPM_SUPPLY("INT3_CLK", SND_SOC_NOPM, INTERP_LO1, 0,
4634 wcd934x_codec_enable_interp_clk,
4635 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4636 SND_SOC_DAPM_SUPPLY("INT4_CLK", SND_SOC_NOPM, INTERP_LO2, 0,
4637 wcd934x_codec_enable_interp_clk,
4638 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4639 SND_SOC_DAPM_SUPPLY("INT7_CLK", SND_SOC_NOPM, INTERP_SPKR1, 0,
4640 wcd934x_codec_enable_interp_clk,
4641 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4642 SND_SOC_DAPM_SUPPLY("INT8_CLK", SND_SOC_NOPM, INTERP_SPKR2, 0,
4643 wcd934x_codec_enable_interp_clk,
4644 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4645 SND_SOC_DAPM_SUPPLY("DSMDEM0_CLK", WCD934X_CDC_RX0_RX_PATH_DSMDEM_CTL,
4646 0, 0, NULL, 0),
4647 SND_SOC_DAPM_SUPPLY("DSMDEM1_CLK", WCD934X_CDC_RX1_RX_PATH_DSMDEM_CTL,
4648 0, 0, NULL, 0),
4649 SND_SOC_DAPM_SUPPLY("DSMDEM2_CLK", WCD934X_CDC_RX2_RX_PATH_DSMDEM_CTL,
4650 0, 0, NULL, 0),
4651 SND_SOC_DAPM_SUPPLY("DSMDEM3_CLK", WCD934X_CDC_RX3_RX_PATH_DSMDEM_CTL,
4652 0, 0, NULL, 0),
4653 SND_SOC_DAPM_SUPPLY("DSMDEM4_CLK", WCD934X_CDC_RX4_RX_PATH_DSMDEM_CTL,
4654 0, 0, NULL, 0),
4655 SND_SOC_DAPM_SUPPLY("DSMDEM7_CLK", WCD934X_CDC_RX7_RX_PATH_DSMDEM_CTL,
4656 0, 0, NULL, 0),
4657 SND_SOC_DAPM_SUPPLY("DSMDEM8_CLK", WCD934X_CDC_RX8_RX_PATH_DSMDEM_CTL,
4658 0, 0, NULL, 0),
4659 SND_SOC_DAPM_SUPPLY("MCLK", SND_SOC_NOPM, 0, 0,
4660 wcd934x_codec_enable_mclk,
4661 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4662
4663 /* TX */
4664 SND_SOC_DAPM_INPUT("AMIC1"),
4665 SND_SOC_DAPM_INPUT("AMIC2"),
4666 SND_SOC_DAPM_INPUT("AMIC3"),
4667 SND_SOC_DAPM_INPUT("AMIC4"),
4668 SND_SOC_DAPM_INPUT("AMIC5"),
4669 SND_SOC_DAPM_INPUT("DMIC0 Pin"),
4670 SND_SOC_DAPM_INPUT("DMIC1 Pin"),
4671 SND_SOC_DAPM_INPUT("DMIC2 Pin"),
4672 SND_SOC_DAPM_INPUT("DMIC3 Pin"),
4673 SND_SOC_DAPM_INPUT("DMIC4 Pin"),
4674 SND_SOC_DAPM_INPUT("DMIC5 Pin"),
4675
4676 SND_SOC_DAPM_AIF_OUT_E("AIF1 CAP", "AIF1 Capture", 0, SND_SOC_NOPM,
4677 AIF1_CAP, 0, wcd934x_codec_enable_slim,
4678 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4679 SND_SOC_DAPM_AIF_OUT_E("AIF2 CAP", "AIF2 Capture", 0, SND_SOC_NOPM,
4680 AIF2_CAP, 0, wcd934x_codec_enable_slim,
4681 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4682 SND_SOC_DAPM_AIF_OUT_E("AIF3 CAP", "AIF3 Capture", 0, SND_SOC_NOPM,
4683 AIF3_CAP, 0, wcd934x_codec_enable_slim,
4684 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4685
4686 SND_SOC_DAPM_MIXER("SLIM TX0", SND_SOC_NOPM, 0, 0, NULL, 0),
4687 SND_SOC_DAPM_MIXER("SLIM TX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4688 SND_SOC_DAPM_MIXER("SLIM TX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4689 SND_SOC_DAPM_MIXER("SLIM TX3", SND_SOC_NOPM, 0, 0, NULL, 0),
4690 SND_SOC_DAPM_MIXER("SLIM TX4", SND_SOC_NOPM, 0, 0, NULL, 0),
4691 SND_SOC_DAPM_MIXER("SLIM TX5", SND_SOC_NOPM, 0, 0, NULL, 0),
4692 SND_SOC_DAPM_MIXER("SLIM TX6", SND_SOC_NOPM, 0, 0, NULL, 0),
4693 SND_SOC_DAPM_MIXER("SLIM TX7", SND_SOC_NOPM, 0, 0, NULL, 0),
4694 SND_SOC_DAPM_MIXER("SLIM TX8", SND_SOC_NOPM, 0, 0, NULL, 0),
4695 SND_SOC_DAPM_MIXER("SLIM TX9", SND_SOC_NOPM, 0, 0, NULL, 0),
4696 SND_SOC_DAPM_MIXER("SLIM TX10", SND_SOC_NOPM, 0, 0, NULL, 0),
4697 SND_SOC_DAPM_MIXER("SLIM TX11", SND_SOC_NOPM, 0, 0, NULL, 0),
4698 SND_SOC_DAPM_MIXER("SLIM TX13", SND_SOC_NOPM, 0, 0, NULL, 0),
4699
4700 /* Digital Mic Inputs */
4701 SND_SOC_DAPM_ADC_E("DMIC0", NULL, SND_SOC_NOPM, 0, 0,
4702 wcd934x_codec_enable_dmic,
4703 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4704 SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
4705 wcd934x_codec_enable_dmic,
4706 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4707 SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 0, 0,
4708 wcd934x_codec_enable_dmic,
4709 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4710 SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 0, 0,
4711 wcd934x_codec_enable_dmic,
4712 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4713 SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 0, 0,
4714 wcd934x_codec_enable_dmic,
4715 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4716 SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 0, 0,
4717 wcd934x_codec_enable_dmic,
4718 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4719 SND_SOC_DAPM_MUX("DMIC MUX0", SND_SOC_NOPM, 0, 0, &tx_dmic_mux0),
4720 SND_SOC_DAPM_MUX("DMIC MUX1", SND_SOC_NOPM, 0, 0, &tx_dmic_mux1),
4721 SND_SOC_DAPM_MUX("DMIC MUX2", SND_SOC_NOPM, 0, 0, &tx_dmic_mux2),
4722 SND_SOC_DAPM_MUX("DMIC MUX3", SND_SOC_NOPM, 0, 0, &tx_dmic_mux3),
4723 SND_SOC_DAPM_MUX("DMIC MUX4", SND_SOC_NOPM, 0, 0, &tx_dmic_mux4),
4724 SND_SOC_DAPM_MUX("DMIC MUX5", SND_SOC_NOPM, 0, 0, &tx_dmic_mux5),
4725 SND_SOC_DAPM_MUX("DMIC MUX6", SND_SOC_NOPM, 0, 0, &tx_dmic_mux6),
4726 SND_SOC_DAPM_MUX("DMIC MUX7", SND_SOC_NOPM, 0, 0, &tx_dmic_mux7),
4727 SND_SOC_DAPM_MUX("DMIC MUX8", SND_SOC_NOPM, 0, 0, &tx_dmic_mux8),
4728 SND_SOC_DAPM_MUX("AMIC MUX0", SND_SOC_NOPM, 0, 0, &tx_amic_mux0),
4729 SND_SOC_DAPM_MUX("AMIC MUX1", SND_SOC_NOPM, 0, 0, &tx_amic_mux1),
4730 SND_SOC_DAPM_MUX("AMIC MUX2", SND_SOC_NOPM, 0, 0, &tx_amic_mux2),
4731 SND_SOC_DAPM_MUX("AMIC MUX3", SND_SOC_NOPM, 0, 0, &tx_amic_mux3),
4732 SND_SOC_DAPM_MUX("AMIC MUX4", SND_SOC_NOPM, 0, 0, &tx_amic_mux4),
4733 SND_SOC_DAPM_MUX("AMIC MUX5", SND_SOC_NOPM, 0, 0, &tx_amic_mux5),
4734 SND_SOC_DAPM_MUX("AMIC MUX6", SND_SOC_NOPM, 0, 0, &tx_amic_mux6),
4735 SND_SOC_DAPM_MUX("AMIC MUX7", SND_SOC_NOPM, 0, 0, &tx_amic_mux7),
4736 SND_SOC_DAPM_MUX("AMIC MUX8", SND_SOC_NOPM, 0, 0, &tx_amic_mux8),
4737 SND_SOC_DAPM_MUX_E("ADC MUX0", WCD934X_CDC_TX0_TX_PATH_CTL, 5, 0,
4738 &tx_adc_mux0_mux, wcd934x_codec_enable_dec,
4739 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4740 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4741 SND_SOC_DAPM_MUX_E("ADC MUX1", WCD934X_CDC_TX1_TX_PATH_CTL, 5, 0,
4742 &tx_adc_mux1_mux, wcd934x_codec_enable_dec,
4743 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4744 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4745 SND_SOC_DAPM_MUX_E("ADC MUX2", WCD934X_CDC_TX2_TX_PATH_CTL, 5, 0,
4746 &tx_adc_mux2_mux, wcd934x_codec_enable_dec,
4747 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4748 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4749 SND_SOC_DAPM_MUX_E("ADC MUX3", WCD934X_CDC_TX3_TX_PATH_CTL, 5, 0,
4750 &tx_adc_mux3_mux, wcd934x_codec_enable_dec,
4751 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4752 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4753 SND_SOC_DAPM_MUX_E("ADC MUX4", WCD934X_CDC_TX4_TX_PATH_CTL, 5, 0,
4754 &tx_adc_mux4_mux, wcd934x_codec_enable_dec,
4755 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4756 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4757 SND_SOC_DAPM_MUX_E("ADC MUX5", WCD934X_CDC_TX5_TX_PATH_CTL, 5, 0,
4758 &tx_adc_mux5_mux, wcd934x_codec_enable_dec,
4759 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4760 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4761 SND_SOC_DAPM_MUX_E("ADC MUX6", WCD934X_CDC_TX6_TX_PATH_CTL, 5, 0,
4762 &tx_adc_mux6_mux, wcd934x_codec_enable_dec,
4763 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4764 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4765 SND_SOC_DAPM_MUX_E("ADC MUX7", WCD934X_CDC_TX7_TX_PATH_CTL, 5, 0,
4766 &tx_adc_mux7_mux, wcd934x_codec_enable_dec,
4767 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4768 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4769 SND_SOC_DAPM_MUX_E("ADC MUX8", WCD934X_CDC_TX8_TX_PATH_CTL, 5, 0,
4770 &tx_adc_mux8_mux, wcd934x_codec_enable_dec,
4771 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4772 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4773 SND_SOC_DAPM_ADC_E("ADC1", NULL, WCD934X_ANA_AMIC1, 7, 0,
4774 wcd934x_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
4775 SND_SOC_DAPM_ADC_E("ADC2", NULL, WCD934X_ANA_AMIC2, 7, 0,
4776 wcd934x_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
4777 SND_SOC_DAPM_ADC_E("ADC3", NULL, WCD934X_ANA_AMIC3, 7, 0,
4778 wcd934x_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
4779 SND_SOC_DAPM_ADC_E("ADC4", NULL, WCD934X_ANA_AMIC4, 7, 0,
4780 wcd934x_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
4781 SND_SOC_DAPM_SUPPLY("MIC BIAS1", WCD934X_ANA_MICB1, 6, 0, NULL,
4782 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4783 SND_SOC_DAPM_SUPPLY("MIC BIAS2", WCD934X_ANA_MICB2, 6, 0, NULL,
4784 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4785 SND_SOC_DAPM_SUPPLY("MIC BIAS3", WCD934X_ANA_MICB3, 6, 0, NULL,
4786 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4787 SND_SOC_DAPM_SUPPLY("MIC BIAS4", WCD934X_ANA_MICB4, 6, 0, NULL,
4788 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4789
4790 SND_SOC_DAPM_MUX("AMIC4_5 SEL", SND_SOC_NOPM, 0, 0, &tx_amic4_5),
4791 SND_SOC_DAPM_MUX("CDC_IF TX0 MUX", SND_SOC_NOPM, WCD934X_TX0, 0,
4792 &cdc_if_tx0_mux),
4793 SND_SOC_DAPM_MUX("CDC_IF TX1 MUX", SND_SOC_NOPM, WCD934X_TX1, 0,
4794 &cdc_if_tx1_mux),
4795 SND_SOC_DAPM_MUX("CDC_IF TX2 MUX", SND_SOC_NOPM, WCD934X_TX2, 0,
4796 &cdc_if_tx2_mux),
4797 SND_SOC_DAPM_MUX("CDC_IF TX3 MUX", SND_SOC_NOPM, WCD934X_TX3, 0,
4798 &cdc_if_tx3_mux),
4799 SND_SOC_DAPM_MUX("CDC_IF TX4 MUX", SND_SOC_NOPM, WCD934X_TX4, 0,
4800 &cdc_if_tx4_mux),
4801 SND_SOC_DAPM_MUX("CDC_IF TX5 MUX", SND_SOC_NOPM, WCD934X_TX5, 0,
4802 &cdc_if_tx5_mux),
4803 SND_SOC_DAPM_MUX("CDC_IF TX6 MUX", SND_SOC_NOPM, WCD934X_TX6, 0,
4804 &cdc_if_tx6_mux),
4805 SND_SOC_DAPM_MUX("CDC_IF TX7 MUX", SND_SOC_NOPM, WCD934X_TX7, 0,
4806 &cdc_if_tx7_mux),
4807 SND_SOC_DAPM_MUX("CDC_IF TX8 MUX", SND_SOC_NOPM, WCD934X_TX8, 0,
4808 &cdc_if_tx8_mux),
4809 SND_SOC_DAPM_MUX("CDC_IF TX9 MUX", SND_SOC_NOPM, WCD934X_TX9, 0,
4810 &cdc_if_tx9_mux),
4811 SND_SOC_DAPM_MUX("CDC_IF TX10 MUX", SND_SOC_NOPM, WCD934X_TX10, 0,
4812 &cdc_if_tx10_mux),
4813 SND_SOC_DAPM_MUX("CDC_IF TX11 MUX", SND_SOC_NOPM, WCD934X_TX11, 0,
4814 &cdc_if_tx11_mux),
4815 SND_SOC_DAPM_MUX("CDC_IF TX11 INP1 MUX", SND_SOC_NOPM, WCD934X_TX11, 0,
4816 &cdc_if_tx11_inp1_mux),
4817 SND_SOC_DAPM_MUX("CDC_IF TX13 MUX", SND_SOC_NOPM, WCD934X_TX13, 0,
4818 &cdc_if_tx13_mux),
4819 SND_SOC_DAPM_MUX("CDC_IF TX13 INP1 MUX", SND_SOC_NOPM, WCD934X_TX13, 0,
4820 &cdc_if_tx13_inp1_mux),
4821 SND_SOC_DAPM_MIXER("AIF1_CAP Mixer", SND_SOC_NOPM, AIF1_CAP, 0,
4822 aif1_slim_cap_mixer,
4823 ARRAY_SIZE(aif1_slim_cap_mixer)),
4824 SND_SOC_DAPM_MIXER("AIF2_CAP Mixer", SND_SOC_NOPM, AIF2_CAP, 0,
4825 aif2_slim_cap_mixer,
4826 ARRAY_SIZE(aif2_slim_cap_mixer)),
4827 SND_SOC_DAPM_MIXER("AIF3_CAP Mixer", SND_SOC_NOPM, AIF3_CAP, 0,
4828 aif3_slim_cap_mixer,
4829 ARRAY_SIZE(aif3_slim_cap_mixer)),
4830 };
4831
4832 static const struct snd_soc_dapm_route wcd934x_audio_map[] = {
4833 /* RX0-RX7 */
4834 WCD934X_SLIM_RX_AIF_PATH(0),
4835 WCD934X_SLIM_RX_AIF_PATH(1),
4836 WCD934X_SLIM_RX_AIF_PATH(2),
4837 WCD934X_SLIM_RX_AIF_PATH(3),
4838 WCD934X_SLIM_RX_AIF_PATH(4),
4839 WCD934X_SLIM_RX_AIF_PATH(5),
4840 WCD934X_SLIM_RX_AIF_PATH(6),
4841 WCD934X_SLIM_RX_AIF_PATH(7),
4842
4843 /* RX0 Ear out */
4844 WCD934X_INTERPOLATOR_PATH(0),
4845 WCD934X_INTERPOLATOR_MIX2(0),
4846 {"RX INT0 DEM MUX", "CLSH_DSM_OUT", "RX INT0 MIX2"},
4847 {"RX INT0 DAC", NULL, "RX INT0 DEM MUX"},
4848 {"RX INT0 DAC", NULL, "RX_BIAS"},
4849 {"EAR PA", NULL, "RX INT0 DAC"},
4850 {"EAR", NULL, "EAR PA"},
4851
4852 /* RX1 Headphone left */
4853 WCD934X_INTERPOLATOR_PATH(1),
4854 WCD934X_INTERPOLATOR_MIX2(1),
4855 {"RX INT1 MIX3", NULL, "RX INT1 MIX2"},
4856 {"RX INT1 DEM MUX", "CLSH_DSM_OUT", "RX INT1 MIX3"},
4857 {"RX INT1 DAC", NULL, "RX INT1 DEM MUX"},
4858 {"RX INT1 DAC", NULL, "RX_BIAS"},
4859 {"HPHL PA", NULL, "RX INT1 DAC"},
4860 {"HPHL", NULL, "HPHL PA"},
4861
4862 /* RX2 Headphone right */
4863 WCD934X_INTERPOLATOR_PATH(2),
4864 WCD934X_INTERPOLATOR_MIX2(2),
4865 {"RX INT2 MIX3", NULL, "RX INT2 MIX2"},
4866 {"RX INT2 DEM MUX", "CLSH_DSM_OUT", "RX INT2 MIX3"},
4867 {"RX INT2 DAC", NULL, "RX INT2 DEM MUX"},
4868 {"RX INT2 DAC", NULL, "RX_BIAS"},
4869 {"HPHR PA", NULL, "RX INT2 DAC"},
4870 {"HPHR", NULL, "HPHR PA"},
4871
4872 /* RX3 HIFi LineOut1 */
4873 WCD934X_INTERPOLATOR_PATH(3),
4874 WCD934X_INTERPOLATOR_MIX2(3),
4875 {"RX INT3 MIX3", NULL, "RX INT3 MIX2"},
4876 {"RX INT3 DAC", NULL, "RX INT3 MIX3"},
4877 {"RX INT3 DAC", NULL, "RX_BIAS"},
4878 {"LINEOUT1 PA", NULL, "RX INT3 DAC"},
4879 {"LINEOUT1", NULL, "LINEOUT1 PA"},
4880
4881 /* RX4 HIFi LineOut2 */
4882 WCD934X_INTERPOLATOR_PATH(4),
4883 WCD934X_INTERPOLATOR_MIX2(4),
4884 {"RX INT4 MIX3", NULL, "RX INT4 MIX2"},
4885 {"RX INT4 DAC", NULL, "RX INT4 MIX3"},
4886 {"RX INT4 DAC", NULL, "RX_BIAS"},
4887 {"LINEOUT2 PA", NULL, "RX INT4 DAC"},
4888 {"LINEOUT2", NULL, "LINEOUT2 PA"},
4889
4890 /* RX7 Speaker Left Out PA */
4891 WCD934X_INTERPOLATOR_PATH(7),
4892 WCD934X_INTERPOLATOR_MIX2(7),
4893 {"RX INT7 CHAIN", NULL, "RX INT7 MIX2"},
4894 {"RX INT7 CHAIN", NULL, "RX_BIAS"},
4895 {"RX INT7 CHAIN", NULL, "SBOOST0"},
4896 {"RX INT7 CHAIN", NULL, "SBOOST0_CLK"},
4897 {"SPK1 OUT", NULL, "RX INT7 CHAIN"},
4898
4899 /* RX8 Speaker Right Out PA */
4900 WCD934X_INTERPOLATOR_PATH(8),
4901 {"RX INT8 CHAIN", NULL, "RX INT8 SEC MIX"},
4902 {"RX INT8 CHAIN", NULL, "RX_BIAS"},
4903 {"RX INT8 CHAIN", NULL, "SBOOST1"},
4904 {"RX INT8 CHAIN", NULL, "SBOOST1_CLK"},
4905 {"SPK2 OUT", NULL, "RX INT8 CHAIN"},
4906
4907 /* Tx */
4908 {"AIF1 CAP", NULL, "AIF1_CAP Mixer"},
4909 {"AIF2 CAP", NULL, "AIF2_CAP Mixer"},
4910 {"AIF3 CAP", NULL, "AIF3_CAP Mixer"},
4911
4912 WCD934X_SLIM_TX_AIF_PATH(0),
4913 WCD934X_SLIM_TX_AIF_PATH(1),
4914 WCD934X_SLIM_TX_AIF_PATH(2),
4915 WCD934X_SLIM_TX_AIF_PATH(3),
4916 WCD934X_SLIM_TX_AIF_PATH(4),
4917 WCD934X_SLIM_TX_AIF_PATH(5),
4918 WCD934X_SLIM_TX_AIF_PATH(6),
4919 WCD934X_SLIM_TX_AIF_PATH(7),
4920 WCD934X_SLIM_TX_AIF_PATH(8),
4921
4922 WCD934X_ADC_MUX(0),
4923 WCD934X_ADC_MUX(1),
4924 WCD934X_ADC_MUX(2),
4925 WCD934X_ADC_MUX(3),
4926 WCD934X_ADC_MUX(4),
4927 WCD934X_ADC_MUX(5),
4928 WCD934X_ADC_MUX(6),
4929 WCD934X_ADC_MUX(7),
4930 WCD934X_ADC_MUX(8),
4931
4932 {"CDC_IF TX0 MUX", "DEC0", "ADC MUX0"},
4933 {"CDC_IF TX1 MUX", "DEC1", "ADC MUX1"},
4934 {"CDC_IF TX2 MUX", "DEC2", "ADC MUX2"},
4935 {"CDC_IF TX3 MUX", "DEC3", "ADC MUX3"},
4936 {"CDC_IF TX4 MUX", "DEC4", "ADC MUX4"},
4937 {"CDC_IF TX5 MUX", "DEC5", "ADC MUX5"},
4938 {"CDC_IF TX6 MUX", "DEC6", "ADC MUX6"},
4939 {"CDC_IF TX7 MUX", "DEC7", "ADC MUX7"},
4940 {"CDC_IF TX8 MUX", "DEC8", "ADC MUX8"},
4941
4942 {"AMIC4_5 SEL", "AMIC4", "AMIC4"},
4943 {"AMIC4_5 SEL", "AMIC5", "AMIC5"},
4944
4945 { "DMIC0", NULL, "DMIC0 Pin" },
4946 { "DMIC1", NULL, "DMIC1 Pin" },
4947 { "DMIC2", NULL, "DMIC2 Pin" },
4948 { "DMIC3", NULL, "DMIC3 Pin" },
4949 { "DMIC4", NULL, "DMIC4 Pin" },
4950 { "DMIC5", NULL, "DMIC5 Pin" },
4951
4952 {"ADC1", NULL, "AMIC1"},
4953 {"ADC2", NULL, "AMIC2"},
4954 {"ADC3", NULL, "AMIC3"},
4955 {"ADC4", NULL, "AMIC4_5 SEL"},
4956
4957 WCD934X_IIR_INP_MUX(0),
4958 WCD934X_IIR_INP_MUX(1),
4959
4960 {"SRC0", NULL, "IIR0"},
4961 {"SRC1", NULL, "IIR1"},
4962 };
4963
4964 static const struct snd_soc_component_driver wcd934x_component_drv = {
4965 .probe = wcd934x_comp_probe,
4966 .remove = wcd934x_comp_remove,
4967 .set_sysclk = wcd934x_comp_set_sysclk,
4968 .controls = wcd934x_snd_controls,
4969 .num_controls = ARRAY_SIZE(wcd934x_snd_controls),
4970 .dapm_widgets = wcd934x_dapm_widgets,
4971 .num_dapm_widgets = ARRAY_SIZE(wcd934x_dapm_widgets),
4972 .dapm_routes = wcd934x_audio_map,
4973 .num_dapm_routes = ARRAY_SIZE(wcd934x_audio_map),
4974 };
4975
wcd934x_codec_parse_data(struct wcd934x_codec * wcd)4976 static int wcd934x_codec_parse_data(struct wcd934x_codec *wcd)
4977 {
4978 struct device *dev = &wcd->sdev->dev;
4979 struct device_node *ifc_dev_np;
4980
4981 ifc_dev_np = of_parse_phandle(dev->of_node, "slim-ifc-dev", 0);
4982 if (!ifc_dev_np) {
4983 dev_err(dev, "No Interface device found\n");
4984 return -EINVAL;
4985 }
4986
4987 wcd->sidev = of_slim_get_device(wcd->sdev->ctrl, ifc_dev_np);
4988 if (!wcd->sidev) {
4989 dev_err(dev, "Unable to get SLIM Interface device\n");
4990 return -EINVAL;
4991 }
4992
4993 slim_get_logical_addr(wcd->sidev);
4994 wcd->if_regmap = regmap_init_slimbus(wcd->sidev,
4995 &wcd934x_ifc_regmap_config);
4996 if (IS_ERR(wcd->if_regmap)) {
4997 dev_err(dev, "Failed to allocate ifc register map\n");
4998 return PTR_ERR(wcd->if_regmap);
4999 }
5000
5001 of_property_read_u32(dev->parent->of_node, "qcom,dmic-sample-rate",
5002 &wcd->dmic_sample_rate);
5003
5004 return 0;
5005 }
5006
wcd934x_codec_probe(struct platform_device * pdev)5007 static int wcd934x_codec_probe(struct platform_device *pdev)
5008 {
5009 struct wcd934x_ddata *data = dev_get_drvdata(pdev->dev.parent);
5010 struct wcd934x_codec *wcd;
5011 struct device *dev = &pdev->dev;
5012 int ret, irq;
5013
5014 wcd = devm_kzalloc(&pdev->dev, sizeof(*wcd), GFP_KERNEL);
5015 if (!wcd)
5016 return -ENOMEM;
5017
5018 wcd->dev = dev;
5019 wcd->regmap = data->regmap;
5020 wcd->extclk = data->extclk;
5021 wcd->sdev = to_slim_device(data->dev);
5022 mutex_init(&wcd->sysclk_mutex);
5023
5024 ret = wcd934x_codec_parse_data(wcd);
5025 if (ret) {
5026 dev_err(wcd->dev, "Failed to get SLIM IRQ\n");
5027 return ret;
5028 }
5029
5030 /* set default rate 9P6MHz */
5031 regmap_update_bits(wcd->regmap, WCD934X_CODEC_RPM_CLK_MCLK_CFG,
5032 WCD934X_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK,
5033 WCD934X_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ);
5034 memcpy(wcd->rx_chs, wcd934x_rx_chs, sizeof(wcd934x_rx_chs));
5035 memcpy(wcd->tx_chs, wcd934x_tx_chs, sizeof(wcd934x_tx_chs));
5036
5037 irq = regmap_irq_get_virq(data->irq_data, WCD934X_IRQ_SLIMBUS);
5038 if (irq < 0) {
5039 dev_err(wcd->dev, "Failed to get SLIM IRQ\n");
5040 return irq;
5041 }
5042
5043 ret = devm_request_threaded_irq(dev, irq, NULL,
5044 wcd934x_slim_irq_handler,
5045 IRQF_TRIGGER_RISING | IRQF_ONESHOT,
5046 "slim", wcd);
5047 if (ret) {
5048 dev_err(dev, "Failed to request slimbus irq\n");
5049 return ret;
5050 }
5051
5052 wcd934x_register_mclk_output(wcd);
5053 platform_set_drvdata(pdev, wcd);
5054
5055 return devm_snd_soc_register_component(dev, &wcd934x_component_drv,
5056 wcd934x_slim_dais,
5057 ARRAY_SIZE(wcd934x_slim_dais));
5058 }
5059
5060 static const struct platform_device_id wcd934x_driver_id[] = {
5061 {
5062 .name = "wcd934x-codec",
5063 },
5064 {},
5065 };
5066 MODULE_DEVICE_TABLE(platform, wcd934x_driver_id);
5067
5068 static struct platform_driver wcd934x_codec_driver = {
5069 .probe = &wcd934x_codec_probe,
5070 .id_table = wcd934x_driver_id,
5071 .driver = {
5072 .name = "wcd934x-codec",
5073 }
5074 };
5075
5076 MODULE_ALIAS("platform:wcd934x-codec");
5077 module_platform_driver(wcd934x_codec_driver);
5078 MODULE_DESCRIPTION("WCD934x codec driver");
5079 MODULE_LICENSE("GPL v2");
5080