1================================== 2Cache and TLB Flushing Under Linux 3================================== 4 5:Author: David S. Miller <davem@redhat.com> 6 7This document describes the cache/tlb flushing interfaces called 8by the Linux VM subsystem. It enumerates over each interface, 9describes its intended purpose, and what side effect is expected 10after the interface is invoked. 11 12The side effects described below are stated for a uniprocessor 13implementation, and what is to happen on that single processor. The 14SMP cases are a simple extension, in that you just extend the 15definition such that the side effect for a particular interface occurs 16on all processors in the system. Don't let this scare you into 17thinking SMP cache/tlb flushing must be so inefficient, this is in 18fact an area where many optimizations are possible. For example, 19if it can be proven that a user address space has never executed 20on a cpu (see mm_cpumask()), one need not perform a flush 21for this address space on that cpu. 22 23First, the TLB flushing interfaces, since they are the simplest. The 24"TLB" is abstracted under Linux as something the cpu uses to cache 25virtual-->physical address translations obtained from the software 26page tables. Meaning that if the software page tables change, it is 27possible for stale translations to exist in this "TLB" cache. 28Therefore when software page table changes occur, the kernel will 29invoke one of the following flush methods _after_ the page table 30changes occur: 31 321) ``void flush_tlb_all(void)`` 33 34 The most severe flush of all. After this interface runs, 35 any previous page table modification whatsoever will be 36 visible to the cpu. 37 38 This is usually invoked when the kernel page tables are 39 changed, since such translations are "global" in nature. 40 412) ``void flush_tlb_mm(struct mm_struct *mm)`` 42 43 This interface flushes an entire user address space from 44 the TLB. After running, this interface must make sure that 45 any previous page table modifications for the address space 46 'mm' will be visible to the cpu. That is, after running, 47 there will be no entries in the TLB for 'mm'. 48 49 This interface is used to handle whole address space 50 page table operations such as what happens during 51 fork, and exec. 52 533) ``void flush_tlb_range(struct vm_area_struct *vma, 54 unsigned long start, unsigned long end)`` 55 56 Here we are flushing a specific range of (user) virtual 57 address translations from the TLB. After running, this 58 interface must make sure that any previous page table 59 modifications for the address space 'vma->vm_mm' in the range 60 'start' to 'end-1' will be visible to the cpu. That is, after 61 running, there will be no entries in the TLB for 'mm' for 62 virtual addresses in the range 'start' to 'end-1'. 63 64 The "vma" is the backing store being used for the region. 65 Primarily, this is used for munmap() type operations. 66 67 The interface is provided in hopes that the port can find 68 a suitably efficient method for removing multiple page 69 sized translations from the TLB, instead of having the kernel 70 call flush_tlb_page (see below) for each entry which may be 71 modified. 72 734) ``void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr)`` 74 75 This time we need to remove the PAGE_SIZE sized translation 76 from the TLB. The 'vma' is the backing structure used by 77 Linux to keep track of mmap'd regions for a process, the 78 address space is available via vma->vm_mm. Also, one may 79 test (vma->vm_flags & VM_EXEC) to see if this region is 80 executable (and thus could be in the 'instruction TLB' in 81 split-tlb type setups). 82 83 After running, this interface must make sure that any previous 84 page table modification for address space 'vma->vm_mm' for 85 user virtual address 'addr' will be visible to the cpu. That 86 is, after running, there will be no entries in the TLB for 87 'vma->vm_mm' for virtual address 'addr'. 88 89 This is used primarily during fault processing. 90 915) ``void update_mmu_cache(struct vm_area_struct *vma, 92 unsigned long address, pte_t *ptep)`` 93 94 At the end of every page fault, this routine is invoked to 95 tell the architecture specific code that a translation 96 now exists at virtual address "address" for address space 97 "vma->vm_mm", in the software page tables. 98 99 A port may use this information in any way it so chooses. 100 For example, it could use this event to pre-load TLB 101 translations for software managed TLB configurations. 102 The sparc64 port currently does this. 103 104Next, we have the cache flushing interfaces. In general, when Linux 105is changing an existing virtual-->physical mapping to a new value, 106the sequence will be in one of the following forms:: 107 108 1) flush_cache_mm(mm); 109 change_all_page_tables_of(mm); 110 flush_tlb_mm(mm); 111 112 2) flush_cache_range(vma, start, end); 113 change_range_of_page_tables(mm, start, end); 114 flush_tlb_range(vma, start, end); 115 116 3) flush_cache_page(vma, addr, pfn); 117 set_pte(pte_pointer, new_pte_val); 118 flush_tlb_page(vma, addr); 119 120The cache level flush will always be first, because this allows 121us to properly handle systems whose caches are strict and require 122a virtual-->physical translation to exist for a virtual address 123when that virtual address is flushed from the cache. The HyperSparc 124cpu is one such cpu with this attribute. 125 126The cache flushing routines below need only deal with cache flushing 127to the extent that it is necessary for a particular cpu. Mostly, 128these routines must be implemented for cpus which have virtually 129indexed caches which must be flushed when virtual-->physical 130translations are changed or removed. So, for example, the physically 131indexed physically tagged caches of IA32 processors have no need to 132implement these interfaces since the caches are fully synchronized 133and have no dependency on translation information. 134 135Here are the routines, one by one: 136 1371) ``void flush_cache_mm(struct mm_struct *mm)`` 138 139 This interface flushes an entire user address space from 140 the caches. That is, after running, there will be no cache 141 lines associated with 'mm'. 142 143 This interface is used to handle whole address space 144 page table operations such as what happens during exit and exec. 145 1462) ``void flush_cache_dup_mm(struct mm_struct *mm)`` 147 148 This interface flushes an entire user address space from 149 the caches. That is, after running, there will be no cache 150 lines associated with 'mm'. 151 152 This interface is used to handle whole address space 153 page table operations such as what happens during fork. 154 155 This option is separate from flush_cache_mm to allow some 156 optimizations for VIPT caches. 157 1583) ``void flush_cache_range(struct vm_area_struct *vma, 159 unsigned long start, unsigned long end)`` 160 161 Here we are flushing a specific range of (user) virtual 162 addresses from the cache. After running, there will be no 163 entries in the cache for 'vma->vm_mm' for virtual addresses in 164 the range 'start' to 'end-1'. 165 166 The "vma" is the backing store being used for the region. 167 Primarily, this is used for munmap() type operations. 168 169 The interface is provided in hopes that the port can find 170 a suitably efficient method for removing multiple page 171 sized regions from the cache, instead of having the kernel 172 call flush_cache_page (see below) for each entry which may be 173 modified. 174 1754) ``void flush_cache_page(struct vm_area_struct *vma, unsigned long addr, unsigned long pfn)`` 176 177 This time we need to remove a PAGE_SIZE sized range 178 from the cache. The 'vma' is the backing structure used by 179 Linux to keep track of mmap'd regions for a process, the 180 address space is available via vma->vm_mm. Also, one may 181 test (vma->vm_flags & VM_EXEC) to see if this region is 182 executable (and thus could be in the 'instruction cache' in 183 "Harvard" type cache layouts). 184 185 The 'pfn' indicates the physical page frame (shift this value 186 left by PAGE_SHIFT to get the physical address) that 'addr' 187 translates to. It is this mapping which should be removed from 188 the cache. 189 190 After running, there will be no entries in the cache for 191 'vma->vm_mm' for virtual address 'addr' which translates 192 to 'pfn'. 193 194 This is used primarily during fault processing. 195 1965) ``void flush_cache_kmaps(void)`` 197 198 This routine need only be implemented if the platform utilizes 199 highmem. It will be called right before all of the kmaps 200 are invalidated. 201 202 After running, there will be no entries in the cache for 203 the kernel virtual address range PKMAP_ADDR(0) to 204 PKMAP_ADDR(LAST_PKMAP). 205 206 This routing should be implemented in asm/highmem.h 207 2086) ``void flush_cache_vmap(unsigned long start, unsigned long end)`` 209 ``void flush_cache_vunmap(unsigned long start, unsigned long end)`` 210 211 Here in these two interfaces we are flushing a specific range 212 of (kernel) virtual addresses from the cache. After running, 213 there will be no entries in the cache for the kernel address 214 space for virtual addresses in the range 'start' to 'end-1'. 215 216 The first of these two routines is invoked after vmap_range() 217 has installed the page table entries. The second is invoked 218 before vunmap_range() deletes the page table entries. 219 220There exists another whole class of cpu cache issues which currently 221require a whole different set of interfaces to handle properly. 222The biggest problem is that of virtual aliasing in the data cache 223of a processor. 224 225Is your port susceptible to virtual aliasing in its D-cache? 226Well, if your D-cache is virtually indexed, is larger in size than 227PAGE_SIZE, and does not prevent multiple cache lines for the same 228physical address from existing at once, you have this problem. 229 230If your D-cache has this problem, first define asm/shmparam.h SHMLBA 231properly, it should essentially be the size of your virtually 232addressed D-cache (or if the size is variable, the largest possible 233size). This setting will force the SYSv IPC layer to only allow user 234processes to mmap shared memory at address which are a multiple of 235this value. 236 237.. note:: 238 239 This does not fix shared mmaps, check out the sparc64 port for 240 one way to solve this (in particular SPARC_FLAG_MMAPSHARED). 241 242Next, you have to solve the D-cache aliasing issue for all 243other cases. Please keep in mind that fact that, for a given page 244mapped into some user address space, there is always at least one more 245mapping, that of the kernel in its linear mapping starting at 246PAGE_OFFSET. So immediately, once the first user maps a given 247physical page into its address space, by implication the D-cache 248aliasing problem has the potential to exist since the kernel already 249maps this page at its virtual address. 250 251 ``void copy_user_page(void *to, void *from, unsigned long addr, struct page *page)`` 252 ``void clear_user_page(void *to, unsigned long addr, struct page *page)`` 253 254 These two routines store data in user anonymous or COW 255 pages. It allows a port to efficiently avoid D-cache alias 256 issues between userspace and the kernel. 257 258 For example, a port may temporarily map 'from' and 'to' to 259 kernel virtual addresses during the copy. The virtual address 260 for these two pages is chosen in such a way that the kernel 261 load/store instructions happen to virtual addresses which are 262 of the same "color" as the user mapping of the page. Sparc64 263 for example, uses this technique. 264 265 The 'addr' parameter tells the virtual address where the 266 user will ultimately have this page mapped, and the 'page' 267 parameter gives a pointer to the struct page of the target. 268 269 If D-cache aliasing is not an issue, these two routines may 270 simply call memcpy/memset directly and do nothing more. 271 272 ``void flush_dcache_page(struct page *page)`` 273 274 Any time the kernel writes to a page cache page, _OR_ 275 the kernel is about to read from a page cache page and 276 user space shared/writable mappings of this page potentially 277 exist, this routine is called. 278 279 .. note:: 280 281 This routine need only be called for page cache pages 282 which can potentially ever be mapped into the address 283 space of a user process. So for example, VFS layer code 284 handling vfs symlinks in the page cache need not call 285 this interface at all. 286 287 The phrase "kernel writes to a page cache page" means, 288 specifically, that the kernel executes store instructions 289 that dirty data in that page at the page->virtual mapping 290 of that page. It is important to flush here to handle 291 D-cache aliasing, to make sure these kernel stores are 292 visible to user space mappings of that page. 293 294 The corollary case is just as important, if there are users 295 which have shared+writable mappings of this file, we must make 296 sure that kernel reads of these pages will see the most recent 297 stores done by the user. 298 299 If D-cache aliasing is not an issue, this routine may 300 simply be defined as a nop on that architecture. 301 302 There is a bit set aside in page->flags (PG_arch_1) as 303 "architecture private". The kernel guarantees that, 304 for pagecache pages, it will clear this bit when such 305 a page first enters the pagecache. 306 307 This allows these interfaces to be implemented much more 308 efficiently. It allows one to "defer" (perhaps indefinitely) 309 the actual flush if there are currently no user processes 310 mapping this page. See sparc64's flush_dcache_page and 311 update_mmu_cache implementations for an example of how to go 312 about doing this. 313 314 The idea is, first at flush_dcache_page() time, if 315 page->mapping->i_mmap is an empty tree, just mark the architecture 316 private page flag bit. Later, in update_mmu_cache(), a check is 317 made of this flag bit, and if set the flush is done and the flag 318 bit is cleared. 319 320 .. important:: 321 322 It is often important, if you defer the flush, 323 that the actual flush occurs on the same CPU 324 as did the cpu stores into the page to make it 325 dirty. Again, see sparc64 for examples of how 326 to deal with this. 327 328 ``void copy_to_user_page(struct vm_area_struct *vma, struct page *page, 329 unsigned long user_vaddr, void *dst, void *src, int len)`` 330 ``void copy_from_user_page(struct vm_area_struct *vma, struct page *page, 331 unsigned long user_vaddr, void *dst, void *src, int len)`` 332 333 When the kernel needs to copy arbitrary data in and out 334 of arbitrary user pages (f.e. for ptrace()) it will use 335 these two routines. 336 337 Any necessary cache flushing or other coherency operations 338 that need to occur should happen here. If the processor's 339 instruction cache does not snoop cpu stores, it is very 340 likely that you will need to flush the instruction cache 341 for copy_to_user_page(). 342 343 ``void flush_anon_page(struct vm_area_struct *vma, struct page *page, 344 unsigned long vmaddr)`` 345 346 When the kernel needs to access the contents of an anonymous 347 page, it calls this function (currently only 348 get_user_pages()). Note: flush_dcache_page() deliberately 349 doesn't work for an anonymous page. The default 350 implementation is a nop (and should remain so for all coherent 351 architectures). For incoherent architectures, it should flush 352 the cache of the page at vmaddr. 353 354 ``void flush_kernel_dcache_page(struct page *page)`` 355 356 When the kernel needs to modify a user page is has obtained 357 with kmap, it calls this function after all modifications are 358 complete (but before kunmapping it) to bring the underlying 359 page up to date. It is assumed here that the user has no 360 incoherent cached copies (i.e. the original page was obtained 361 from a mechanism like get_user_pages()). The default 362 implementation is a nop and should remain so on all coherent 363 architectures. On incoherent architectures, this should flush 364 the kernel cache for page (using page_address(page)). 365 366 367 ``void flush_icache_range(unsigned long start, unsigned long end)`` 368 369 When the kernel stores into addresses that it will execute 370 out of (eg when loading modules), this function is called. 371 372 If the icache does not snoop stores then this routine will need 373 to flush it. 374 375 ``void flush_icache_page(struct vm_area_struct *vma, struct page *page)`` 376 377 All the functionality of flush_icache_page can be implemented in 378 flush_dcache_page and update_mmu_cache. In the future, the hope 379 is to remove this interface completely. 380 381The final category of APIs is for I/O to deliberately aliased address 382ranges inside the kernel. Such aliases are set up by use of the 383vmap/vmalloc API. Since kernel I/O goes via physical pages, the I/O 384subsystem assumes that the user mapping and kernel offset mapping are 385the only aliases. This isn't true for vmap aliases, so anything in 386the kernel trying to do I/O to vmap areas must manually manage 387coherency. It must do this by flushing the vmap range before doing 388I/O and invalidating it after the I/O returns. 389 390 ``void flush_kernel_vmap_range(void *vaddr, int size)`` 391 392 flushes the kernel cache for a given virtual address range in 393 the vmap area. This is to make sure that any data the kernel 394 modified in the vmap range is made visible to the physical 395 page. The design is to make this area safe to perform I/O on. 396 Note that this API does *not* also flush the offset map alias 397 of the area. 398 399 ``void invalidate_kernel_vmap_range(void *vaddr, int size) invalidates`` 400 401 the cache for a given virtual address range in the vmap area 402 which prevents the processor from making the cache stale by 403 speculatively reading data while the I/O was occurring to the 404 physical pages. This is only necessary for data reads into the 405 vmap area. 406