1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (C) 2020 MOXA Inc. - https://www.moxa.com/ 4 * 5 * Author: Johnson Chen <johnsonch.chen@moxa.com> 6 */ 7 8#include "am33xx.dtsi" 9 10/ { 11 12 cpus { 13 cpu@0 { 14 cpu0-supply = <&vdd1_reg>; 15 }; 16 }; 17 18 vbat: vbat-regulator { 19 compatible = "regulator-fixed"; 20 }; 21 22 /* Power supply provides a fixed 3.3V @3A */ 23 vmmcsd_fixed: vmmcsd-regulator { 24 compatible = "regulator-fixed"; 25 regulator-name = "vmmcsd_fixed"; 26 regulator-min-microvolt = <3300000>; 27 regulator-max-microvolt = <3300000>; 28 regulator-boot-on; 29 }; 30 31 buttons: push_button { 32 compatible = "gpio-keys"; 33 }; 34 35}; 36 37&am33xx_pinmux { 38 pinctrl-names = "default"; 39 pinctrl-0 = <&minipcie_pins>; 40 41 minipcie_pins: pinmux_minipcie { 42 pinctrl-single,pins = < 43 AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_pclk.gpio2_24 */ 44 AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_ac_bias_en.gpio2_25 */ 45 AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_vsync.gpio2_22 Power off PIN*/ 46 >; 47 }; 48 49 push_button_pins: pinmux_push_button { 50 pinctrl-single,pins = < 51 AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLDOWN, MUX_MODE7) /* mcasp0_ahcklx.gpio3_21 */ 52 >; 53 }; 54 55 i2c0_pins: pinmux_i2c0_pins { 56 pinctrl-single,pins = < 57 AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) 58 AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) 59 >; 60 }; 61 62 63 i2c1_pins: pinmux_i2c1_pins { 64 pinctrl-single,pins = < 65 AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart0_ctsn.i2c1_sda */ 66 AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart0_rtsn.i2c1_scl */ 67 >; 68 }; 69 70 uart0_pins: pinmux_uart0_pins { 71 pinctrl-single,pins = < 72 AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) 73 AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) 74 >; 75 }; 76 77 uart1_pins: pinmux_uart1_pins { 78 pinctrl-single,pins = < 79 AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT, MUX_MODE0) 80 AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) 81 AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) 82 AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT, MUX_MODE0) 83 >; 84 }; 85 86 uart2_pins: pinmux_uart2_pins { 87 pinctrl-single,pins = < 88 AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_INPUT, MUX_MODE6) /* lcd_data14.uart5_ctsn */ 89 AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT_PULLDOWN, MUX_MODE6) /* lcd_data15.uart5_rtsn */ 90 AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_INPUT_PULLUP, MUX_MODE4) /* lcd_data9.uart5_rxd */ 91 AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE4) /* lcd_data8.uart5_txd */ 92 >; 93 }; 94 95 cpsw_default: cpsw_default { 96 pinctrl-single,pins = < 97 /* Slave 1 */ 98 AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1) 99 AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE1) 100 AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE1) 101 AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE1) 102 AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE1) 103 AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE1) 104 AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE1) 105 AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0) 106 107 /* Slave 2 */ 108 AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_crs_dv */ 109 AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_rxer */ 110 AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* rmii2_txen */ 111 AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* rmii2_td1 */ 112 AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* rmii2_td0 */ 113 AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_rd1 */ 114 AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_rd0 */ 115 AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE1) /* rmii2_refclk */ 116 117 >; 118 }; 119 120 davinci_mdio_default: davinci_mdio_default { 121 pinctrl-single,pins = < 122 /* MDIO */ 123 AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) 124 AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) 125 >; 126 }; 127 128 mmc0_pins_default: pinmux_mmc0_pins { 129 pinctrl-single,pins = < 130 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) 131 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) 132 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) 133 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) 134 AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) 135 AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) 136 AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_INPUT_PULLUP, MUX_MODE7) /* mcasp0_aclkx.gpio3_14 */ 137 AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT_PULLUP, MUX_MODE7) /* mcasp0_aclkx.gpio3_18 */ 138 >; 139 }; 140 141 mmc2_pins_default: pinmux_mmc2_pins { 142 pinctrl-single,pins = < 143 /* eMMC */ 144 AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad12.mmc2_dat0 */ 145 AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad13.mmc2_dat1 */ 146 AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad14.mmc2_dat2 */ 147 AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad15.mmc2_dat3 */ 148 AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad8.mmc2_dat4 */ 149 AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad9.mmc2_dat5 */ 150 AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad10.mmc2_dat6 */ 151 AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad11.mmc2_dat7 */ 152 AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_csn3.mmc2_cmd */ 153 AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_clk.mmc2_clk */ 154 >; 155 }; 156 157 spi0_pins: pinmux_spi0 { 158 pinctrl-single,pins = < 159 AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE0) 160 AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0) 161 AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE0) 162 AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0) 163 >; 164 }; 165 166}; 167 168&uart0 { 169 /* Console */ 170 status = "okay"; 171 pinctrl-names = "default"; 172 pinctrl-0 = <&uart0_pins>; 173}; 174 175&uart1 { 176 /* UART 1 setting */ 177 status = "okay"; 178 pinctrl-names = "default"; 179 pinctrl-0 = <&uart1_pins>; 180}; 181 182&uart5 { 183 /* UART 2 setting */ 184 status = "okay"; 185 pinctrl-names = "default"; 186 pinctrl-0 = <&uart2_pins>; 187}; 188 189&i2c0 { 190 pinctrl-names = "default"; 191 pinctrl-0 = <&i2c0_pins>; 192 193 status = "okay"; 194 clock-frequency = <400000>; 195 196 tps: tps@2d { 197 compatible = "ti,tps65910"; 198 reg = <0x2d>; 199 }; 200 201 eeprom: eeprom@50 { 202 compatible = "atmel,24c16"; 203 pagesize = <16>; 204 reg = <0x50>; 205 }; 206 207 rtc_wdt: rtc_wdt@68 { 208 compatible = "dallas,ds1374"; 209 reg = <0x68>; 210 }; 211}; 212 213&i2c1 { 214 pinctrl-names = "default"; 215 pinctrl-0 = <&i2c1_pins>; 216 217 status = "okay"; 218 clock-frequency = <400000>; 219 gpio_xten: gpio_xten@27 { 220 compatible = "nxp,pca9535"; 221 gpio-controller; 222 #gpio-cells = <2>; 223 reg = <0x27>; 224 }; 225}; 226 227&usb0 { 228 dr_mode = "host"; 229}; 230 231&usb1 { 232 dr_mode = "host"; 233}; 234 235 236#include "tps65910.dtsi" 237&tps { 238 vcc1-supply = <&vbat>; 239 vcc2-supply = <&vbat>; 240 vcc3-supply = <&vbat>; 241 vcc4-supply = <&vbat>; 242 vcc5-supply = <&vbat>; 243 vcc6-supply = <&vbat>; 244 vcc7-supply = <&vbat>; 245 vccio-supply = <&vbat>; 246 247 regulators { 248 vrtc_reg: regulator@0 { 249 regulator-always-on; 250 }; 251 252 vio_reg: regulator@1 { 253 regulator-always-on; 254 }; 255 256 vdd1_reg: regulator@2 { 257 regulator-always-on; 258 }; 259 260 vdd2_reg: regulator@3 { 261 regulator-always-on; 262 }; 263 264 vdd3_reg: regulator@4 { 265 regulator-always-on; 266 }; 267 268 vdig1_reg: regulator@5 { 269 regulator-always-on; 270 }; 271 272 vdig2_reg: regulator@6 { 273 regulator-always-on; 274 }; 275 276 vpll_reg: regulator@7 { 277 regulator-always-on; 278 }; 279 280 vdac_reg: regulator@8 { 281 regulator-always-on; 282 }; 283 284 vaux1_reg: regulator@9 { 285 regulator-always-on; 286 }; 287 288 vaux2_reg: regulator@10 { 289 regulator-always-on; 290 }; 291 292 vaux33_reg: regulator@11 { 293 regulator-always-on; 294 }; 295 296 vmmc_reg: regulator@12 { 297 compatible = "regulator-fixed"; 298 regulator-name = "vmmc_reg"; 299 regulator-min-microvolt = <3300000>; 300 regulator-max-microvolt = <3300000>; 301 regulator-always-on; 302 }; 303 }; 304}; 305 306/* Power */ 307&vbat { 308 regulator-name = "vbat"; 309 regulator-min-microvolt = <5000000>; 310 regulator-max-microvolt = <5000000>; 311}; 312 313&mac { 314 pinctrl-names = "default"; 315 pinctrl-0 = <&cpsw_default>; 316 dual_emac = <1>; 317 status = "okay"; 318}; 319 320&davinci_mdio { 321 pinctrl-names = "default"; 322 pinctrl-0 = <&davinci_mdio_default>; 323 status = "okay"; 324 325 ethphy0: ethernet-phy@4 { 326 reg = <4>; 327 }; 328 329 ethphy1: ethernet-phy@5 { 330 reg = <5>; 331 }; 332}; 333 334&cpsw_emac0 { 335 status = "okay"; 336 phy-handle = <ðphy0>; 337 phy-mode = "rmii"; 338 dual_emac_res_vlan = <1>; 339}; 340 341&cpsw_emac1 { 342 status = "okay"; 343 phy-handle = <ðphy1>; 344 phy-mode = "rmii"; 345 dual_emac_res_vlan = <2>; 346}; 347 348&sham { 349 status = "okay"; 350}; 351 352&aes { 353 status = "okay"; 354}; 355 356&gpio0 { 357 ti,no-reset-on-init; 358}; 359 360&mmc1 { 361 pinctrl-names = "default"; 362 vmmc-supply = <&vmmcsd_fixed>; 363 bus-width = <4>; 364 pinctrl-0 = <&mmc0_pins_default>; 365 cd-gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; 366 wp-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>; 367 status = "okay"; 368}; 369 370&mmc3 { 371 dmas = <&edma_xbar 12 0 1 372 &edma_xbar 13 0 2>; 373 dma-names = "tx", "rx"; 374 pinctrl-names = "default"; 375 vmmc-supply = <&vmmcsd_fixed>; 376 bus-width = <8>; 377 pinctrl-0 = <&mmc2_pins_default>; 378 ti,non-removable; 379 status = "okay"; 380}; 381 382&buttons { 383 pinctrl-names = "default"; 384 pinctrl-0 = <&push_button_pins>; 385 #address-cells = <1>; 386 #size-cells = <0>; 387 388 button@0 { 389 label = "push_button"; 390 linux,code = <0x100>; 391 gpios = <&gpio3 21 GPIO_ACTIVE_LOW>; 392 }; 393}; 394 395/* SPI Busses */ 396&spi0 { 397 status = "okay"; 398 pinctrl-names = "default"; 399 pinctrl-0 = <&spi0_pins>; 400 401 m25p80@0 { 402 compatible = "mx25l6405d"; 403 spi-max-frequency = <40000000>; 404 405 reg = <0>; 406 spi-cpol; 407 spi-cpha; 408 #address-cells = <1>; 409 #size-cells = <1>; 410 411 /* reg : The partition's offset and size within the mtd bank. */ 412 partitions@0 { 413 label = "MLO"; 414 reg = <0x0 0x80000>; 415 }; 416 417 partitions@1 { 418 label = "U-Boot"; 419 reg = <0x80000 0x100000>; 420 }; 421 422 partitions@2 { 423 label = "U-Boot Env"; 424 reg = <0x180000 0x20000>; 425 }; 426 }; 427}; 428