1/* 2 * Copyright 2014 Linaro Ltd 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a copy 5 * of this software and associated documentation files (the "Software"), to deal 6 * in the Software without restriction, including without limitation the rights 7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 8 * copies of the Software, and to permit persons to whom the Software is 9 * furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 20 * THE SOFTWARE. 21 */ 22 23/dts-v1/; 24#include <dt-bindings/interrupt-controller/irq.h> 25#include <dt-bindings/gpio/gpio.h> 26 27/ { 28 #address-cells = <1>; 29 #size-cells = <1>; 30 model = "ARM RealView PB1176"; 31 compatible = "arm,realview-pb1176"; 32 33 chosen { }; 34 35 aliases { 36 serial0 = &pb1176_serial0; 37 serial1 = &pb1176_serial1; 38 serial2 = &pb1176_serial2; 39 serial3 = &pb1176_serial3; 40 serial4 = &fpga_serial; 41 }; 42 43 memory { 44 device_type = "memory"; 45 /* 128 MiB memory @ 0x0 */ 46 reg = <0x00000000 0x08000000>; 47 }; 48 49 /* The voltage to the MMC card is hardwired at 3.3V */ 50 vmmc: regulator-vmmc { 51 compatible = "regulator-fixed"; 52 regulator-name = "vmmc"; 53 regulator-min-microvolt = <3300000>; 54 regulator-max-microvolt = <3300000>; 55 regulator-boot-on; 56 }; 57 58 veth: regulator-veth { 59 compatible = "regulator-fixed"; 60 regulator-name = "veth"; 61 regulator-min-microvolt = <3300000>; 62 regulator-max-microvolt = <3300000>; 63 regulator-boot-on; 64 }; 65 66 xtal24mhz: xtal24mhz@24M { 67 #clock-cells = <0>; 68 compatible = "fixed-clock"; 69 clock-frequency = <24000000>; 70 }; 71 72 timclk: timclk@1M { 73 #clock-cells = <0>; 74 compatible = "fixed-factor-clock"; 75 clock-div = <24>; 76 clock-mult = <1>; 77 clocks = <&xtal24mhz>; 78 }; 79 80 mclk: mclk@24M { 81 #clock-cells = <0>; 82 compatible = "fixed-factor-clock"; 83 clock-div = <1>; 84 clock-mult = <1>; 85 clocks = <&xtal24mhz>; 86 }; 87 88 kmiclk: kmiclk@24M { 89 #clock-cells = <0>; 90 compatible = "fixed-factor-clock"; 91 clock-div = <1>; 92 clock-mult = <1>; 93 clocks = <&xtal24mhz>; 94 }; 95 96 sspclk: sspclk@24M { 97 #clock-cells = <0>; 98 compatible = "fixed-factor-clock"; 99 clock-div = <1>; 100 clock-mult = <1>; 101 clocks = <&xtal24mhz>; 102 }; 103 104 uartclk: uartclk@24M { 105 #clock-cells = <0>; 106 compatible = "fixed-factor-clock"; 107 clock-div = <1>; 108 clock-mult = <1>; 109 clocks = <&xtal24mhz>; 110 }; 111 112 /* FIXME: this actually hangs off the PLL clocks */ 113 pclk: pclk@0 { 114 #clock-cells = <0>; 115 compatible = "fixed-clock"; 116 clock-frequency = <0>; 117 }; 118 119 flash@30000000 { 120 compatible = "arm,versatile-flash", "cfi-flash"; 121 reg = <0x30000000 0x4000000>; 122 bank-width = <4>; 123 partitions { 124 compatible = "arm,arm-firmware-suite"; 125 }; 126 }; 127 128 fpga_flash@38000000 { 129 compatible = "arm,versatile-flash", "cfi-flash"; 130 reg = <0x38000000 0x800000>; 131 bank-width = <4>; 132 partitions { 133 compatible = "arm,arm-firmware-suite"; 134 }; 135 }; 136 137 /* 138 * The "secure flash" contains things like the boot 139 * monitor so we don't want people to accidentally 140 * screw this up. Mark the device tree node disabled 141 * by default. 142 */ 143 secflash@3c000000 { 144 compatible = "arm,versatile-flash", "cfi-flash"; 145 reg = <0x3c000000 0x4000000>; 146 bank-width = <4>; 147 status = "disabled"; 148 }; 149 150 /* SMSC 9118 ethernet with PHY and EEPROM */ 151 ethernet@3a000000 { 152 compatible = "smsc,lan9118", "smsc,lan9115"; 153 reg = <0x3a000000 0x10000>; 154 interrupt-parent = <&intc_fpga1176>; 155 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; 156 phy-mode = "mii"; 157 reg-io-width = <4>; 158 smsc,irq-active-high; 159 smsc,irq-push-pull; 160 vdd33a-supply = <&veth>; 161 vddvario-supply = <&veth>; 162 }; 163 164 usb@3b000000 { 165 compatible = "nxp,usb-isp1761"; 166 reg = <0x3b000000 0x20000>; 167 interrupt-parent = <&intc_fpga1176>; 168 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; 169 port1-otg; 170 }; 171 172 bridge { 173 compatible = "ti,ths8134a", "ti,ths8134"; 174 #address-cells = <1>; 175 #size-cells = <0>; 176 177 ports { 178 #address-cells = <1>; 179 #size-cells = <0>; 180 181 port@0 { 182 reg = <0>; 183 184 vga_bridge_in: endpoint { 185 remote-endpoint = <&clcd_pads>; 186 }; 187 }; 188 189 port@1 { 190 reg = <1>; 191 192 vga_bridge_out: endpoint { 193 remote-endpoint = <&vga_con_in>; 194 }; 195 }; 196 }; 197 }; 198 199 vga { 200 compatible = "vga-connector"; 201 202 port { 203 vga_con_in: endpoint { 204 remote-endpoint = <&vga_bridge_out>; 205 }; 206 }; 207 }; 208 209 soc { 210 #address-cells = <1>; 211 #size-cells = <1>; 212 compatible = "arm,realview-pb1176-soc", "simple-bus"; 213 regmap = <&syscon>; 214 ranges; 215 216 syscon: syscon@10000000 { 217 compatible = "arm,realview-pb1176-syscon", "syscon", "simple-mfd"; 218 reg = <0x10000000 0x1000>; 219 220 led@08.0 { 221 compatible = "register-bit-led"; 222 offset = <0x08>; 223 mask = <0x01>; 224 label = "versatile:0"; 225 linux,default-trigger = "heartbeat"; 226 default-state = "on"; 227 }; 228 led@08.1 { 229 compatible = "register-bit-led"; 230 offset = <0x08>; 231 mask = <0x02>; 232 label = "versatile:1"; 233 linux,default-trigger = "mmc0"; 234 default-state = "off"; 235 }; 236 led@08.2 { 237 compatible = "register-bit-led"; 238 offset = <0x08>; 239 mask = <0x04>; 240 label = "versatile:2"; 241 linux,default-trigger = "cpu0"; 242 default-state = "off"; 243 }; 244 led@08.3 { 245 compatible = "register-bit-led"; 246 offset = <0x08>; 247 mask = <0x08>; 248 label = "versatile:3"; 249 default-state = "off"; 250 }; 251 led@08.4 { 252 compatible = "register-bit-led"; 253 offset = <0x08>; 254 mask = <0x10>; 255 label = "versatile:4"; 256 default-state = "off"; 257 }; 258 led@08.5 { 259 compatible = "register-bit-led"; 260 offset = <0x08>; 261 mask = <0x20>; 262 label = "versatile:5"; 263 default-state = "off"; 264 }; 265 led@08.6 { 266 compatible = "register-bit-led"; 267 offset = <0x08>; 268 mask = <0x40>; 269 label = "versatile:6"; 270 default-state = "off"; 271 }; 272 led@08.7 { 273 compatible = "register-bit-led"; 274 offset = <0x08>; 275 mask = <0x80>; 276 label = "versatile:7"; 277 default-state = "off"; 278 }; 279 oscclk0: osc0@0c { 280 compatible = "arm,syscon-icst307"; 281 #clock-cells = <0>; 282 lock-offset = <0x20>; 283 vco-offset = <0x0C>; 284 clocks = <&xtal24mhz>; 285 }; 286 oscclk1: osc1@10 { 287 compatible = "arm,syscon-icst307"; 288 #clock-cells = <0>; 289 lock-offset = <0x20>; 290 vco-offset = <0x10>; 291 clocks = <&xtal24mhz>; 292 }; 293 oscclk2: osc2@14 { 294 compatible = "arm,syscon-icst307"; 295 #clock-cells = <0>; 296 lock-offset = <0x20>; 297 vco-offset = <0x14>; 298 clocks = <&xtal24mhz>; 299 }; 300 oscclk3: osc3@18 { 301 compatible = "arm,syscon-icst307"; 302 #clock-cells = <0>; 303 lock-offset = <0x20>; 304 vco-offset = <0x18>; 305 clocks = <&xtal24mhz>; 306 }; 307 oscclk4: osc4@1c { 308 compatible = "arm,syscon-icst307"; 309 #clock-cells = <0>; 310 lock-offset = <0x20>; 311 vco-offset = <0x1c>; 312 clocks = <&xtal24mhz>; 313 }; 314 }; 315 316 /* Primary DevChip GIC synthesized with the CPU */ 317 intc_dc1176: interrupt-controller@10120000 { 318 compatible = "arm,arm1176jzf-devchip-gic", "arm,arm11mp-gic"; 319 #interrupt-cells = <3>; 320 #address-cells = <1>; 321 interrupt-controller; 322 reg = <0x10121000 0x1000>, 323 <0x10120000 0x100>; 324 }; 325 326 L2: cache-controller { 327 compatible = "arm,l220-cache"; 328 reg = <0x10110000 0x1000>; 329 interrupt-parent = <&intc_dc1176>; 330 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>; 331 cache-unified; 332 cache-level = <2>; 333 /* 334 * Override default cache size, sets and 335 * associativity as these may be erroneously set 336 * up by boot loader(s). 337 */ 338 arm,override-auxreg; 339 cache-size = <131072>; // 128kB 340 cache-sets = <512>; 341 cache-line-size = <32>; 342 }; 343 344 pmu { 345 compatible = "arm,arm1176-pmu"; 346 interrupt-parent = <&intc_dc1176>; 347 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; 348 }; 349 350 timer01: timer@10104000 { 351 compatible = "arm,sp804", "arm,primecell"; 352 reg = <0x10104000 0x1000>; 353 interrupt-parent = <&intc_dc1176>; 354 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>, <0 9 IRQ_TYPE_LEVEL_HIGH>; 355 clocks = <&timclk>, <&timclk>, <&pclk>; 356 clock-names = "timer1", "timer2", "apb_pclk"; 357 }; 358 359 timer23: timer@10105000 { 360 compatible = "arm,sp804", "arm,primecell"; 361 reg = <0x10105000 0x1000>; 362 interrupt-parent = <&intc_dc1176>; 363 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; 364 arm,sp804-has-irq = <1>; 365 clocks = <&timclk>, <&timclk>, <&pclk>; 366 clock-names = "timer1", "timer2", "apb_pclk"; 367 }; 368 369 pb1176_rtc: rtc@10108000 { 370 compatible = "arm,pl031", "arm,primecell"; 371 reg = <0x10108000 0x1000>; 372 interrupt-parent = <&intc_dc1176>; 373 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; 374 clocks = <&pclk>; 375 clock-names = "apb_pclk"; 376 }; 377 378 pb1176_gpio0: gpio@1010a000 { 379 compatible = "arm,pl061", "arm,primecell"; 380 reg = <0x1010a000 0x1000>; 381 gpio-controller; 382 interrupt-parent = <&intc_dc1176>; 383 interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>; 384 #gpio-cells = <2>; 385 interrupt-controller; 386 #interrupt-cells = <2>; 387 clocks = <&pclk>; 388 clock-names = "apb_pclk"; 389 }; 390 391 pb1176_ssp: spi@1010b000 { 392 compatible = "arm,pl022", "arm,primecell"; 393 reg = <0x1010b000 0x1000>; 394 interrupt-parent = <&intc_dc1176>; 395 interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>; 396 clocks = <&sspclk>, <&pclk>; 397 clock-names = "SSPCLK", "apb_pclk"; 398 }; 399 400 pb1176_serial0: serial@1010c000 { 401 compatible = "arm,pl011", "arm,primecell"; 402 reg = <0x1010c000 0x1000>; 403 interrupt-parent = <&intc_dc1176>; 404 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>; 405 clocks = <&uartclk>, <&pclk>; 406 clock-names = "uartclk", "apb_pclk"; 407 }; 408 409 pb1176_serial1: serial@1010d000 { 410 compatible = "arm,pl011", "arm,primecell"; 411 reg = <0x1010d000 0x1000>; 412 interrupt-parent = <&intc_dc1176>; 413 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>; 414 clocks = <&uartclk>, <&pclk>; 415 clock-names = "uartclk", "apb_pclk"; 416 }; 417 418 pb1176_serial2: serial@1010e000 { 419 compatible = "arm,pl011", "arm,primecell"; 420 reg = <0x1010e000 0x1000>; 421 interrupt-parent = <&intc_dc1176>; 422 interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>; 423 clocks = <&uartclk>, <&pclk>; 424 clock-names = "uartclk", "apb_pclk"; 425 }; 426 427 pb1176_serial3: serial@1010f000 { 428 compatible = "arm,pl011", "arm,primecell"; 429 reg = <0x1010f000 0x1000>; 430 interrupt-parent = <&intc_dc1176>; 431 interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; 432 clocks = <&uartclk>, <&pclk>; 433 clock-names = "uartclk", "apb_pclk"; 434 }; 435 436 /* Direct-mapped development chip ROM */ 437 pb1176_rom@10200000 { 438 compatible = "direct-mapped"; 439 reg = <0x10200000 0x4000>; 440 bank-width = <1>; 441 }; 442 443 clcd@10112000 { 444 compatible = "arm,pl111", "arm,primecell"; 445 reg = <0x10112000 0x1000>; 446 interrupt-parent = <&intc_dc1176>; 447 interrupt-names = "combined"; 448 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>; 449 clocks = <&oscclk0>, <&pclk>; 450 clock-names = "clcdclk", "apb_pclk"; 451 /* 1024x768 16bpp @65MHz works fine */ 452 max-memory-bandwidth = <95000000>; 453 454 port { 455 clcd_pads: endpoint { 456 remote-endpoint = <&vga_bridge_in>; 457 arm,pl11x,tft-r0g0b0-pads = <0 8 16>; 458 }; 459 }; 460 }; 461 }; 462 463 /* These peripherals are inside the FPGA rather than the DevChip */ 464 fpga { 465 #address-cells = <1>; 466 #size-cells = <1>; 467 compatible = "simple-bus"; 468 ranges; 469 470 i2c0: i2c@10002000 { 471 #address-cells = <1>; 472 #size-cells = <0>; 473 compatible = "arm,versatile-i2c"; 474 reg = <0x10002000 0x1000>; 475 476 rtc@68 { 477 compatible = "dallas,ds1338"; 478 reg = <0x68>; 479 }; 480 }; 481 482 fpga_aaci: aaci@10004000 { 483 compatible = "arm,pl041", "arm,primecell"; 484 reg = <0x10004000 0x1000>; 485 interrupt-parent = <&intc_fpga1176>; 486 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>; 487 clocks = <&pclk>; 488 clock-names = "apb_pclk"; 489 }; 490 491 fpga_mci: mmcsd@10005000 { 492 compatible = "arm,pl18x", "arm,primecell"; 493 reg = <0x10005000 0x1000>; 494 interrupt-parent = <&intc_fpga1176>; 495 interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>, 496 <0 2 IRQ_TYPE_LEVEL_HIGH>; 497 /* Due to frequent FIFO overruns, use just 500 kHz */ 498 max-frequency = <500000>; 499 bus-width = <4>; 500 cap-sd-highspeed; 501 cap-mmc-highspeed; 502 clocks = <&mclk>, <&pclk>; 503 clock-names = "mclk", "apb_pclk"; 504 vmmc-supply = <&vmmc>; 505 cd-gpios = <&fpga_gpio1 0 GPIO_ACTIVE_LOW>; 506 wp-gpios = <&fpga_gpio1 1 GPIO_ACTIVE_HIGH>; 507 }; 508 509 fpga_kmi0: kmi@10006000 { 510 compatible = "arm,pl050", "arm,primecell"; 511 reg = <0x10006000 0x1000>; 512 interrupt-parent = <&intc_fpga1176>; 513 interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>; 514 clocks = <&kmiclk>, <&pclk>; 515 clock-names = "KMIREFCLK", "apb_pclk"; 516 }; 517 518 fpga_kmi1: kmi@10007000 { 519 compatible = "arm,pl050", "arm,primecell"; 520 reg = <0x10007000 0x1000>; 521 interrupt-parent = <&intc_fpga1176>; 522 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; 523 clocks = <&kmiclk>, <&pclk>; 524 clock-names = "KMIREFCLK", "apb_pclk"; 525 }; 526 527 fpga_charlcd: charlcd@10008000 { 528 compatible = "arm,versatile-lcd"; 529 reg = <0x10008000 0x1000>; 530 interrupt-parent = <&intc_fpga1176>; 531 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; 532 clocks = <&pclk>; 533 clock-names = "apb_pclk"; 534 }; 535 536 fpga_serial: serial@10009000 { 537 compatible = "arm,pl011", "arm,primecell"; 538 reg = <0x10009000 0x1000>; 539 interrupt-parent = <&intc_fpga1176>; 540 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; 541 clocks = <&uartclk>, <&pclk>; 542 clock-names = "uartclk", "apb_pclk"; 543 }; 544 545 /* This GIC on the board is cascaded off the DevChip GIC */ 546 intc_fpga1176: interrupt-controller@10040000 { 547 compatible = "arm,arm1176jzf-devchip-gic", "arm,arm11mp-gic"; 548 #interrupt-cells = <3>; 549 #address-cells = <1>; 550 interrupt-controller; 551 reg = <0x10041000 0x1000>, 552 <0x10040000 0x100>; 553 interrupt-parent = <&intc_dc1176>; 554 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; 555 }; 556 557 fpga_gpio0: gpio@10014000 { 558 compatible = "arm,pl061", "arm,primecell"; 559 reg = <0x10014000 0x1000>; 560 gpio-controller; 561 interrupt-parent = <&intc_fpga1176>; 562 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; 563 #gpio-cells = <2>; 564 interrupt-controller; 565 #interrupt-cells = <2>; 566 clocks = <&pclk>; 567 clock-names = "apb_pclk"; 568 }; 569 570 fpga_gpio1: gpio@10015000 { 571 compatible = "arm,pl061", "arm,primecell"; 572 reg = <0x10015000 0x1000>; 573 gpio-controller; 574 interrupt-parent = <&intc_fpga1176>; 575 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; 576 #gpio-cells = <2>; 577 interrupt-controller; 578 #interrupt-cells = <2>; 579 clocks = <&pclk>; 580 clock-names = "apb_pclk"; 581 }; 582 583 fpga_rtc: rtc@10017000 { 584 compatible = "arm,pl031", "arm,primecell"; 585 reg = <0x10017000 0x1000>; 586 interrupt-parent = <&intc_fpga1176>; 587 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>; 588 clocks = <&pclk>; 589 clock-names = "apb_pclk"; 590 }; 591 }; 592}; 593