1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Device Tree Include file for Marvell Armada 370 family SoC
4 *
5 * Copyright (C) 2012 Marvell
6 *
7 * Lior Amsalem <alior@marvell.com>
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10 *
11 * Contains definitions specific to the Armada 370 SoC that are not
12 * common to all Armada SoCs.
13 */
14
15#include "armada-370-xp.dtsi"
16
17/ {
18	#address-cells = <1>;
19	#size-cells = <1>;
20
21	model = "Marvell Armada 370 family SoC";
22	compatible = "marvell,armada370", "marvell,armada-370-xp";
23
24	aliases {
25		gpio0 = &gpio0;
26		gpio1 = &gpio1;
27		gpio2 = &gpio2;
28	};
29
30	soc {
31		compatible = "marvell,armada370-mbus", "simple-bus";
32
33		bootrom {
34			compatible = "marvell,bootrom";
35			reg = <MBUS_ID(0x01, 0xe0) 0 0x100000>;
36		};
37
38		pciec: pcie@82000000 {
39			compatible = "marvell,armada-370-pcie";
40			status = "disabled";
41			device_type = "pci";
42
43			#address-cells = <3>;
44			#size-cells = <2>;
45
46			msi-parent = <&mpic>;
47			bus-range = <0x00 0xff>;
48
49			ranges =
50			       <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
51				0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
52				0x82000000 0x1 0     MBUS_ID(0x04, 0xe8) 0       1 0 /* Port 0.0 MEM */
53				0x81000000 0x1 0     MBUS_ID(0x04, 0xe0) 0       1 0 /* Port 0.0 IO  */
54				0x82000000 0x2 0     MBUS_ID(0x08, 0xe8) 0       1 0 /* Port 1.0 MEM */
55				0x81000000 0x2 0     MBUS_ID(0x08, 0xe0) 0       1 0 /* Port 1.0 IO  */>;
56
57			pcie0: pcie@1,0 {
58				device_type = "pci";
59				assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
60				reg = <0x0800 0 0 0 0>;
61				#address-cells = <3>;
62				#size-cells = <2>;
63				#interrupt-cells = <1>;
64                                ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
65                                          0x81000000 0 0 0x81000000 0x1 0 1 0>;
66				bus-range = <0x00 0xff>;
67				interrupt-map-mask = <0 0 0 0>;
68				interrupt-map = <0 0 0 0 &mpic 58>;
69				marvell,pcie-port = <0>;
70				marvell,pcie-lane = <0>;
71				clocks = <&gateclk 5>;
72				status = "disabled";
73			};
74
75			pcie2: pcie@2,0 {
76				device_type = "pci";
77				assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
78				reg = <0x1000 0 0 0 0>;
79				#address-cells = <3>;
80				#size-cells = <2>;
81				#interrupt-cells = <1>;
82                                ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
83                                          0x81000000 0 0 0x81000000 0x2 0 1 0>;
84				bus-range = <0x00 0xff>;
85				interrupt-map-mask = <0 0 0 0>;
86				interrupt-map = <0 0 0 0 &mpic 62>;
87				marvell,pcie-port = <1>;
88				marvell,pcie-lane = <0>;
89				clocks = <&gateclk 9>;
90				status = "disabled";
91			};
92		};
93
94		internal-regs {
95			L2: l2-cache@8000 {
96				compatible = "marvell,aurora-outer-cache";
97				reg = <0x08000 0x1000>;
98				cache-id-part = <0x100>;
99				cache-level = <2>;
100				cache-unified;
101				wt-override;
102			};
103
104			gpio0: gpio@18100 {
105				compatible = "marvell,armada-370-gpio",
106					     "marvell,orion-gpio";
107				reg = <0x18100 0x40>, <0x181c0 0x08>;
108				reg-names = "gpio", "pwm";
109				ngpios = <32>;
110				gpio-controller;
111				#gpio-cells = <2>;
112				#pwm-cells = <2>;
113				interrupt-controller;
114				#interrupt-cells = <2>;
115				interrupts = <82>, <83>, <84>, <85>;
116				clocks = <&coreclk 0>;
117			};
118
119			gpio1: gpio@18140 {
120				compatible = "marvell,armada-370-gpio",
121					     "marvell,orion-gpio";
122				reg = <0x18140 0x40>, <0x181c8 0x08>;
123				reg-names = "gpio", "pwm";
124				ngpios = <32>;
125				gpio-controller;
126				#gpio-cells = <2>;
127				#pwm-cells = <2>;
128				interrupt-controller;
129				#interrupt-cells = <2>;
130				interrupts = <87>, <88>, <89>, <90>;
131				clocks = <&coreclk 0>;
132			};
133
134			gpio2: gpio@18180 {
135				compatible = "marvell,armada-370-gpio",
136					     "marvell,orion-gpio";
137				reg = <0x18180 0x40>;
138				ngpios = <2>;
139				gpio-controller;
140				#gpio-cells = <2>;
141				interrupt-controller;
142				#interrupt-cells = <2>;
143				interrupts = <91>;
144			};
145
146
147			systemc: system-controller@18200 {
148				compatible = "marvell,armada-370-xp-system-controller";
149				reg = <0x18200 0x100>;
150			};
151
152			gateclk: clock-gating-control@18220 {
153				compatible = "marvell,armada-370-gating-clock";
154				reg = <0x18220 0x4>;
155				clocks = <&coreclk 0>;
156				#clock-cells = <1>;
157			};
158
159			coreclk: mvebu-sar@18230 {
160				compatible = "marvell,armada-370-core-clock";
161				reg = <0x18230 0x08>;
162				#clock-cells = <1>;
163			};
164
165			thermal: thermal@18300 {
166				compatible = "marvell,armada370-thermal";
167				reg = <0x18300 0x4
168					0x18304 0x4>;
169				status = "okay";
170			};
171
172			sscg: sscg@18330 {
173				reg = <0x18330 0x4>;
174			};
175
176			cpuconf: cpu-config@21000 {
177				compatible = "marvell,armada-370-cpu-config";
178				reg = <0x21000 0x8>;
179			};
180
181			audio_controller: audio-controller@30000 {
182				#sound-dai-cells = <1>;
183				compatible = "marvell,armada370-audio";
184				reg = <0x30000 0x4000>;
185				interrupts = <93>;
186				clocks = <&gateclk 0>;
187				clock-names = "internal";
188				status = "disabled";
189			};
190
191			xor0: xor@60800 {
192				compatible = "marvell,orion-xor";
193				reg = <0x60800 0x100
194				       0x60A00 0x100>;
195				status = "okay";
196
197				xor00 {
198					interrupts = <51>;
199					dmacap,memcpy;
200					dmacap,xor;
201				};
202				xor01 {
203					interrupts = <52>;
204					dmacap,memcpy;
205					dmacap,xor;
206					dmacap,memset;
207				};
208			};
209
210			xor1: xor@60900 {
211				compatible = "marvell,orion-xor";
212				reg = <0x60900 0x100
213				       0x60b00 0x100>;
214				status = "okay";
215
216				xor10 {
217					interrupts = <94>;
218					dmacap,memcpy;
219					dmacap,xor;
220				};
221				xor11 {
222					interrupts = <95>;
223					dmacap,memcpy;
224					dmacap,xor;
225					dmacap,memset;
226				};
227			};
228
229			cesa: crypto@90000 {
230				compatible = "marvell,armada-370-crypto";
231				reg = <0x90000 0x10000>;
232				reg-names = "regs";
233				interrupts = <48>;
234				clocks = <&gateclk 23>;
235				clock-names = "cesa0";
236				marvell,crypto-srams = <&crypto_sram>;
237				marvell,crypto-sram-size = <0x7e0>;
238			};
239		};
240
241		crypto_sram: sa-sram {
242			compatible = "mmio-sram";
243			reg = <MBUS_ID(0x09, 0x01) 0 0x800>;
244			reg-names = "sram";
245			clocks = <&gateclk 23>;
246			#address-cells = <1>;
247			#size-cells = <1>;
248			ranges = <0 MBUS_ID(0x09, 0x01) 0 0x800>;
249
250			/*
251			 * The Armada 370 has an erratum preventing the use of
252			 * the standard workflow for CPU idle support (relying
253			 * on the BootROM code to enter/exit idle state).
254			 * Reserve some amount of the crypto SRAM to put the
255			 * cpuidle workaround.
256			 */
257			idle-sram@0 {
258				reg = <0x0 0x20>;
259			};
260		};
261	};
262};
263
264/*
265 * Default UART pinctrl setting without RTS/CTS, can be overwritten on
266 * board level if a different configuration is used.
267 */
268
269&uart0 {
270	pinctrl-0 = <&uart0_pins>;
271	pinctrl-names = "default";
272};
273
274&uart1 {
275	pinctrl-0 = <&uart1_pins>;
276	pinctrl-names = "default";
277};
278
279&i2c0 {
280	reg = <0x11000 0x20>;
281};
282
283&i2c1 {
284	reg = <0x11100 0x20>;
285};
286
287&mpic {
288	reg = <0x20a00 0x1d0>, <0x21870 0x58>;
289};
290
291&timer {
292	compatible = "marvell,armada-370-timer";
293	clocks = <&coreclk 2>;
294};
295
296&watchdog {
297	compatible = "marvell,armada-370-wdt";
298	clocks = <&coreclk 2>;
299};
300
301&usb0 {
302	clocks = <&coreclk 0>;
303};
304
305&usb1 {
306	clocks = <&coreclk 0>;
307};
308
309&eth0 {
310	compatible = "marvell,armada-370-neta";
311};
312
313&eth1 {
314	compatible = "marvell,armada-370-neta";
315};
316
317&pinctrl {
318	compatible = "marvell,mv88f6710-pinctrl";
319
320	spi0_pins1: spi0-pins1 {
321		marvell,pins = "mpp33", "mpp34",
322			       "mpp35", "mpp36";
323		marvell,function = "spi0";
324	};
325
326	spi0_pins2: spi0_pins2 {
327		marvell,pins = "mpp32", "mpp63",
328			       "mpp64", "mpp65";
329		marvell,function = "spi0";
330	};
331
332	spi1_pins: spi1-pins {
333		marvell,pins = "mpp49", "mpp50",
334			       "mpp51", "mpp52";
335		marvell,function = "spi1";
336	};
337
338	uart0_pins: uart0-pins {
339		marvell,pins = "mpp0", "mpp1";
340		marvell,function = "uart0";
341	};
342
343	uart1_pins: uart1-pins {
344		marvell,pins = "mpp41", "mpp42";
345		marvell,function = "uart1";
346	};
347
348	sdio_pins1: sdio-pins1 {
349		marvell,pins = "mpp9",  "mpp11", "mpp12",
350				"mpp13", "mpp14", "mpp15";
351		marvell,function = "sd0";
352	};
353
354	sdio_pins2: sdio-pins2 {
355		marvell,pins = "mpp47", "mpp48", "mpp49",
356				"mpp50", "mpp51", "mpp52";
357		marvell,function = "sd0";
358	};
359
360	sdio_pins3: sdio-pins3 {
361		marvell,pins = "mpp48", "mpp49", "mpp50",
362				"mpp51", "mpp52", "mpp53";
363		marvell,function = "sd0";
364	};
365
366	i2c0_pins: i2c0-pins {
367		marvell,pins = "mpp2", "mpp3";
368		marvell,function = "i2c0";
369	};
370
371	i2s_pins1: i2s-pins1 {
372		marvell,pins = "mpp5", "mpp6", "mpp7",
373			       "mpp8", "mpp9", "mpp10",
374			       "mpp12", "mpp13";
375		marvell,function = "audio";
376	};
377
378	i2s_pins2: i2s-pins2 {
379		marvell,pins = "mpp49", "mpp47", "mpp50",
380			       "mpp59", "mpp57", "mpp61",
381			       "mpp62", "mpp60", "mpp58";
382		marvell,function = "audio";
383	};
384
385	mdio_pins: mdio-pins {
386		marvell,pins = "mpp17", "mpp18";
387		marvell,function = "ge";
388	};
389
390	ge0_rgmii_pins: ge0-rgmii-pins {
391		marvell,pins = "mpp5", "mpp6", "mpp7", "mpp8",
392			       "mpp9", "mpp10", "mpp11", "mpp12",
393			       "mpp13", "mpp14", "mpp15", "mpp16";
394		marvell,function = "ge0";
395	};
396
397	ge1_rgmii_pins: ge1-rgmii-pins {
398		marvell,pins = "mpp19", "mpp20", "mpp21", "mpp22",
399			       "mpp23", "mpp24", "mpp25", "mpp26",
400			       "mpp27", "mpp28", "mpp29", "mpp30";
401		marvell,function = "ge1";
402	};
403};
404
405/*
406 * Default SPI pinctrl setting, can be overwritten on
407 * board level if a different configuration is used.
408 */
409&spi0 {
410	compatible = "marvell,armada-370-spi", "marvell,orion-spi";
411	pinctrl-0 = <&spi0_pins1>;
412	pinctrl-names = "default";
413};
414
415&spi1 {
416	compatible = "marvell,armada-370-spi", "marvell,orion-spi";
417	pinctrl-0 = <&spi1_pins>;
418	pinctrl-names = "default";
419};
420