1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Device Tree file for the Turris Omnia
4 *
5 * Copyright (C) 2016 Uwe Kleine-König <uwe@kleine-koenig.org>
6 * Copyright (C) 2016 Tomas Hlavacek <tmshlvkc@gmail.com>
7 *
8 * Schematic available at https://www.turris.cz/doc/_media/rtrom01-schema.pdf
9 */
10
11/dts-v1/;
12
13#include <dt-bindings/gpio/gpio.h>
14#include <dt-bindings/input/input.h>
15#include <dt-bindings/leds/common.h>
16#include "armada-385.dtsi"
17
18/ {
19	model = "Turris Omnia";
20	compatible = "cznic,turris-omnia", "marvell,armada385", "marvell,armada380";
21
22	chosen {
23		stdout-path = &uart0;
24	};
25
26	memory {
27		device_type = "memory";
28		reg = <0x00000000 0x40000000>; /* 1024 MB */
29	};
30
31	soc {
32		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
33			  MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
34			  MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
35			  MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
36			  MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
37
38		internal-regs {
39
40			/* USB part of the PCIe2/USB 2.0 port */
41			usb@58000 {
42				status = "okay";
43			};
44
45			sata@a8000 {
46				status = "okay";
47			};
48
49			sdhci@d8000 {
50				pinctrl-names = "default";
51				pinctrl-0 = <&sdhci_pins>;
52				status = "okay";
53
54				bus-width = <8>;
55				no-1-8-v;
56				non-removable;
57			};
58
59			usb3@f0000 {
60				status = "okay";
61			};
62
63			usb3@f8000 {
64				status = "okay";
65			};
66		};
67
68		pcie {
69			status = "okay";
70
71			pcie@1,0 {
72				/* Port 0, Lane 0 */
73				status = "okay";
74			};
75
76			pcie@2,0 {
77				/* Port 1, Lane 0 */
78				status = "okay";
79			};
80
81			pcie@3,0 {
82				/* Port 2, Lane 0 */
83				status = "okay";
84			};
85		};
86	};
87
88	sfp: sfp {
89		compatible = "sff,sfp";
90		i2c-bus = <&sfp_i2c>;
91		tx-fault-gpios = <&pcawan 0 GPIO_ACTIVE_HIGH>;
92		tx-disable-gpios = <&pcawan 1 GPIO_ACTIVE_HIGH>;
93		rate-select0-gpios = <&pcawan 2 GPIO_ACTIVE_HIGH>;
94		los-gpios = <&pcawan 3 GPIO_ACTIVE_HIGH>;
95		mod-def0-gpios = <&pcawan 4 GPIO_ACTIVE_LOW>;
96		maximum-power-milliwatt = <3000>;
97
98		/*
99		 * For now this has to be enabled at boot time by U-Boot when
100		 * a SFP module is present. Read more in the comment in the
101		 * eth2 node below.
102		 */
103		status = "disabled";
104	};
105};
106
107&bm {
108	status = "okay";
109};
110
111&bm_bppi {
112	status = "okay";
113};
114
115/* Connected to 88E6176 switch, port 6 */
116&eth0 {
117	pinctrl-names = "default";
118	pinctrl-0 = <&ge0_rgmii_pins>;
119	status = "okay";
120	phy-mode = "rgmii";
121	buffer-manager = <&bm>;
122	bm,pool-long = <0>;
123	bm,pool-short = <3>;
124
125	fixed-link {
126		speed = <1000>;
127		full-duplex;
128	};
129};
130
131/* Connected to 88E6176 switch, port 5 */
132&eth1 {
133	pinctrl-names = "default";
134	pinctrl-0 = <&ge1_rgmii_pins>;
135	status = "okay";
136	phy-mode = "rgmii";
137	buffer-manager = <&bm>;
138	bm,pool-long = <1>;
139	bm,pool-short = <3>;
140
141	fixed-link {
142		speed = <1000>;
143		full-duplex;
144	};
145};
146
147/* WAN port */
148&eth2 {
149	/*
150	 * eth2 is connected via a multiplexor to both the SFP cage and to
151	 * ethernet-phy@1. The multiplexor switches the signal to SFP cage when
152	 * a SFP module is present, as determined by the mode-def0 GPIO.
153	 *
154	 * Until kernel supports this configuration properly, in case SFP module
155	 * is present, U-Boot has to enable the sfp node above, remove phy
156	 * handle and add managed = "in-band-status" property.
157	 */
158	status = "okay";
159	phy-mode = "sgmii";
160	phy-handle = <&phy1>;
161	phys = <&comphy5 2>;
162	sfp = <&sfp>;
163	buffer-manager = <&bm>;
164	bm,pool-long = <2>;
165	bm,pool-short = <3>;
166};
167
168&i2c0 {
169	pinctrl-names = "default";
170	pinctrl-0 = <&i2c0_pins>;
171	status = "okay";
172
173	i2cmux@70 {
174		compatible = "nxp,pca9547";
175		#address-cells = <1>;
176		#size-cells = <0>;
177		reg = <0x70>;
178
179		i2c@0 {
180			#address-cells = <1>;
181			#size-cells = <0>;
182			reg = <0>;
183
184			/* STM32F0 command interface at address 0x2a */
185
186			led-controller@2b {
187				compatible = "cznic,turris-omnia-leds";
188				reg = <0x2b>;
189				#address-cells = <1>;
190				#size-cells = <0>;
191
192				/*
193				 * LEDs are controlled by MCU (STM32F0) at
194				 * address 0x2b.
195				 *
196				 * The driver does not support HW control mode
197				 * for the LEDs yet. Disable the LEDs for now.
198				 *
199				 * Also LED functions are not stable yet:
200				 * - there are 3 LEDs connected via MCU to PCIe
201				 *   ports. One of these ports supports mSATA.
202				 *   There is no mSATA nor PCIe function.
203				 *   For now we use LED_FUNCTION_WLAN, since
204				 *   in most cases users have wifi cards in
205				 *   these slots
206				 * - there are 2 LEDs dedicated for user: A and
207				 *   B. Again there is no such function defined.
208				 *   For now we use LED_FUNCTION_INDICATOR
209				 */
210				status = "disabled";
211
212				multi-led@0 {
213					reg = <0x0>;
214					color = <LED_COLOR_ID_RGB>;
215					function = LED_FUNCTION_INDICATOR;
216					function-enumerator = <2>;
217				};
218
219				multi-led@1 {
220					reg = <0x1>;
221					color = <LED_COLOR_ID_RGB>;
222					function = LED_FUNCTION_INDICATOR;
223					function-enumerator = <1>;
224				};
225
226				multi-led@2 {
227					reg = <0x2>;
228					color = <LED_COLOR_ID_RGB>;
229					function = LED_FUNCTION_WLAN;
230					function-enumerator = <3>;
231				};
232
233				multi-led@3 {
234					reg = <0x3>;
235					color = <LED_COLOR_ID_RGB>;
236					function = LED_FUNCTION_WLAN;
237					function-enumerator = <2>;
238				};
239
240				multi-led@4 {
241					reg = <0x4>;
242					color = <LED_COLOR_ID_RGB>;
243					function = LED_FUNCTION_WLAN;
244					function-enumerator = <1>;
245				};
246
247				multi-led@5 {
248					reg = <0x5>;
249					color = <LED_COLOR_ID_RGB>;
250					function = LED_FUNCTION_WAN;
251				};
252
253				multi-led@6 {
254					reg = <0x6>;
255					color = <LED_COLOR_ID_RGB>;
256					function = LED_FUNCTION_LAN;
257					function-enumerator = <4>;
258				};
259
260				multi-led@7 {
261					reg = <0x7>;
262					color = <LED_COLOR_ID_RGB>;
263					function = LED_FUNCTION_LAN;
264					function-enumerator = <3>;
265				};
266
267				multi-led@8 {
268					reg = <0x8>;
269					color = <LED_COLOR_ID_RGB>;
270					function = LED_FUNCTION_LAN;
271					function-enumerator = <2>;
272				};
273
274				multi-led@9 {
275					reg = <0x9>;
276					color = <LED_COLOR_ID_RGB>;
277					function = LED_FUNCTION_LAN;
278					function-enumerator = <1>;
279				};
280
281				multi-led@a {
282					reg = <0xa>;
283					color = <LED_COLOR_ID_RGB>;
284					function = LED_FUNCTION_LAN;
285					function-enumerator = <0>;
286				};
287
288				multi-led@b {
289					reg = <0xb>;
290					color = <LED_COLOR_ID_RGB>;
291					function = LED_FUNCTION_POWER;
292				};
293			};
294
295			eeprom@54 {
296				compatible = "atmel,24c64";
297				reg = <0x54>;
298
299				/* The EEPROM contains data for bootloader.
300				 * Contents:
301				 * 	struct omnia_eeprom {
302				 * 		u32 magic; (=0x0341a034 in LE)
303				 *		u32 ramsize; (in GiB)
304				 * 		char regdomain[4];
305				 * 		u32 crc32;
306				 * 	};
307				 */
308			};
309		};
310
311		i2c@1 {
312			#address-cells = <1>;
313			#size-cells = <0>;
314			reg = <1>;
315
316			/* routed to PCIe0/mSATA connector (CN7A) */
317		};
318
319		i2c@2 {
320			#address-cells = <1>;
321			#size-cells = <0>;
322			reg = <2>;
323
324			/* routed to PCIe1/USB2 connector (CN61A) */
325		};
326
327		i2c@3 {
328			#address-cells = <1>;
329			#size-cells = <0>;
330			reg = <3>;
331
332			/* routed to PCIe2 connector (CN62A) */
333		};
334
335		sfp_i2c: i2c@4 {
336			#address-cells = <1>;
337			#size-cells = <0>;
338			reg = <4>;
339
340			/* routed to SFP+ */
341		};
342
343		i2c@5 {
344			#address-cells = <1>;
345			#size-cells = <0>;
346			reg = <5>;
347
348			/* ATSHA204A at address 0x64 */
349		};
350
351		i2c@6 {
352			#address-cells = <1>;
353			#size-cells = <0>;
354			reg = <6>;
355
356			/* exposed on pin header */
357		};
358
359		i2c@7 {
360			#address-cells = <1>;
361			#size-cells = <0>;
362			reg = <7>;
363
364			pcawan: gpio@71 {
365				/*
366				 * GPIO expander for SFP+ signals and
367				 * and phy irq
368				 */
369				compatible = "nxp,pca9538";
370				reg = <0x71>;
371
372				pinctrl-names = "default";
373				pinctrl-0 = <&pcawan_pins>;
374
375				interrupt-parent = <&gpio1>;
376				interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
377
378				gpio-controller;
379				#gpio-cells = <2>;
380			};
381		};
382	};
383};
384
385&mdio {
386	pinctrl-names = "default";
387	pinctrl-0 = <&mdio_pins>;
388	status = "okay";
389
390	phy1: ethernet-phy@1 {
391		compatible = "ethernet-phy-ieee802.3-c22";
392		reg = <1>;
393		marvell,reg-init = <3 18 0 0x4985>;
394
395		/* irq is connected to &pcawan pin 7 */
396	};
397
398	/* Switch MV88E6176 at address 0x10 */
399	switch@10 {
400		pinctrl-names = "default";
401		pinctrl-0 = <&swint_pins>;
402		compatible = "marvell,mv88e6085";
403		#address-cells = <1>;
404		#size-cells = <0>;
405
406		dsa,member = <0 0>;
407		reg = <0x10>;
408
409		interrupt-parent = <&gpio1>;
410		interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
411
412		ports {
413			#address-cells = <1>;
414			#size-cells = <0>;
415
416			ports@0 {
417				reg = <0>;
418				label = "lan0";
419			};
420
421			ports@1 {
422				reg = <1>;
423				label = "lan1";
424			};
425
426			ports@2 {
427				reg = <2>;
428				label = "lan2";
429			};
430
431			ports@3 {
432				reg = <3>;
433				label = "lan3";
434			};
435
436			ports@4 {
437				reg = <4>;
438				label = "lan4";
439			};
440
441			ports@5 {
442				reg = <5>;
443				label = "cpu";
444				ethernet = <&eth1>;
445				phy-mode = "rgmii-id";
446
447				fixed-link {
448					speed = <1000>;
449					full-duplex;
450				};
451			};
452
453			/* port 6 is connected to eth0 */
454		};
455	};
456};
457
458&pinctrl {
459	pcawan_pins: pcawan-pins {
460		marvell,pins = "mpp46";
461		marvell,function = "gpio";
462	};
463
464	swint_pins: swint-pins {
465		marvell,pins = "mpp45";
466		marvell,function = "gpio";
467	};
468
469	spi0cs0_pins: spi0cs0-pins {
470		marvell,pins = "mpp25";
471		marvell,function = "spi0";
472	};
473
474	spi0cs1_pins: spi0cs1-pins {
475		marvell,pins = "mpp26";
476		marvell,function = "spi0";
477	};
478};
479
480&spi0 {
481	pinctrl-names = "default";
482	pinctrl-0 = <&spi0_pins &spi0cs0_pins>;
483	status = "okay";
484
485	spi-nor@0 {
486		compatible = "spansion,s25fl164k", "jedec,spi-nor";
487		#address-cells = <1>;
488		#size-cells = <1>;
489		reg = <0>;
490		spi-max-frequency = <40000000>;
491
492		partitions {
493			compatible = "fixed-partitions";
494			#address-cells = <1>;
495			#size-cells = <1>;
496
497			partition@0 {
498				reg = <0x0 0x00100000>;
499				label = "U-Boot";
500			};
501
502			partition@100000 {
503				reg = <0x00100000 0x00700000>;
504				label = "Rescue system";
505			};
506		};
507	};
508
509	/* MISO, MOSI, SCLK and CS1 are routed to pin header CN11 */
510};
511
512&uart0 {
513	/* Pin header CN10 */
514	pinctrl-names = "default";
515	pinctrl-0 = <&uart0_pins>;
516	status = "okay";
517};
518
519&uart1 {
520	/* Pin header CN11 */
521	pinctrl-names = "default";
522	pinctrl-0 = <&uart1_pins>;
523	status = "okay";
524};
525