1// SPDX-License-Identifier: GPL-2.0+
2// Copyright (c) 2019 Facebook Inc.
3/dts-v1/;
4
5#include <dt-bindings/gpio/aspeed-gpio.h>
6#include "ast2500-facebook-netbmc-common.dtsi"
7
8/ {
9	model = "Facebook Wedge 400 BMC";
10	compatible = "facebook,wedge400-bmc", "aspeed,ast2500";
11
12	aliases {
13		/*
14		 * PCA9548 (2-0070) provides 8 channels connecting to
15		 * SCM (System Controller Module).
16		 */
17		i2c16 = &imux16;
18		i2c17 = &imux17;
19		i2c18 = &imux18;
20		i2c19 = &imux19;
21		i2c20 = &imux20;
22		i2c21 = &imux21;
23		i2c22 = &imux22;
24		i2c23 = &imux23;
25
26		/*
27		 * PCA9548 (8-0070) provides 8 channels connecting to
28		 * SMB (Switch Main Board).
29		 */
30		i2c24 = &imux24;
31		i2c25 = &imux25;
32		i2c26 = &imux26;
33		i2c27 = &imux27;
34		i2c28 = &imux28;
35		i2c29 = &imux29;
36		i2c30 = &imux30;
37		i2c31 = &imux31;
38
39		/*
40		 * PCA9548 (11-0076) provides 8 channels connecting to
41		 * FCM (Fan Controller Module).
42		 */
43		i2c32 = &imux32;
44		i2c33 = &imux33;
45		i2c34 = &imux34;
46		i2c35 = &imux35;
47		i2c36 = &imux36;
48		i2c37 = &imux37;
49		i2c38 = &imux38;
50		i2c39 = &imux39;
51
52		spi2 = &spi_gpio;
53	};
54
55	chosen {
56		stdout-path = &uart1;
57		bootargs = "console=ttyS0,9600n8 root=/dev/ram rw";
58	};
59
60	ast-adc-hwmon {
61		compatible = "iio-hwmon";
62		io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, <&adc 4>;
63	};
64
65	/*
66	 * GPIO-based SPI Master is required to access SPI TPM, because
67	 * full-duplex SPI transactions are not supported by ASPEED SPI
68	 * Controllers.
69	 */
70	spi_gpio: spi-gpio {
71		status = "okay";
72		compatible = "spi-gpio";
73		#address-cells = <1>;
74		#size-cells = <0>;
75
76		cs-gpios = <&gpio ASPEED_GPIO(R, 2) GPIO_ACTIVE_LOW>;
77		gpio-sck = <&gpio ASPEED_GPIO(R, 3) GPIO_ACTIVE_HIGH>;
78		gpio-mosi = <&gpio ASPEED_GPIO(R, 4) GPIO_ACTIVE_HIGH>;
79		gpio-miso = <&gpio ASPEED_GPIO(R, 5) GPIO_ACTIVE_HIGH>;
80		num-chipselects = <1>;
81
82		tpmdev@0 {
83			compatible = "tcg,tpm_tis-spi";
84			spi-max-frequency = <33000000>;
85			reg = <0>;
86		};
87	};
88};
89
90/*
91 * Both firmware flashes are 128MB on Wedge400 BMC.
92 */
93&fmc_flash0 {
94	partitions {
95		compatible = "fixed-partitions";
96		#address-cells = <1>;
97		#size-cells = <1>;
98
99		/*
100		 * u-boot partition: 384KB.
101		 */
102		u-boot@0 {
103			reg = <0x0 0x60000>;
104			label = "u-boot";
105		};
106
107		/*
108		 * u-boot environment variables: 128KB.
109		 */
110		u-boot-env@60000 {
111			reg = <0x60000 0x20000>;
112			label = "env";
113		};
114
115		/*
116		 * FIT image: 123.5 MB.
117		 */
118		fit@80000 {
119			reg = <0x80000 0x7b80000>;
120			label = "fit";
121		};
122
123		/*
124		 * "data0" partition (4MB) is reserved for persistent
125		 * data store.
126		 */
127		data0@7c00000 {
128			reg = <0x7c00000 0x400000>;
129			label = "data0";
130		};
131
132		/*
133		 * "flash0" partition (covering the entire flash) is
134		 * explicitly created to avoid breaking legacy applications.
135		 */
136		flash0@0 {
137			reg = <0x0 0x8000000>;
138			label = "flash0";
139		};
140	};
141};
142
143&fmc_flash1 {
144	partitions {
145		compatible = "fixed-partitions";
146		#address-cells = <1>;
147		#size-cells = <1>;
148
149		flash1@0 {
150			reg = <0x0 0x8000000>;
151			label = "flash1";
152		};
153	};
154};
155
156&uart2 {
157	status = "okay";
158	pinctrl-names = "default";
159	pinctrl-0 = <&pinctrl_txd2_default
160		     &pinctrl_rxd2_default>;
161};
162
163&uart4 {
164	status = "okay";
165	pinctrl-names = "default";
166	pinctrl-0 = <&pinctrl_txd4_default
167		     &pinctrl_rxd4_default>;
168};
169
170/*
171 * I2C bus #0 is multi-master environment dedicated for BMC and Bridge IC
172 * communication.
173 */
174&i2c0 {
175	status = "okay";
176	multi-master;
177	bus-frequency = <1000000>;
178};
179
180&i2c1 {
181	status = "okay";
182};
183
184&i2c2 {
185	status = "okay";
186
187	i2c-switch@70 {
188		compatible = "nxp,pca9548";
189		#address-cells = <1>;
190		#size-cells = <0>;
191		reg = <0x70>;
192		i2c-mux-idle-disconnect;
193
194		imux16: i2c@0 {
195			#address-cells = <1>;
196			#size-cells = <0>;
197			reg = <0>;
198		};
199
200		imux17: i2c@1 {
201			#address-cells = <1>;
202			#size-cells = <0>;
203			reg = <1>;
204		};
205
206		imux18: i2c@2 {
207			#address-cells = <1>;
208			#size-cells = <0>;
209			reg = <2>;
210		};
211
212		imux19: i2c@3 {
213			#address-cells = <1>;
214			#size-cells = <0>;
215			reg = <3>;
216		};
217
218		imux20: i2c@4 {
219			#address-cells = <1>;
220			#size-cells = <0>;
221			reg = <4>;
222		};
223
224		imux21: i2c@5 {
225			#address-cells = <1>;
226			#size-cells = <0>;
227			reg = <5>;
228		};
229
230		imux22: i2c@6 {
231			#address-cells = <1>;
232			#size-cells = <0>;
233			reg = <6>;
234		};
235
236		imux23: i2c@7 {
237			#address-cells = <1>;
238			#size-cells = <0>;
239			reg = <7>;
240		};
241	};
242};
243
244&i2c3 {
245	status = "okay";
246};
247
248&i2c4 {
249	status = "okay";
250};
251
252&i2c5 {
253	status = "okay";
254};
255
256&i2c6 {
257	status = "okay";
258};
259
260&i2c7 {
261	status = "okay";
262};
263
264&i2c8 {
265	status = "okay";
266
267	i2c-switch@70 {
268		compatible = "nxp,pca9548";
269		#address-cells = <1>;
270		#size-cells = <0>;
271		reg = <0x70>;
272		i2c-mux-idle-disconnect;
273
274		imux24: i2c@0 {
275			#address-cells = <1>;
276			#size-cells = <0>;
277			reg = <0>;
278		};
279
280		imux25: i2c@1 {
281			#address-cells = <1>;
282			#size-cells = <0>;
283			reg = <1>;
284		};
285
286		imux26: i2c@2 {
287			#address-cells = <1>;
288			#size-cells = <0>;
289			reg = <2>;
290		};
291
292		imux27: i2c@3 {
293			#address-cells = <1>;
294			#size-cells = <0>;
295			reg = <3>;
296		};
297
298		imux28: i2c@4 {
299			#address-cells = <1>;
300			#size-cells = <0>;
301			reg = <4>;
302		};
303
304		imux29: i2c@5 {
305			#address-cells = <1>;
306			#size-cells = <0>;
307			reg = <5>;
308		};
309
310		imux30: i2c@6 {
311			#address-cells = <1>;
312			#size-cells = <0>;
313			reg = <6>;
314		};
315
316		imux31: i2c@7 {
317			#address-cells = <1>;
318			#size-cells = <0>;
319			reg = <7>;
320		};
321
322	};
323};
324
325&i2c9 {
326	status = "okay";
327};
328
329&i2c10 {
330	status = "okay";
331};
332
333&i2c11 {
334	status = "okay";
335
336	i2c-switch@76 {
337		compatible = "nxp,pca9548";
338		#address-cells = <1>;
339		#size-cells = <0>;
340		reg = <0x76>;
341		i2c-mux-idle-disconnect;
342
343		imux32: i2c@0 {
344			#address-cells = <1>;
345			#size-cells = <0>;
346			reg = <0>;
347		};
348
349		imux33: i2c@1 {
350			#address-cells = <1>;
351			#size-cells = <0>;
352			reg = <1>;
353		};
354
355		imux34: i2c@2 {
356			#address-cells = <1>;
357			#size-cells = <0>;
358			reg = <2>;
359		};
360
361		imux35: i2c@3 {
362			#address-cells = <1>;
363			#size-cells = <0>;
364			reg = <3>;
365		};
366
367		imux36: i2c@4 {
368			#address-cells = <1>;
369			#size-cells = <0>;
370			reg = <4>;
371		};
372
373		imux37: i2c@5 {
374			#address-cells = <1>;
375			#size-cells = <0>;
376			reg = <5>;
377		};
378
379		imux38: i2c@6 {
380			#address-cells = <1>;
381			#size-cells = <0>;
382			reg = <6>;
383		};
384
385		imux39: i2c@7 {
386			#address-cells = <1>;
387			#size-cells = <0>;
388			reg = <7>;
389		};
390
391	};
392};
393
394&i2c12 {
395	status = "okay";
396};
397
398&i2c13 {
399	status = "okay";
400};
401
402&adc {
403	status = "okay";
404};
405
406&ehci1 {
407	status = "okay";
408};
409
410&uhci {
411	status = "okay";
412};
413
414&sdhci1 {
415	/*
416	 * DMA mode needs to be disabled to avoid conflicts with UHCI
417	 * Controller in AST2500 SoC.
418	 */
419	sdhci-caps-mask = <0x0 0x580000>;
420};
421