1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright 2012 DENX Software Engineering GmbH
4 * Heiko Schocher <hs@denx.de>
5 */
6#include <dt-bindings/interrupt-controller/irq.h>
7
8/ {
9	#address-cells = <1>;
10	#size-cells = <1>;
11	chosen { };
12	aliases { };
13
14	memory@c0000000 {
15		device_type = "memory";
16		reg = <0xc0000000 0x0>;
17	};
18
19	cpus {
20		#address-cells = <1>;
21		#size-cells = <0>;
22
23		cpu: cpu@0 {
24			compatible = "arm,arm926ej-s";
25			device_type = "cpu";
26			reg = <0>;
27			clocks = <&psc0 14>;
28			operating-points-v2 = <&opp_table>;
29		};
30	};
31
32	opp_table: opp-table {
33		compatible = "operating-points-v2";
34
35		opp_100: opp100-100000000 {
36			opp-hz = /bits/ 64 <100000000>;
37			opp-microvolt = <1000000 950000 1050000>;
38		};
39
40		opp_200: opp110-200000000 {
41			opp-hz = /bits/ 64 <200000000>;
42			opp-microvolt = <1100000 1050000 1160000>;
43		};
44
45		opp_300: opp120-300000000 {
46			opp-hz = /bits/ 64 <300000000>;
47			opp-microvolt = <1200000 1140000 1320000>;
48		};
49
50		/*
51		 * Original silicon was 300MHz max, so higher frequencies
52		 * need to be enabled on a per-board basis if the chip is
53		 * capable.
54		 */
55
56		opp_375: opp120-375000000 {
57			status = "disabled";
58			opp-hz = /bits/ 64 <375000000>;
59			opp-microvolt = <1200000 1140000 1320000>;
60		};
61
62		opp_456: opp130-456000000 {
63			status = "disabled";
64			opp-hz = /bits/ 64 <456000000>;
65			opp-microvolt = <1300000 1250000 1350000>;
66		};
67	};
68
69	arm {
70		#address-cells = <1>;
71		#size-cells = <1>;
72		ranges;
73		intc: interrupt-controller@fffee000 {
74			compatible = "ti,cp-intc";
75			interrupt-controller;
76			#interrupt-cells = <1>;
77			ti,intc-size = <101>;
78			reg = <0xfffee000 0x2000>;
79		};
80	};
81	clocks: clocks {
82		ref_clk: ref_clk {
83			compatible = "fixed-clock";
84			#clock-cells = <0>;
85			clock-output-names = "ref_clk";
86		};
87		sata_refclk: sata_refclk {
88			compatible = "fixed-clock";
89			#clock-cells = <0>;
90			clock-output-names = "sata_refclk";
91			status = "disabled";
92		};
93		usb_refclkin: usb_refclkin {
94			compatible = "fixed-clock";
95			#clock-cells = <0>;
96			clock-output-names = "usb_refclkin";
97			status = "disabled";
98		};
99	};
100	dsp: dsp@11800000 {
101		compatible = "ti,da850-dsp";
102		reg = <0x11800000 0x40000>,
103		      <0x11e00000 0x8000>,
104		      <0x11f00000 0x8000>,
105		      <0x01c14044 0x4>,
106		      <0x01c14174 0x8>;
107		reg-names = "l2sram", "l1pram", "l1dram", "host1cfg", "chipsig";
108		interrupt-parent = <&intc>;
109		interrupts = <28>;
110		clocks = <&psc0 15>;
111		resets = <&psc0 15>;
112		status = "disabled";
113	};
114	soc@1c00000 {
115		compatible = "simple-bus";
116		model = "da850";
117		#address-cells = <1>;
118		#size-cells = <1>;
119		ranges = <0x0 0x01c00000 0x400000>;
120		interrupt-parent = <&intc>;
121
122		psc0: clock-controller@10000 {
123			compatible = "ti,da850-psc0";
124			reg = <0x10000 0x1000>;
125			#clock-cells = <1>;
126			#reset-cells = <1>;
127			#power-domain-cells = <1>;
128			clocks = <&pll0_sysclk 1>, <&pll0_sysclk 2>,
129				 <&pll0_sysclk 4>, <&pll0_sysclk 6>,
130				 <&async1_clk>;
131			clock-names = "pll0_sysclk1", "pll0_sysclk2",
132				      "pll0_sysclk4", "pll0_sysclk6",
133				      "async1";
134		};
135		pll0: clock-controller@11000 {
136			compatible = "ti,da850-pll0";
137			reg = <0x11000 0x1000>;
138			clocks = <&ref_clk>, <&pll1_sysclk 3>;
139			clock-names = "clksrc", "extclksrc";
140
141			pll0_pllout: pllout {
142				#clock-cells = <0>;
143			};
144			pll0_sysclk: sysclk {
145				#clock-cells = <1>;
146			};
147			pll0_auxclk: auxclk {
148				#clock-cells = <0>;
149			};
150			pll0_obsclk: obsclk {
151				#clock-cells = <0>;
152			};
153		};
154		pmx_core: pinmux@14120 {
155			compatible = "pinctrl-single";
156			reg = <0x14120 0x50>;
157			#pinctrl-cells = <2>;
158			pinctrl-single,bit-per-mux;
159			pinctrl-single,register-width = <32>;
160			pinctrl-single,function-mask = <0xf>;
161			/* pin base, nr pins & gpio function */
162			pinctrl-single,gpio-range = <&range   0 17 0x8>,
163						    <&range  17  8 0x4>,
164						    <&range  26  8 0x4>,
165						    <&range  34 80 0x8>,
166						    <&range 129 31 0x8>;
167			status = "disabled";
168
169			range: gpio-range {
170				#pinctrl-single,gpio-range-cells = <3>;
171			};
172
173			serial0_rtscts_pins: pinmux_serial0_rtscts_pins {
174				pinctrl-single,bits = <
175					/* UART0_RTS UART0_CTS */
176					0x0c 0x22000000 0xff000000
177				>;
178			};
179			serial0_rxtx_pins: pinmux_serial0_rxtx_pins {
180				pinctrl-single,bits = <
181					/* UART0_TXD UART0_RXD */
182					0x0c 0x00220000 0x00ff0000
183				>;
184			};
185			serial1_rtscts_pins: pinmux_serial1_rtscts_pins {
186				pinctrl-single,bits = <
187					/* UART1_CTS UART1_RTS */
188					0x00 0x00440000 0x00ff0000
189				>;
190			};
191			serial1_rxtx_pins: pinmux_serial1_rxtx_pins {
192				pinctrl-single,bits = <
193					/* UART1_TXD UART1_RXD */
194					0x10 0x22000000 0xff000000
195				>;
196			};
197			serial2_rtscts_pins: pinmux_serial2_rtscts_pins {
198				pinctrl-single,bits = <
199					/* UART2_CTS UART2_RTS */
200					0x00 0x44000000 0xff000000
201				>;
202			};
203			serial2_rxtx_pins: pinmux_serial2_rxtx_pins {
204				pinctrl-single,bits = <
205					/* UART2_TXD UART2_RXD */
206					0x10 0x00220000 0x00ff0000
207				>;
208			};
209			i2c0_pins: pinmux_i2c0_pins {
210				pinctrl-single,bits = <
211					/* I2C0_SDA,I2C0_SCL */
212					0x10 0x00002200 0x0000ff00
213				>;
214			};
215			i2c1_pins: pinmux_i2c1_pins {
216				pinctrl-single,bits = <
217					/* I2C1_SDA, I2C1_SCL */
218					0x10 0x00440000 0x00ff0000
219				>;
220			};
221			mmc0_pins: pinmux_mmc_pins {
222				pinctrl-single,bits = <
223					/* MMCSD0_DAT[3] MMCSD0_DAT[2]
224					 * MMCSD0_DAT[1] MMCSD0_DAT[0]
225					 * MMCSD0_CMD    MMCSD0_CLK
226					 */
227					0x28 0x00222222  0x00ffffff
228				>;
229			};
230			ehrpwm0a_pins: pinmux_ehrpwm0a_pins {
231				pinctrl-single,bits = <
232					/* EPWM0A */
233					0xc 0x00000002 0x0000000f
234				>;
235			};
236			ehrpwm0b_pins: pinmux_ehrpwm0b_pins {
237				pinctrl-single,bits = <
238					/* EPWM0B */
239					0xc 0x00000020 0x000000f0
240				>;
241			};
242			ehrpwm1a_pins: pinmux_ehrpwm1a_pins {
243				pinctrl-single,bits = <
244					/* EPWM1A */
245					0x14 0x00000002 0x0000000f
246				>;
247			};
248			ehrpwm1b_pins: pinmux_ehrpwm1b_pins {
249				pinctrl-single,bits = <
250					/* EPWM1B */
251					0x14 0x00000020 0x000000f0
252				>;
253			};
254			ecap0_pins: pinmux_ecap0_pins {
255				pinctrl-single,bits = <
256					/* ECAP0_APWM0 */
257					0x8 0x20000000 0xf0000000
258				>;
259			};
260			ecap1_pins: pinmux_ecap1_pins {
261				pinctrl-single,bits = <
262					/* ECAP1_APWM1 */
263					0x4 0x40000000 0xf0000000
264				>;
265			};
266			ecap2_pins: pinmux_ecap2_pins {
267				pinctrl-single,bits = <
268					/* ECAP2_APWM2 */
269					0x4 0x00000004 0x0000000f
270				>;
271			};
272			spi0_pins: pinmux_spi0_pins {
273				pinctrl-single,bits = <
274					/* SIMO, SOMI, CLK */
275					0xc 0x00001101 0x0000ff0f
276				>;
277			};
278			spi0_cs0_pin: pinmux_spi0_cs0 {
279				pinctrl-single,bits = <
280					/* CS0 */
281					0x10 0x00000010 0x000000f0
282				>;
283			};
284			spi0_cs3_pin: pinmux_spi0_cs3_pin {
285				pinctrl-single,bits = <
286					/* CS3 */
287					0xc 0x01000000 0x0f000000
288				>;
289			};
290			spi1_pins: pinmux_spi1_pins {
291				pinctrl-single,bits = <
292					/* SIMO, SOMI, CLK */
293					0x14 0x00110100 0x00ff0f00
294				>;
295			};
296			spi1_cs0_pin: pinmux_spi1_cs0 {
297				pinctrl-single,bits = <
298					/* CS0 */
299					0x14 0x00000010 0x000000f0
300				>;
301			};
302			mdio_pins: pinmux_mdio_pins {
303				pinctrl-single,bits = <
304					/* MDIO_CLK, MDIO_D */
305					0x10 0x00000088 0x000000ff
306				>;
307			};
308			mii_pins: pinmux_mii_pins {
309				pinctrl-single,bits = <
310					/*
311					 * MII_TXEN, MII_TXCLK, MII_COL
312					 * MII_TXD_3, MII_TXD_2, MII_TXD_1
313					 * MII_TXD_0
314					 */
315					0x8 0x88888880 0xfffffff0
316					/*
317					 * MII_RXER, MII_CRS, MII_RXCLK
318					 * MII_RXDV, MII_RXD_3, MII_RXD_2
319					 * MII_RXD_1, MII_RXD_0
320					 */
321					0xc 0x88888888 0xffffffff
322				>;
323			};
324			lcd_pins: pinmux_lcd_pins {
325				pinctrl-single,bits = <
326					/*
327					 * LCD_D[2], LCD_D[3], LCD_D[4], LCD_D[5],
328					 * LCD_D[6], LCD_D[7]
329					 */
330					0x40 0x22222200 0xffffff00
331					/*
332					 * LCD_D[10], LCD_D[11], LCD_D[12], LCD_D[13],
333					 * LCD_D[14], LCD_D[15], LCD_D[0], LCD_D[1]
334					 */
335					0x44 0x22222222 0xffffffff
336					/* LCD_D[8], LCD_D[9] */
337					0x48 0x00000022 0x000000ff
338
339					/* LCD_PCLK */
340					0x48 0x02000000 0x0f000000
341					/* LCD_AC_ENB_CS, LCD_VSYNC, LCD_HSYNC */
342					0x4c 0x02000022 0x0f0000ff
343				>;
344			};
345			vpif_capture_pins: vpif_capture_pins {
346				pinctrl-single,bits = <
347					/* VP_DIN[2..7], VP_CLKIN1, VP_CLKIN0 */
348					0x38 0x11111111 0xffffffff
349					/* VP_DIN[10..15,0..1] */
350					0x3c 0x11111111 0xffffffff
351					/* VP_DIN[8..9] */
352					0x40 0x00000011 0x000000ff
353				>;
354			};
355			vpif_display_pins: vpif_display_pins {
356				pinctrl-single,bits = <
357					/* VP_DOUT[2..7] */
358					0x40 0x11111100 0xffffff00
359					/* VP_DOUT[10..15,0..1] */
360					0x44 0x11111111 0xffffffff
361					/*  VP_DOUT[8..9] */
362					0x48 0x00000011 0x000000ff
363					/*
364					 * VP_CLKOUT3, VP_CLKIN3,
365					 * VP_CLKOUT2, VP_CLKIN2
366					 */
367					0x4c 0x00111100 0x00ffff00
368				>;
369			};
370		};
371		prictrl: priority-controller@14110 {
372			compatible = "ti,da850-mstpri";
373			reg = <0x14110 0x0c>;
374			status = "disabled";
375		};
376		cfgchip: chip-controller@1417c {
377			compatible = "ti,da830-cfgchip", "syscon", "simple-mfd";
378			reg = <0x1417c 0x14>;
379
380			usb_phy: usb-phy {
381				compatible = "ti,da830-usb-phy";
382				#phy-cells = <1>;
383				clocks = <&usb_phy_clk 0>, <&usb_phy_clk 1>;
384				clock-names = "usb0_clk48", "usb1_clk48";
385				status = "disabled";
386			};
387			usb_phy_clk: usb-phy-clocks {
388				compatible = "ti,da830-usb-phy-clocks";
389				#clock-cells = <1>;
390				clocks = <&psc1 1>, <&usb_refclkin>,
391					 <&pll0_auxclk>;
392				clock-names = "fck", "usb_refclkin", "auxclk";
393			};
394			ehrpwm_tbclk: ehrpwm_tbclk {
395				compatible = "ti,da830-tbclksync";
396				#clock-cells = <0>;
397				clocks = <&psc1 17>;
398				clock-names = "fck";
399			};
400			div4p5_clk: div4.5 {
401				compatible = "ti,da830-div4p5ena";
402				#clock-cells = <0>;
403				clocks = <&pll0_pllout>;
404				clock-names = "pll0_pllout";
405			};
406			async1_clk: async1 {
407				compatible = "ti,da850-async1-clksrc";
408				#clock-cells = <0>;
409				clocks = <&pll0_sysclk 3>, <&div4p5_clk>;
410				clock-names = "pll0_sysclk3", "div4.5";
411			};
412			async3_clk: async3 {
413				compatible = "ti,da850-async3-clksrc";
414				#clock-cells = <0>;
415				clocks = <&pll0_sysclk 2>, <&pll1_sysclk 2>;
416				clock-names = "pll0_sysclk2", "pll1_sysclk2";
417			};
418		};
419		edma0: edma@0 {
420			compatible = "ti,edma3-tpcc";
421			/* eDMA3 CC0: 0x01c0 0000 - 0x01c0 7fff */
422			reg =	<0x0 0x8000>;
423			reg-names = "edma3_cc";
424			interrupts = <11 12>;
425			interrupt-names = "edma3_ccint", "edma3_ccerrint";
426			#dma-cells = <2>;
427
428			ti,tptcs = <&edma0_tptc0 7>, <&edma0_tptc1 0>;
429			power-domains = <&psc0 0>;
430		};
431		edma0_tptc0: tptc@8000 {
432			compatible = "ti,edma3-tptc";
433			reg =	<0x8000 0x400>;
434			interrupts = <13>;
435			interrupt-names = "edm3_tcerrint";
436			power-domains = <&psc0 1>;
437		};
438		edma0_tptc1: tptc@8400 {
439			compatible = "ti,edma3-tptc";
440			reg =	<0x8400 0x400>;
441			interrupts = <32>;
442			interrupt-names = "edm3_tcerrint";
443			power-domains = <&psc0 2>;
444		};
445		edma1: edma@230000 {
446			compatible = "ti,edma3-tpcc";
447			/* eDMA3 CC1: 0x01e3 0000 - 0x01e3 7fff */
448			reg =	<0x230000 0x8000>;
449			reg-names = "edma3_cc";
450			interrupts = <93 94>;
451			interrupt-names = "edma3_ccint", "edma3_ccerrint";
452			#dma-cells = <2>;
453
454			ti,tptcs = <&edma1_tptc0 7>;
455			power-domains = <&psc1 0>;
456		};
457		edma1_tptc0: tptc@238000 {
458			compatible = "ti,edma3-tptc";
459			reg =	<0x238000 0x400>;
460			interrupts = <95>;
461			interrupt-names = "edm3_tcerrint";
462			power-domains = <&psc1 21>;
463		};
464		serial0: serial@42000 {
465			compatible = "ti,da830-uart", "ns16550a";
466			reg = <0x42000 0x100>;
467			reg-io-width = <4>;
468			reg-shift = <2>;
469			interrupts = <25>;
470			clocks = <&psc0 9>;
471			power-domains = <&psc0 9>;
472			status = "disabled";
473		};
474		serial1: serial@10c000 {
475			compatible = "ti,da830-uart", "ns16550a";
476			reg = <0x10c000 0x100>;
477			reg-io-width = <4>;
478			reg-shift = <2>;
479			interrupts = <53>;
480			clocks = <&psc1 12>;
481			power-domains = <&psc1 12>;
482			status = "disabled";
483		};
484		serial2: serial@10d000 {
485			compatible = "ti,da830-uart", "ns16550a";
486			reg = <0x10d000 0x100>;
487			reg-io-width = <4>;
488			reg-shift = <2>;
489			interrupts = <61>;
490			clocks = <&psc1 13>;
491			power-domains = <&psc1 13>;
492			status = "disabled";
493		};
494		rtc0: rtc@23000 {
495			compatible = "ti,da830-rtc";
496			reg = <0x23000 0x1000>;
497			interrupts = <19
498				      19>;
499			clocks = <&pll0_auxclk>;
500			clock-names = "int-clk";
501			status = "disabled";
502		};
503		i2c0: i2c@22000 {
504			compatible = "ti,davinci-i2c";
505			reg = <0x22000 0x1000>;
506			interrupts = <15>;
507			#address-cells = <1>;
508			#size-cells = <0>;
509			clocks = <&pll0_auxclk>;
510			status = "disabled";
511		};
512		i2c1: i2c@228000 {
513			compatible = "ti,davinci-i2c";
514			reg = <0x228000 0x1000>;
515			interrupts = <51>;
516			#address-cells = <1>;
517			#size-cells = <0>;
518			clocks = <&psc1 11>;
519			power-domains = <&psc1 11>;
520			status = "disabled";
521		};
522		clocksource: timer@20000 {
523			compatible = "ti,da830-timer";
524			reg = <0x20000 0x1000>;
525			interrupts = <21>, <22>;
526			interrupt-names = "tint12", "tint34";
527			clocks = <&pll0_auxclk>;
528		};
529		wdt: wdt@21000 {
530			compatible = "ti,davinci-wdt";
531			reg = <0x21000 0x1000>;
532			clocks = <&pll0_auxclk>;
533			status = "disabled";
534		};
535		mmc0: mmc@40000 {
536			compatible = "ti,da830-mmc";
537			reg = <0x40000 0x1000>;
538			cap-sd-highspeed;
539			cap-mmc-highspeed;
540			interrupts = <16>;
541			dmas = <&edma0 16 0>, <&edma0 17 0>;
542			dma-names = "rx", "tx";
543			clocks = <&psc0 5>;
544			status = "disabled";
545		};
546		vpif: video@217000 {
547			compatible = "ti,da850-vpif";
548			reg = <0x217000 0x1000>;
549			interrupts = <92>;
550			power-domains = <&psc1 9>;
551			status = "disabled";
552
553			/* VPIF capture port */
554			port@0 {
555				#address-cells = <1>;
556				#size-cells = <0>;
557			};
558
559			/* VPIF display port */
560			port@1 {
561				#address-cells = <1>;
562				#size-cells = <0>;
563			};
564		};
565		mmc1: mmc@21b000 {
566			compatible = "ti,da830-mmc";
567			reg = <0x21b000 0x1000>;
568			cap-sd-highspeed;
569			cap-mmc-highspeed;
570			interrupts = <72>;
571			dmas = <&edma1 28 0>, <&edma1 29 0>;
572			dma-names = "rx", "tx";
573			clocks = <&psc1 18>;
574			status = "disabled";
575		};
576		ehrpwm0: pwm@300000 {
577			compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm",
578				     "ti,am33xx-ehrpwm";
579			#pwm-cells = <3>;
580			reg = <0x300000 0x2000>;
581			clocks = <&psc1 17>, <&ehrpwm_tbclk>;
582			clock-names = "fck", "tbclk";
583			power-domains = <&psc1 17>;
584			status = "disabled";
585		};
586		ehrpwm1: pwm@302000 {
587			compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm",
588				     "ti,am33xx-ehrpwm";
589			#pwm-cells = <3>;
590			reg = <0x302000 0x2000>;
591			clocks = <&psc1 17>, <&ehrpwm_tbclk>;
592			clock-names = "fck", "tbclk";
593			power-domains = <&psc1 17>;
594			status = "disabled";
595		};
596		ecap0: ecap@306000 {
597			compatible = "ti,da850-ecap", "ti,am3352-ecap",
598				     "ti,am33xx-ecap";
599			#pwm-cells = <3>;
600			reg = <0x306000 0x80>;
601			clocks = <&psc1 20>;
602			clock-names = "fck";
603			power-domains = <&psc1 20>;
604			status = "disabled";
605		};
606		ecap1: ecap@307000 {
607			compatible = "ti,da850-ecap", "ti,am3352-ecap",
608				     "ti,am33xx-ecap";
609			#pwm-cells = <3>;
610			reg = <0x307000 0x80>;
611			clocks = <&psc1 20>;
612			clock-names = "fck";
613			power-domains = <&psc1 20>;
614			status = "disabled";
615		};
616		ecap2: ecap@308000 {
617			compatible = "ti,da850-ecap", "ti,am3352-ecap",
618				     "ti,am33xx-ecap";
619			#pwm-cells = <3>;
620			reg = <0x308000 0x80>;
621			clocks = <&psc1 20>;
622			clock-names = "fck";
623			power-domains = <&psc1 20>;
624			status = "disabled";
625		};
626		spi0: spi@41000 {
627			#address-cells = <1>;
628			#size-cells = <0>;
629			compatible = "ti,da830-spi";
630			reg = <0x41000 0x1000>;
631			num-cs = <6>;
632			ti,davinci-spi-intr-line = <1>;
633			interrupts = <20>;
634			dmas = <&edma0 14 0>, <&edma0 15 0>;
635			dma-names = "rx", "tx";
636			clocks = <&psc0 4>;
637			power-domains = <&psc0 4>;
638			status = "disabled";
639		};
640		spi1: spi@30e000 {
641			#address-cells = <1>;
642			#size-cells = <0>;
643			compatible = "ti,da830-spi";
644			reg = <0x30e000 0x1000>;
645			num-cs = <4>;
646			ti,davinci-spi-intr-line = <1>;
647			interrupts = <56>;
648			dmas = <&edma0 18 0>, <&edma0 19 0>;
649			dma-names = "rx", "tx";
650			clocks = <&psc1 10>;
651			power-domains = <&psc1 10>;
652			status = "disabled";
653		};
654		usb0: usb@200000 {
655			compatible = "ti,da830-musb";
656			reg = <0x200000 0x1000>;
657			ranges;
658			interrupts = <58>;
659			interrupt-names = "mc";
660			dr_mode = "otg";
661			phys = <&usb_phy 0>;
662			phy-names = "usb-phy";
663			clocks = <&psc1 1>;
664			clock-ranges;
665			status = "disabled";
666
667			#address-cells = <1>;
668			#size-cells = <1>;
669
670			dmas = <&cppi41dma 0 0 &cppi41dma 1 0
671				&cppi41dma 2 0 &cppi41dma 3 0
672				&cppi41dma 0 1 &cppi41dma 1 1
673				&cppi41dma 2 1 &cppi41dma 3 1>;
674			dma-names =
675				"rx1", "rx2", "rx3", "rx4",
676				"tx1", "tx2", "tx3", "tx4";
677
678			cppi41dma: dma-controller@201000 {
679				compatible = "ti,da830-cppi41";
680				reg =  <0x201000 0x1000
681					0x202000 0x1000
682					0x204000 0x4000>;
683				reg-names = "controller",
684					    "scheduler", "queuemgr";
685				interrupts = <58>;
686				#dma-cells = <2>;
687				#dma-channels = <4>;
688				power-domains = <&psc1 1>;
689				status = "okay";
690			};
691		};
692		sata: sata@218000 {
693			compatible = "ti,da850-ahci";
694			reg = <0x218000 0x2000>, <0x22c018 0x4>;
695			interrupts = <67>;
696			clocks = <&psc1 8>, <&sata_refclk>;
697			clock-names = "fck", "refclk";
698			status = "disabled";
699		};
700		pll1: clock-controller@21a000 {
701			compatible = "ti,da850-pll1";
702			reg = <0x21a000 0x1000>;
703			clocks = <&ref_clk>;
704			clock-names = "clksrc";
705
706			pll1_sysclk: sysclk {
707				#clock-cells = <1>;
708			};
709			pll1_obsclk: obsclk {
710				#clock-cells = <0>;
711			};
712		};
713		mdio: mdio@224000 {
714			compatible = "ti,davinci_mdio";
715			#address-cells = <1>;
716			#size-cells = <0>;
717			reg = <0x224000 0x1000>;
718			clocks = <&psc1 5>;
719			clock-names = "fck";
720			power-domains = <&psc1 5>;
721			status = "disabled";
722		};
723		eth0: ethernet@220000 {
724			compatible = "ti,davinci-dm6467-emac";
725			reg = <0x220000 0x4000>;
726			ti,davinci-ctrl-reg-offset = <0x3000>;
727			ti,davinci-ctrl-mod-reg-offset = <0x2000>;
728			ti,davinci-ctrl-ram-offset = <0>;
729			ti,davinci-ctrl-ram-size = <0x2000>;
730			local-mac-address = [ 00 00 00 00 00 00 ];
731			interrupts = <33
732					34
733					35
734					36
735					>;
736			clocks = <&psc1 5>;
737			power-domains = <&psc1 5>;
738			status = "disabled";
739		};
740		usb1: usb@225000 {
741			compatible = "ti,da830-ohci";
742			reg = <0x225000 0x1000>;
743			interrupts = <59>;
744			phys = <&usb_phy 1>;
745			phy-names = "usb-phy";
746			clocks = <&psc1 2>;
747			status = "disabled";
748		};
749		gpio: gpio@226000 {
750			compatible = "ti,dm6441-gpio";
751			gpio-controller;
752			#gpio-cells = <2>;
753			reg = <0x226000 0x1000>;
754			interrupts = <42 43 44 45 46 47 48 49 50>;
755			ti,ngpio = <144>;
756			ti,davinci-gpio-unbanked = <0>;
757			clocks = <&psc1 3>;
758			clock-names = "gpio";
759			status = "disabled";
760			interrupt-controller;
761			#interrupt-cells = <2>;
762			gpio-ranges = <&pmx_core   0  15 1>,
763				      <&pmx_core   1  14 1>,
764				      <&pmx_core   2  13 1>,
765				      <&pmx_core   3  12 1>,
766				      <&pmx_core   4  11 1>,
767				      <&pmx_core   5  10 1>,
768				      <&pmx_core   6   9 1>,
769				      <&pmx_core   7   8 1>,
770				      <&pmx_core   8   7 1>,
771				      <&pmx_core   9   6 1>,
772				      <&pmx_core  10   5 1>,
773				      <&pmx_core  11   4 1>,
774				      <&pmx_core  12   3 1>,
775				      <&pmx_core  13   2 1>,
776				      <&pmx_core  14   1 1>,
777				      <&pmx_core  15   0 1>,
778				      <&pmx_core  16  39 1>,
779				      <&pmx_core  17  38 1>,
780				      <&pmx_core  18  37 1>,
781				      <&pmx_core  19  36 1>,
782				      <&pmx_core  20  35 1>,
783				      <&pmx_core  21  34 1>,
784				      <&pmx_core  22  33 1>,
785				      <&pmx_core  23  32 1>,
786				      <&pmx_core  24  24 1>,
787				      <&pmx_core  25  22 1>,
788				      <&pmx_core  26  21 1>,
789				      <&pmx_core  27  20 1>,
790				      <&pmx_core  28  19 1>,
791				      <&pmx_core  29  18 1>,
792				      <&pmx_core  30  17 1>,
793				      <&pmx_core  31  16 1>,
794				      <&pmx_core  32  55 1>,
795				      <&pmx_core  33  54 1>,
796				      <&pmx_core  34  53 1>,
797				      <&pmx_core  35  52 1>,
798				      <&pmx_core  36  51 1>,
799				      <&pmx_core  37  50 1>,
800				      <&pmx_core  38  49 1>,
801				      <&pmx_core  39  48 1>,
802				      <&pmx_core  40  47 1>,
803				      <&pmx_core  41  46 1>,
804				      <&pmx_core  42  45 1>,
805				      <&pmx_core  43  44 1>,
806				      <&pmx_core  44  43 1>,
807				      <&pmx_core  45  42 1>,
808				      <&pmx_core  46  41 1>,
809				      <&pmx_core  47  40 1>,
810				      <&pmx_core  48  71 1>,
811				      <&pmx_core  49  70 1>,
812				      <&pmx_core  50  69 1>,
813				      <&pmx_core  51  68 1>,
814				      <&pmx_core  52  67 1>,
815				      <&pmx_core  53  66 1>,
816				      <&pmx_core  54  65 1>,
817				      <&pmx_core  55  64 1>,
818				      <&pmx_core  56  63 1>,
819				      <&pmx_core  57  62 1>,
820				      <&pmx_core  58  61 1>,
821				      <&pmx_core  59  60 1>,
822				      <&pmx_core  60  59 1>,
823				      <&pmx_core  61  58 1>,
824				      <&pmx_core  62  57 1>,
825				      <&pmx_core  63  56 1>,
826				      <&pmx_core  64  87 1>,
827				      <&pmx_core  65  86 1>,
828				      <&pmx_core  66  85 1>,
829				      <&pmx_core  67  84 1>,
830				      <&pmx_core  68  83 1>,
831				      <&pmx_core  69  82 1>,
832				      <&pmx_core  70  81 1>,
833				      <&pmx_core  71  80 1>,
834				      <&pmx_core  72  70 1>,
835				      <&pmx_core  73  78 1>,
836				      <&pmx_core  74  77 1>,
837				      <&pmx_core  75  76 1>,
838				      <&pmx_core  76  75 1>,
839				      <&pmx_core  77  74 1>,
840				      <&pmx_core  78  73 1>,
841				      <&pmx_core  79  72 1>,
842				      <&pmx_core  80 103 1>,
843				      <&pmx_core  81 102 1>,
844				      <&pmx_core  82 101 1>,
845				      <&pmx_core  83 100 1>,
846				      <&pmx_core  84  99 1>,
847				      <&pmx_core  85  98 1>,
848				      <&pmx_core  86  97 1>,
849				      <&pmx_core  87  96 1>,
850				      <&pmx_core  88  95 1>,
851				      <&pmx_core  89  94 1>,
852				      <&pmx_core  90  93 1>,
853				      <&pmx_core  91  92 1>,
854				      <&pmx_core  92  91 1>,
855				      <&pmx_core  93  90 1>,
856				      <&pmx_core  94  89 1>,
857				      <&pmx_core  95  88 1>,
858				      <&pmx_core  96 158 1>,
859				      <&pmx_core  97 157 1>,
860				      <&pmx_core  98 156 1>,
861				      <&pmx_core  99 155 1>,
862				      <&pmx_core 100 154 1>,
863				      <&pmx_core 101 129 1>,
864				      <&pmx_core 102 113 1>,
865				      <&pmx_core 103 112 1>,
866				      <&pmx_core 104 111 1>,
867				      <&pmx_core 105 110 1>,
868				      <&pmx_core 106 109 1>,
869				      <&pmx_core 107 108 1>,
870				      <&pmx_core 108 107 1>,
871				      <&pmx_core 109 106 1>,
872				      <&pmx_core 110 105 1>,
873				      <&pmx_core 111 104 1>,
874				      <&pmx_core 112 145 1>,
875				      <&pmx_core 113 144 1>,
876				      <&pmx_core 114 143 1>,
877				      <&pmx_core 115 142 1>,
878				      <&pmx_core 116 141 1>,
879				      <&pmx_core 117 140 1>,
880				      <&pmx_core 118 139 1>,
881				      <&pmx_core 119 138 1>,
882				      <&pmx_core 120 137 1>,
883				      <&pmx_core 121 136 1>,
884				      <&pmx_core 122 135 1>,
885				      <&pmx_core 123 134 1>,
886				      <&pmx_core 124 133 1>,
887				      <&pmx_core 125 132 1>,
888				      <&pmx_core 126 131 1>,
889				      <&pmx_core 127 130 1>,
890				      <&pmx_core 128 159 1>,
891				      <&pmx_core 129  31 1>,
892				      <&pmx_core 130  30 1>,
893				      <&pmx_core 131  20 1>,
894				      <&pmx_core 132  28 1>,
895				      <&pmx_core 133  27 1>,
896				      <&pmx_core 134  26 1>,
897				      <&pmx_core 135  23 1>,
898				      <&pmx_core 136 153 1>,
899				      <&pmx_core 137 152 1>,
900				      <&pmx_core 138 151 1>,
901				      <&pmx_core 139 150 1>,
902				      <&pmx_core 140 149 1>,
903				      <&pmx_core 141 148 1>,
904				      <&pmx_core 142 147 1>,
905				      <&pmx_core 143 146 1>;
906		};
907		psc1: clock-controller@227000 {
908			compatible = "ti,da850-psc1";
909			reg = <0x227000 0x1000>;
910			#clock-cells = <1>;
911			#power-domain-cells = <1>;
912			clocks = <&pll0_sysclk 2>, <&pll0_sysclk 4>,
913				 <&async3_clk>;
914			clock-names = "pll0_sysclk2", "pll0_sysclk4", "async3";
915			assigned-clocks = <&async3_clk>;
916			assigned-clock-parents = <&pll1_sysclk 2>;
917		};
918		pinconf: pin-controller@22c00c {
919			compatible = "ti,da850-pupd";
920			reg = <0x22c00c 0x8>;
921			status = "disabled";
922		};
923
924		mcasp0: mcasp@100000 {
925			compatible = "ti,da830-mcasp-audio";
926			reg = <0x100000 0x2000>,
927			      <0x102000 0x400000>;
928			reg-names = "mpu", "dat";
929			interrupts = <54>;
930			interrupt-names = "common";
931			power-domains = <&psc1 7>;
932			status = "disabled";
933			dmas = <&edma0 1 1>,
934				<&edma0 0 1>;
935			dma-names = "tx", "rx";
936		};
937
938		lcdc: display@213000 {
939			compatible = "ti,da850-tilcdc";
940			reg = <0x213000 0x1000>;
941			interrupts = <52>;
942			max-pixelclock = <37500>;
943			clocks = <&psc1 16>;
944			clock-names = "fck";
945			power-domains = <&psc1 16>;
946			status = "disabled";
947		};
948	};
949	aemif: aemif@68000000 {
950		compatible = "ti,da850-aemif";
951		#address-cells = <2>;
952		#size-cells = <1>;
953
954		reg = <0x68000000 0x00008000>;
955		ranges = <0 0 0x60000000 0x08000000
956			  1 0 0x68000000 0x00008000>;
957		clocks = <&psc0 3>;
958		clock-names = "aemif";
959		clock-ranges;
960		status = "disabled";
961	};
962	memctrl: memory-controller@b0000000 {
963		compatible = "ti,da850-ddr-controller";
964		reg = <0xb0000000 0xe8>;
965		status = "disabled";
966	};
967};
968