1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/
4 *
5 * Based on "omap4.dtsi"
6 */
7
8#include "dra7.dtsi"
9
10/ {
11	compatible = "ti,dra742", "ti,dra74", "ti,dra7";
12
13	cpus {
14		cpu@1 {
15			device_type = "cpu";
16			compatible = "arm,cortex-a15";
17			reg = <1>;
18			operating-points-v2 = <&cpu0_opp_table>;
19
20			clocks = <&dpll_mpu_ck>;
21			clock-names = "cpu";
22
23			clock-latency = <300000>; /* From omap-cpufreq driver */
24
25			/* cooling options */
26			#cooling-cells = <2>; /* min followed by max */
27
28			vbb-supply = <&abb_mpu>;
29		};
30	};
31
32	aliases {
33		rproc0 = &ipu1;
34		rproc1 = &ipu2;
35		rproc2 = &dsp1;
36		rproc3 = &dsp2;
37	};
38
39	pmu {
40		compatible = "arm,cortex-a15-pmu";
41		interrupt-parent = <&wakeupgen>;
42		interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
43			     <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
44	};
45
46	ocp {
47		dsp2_system: dsp_system@41500000 {
48			compatible = "syscon";
49			reg = <0x41500000 0x100>;
50		};
51
52		target-module@48940000 {
53			compatible = "ti,sysc-omap4", "ti,sysc";
54			reg = <0x48940000 0x4>,
55			      <0x48940010 0x4>;
56			reg-names = "rev", "sysc";
57			ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>;
58			ti,sysc-midle = <SYSC_IDLE_FORCE>,
59					<SYSC_IDLE_NO>,
60					<SYSC_IDLE_SMART>,
61					<SYSC_IDLE_SMART_WKUP>;
62			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
63					<SYSC_IDLE_NO>,
64					<SYSC_IDLE_SMART>,
65					<SYSC_IDLE_SMART_WKUP>;
66			clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS4_CLKCTRL 0>;
67			clock-names = "fck";
68			#address-cells = <1>;
69			#size-cells = <1>;
70			ranges = <0x0 0x48940000 0x20000>;
71
72			omap_dwc3_4: omap_dwc3_4@0 {
73				compatible = "ti,dwc3";
74				reg = <0 0x10000>;
75				interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
76				#address-cells = <1>;
77				#size-cells = <1>;
78				utmi-mode = <2>;
79				ranges;
80				status = "disabled";
81				usb4: usb@10000 {
82					compatible = "snps,dwc3";
83					reg = <0x10000 0x17000>;
84					interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
85						     <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
86						     <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
87					interrupt-names = "peripheral",
88							  "host",
89							  "otg";
90					maximum-speed = "high-speed";
91					dr_mode = "otg";
92				};
93			};
94		};
95
96		target-module@41501000 {
97			compatible = "ti,sysc-omap2", "ti,sysc";
98			reg = <0x41501000 0x4>,
99			      <0x41501010 0x4>,
100			      <0x41501014 0x4>;
101			reg-names = "rev", "sysc", "syss";
102			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
103					<SYSC_IDLE_NO>,
104					<SYSC_IDLE_SMART>;
105			ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
106					 SYSC_OMAP2_SOFTRESET |
107					 SYSC_OMAP2_AUTOIDLE)>;
108			clocks = <&dsp2_clkctrl DRA7_DSP2_MMU0_DSP2_CLKCTRL 0>;
109			clock-names = "fck";
110			resets = <&prm_dsp2 1>;
111			reset-names = "rstctrl";
112			ranges = <0x0 0x41501000 0x1000>;
113			#size-cells = <1>;
114			#address-cells = <1>;
115
116			mmu0_dsp2: mmu@0 {
117				compatible = "ti,dra7-dsp-iommu";
118				reg = <0x0 0x100>;
119				interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
120				#iommu-cells = <0>;
121				ti,syscon-mmuconfig = <&dsp2_system 0x0>;
122			};
123		};
124
125		target-module@41502000 {
126			compatible = "ti,sysc-omap2", "ti,sysc";
127			reg = <0x41502000 0x4>,
128			      <0x41502010 0x4>,
129			      <0x41502014 0x4>;
130			reg-names = "rev", "sysc", "syss";
131			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
132					<SYSC_IDLE_NO>,
133					<SYSC_IDLE_SMART>;
134			ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
135					 SYSC_OMAP2_SOFTRESET |
136					 SYSC_OMAP2_AUTOIDLE)>;
137
138			clocks = <&dsp2_clkctrl DRA7_DSP2_MMU0_DSP2_CLKCTRL 0>;
139			clock-names = "fck";
140			resets = <&prm_dsp2 1>;
141			reset-names = "rstctrl";
142			ranges = <0x0 0x41502000 0x1000>;
143			#size-cells = <1>;
144			#address-cells = <1>;
145
146			mmu1_dsp2: mmu@0 {
147				compatible = "ti,dra7-dsp-iommu";
148				reg = <0x0 0x100>;
149				interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
150				#iommu-cells = <0>;
151				ti,syscon-mmuconfig = <&dsp2_system 0x1>;
152			};
153		};
154
155		dsp2: dsp@41000000 {
156			compatible = "ti,dra7-dsp";
157			reg = <0x41000000 0x48000>,
158			      <0x41600000 0x8000>,
159			      <0x41700000 0x8000>;
160			reg-names = "l2ram", "l1pram", "l1dram";
161			ti,bootreg = <&scm_conf 0x560 10>;
162			iommus = <&mmu0_dsp2>, <&mmu1_dsp2>;
163			status = "disabled";
164			resets = <&prm_dsp2 0>;
165			clocks = <&dsp2_clkctrl DRA7_DSP2_MMU0_DSP2_CLKCTRL 0>;
166			firmware-name = "dra7-dsp2-fw.xe66";
167		};
168	};
169};
170
171&cpu0_opp_table {
172	opp-shared;
173};
174
175&dss {
176	reg = <0 0x80>,
177	      <0x4054 0x4>,
178	      <0x4300 0x20>,
179	      <0x9054 0x4>,
180	      <0x9300 0x20>;
181	reg-names = "dss", "pll1_clkctrl", "pll1",
182		    "pll2_clkctrl", "pll2";
183
184	clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>,
185		 <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 12>,
186		 <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 13>;
187	clock-names = "fck", "video1_clk", "video2_clk";
188};
189
190&mailbox5 {
191	mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
192		ti,mbox-tx = <6 2 2>;
193		ti,mbox-rx = <4 2 2>;
194		status = "disabled";
195	};
196	mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
197		ti,mbox-tx = <5 2 2>;
198		ti,mbox-rx = <1 2 2>;
199		status = "disabled";
200	};
201};
202
203&mailbox6 {
204	mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
205		ti,mbox-tx = <6 2 2>;
206		ti,mbox-rx = <4 2 2>;
207		status = "disabled";
208	};
209	mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
210		ti,mbox-tx = <5 2 2>;
211		ti,mbox-rx = <1 2 2>;
212		status = "disabled";
213	};
214};
215
216&pcie1_rc {
217	compatible = "ti,dra746-pcie-rc", "ti,dra7-pcie";
218};
219
220&pcie1_ep {
221	compatible = "ti,dra746-pcie-ep", "ti,dra7-pcie-ep";
222};
223
224&pcie2_rc {
225	compatible = "ti,dra746-pcie-rc", "ti,dra7-pcie";
226};
227