1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Samsung Exynos5250 SoC device tree source 4 * 5 * Copyright (c) 2012 Samsung Electronics Co., Ltd. 6 * http://www.samsung.com 7 * 8 * Samsung Exynos5250 SoC device nodes are listed in this file. 9 * Exynos5250 based board files can include this file and provide 10 * values for board specfic bindings. 11 * 12 * Note: This file does not include device nodes for all the controllers in 13 * Exynos5250 SoC. As device tree coverage for Exynos5250 increases, 14 * additional nodes can be added to this file. 15 */ 16 17#include <dt-bindings/clock/exynos5250.h> 18#include "exynos5.dtsi" 19#include "exynos4-cpu-thermal.dtsi" 20#include <dt-bindings/clock/exynos-audss-clk.h> 21 22/ { 23 compatible = "samsung,exynos5250", "samsung,exynos5"; 24 25 aliases { 26 spi0 = &spi_0; 27 spi1 = &spi_1; 28 spi2 = &spi_2; 29 gsc0 = &gsc_0; 30 gsc1 = &gsc_1; 31 gsc2 = &gsc_2; 32 gsc3 = &gsc_3; 33 mshc0 = &mmc_0; 34 mshc1 = &mmc_1; 35 mshc2 = &mmc_2; 36 mshc3 = &mmc_3; 37 i2c4 = &i2c_4; 38 i2c5 = &i2c_5; 39 i2c6 = &i2c_6; 40 i2c7 = &i2c_7; 41 i2c8 = &i2c_8; 42 i2c9 = &i2c_9; 43 pinctrl0 = &pinctrl_0; 44 pinctrl1 = &pinctrl_1; 45 pinctrl2 = &pinctrl_2; 46 pinctrl3 = &pinctrl_3; 47 }; 48 49 cpus { 50 #address-cells = <1>; 51 #size-cells = <0>; 52 53 cpu0: cpu@0 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-a15"; 56 reg = <0>; 57 clocks = <&clock CLK_ARM_CLK>; 58 clock-names = "cpu"; 59 operating-points-v2 = <&cpu0_opp_table>; 60 #cooling-cells = <2>; /* min followed by max */ 61 }; 62 cpu1: cpu@1 { 63 device_type = "cpu"; 64 compatible = "arm,cortex-a15"; 65 reg = <1>; 66 clocks = <&clock CLK_ARM_CLK>; 67 clock-names = "cpu"; 68 operating-points-v2 = <&cpu0_opp_table>; 69 #cooling-cells = <2>; /* min followed by max */ 70 }; 71 }; 72 73 cpu0_opp_table: opp-table0 { 74 compatible = "operating-points-v2"; 75 opp-shared; 76 77 opp-200000000 { 78 opp-hz = /bits/ 64 <200000000>; 79 opp-microvolt = <925000>; 80 clock-latency-ns = <140000>; 81 }; 82 opp-300000000 { 83 opp-hz = /bits/ 64 <300000000>; 84 opp-microvolt = <937500>; 85 clock-latency-ns = <140000>; 86 }; 87 opp-400000000 { 88 opp-hz = /bits/ 64 <400000000>; 89 opp-microvolt = <950000>; 90 clock-latency-ns = <140000>; 91 }; 92 opp-500000000 { 93 opp-hz = /bits/ 64 <500000000>; 94 opp-microvolt = <975000>; 95 clock-latency-ns = <140000>; 96 }; 97 opp-600000000 { 98 opp-hz = /bits/ 64 <600000000>; 99 opp-microvolt = <1000000>; 100 clock-latency-ns = <140000>; 101 }; 102 opp-700000000 { 103 opp-hz = /bits/ 64 <700000000>; 104 opp-microvolt = <1012500>; 105 clock-latency-ns = <140000>; 106 }; 107 opp-800000000 { 108 opp-hz = /bits/ 64 <800000000>; 109 opp-microvolt = <1025000>; 110 clock-latency-ns = <140000>; 111 }; 112 opp-900000000 { 113 opp-hz = /bits/ 64 <900000000>; 114 opp-microvolt = <1050000>; 115 clock-latency-ns = <140000>; 116 }; 117 opp-1000000000 { 118 opp-hz = /bits/ 64 <1000000000>; 119 opp-microvolt = <1075000>; 120 clock-latency-ns = <140000>; 121 opp-suspend; 122 }; 123 opp-1100000000 { 124 opp-hz = /bits/ 64 <1100000000>; 125 opp-microvolt = <1100000>; 126 clock-latency-ns = <140000>; 127 }; 128 opp-1200000000 { 129 opp-hz = /bits/ 64 <1200000000>; 130 opp-microvolt = <1125000>; 131 clock-latency-ns = <140000>; 132 }; 133 opp-1300000000 { 134 opp-hz = /bits/ 64 <1300000000>; 135 opp-microvolt = <1150000>; 136 clock-latency-ns = <140000>; 137 }; 138 opp-1400000000 { 139 opp-hz = /bits/ 64 <1400000000>; 140 opp-microvolt = <1200000>; 141 clock-latency-ns = <140000>; 142 }; 143 opp-1500000000 { 144 opp-hz = /bits/ 64 <1500000000>; 145 opp-microvolt = <1225000>; 146 clock-latency-ns = <140000>; 147 }; 148 opp-1600000000 { 149 opp-hz = /bits/ 64 <1600000000>; 150 opp-microvolt = <1250000>; 151 clock-latency-ns = <140000>; 152 }; 153 opp-1700000000 { 154 opp-hz = /bits/ 64 <1700000000>; 155 opp-microvolt = <1300000>; 156 clock-latency-ns = <140000>; 157 }; 158 }; 159 160 pmu { 161 compatible = "arm,cortex-a15-pmu"; 162 interrupt-parent = <&combiner>; 163 interrupts = <1 2>, <22 4>; 164 }; 165 166 soc: soc { 167 sram@2020000 { 168 compatible = "mmio-sram"; 169 reg = <0x02020000 0x30000>; 170 #address-cells = <1>; 171 #size-cells = <1>; 172 ranges = <0 0x02020000 0x30000>; 173 174 smp-sram@0 { 175 compatible = "samsung,exynos4210-sysram"; 176 reg = <0x0 0x1000>; 177 }; 178 179 smp-sram@2f000 { 180 compatible = "samsung,exynos4210-sysram-ns"; 181 reg = <0x2f000 0x1000>; 182 }; 183 }; 184 185 pd_gsc: power-domain@10044000 { 186 compatible = "samsung,exynos4210-pd"; 187 reg = <0x10044000 0x20>; 188 #power-domain-cells = <0>; 189 label = "GSC"; 190 }; 191 192 pd_mfc: power-domain@10044040 { 193 compatible = "samsung,exynos4210-pd"; 194 reg = <0x10044040 0x20>; 195 #power-domain-cells = <0>; 196 label = "MFC"; 197 }; 198 199 pd_g3d: power-domain@10044060 { 200 compatible = "samsung,exynos4210-pd"; 201 reg = <0x10044060 0x20>; 202 #power-domain-cells = <0>; 203 label = "G3D"; 204 }; 205 206 pd_disp1: power-domain@100440a0 { 207 compatible = "samsung,exynos4210-pd"; 208 reg = <0x100440A0 0x20>; 209 #power-domain-cells = <0>; 210 label = "DISP1"; 211 }; 212 213 pd_mau: power-domain@100440c0 { 214 compatible = "samsung,exynos4210-pd"; 215 reg = <0x100440C0 0x20>; 216 #power-domain-cells = <0>; 217 label = "MAU"; 218 }; 219 220 clock: clock-controller@10010000 { 221 compatible = "samsung,exynos5250-clock"; 222 reg = <0x10010000 0x30000>; 223 #clock-cells = <1>; 224 }; 225 226 clock_audss: audss-clock-controller@3810000 { 227 compatible = "samsung,exynos5250-audss-clock"; 228 reg = <0x03810000 0x0C>; 229 #clock-cells = <1>; 230 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>, 231 <&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>; 232 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in"; 233 power-domains = <&pd_mau>; 234 }; 235 236 timer@101c0000 { 237 compatible = "samsung,exynos4210-mct"; 238 reg = <0x101C0000 0x800>; 239 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; 240 clock-names = "fin_pll", "mct"; 241 interrupts-extended = <&combiner 23 3>, 242 <&combiner 23 4>, 243 <&combiner 25 2>, 244 <&combiner 25 3>, 245 <&gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 246 <&gic GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 247 }; 248 249 pinctrl_0: pinctrl@11400000 { 250 compatible = "samsung,exynos5250-pinctrl"; 251 reg = <0x11400000 0x1000>; 252 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 253 254 wakup_eint: wakeup-interrupt-controller { 255 compatible = "samsung,exynos4210-wakeup-eint"; 256 interrupt-parent = <&gic>; 257 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 258 }; 259 }; 260 261 pinctrl_1: pinctrl@13400000 { 262 compatible = "samsung,exynos5250-pinctrl"; 263 reg = <0x13400000 0x1000>; 264 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 265 }; 266 267 pinctrl_2: pinctrl@10d10000 { 268 compatible = "samsung,exynos5250-pinctrl"; 269 reg = <0x10d10000 0x1000>; 270 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 271 }; 272 273 pinctrl_3: pinctrl@3860000 { 274 compatible = "samsung,exynos5250-pinctrl"; 275 reg = <0x03860000 0x1000>; 276 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 277 power-domains = <&pd_mau>; 278 }; 279 280 pmu_system_controller: system-controller@10040000 { 281 compatible = "samsung,exynos5250-pmu", "syscon"; 282 reg = <0x10040000 0x5000>; 283 clock-names = "clkout16"; 284 clocks = <&clock CLK_FIN_PLL>; 285 #clock-cells = <1>; 286 interrupt-controller; 287 #interrupt-cells = <3>; 288 interrupt-parent = <&gic>; 289 }; 290 291 watchdog@101d0000 { 292 compatible = "samsung,exynos5250-wdt"; 293 reg = <0x101D0000 0x100>; 294 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 295 clocks = <&clock CLK_WDT>; 296 clock-names = "watchdog"; 297 samsung,syscon-phandle = <&pmu_system_controller>; 298 }; 299 300 mfc: codec@11000000 { 301 compatible = "samsung,mfc-v6"; 302 reg = <0x11000000 0x10000>; 303 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 304 power-domains = <&pd_mfc>; 305 clocks = <&clock CLK_MFC>; 306 clock-names = "mfc"; 307 iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>; 308 iommu-names = "left", "right"; 309 }; 310 311 rotator: rotator@11c00000 { 312 compatible = "samsung,exynos5250-rotator"; 313 reg = <0x11C00000 0x64>; 314 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 315 clocks = <&clock CLK_ROTATOR>; 316 clock-names = "rotator"; 317 iommus = <&sysmmu_rotator>; 318 }; 319 320 mali: gpu@11800000 { 321 compatible = "samsung,exynos5250-mali", "arm,mali-t604"; 322 reg = <0x11800000 0x5000>; 323 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 324 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 325 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 326 interrupt-names = "job", "mmu", "gpu"; 327 clocks = <&clock CLK_G3D>; 328 clock-names = "core"; 329 operating-points-v2 = <&gpu_opp_table>; 330 power-domains = <&pd_g3d>; 331 status = "disabled"; 332 333 gpu_opp_table: opp-table { 334 compatible = "operating-points-v2"; 335 336 opp-100000000 { 337 opp-hz = /bits/ 64 <100000000>; 338 opp-microvolt = <925000>; 339 }; 340 opp-160000000 { 341 opp-hz = /bits/ 64 <160000000>; 342 opp-microvolt = <925000>; 343 }; 344 opp-266000000 { 345 opp-hz = /bits/ 64 <266000000>; 346 opp-microvolt = <1025000>; 347 }; 348 opp-350000000 { 349 opp-hz = /bits/ 64 <350000000>; 350 opp-microvolt = <1075000>; 351 }; 352 opp-400000000 { 353 opp-hz = /bits/ 64 <400000000>; 354 opp-microvolt = <1125000>; 355 }; 356 opp-450000000 { 357 opp-hz = /bits/ 64 <450000000>; 358 opp-microvolt = <1150000>; 359 }; 360 opp-533000000 { 361 opp-hz = /bits/ 64 <533000000>; 362 opp-microvolt = <1250000>; 363 }; 364 }; 365 }; 366 367 tmu: tmu@10060000 { 368 compatible = "samsung,exynos5250-tmu"; 369 reg = <0x10060000 0x100>; 370 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 371 clocks = <&clock CLK_TMU>; 372 clock-names = "tmu_apbif"; 373 #thermal-sensor-cells = <0>; 374 }; 375 376 sata: sata@122f0000 { 377 compatible = "snps,dwc-ahci"; 378 samsung,sata-freq = <66>; 379 reg = <0x122F0000 0x1ff>; 380 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 381 clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>; 382 clock-names = "sata", "sclk_sata"; 383 phys = <&sata_phy>; 384 phy-names = "sata-phy"; 385 ports-implemented = <0x1>; 386 status = "disabled"; 387 }; 388 389 sata_phy: sata-phy@12170000 { 390 compatible = "samsung,exynos5250-sata-phy"; 391 reg = <0x12170000 0x1ff>; 392 clocks = <&clock CLK_SATA_PHYCTRL>; 393 clock-names = "sata_phyctrl"; 394 #phy-cells = <0>; 395 samsung,syscon-phandle = <&pmu_system_controller>; 396 status = "disabled"; 397 }; 398 399 /* i2c_0-3 are defined in exynos5.dtsi */ 400 i2c_4: i2c@12ca0000 { 401 compatible = "samsung,s3c2440-i2c"; 402 reg = <0x12CA0000 0x100>; 403 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 404 #address-cells = <1>; 405 #size-cells = <0>; 406 clocks = <&clock CLK_I2C4>; 407 clock-names = "i2c"; 408 pinctrl-names = "default"; 409 pinctrl-0 = <&i2c4_bus>; 410 status = "disabled"; 411 }; 412 413 i2c_5: i2c@12cb0000 { 414 compatible = "samsung,s3c2440-i2c"; 415 reg = <0x12CB0000 0x100>; 416 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 417 #address-cells = <1>; 418 #size-cells = <0>; 419 clocks = <&clock CLK_I2C5>; 420 clock-names = "i2c"; 421 pinctrl-names = "default"; 422 pinctrl-0 = <&i2c5_bus>; 423 status = "disabled"; 424 }; 425 426 i2c_6: i2c@12cc0000 { 427 compatible = "samsung,s3c2440-i2c"; 428 reg = <0x12CC0000 0x100>; 429 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 430 #address-cells = <1>; 431 #size-cells = <0>; 432 clocks = <&clock CLK_I2C6>; 433 clock-names = "i2c"; 434 pinctrl-names = "default"; 435 pinctrl-0 = <&i2c6_bus>; 436 status = "disabled"; 437 }; 438 439 i2c_7: i2c@12cd0000 { 440 compatible = "samsung,s3c2440-i2c"; 441 reg = <0x12CD0000 0x100>; 442 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 443 #address-cells = <1>; 444 #size-cells = <0>; 445 clocks = <&clock CLK_I2C7>; 446 clock-names = "i2c"; 447 pinctrl-names = "default"; 448 pinctrl-0 = <&i2c7_bus>; 449 status = "disabled"; 450 }; 451 452 i2c_8: i2c@12ce0000 { 453 compatible = "samsung,s3c2440-hdmiphy-i2c"; 454 reg = <0x12CE0000 0x1000>; 455 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 456 #address-cells = <1>; 457 #size-cells = <0>; 458 clocks = <&clock CLK_I2C_HDMI>; 459 clock-names = "i2c"; 460 status = "disabled"; 461 462 hdmiphy: hdmiphy@38 { 463 compatible = "samsung,exynos4212-hdmiphy"; 464 reg = <0x38>; 465 }; 466 }; 467 468 i2c_9: i2c@121d0000 { 469 compatible = "samsung,exynos5-sata-phy-i2c"; 470 reg = <0x121D0000 0x100>; 471 #address-cells = <1>; 472 #size-cells = <0>; 473 clocks = <&clock CLK_SATA_PHYI2C>; 474 clock-names = "i2c"; 475 status = "disabled"; 476 477 sata_phy_i2c: sata-phy-i2c@38 { 478 compatible = "samsung,exynos-sataphy-i2c"; 479 reg = <0x38>; 480 status = "disabled"; 481 }; 482 }; 483 484 spi_0: spi@12d20000 { 485 compatible = "samsung,exynos4210-spi"; 486 status = "disabled"; 487 reg = <0x12d20000 0x100>; 488 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 489 dmas = <&pdma0 5 490 &pdma0 4>; 491 dma-names = "tx", "rx"; 492 #address-cells = <1>; 493 #size-cells = <0>; 494 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>; 495 clock-names = "spi", "spi_busclk0"; 496 pinctrl-names = "default"; 497 pinctrl-0 = <&spi0_bus>; 498 }; 499 500 spi_1: spi@12d30000 { 501 compatible = "samsung,exynos4210-spi"; 502 status = "disabled"; 503 reg = <0x12d30000 0x100>; 504 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 505 dmas = <&pdma1 5 506 &pdma1 4>; 507 dma-names = "tx", "rx"; 508 #address-cells = <1>; 509 #size-cells = <0>; 510 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>; 511 clock-names = "spi", "spi_busclk0"; 512 pinctrl-names = "default"; 513 pinctrl-0 = <&spi1_bus>; 514 }; 515 516 spi_2: spi@12d40000 { 517 compatible = "samsung,exynos4210-spi"; 518 status = "disabled"; 519 reg = <0x12d40000 0x100>; 520 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 521 dmas = <&pdma0 7 522 &pdma0 6>; 523 dma-names = "tx", "rx"; 524 #address-cells = <1>; 525 #size-cells = <0>; 526 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>; 527 clock-names = "spi", "spi_busclk0"; 528 pinctrl-names = "default"; 529 pinctrl-0 = <&spi2_bus>; 530 }; 531 532 mmc_0: mmc@12200000 { 533 compatible = "samsung,exynos5250-dw-mshc"; 534 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 535 #address-cells = <1>; 536 #size-cells = <0>; 537 reg = <0x12200000 0x1000>; 538 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>; 539 clock-names = "biu", "ciu"; 540 fifo-depth = <0x80>; 541 status = "disabled"; 542 }; 543 544 mmc_1: mmc@12210000 { 545 compatible = "samsung,exynos5250-dw-mshc"; 546 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 547 #address-cells = <1>; 548 #size-cells = <0>; 549 reg = <0x12210000 0x1000>; 550 clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>; 551 clock-names = "biu", "ciu"; 552 fifo-depth = <0x80>; 553 status = "disabled"; 554 }; 555 556 mmc_2: mmc@12220000 { 557 compatible = "samsung,exynos5250-dw-mshc"; 558 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 559 #address-cells = <1>; 560 #size-cells = <0>; 561 reg = <0x12220000 0x1000>; 562 clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>; 563 clock-names = "biu", "ciu"; 564 fifo-depth = <0x80>; 565 status = "disabled"; 566 }; 567 568 mmc_3: mmc@12230000 { 569 compatible = "samsung,exynos5250-dw-mshc"; 570 reg = <0x12230000 0x1000>; 571 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 572 #address-cells = <1>; 573 #size-cells = <0>; 574 clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>; 575 clock-names = "biu", "ciu"; 576 fifo-depth = <0x80>; 577 status = "disabled"; 578 }; 579 580 i2s0: i2s@3830000 { 581 compatible = "samsung,s5pv210-i2s"; 582 status = "disabled"; 583 reg = <0x03830000 0x100>; 584 dmas = <&pdma0 10>, 585 <&pdma0 9>, 586 <&pdma0 8>; 587 dma-names = "tx", "rx", "tx-sec"; 588 clocks = <&clock_audss EXYNOS_I2S_BUS>, 589 <&clock_audss EXYNOS_I2S_BUS>, 590 <&clock_audss EXYNOS_SCLK_I2S>; 591 clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; 592 samsung,idma-addr = <0x03000000>; 593 pinctrl-names = "default"; 594 pinctrl-0 = <&i2s0_bus>; 595 power-domains = <&pd_mau>; 596 #clock-cells = <1>; 597 #sound-dai-cells = <1>; 598 }; 599 600 i2s1: i2s@12d60000 { 601 compatible = "samsung,s3c6410-i2s"; 602 status = "disabled"; 603 reg = <0x12D60000 0x100>; 604 dmas = <&pdma1 12>, 605 <&pdma1 11>; 606 dma-names = "tx", "rx"; 607 clocks = <&clock CLK_I2S1>, <&clock CLK_DIV_I2S1>; 608 clock-names = "iis", "i2s_opclk0"; 609 pinctrl-names = "default"; 610 pinctrl-0 = <&i2s1_bus>; 611 power-domains = <&pd_mau>; 612 #sound-dai-cells = <1>; 613 }; 614 615 i2s2: i2s@12d70000 { 616 compatible = "samsung,s3c6410-i2s"; 617 status = "disabled"; 618 reg = <0x12D70000 0x100>; 619 dmas = <&pdma0 12>, 620 <&pdma0 11>; 621 dma-names = "tx", "rx"; 622 clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>; 623 clock-names = "iis", "i2s_opclk0"; 624 pinctrl-names = "default"; 625 pinctrl-0 = <&i2s2_bus>; 626 power-domains = <&pd_mau>; 627 #sound-dai-cells = <1>; 628 }; 629 630 usb_dwc3 { 631 compatible = "samsung,exynos5250-dwusb3"; 632 clocks = <&clock CLK_USB3>; 633 clock-names = "usbdrd30"; 634 #address-cells = <1>; 635 #size-cells = <1>; 636 ranges; 637 638 usbdrd_dwc3: usb@12000000 { 639 compatible = "snps,dwc3"; 640 reg = <0x12000000 0x10000>; 641 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 642 phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>; 643 phy-names = "usb2-phy", "usb3-phy"; 644 }; 645 }; 646 647 usbdrd_phy: phy@12100000 { 648 compatible = "samsung,exynos5250-usbdrd-phy"; 649 reg = <0x12100000 0x100>; 650 clocks = <&clock CLK_USB3>, <&clock CLK_FIN_PLL>; 651 clock-names = "phy", "ref"; 652 samsung,pmu-syscon = <&pmu_system_controller>; 653 #phy-cells = <1>; 654 }; 655 656 ehci: usb@12110000 { 657 compatible = "samsung,exynos4210-ehci"; 658 reg = <0x12110000 0x100>; 659 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 660 661 clocks = <&clock CLK_USB2>; 662 clock-names = "usbhost"; 663 phys = <&usb2_phy_gen 1>; 664 phy-names = "host"; 665 }; 666 667 ohci: usb@12120000 { 668 compatible = "samsung,exynos4210-ohci"; 669 reg = <0x12120000 0x100>; 670 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 671 672 clocks = <&clock CLK_USB2>; 673 clock-names = "usbhost"; 674 phys = <&usb2_phy_gen 1>; 675 phy-names = "host"; 676 }; 677 678 usb2_phy_gen: phy@12130000 { 679 compatible = "samsung,exynos5250-usb2-phy"; 680 reg = <0x12130000 0x100>; 681 clocks = <&clock CLK_USB2>, <&clock CLK_FIN_PLL>; 682 clock-names = "phy", "ref"; 683 #phy-cells = <1>; 684 samsung,sysreg-phandle = <&sysreg_system_controller>; 685 samsung,pmureg-phandle = <&pmu_system_controller>; 686 }; 687 688 pdma0: pdma@121a0000 { 689 compatible = "arm,pl330", "arm,primecell"; 690 reg = <0x121A0000 0x1000>; 691 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 692 clocks = <&clock CLK_PDMA0>; 693 clock-names = "apb_pclk"; 694 #dma-cells = <1>; 695 #dma-channels = <8>; 696 #dma-requests = <32>; 697 }; 698 699 pdma1: pdma@121b0000 { 700 compatible = "arm,pl330", "arm,primecell"; 701 reg = <0x121B0000 0x1000>; 702 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 703 clocks = <&clock CLK_PDMA1>; 704 clock-names = "apb_pclk"; 705 #dma-cells = <1>; 706 #dma-channels = <8>; 707 #dma-requests = <32>; 708 }; 709 710 mdma0: mdma@10800000 { 711 compatible = "arm,pl330", "arm,primecell"; 712 reg = <0x10800000 0x1000>; 713 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 714 clocks = <&clock CLK_MDMA0>; 715 clock-names = "apb_pclk"; 716 #dma-cells = <1>; 717 #dma-channels = <8>; 718 #dma-requests = <1>; 719 }; 720 721 mdma1: mdma@11c10000 { 722 compatible = "arm,pl330", "arm,primecell"; 723 reg = <0x11C10000 0x1000>; 724 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 725 clocks = <&clock CLK_MDMA1>; 726 clock-names = "apb_pclk"; 727 #dma-cells = <1>; 728 #dma-channels = <8>; 729 #dma-requests = <1>; 730 }; 731 732 gsc_0: gsc@13e00000 { 733 compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc"; 734 reg = <0x13e00000 0x1000>; 735 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 736 power-domains = <&pd_gsc>; 737 clocks = <&clock CLK_GSCL0>; 738 clock-names = "gscl"; 739 iommus = <&sysmmu_gsc0>; 740 }; 741 742 gsc_1: gsc@13e10000 { 743 compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc"; 744 reg = <0x13e10000 0x1000>; 745 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 746 power-domains = <&pd_gsc>; 747 clocks = <&clock CLK_GSCL1>; 748 clock-names = "gscl"; 749 iommus = <&sysmmu_gsc1>; 750 }; 751 752 gsc_2: gsc@13e20000 { 753 compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc"; 754 reg = <0x13e20000 0x1000>; 755 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 756 power-domains = <&pd_gsc>; 757 clocks = <&clock CLK_GSCL2>; 758 clock-names = "gscl"; 759 iommus = <&sysmmu_gsc2>; 760 }; 761 762 gsc_3: gsc@13e30000 { 763 compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc"; 764 reg = <0x13e30000 0x1000>; 765 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 766 power-domains = <&pd_gsc>; 767 clocks = <&clock CLK_GSCL3>; 768 clock-names = "gscl"; 769 iommus = <&sysmmu_gsc3>; 770 }; 771 772 hdmi: hdmi@14530000 { 773 compatible = "samsung,exynos4212-hdmi"; 774 reg = <0x14530000 0x70000>; 775 power-domains = <&pd_disp1>; 776 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 777 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>, 778 <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>, 779 <&clock CLK_MOUT_HDMI>; 780 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", 781 "sclk_hdmiphy", "mout_hdmi"; 782 samsung,syscon-phandle = <&pmu_system_controller>; 783 phy = <&hdmiphy>; 784 #sound-dai-cells = <0>; 785 status = "disabled"; 786 }; 787 788 hdmicec: cec@101b0000 { 789 compatible = "samsung,s5p-cec"; 790 reg = <0x101B0000 0x200>; 791 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 792 clocks = <&clock CLK_HDMI_CEC>; 793 clock-names = "hdmicec"; 794 samsung,syscon-phandle = <&pmu_system_controller>; 795 hdmi-phandle = <&hdmi>; 796 pinctrl-names = "default"; 797 pinctrl-0 = <&hdmi_cec>; 798 status = "disabled"; 799 }; 800 801 mixer: mixer@14450000 { 802 compatible = "samsung,exynos5250-mixer"; 803 reg = <0x14450000 0x10000>; 804 power-domains = <&pd_disp1>; 805 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 806 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>, 807 <&clock CLK_SCLK_HDMI>; 808 clock-names = "mixer", "hdmi", "sclk_hdmi"; 809 iommus = <&sysmmu_tv>; 810 status = "disabled"; 811 }; 812 813 dp_phy: video-phy { 814 compatible = "samsung,exynos5250-dp-video-phy"; 815 samsung,pmu-syscon = <&pmu_system_controller>; 816 #phy-cells = <0>; 817 }; 818 819 mipi_phy: video-phy@10040710 { 820 compatible = "samsung,s5pv210-mipi-video-phy"; 821 reg = <0x10040710 0x100>; 822 #phy-cells = <1>; 823 syscon = <&pmu_system_controller>; 824 }; 825 826 dsi_0: dsi@14500000 { 827 compatible = "samsung,exynos4210-mipi-dsi"; 828 reg = <0x14500000 0x10000>; 829 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 830 samsung,power-domain = <&pd_disp1>; 831 phys = <&mipi_phy 3>; 832 phy-names = "dsim"; 833 clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI1>; 834 clock-names = "bus_clk", "sclk_mipi"; 835 status = "disabled"; 836 #address-cells = <1>; 837 #size-cells = <0>; 838 }; 839 840 adc: adc@12d10000 { 841 compatible = "samsung,exynos-adc-v1"; 842 reg = <0x12D10000 0x100>; 843 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 844 clocks = <&clock CLK_ADC>; 845 clock-names = "adc"; 846 #io-channel-cells = <1>; 847 samsung,syscon-phandle = <&pmu_system_controller>; 848 status = "disabled"; 849 }; 850 851 sysmmu_g2d: sysmmu@10a60000 { 852 compatible = "samsung,exynos-sysmmu"; 853 reg = <0x10A60000 0x1000>; 854 interrupt-parent = <&combiner>; 855 interrupts = <24 5>; 856 clock-names = "sysmmu", "master"; 857 clocks = <&clock CLK_SMMU_2D>, <&clock CLK_G2D>; 858 #iommu-cells = <0>; 859 }; 860 861 sysmmu_mfc_r: sysmmu@11200000 { 862 compatible = "samsung,exynos-sysmmu"; 863 reg = <0x11200000 0x1000>; 864 interrupt-parent = <&combiner>; 865 interrupts = <6 2>; 866 power-domains = <&pd_mfc>; 867 clock-names = "sysmmu", "master"; 868 clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>; 869 #iommu-cells = <0>; 870 }; 871 872 sysmmu_mfc_l: sysmmu@11210000 { 873 compatible = "samsung,exynos-sysmmu"; 874 reg = <0x11210000 0x1000>; 875 interrupt-parent = <&combiner>; 876 interrupts = <8 5>; 877 power-domains = <&pd_mfc>; 878 clock-names = "sysmmu", "master"; 879 clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>; 880 #iommu-cells = <0>; 881 }; 882 883 sysmmu_rotator: sysmmu@11d40000 { 884 compatible = "samsung,exynos-sysmmu"; 885 reg = <0x11D40000 0x1000>; 886 interrupt-parent = <&combiner>; 887 interrupts = <4 0>; 888 clock-names = "sysmmu", "master"; 889 clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>; 890 #iommu-cells = <0>; 891 }; 892 893 sysmmu_jpeg: sysmmu@11f20000 { 894 compatible = "samsung,exynos-sysmmu"; 895 reg = <0x11F20000 0x1000>; 896 interrupt-parent = <&combiner>; 897 interrupts = <4 2>; 898 power-domains = <&pd_gsc>; 899 clock-names = "sysmmu", "master"; 900 clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>; 901 #iommu-cells = <0>; 902 }; 903 904 sysmmu_fimc_isp: sysmmu@13260000 { 905 compatible = "samsung,exynos-sysmmu"; 906 reg = <0x13260000 0x1000>; 907 interrupt-parent = <&combiner>; 908 interrupts = <10 6>; 909 clock-names = "sysmmu"; 910 clocks = <&clock CLK_SMMU_FIMC_ISP>; 911 #iommu-cells = <0>; 912 }; 913 914 sysmmu_fimc_drc: sysmmu@13270000 { 915 compatible = "samsung,exynos-sysmmu"; 916 reg = <0x13270000 0x1000>; 917 interrupt-parent = <&combiner>; 918 interrupts = <11 6>; 919 clock-names = "sysmmu"; 920 clocks = <&clock CLK_SMMU_FIMC_DRC>; 921 #iommu-cells = <0>; 922 }; 923 924 sysmmu_fimc_fd: sysmmu@132a0000 { 925 compatible = "samsung,exynos-sysmmu"; 926 reg = <0x132A0000 0x1000>; 927 interrupt-parent = <&combiner>; 928 interrupts = <5 0>; 929 clock-names = "sysmmu"; 930 clocks = <&clock CLK_SMMU_FIMC_FD>; 931 #iommu-cells = <0>; 932 }; 933 934 sysmmu_fimc_scc: sysmmu@13280000 { 935 compatible = "samsung,exynos-sysmmu"; 936 reg = <0x13280000 0x1000>; 937 interrupt-parent = <&combiner>; 938 interrupts = <5 2>; 939 clock-names = "sysmmu"; 940 clocks = <&clock CLK_SMMU_FIMC_SCC>; 941 #iommu-cells = <0>; 942 }; 943 944 sysmmu_fimc_scp: sysmmu@13290000 { 945 compatible = "samsung,exynos-sysmmu"; 946 reg = <0x13290000 0x1000>; 947 interrupt-parent = <&combiner>; 948 interrupts = <3 6>; 949 clock-names = "sysmmu"; 950 clocks = <&clock CLK_SMMU_FIMC_SCP>; 951 #iommu-cells = <0>; 952 }; 953 954 sysmmu_fimc_mcuctl: sysmmu@132b0000 { 955 compatible = "samsung,exynos-sysmmu"; 956 reg = <0x132B0000 0x1000>; 957 interrupt-parent = <&combiner>; 958 interrupts = <5 4>; 959 clock-names = "sysmmu"; 960 clocks = <&clock CLK_SMMU_FIMC_MCU>; 961 #iommu-cells = <0>; 962 }; 963 964 sysmmu_fimc_odc: sysmmu@132c0000 { 965 compatible = "samsung,exynos-sysmmu"; 966 reg = <0x132C0000 0x1000>; 967 interrupt-parent = <&combiner>; 968 interrupts = <11 0>; 969 clock-names = "sysmmu"; 970 clocks = <&clock CLK_SMMU_FIMC_ODC>; 971 #iommu-cells = <0>; 972 }; 973 974 sysmmu_fimc_dis0: sysmmu@132d0000 { 975 compatible = "samsung,exynos-sysmmu"; 976 reg = <0x132D0000 0x1000>; 977 interrupt-parent = <&combiner>; 978 interrupts = <10 4>; 979 clock-names = "sysmmu"; 980 clocks = <&clock CLK_SMMU_FIMC_DIS0>; 981 #iommu-cells = <0>; 982 }; 983 984 sysmmu_fimc_dis1: sysmmu@132e0000 { 985 compatible = "samsung,exynos-sysmmu"; 986 reg = <0x132E0000 0x1000>; 987 interrupt-parent = <&combiner>; 988 interrupts = <9 4>; 989 clock-names = "sysmmu"; 990 clocks = <&clock CLK_SMMU_FIMC_DIS1>; 991 #iommu-cells = <0>; 992 }; 993 994 sysmmu_fimc_3dnr: sysmmu@132f0000 { 995 compatible = "samsung,exynos-sysmmu"; 996 reg = <0x132F0000 0x1000>; 997 interrupt-parent = <&combiner>; 998 interrupts = <5 6>; 999 clock-names = "sysmmu"; 1000 clocks = <&clock CLK_SMMU_FIMC_3DNR>; 1001 #iommu-cells = <0>; 1002 }; 1003 1004 sysmmu_fimc_lite0: sysmmu@13c40000 { 1005 compatible = "samsung,exynos-sysmmu"; 1006 reg = <0x13C40000 0x1000>; 1007 interrupt-parent = <&combiner>; 1008 interrupts = <3 4>; 1009 power-domains = <&pd_gsc>; 1010 clock-names = "sysmmu", "master"; 1011 clocks = <&clock CLK_SMMU_FIMC_LITE0>, <&clock CLK_CAMIF_TOP>; 1012 #iommu-cells = <0>; 1013 }; 1014 1015 sysmmu_fimc_lite1: sysmmu@13c50000 { 1016 compatible = "samsung,exynos-sysmmu"; 1017 reg = <0x13C50000 0x1000>; 1018 interrupt-parent = <&combiner>; 1019 interrupts = <24 1>; 1020 power-domains = <&pd_gsc>; 1021 clock-names = "sysmmu", "master"; 1022 clocks = <&clock CLK_SMMU_FIMC_LITE1>, <&clock CLK_CAMIF_TOP>; 1023 #iommu-cells = <0>; 1024 }; 1025 1026 sysmmu_gsc0: sysmmu@13e80000 { 1027 compatible = "samsung,exynos-sysmmu"; 1028 reg = <0x13E80000 0x1000>; 1029 interrupt-parent = <&combiner>; 1030 interrupts = <2 0>; 1031 power-domains = <&pd_gsc>; 1032 clock-names = "sysmmu", "master"; 1033 clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>; 1034 #iommu-cells = <0>; 1035 }; 1036 1037 sysmmu_gsc1: sysmmu@13e90000 { 1038 compatible = "samsung,exynos-sysmmu"; 1039 reg = <0x13E90000 0x1000>; 1040 interrupt-parent = <&combiner>; 1041 interrupts = <2 2>; 1042 power-domains = <&pd_gsc>; 1043 clock-names = "sysmmu", "master"; 1044 clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>; 1045 #iommu-cells = <0>; 1046 }; 1047 1048 sysmmu_gsc2: sysmmu@13ea0000 { 1049 compatible = "samsung,exynos-sysmmu"; 1050 reg = <0x13EA0000 0x1000>; 1051 interrupt-parent = <&combiner>; 1052 interrupts = <2 4>; 1053 power-domains = <&pd_gsc>; 1054 clock-names = "sysmmu", "master"; 1055 clocks = <&clock CLK_SMMU_GSCL2>, <&clock CLK_GSCL2>; 1056 #iommu-cells = <0>; 1057 }; 1058 1059 sysmmu_gsc3: sysmmu@13eb0000 { 1060 compatible = "samsung,exynos-sysmmu"; 1061 reg = <0x13EB0000 0x1000>; 1062 interrupt-parent = <&combiner>; 1063 interrupts = <2 6>; 1064 power-domains = <&pd_gsc>; 1065 clock-names = "sysmmu", "master"; 1066 clocks = <&clock CLK_SMMU_GSCL3>, <&clock CLK_GSCL3>; 1067 #iommu-cells = <0>; 1068 }; 1069 1070 sysmmu_fimd1: sysmmu@14640000 { 1071 compatible = "samsung,exynos-sysmmu"; 1072 reg = <0x14640000 0x1000>; 1073 interrupt-parent = <&combiner>; 1074 interrupts = <3 2>; 1075 power-domains = <&pd_disp1>; 1076 clock-names = "sysmmu", "master"; 1077 clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>; 1078 #iommu-cells = <0>; 1079 }; 1080 1081 sysmmu_tv: sysmmu@14650000 { 1082 compatible = "samsung,exynos-sysmmu"; 1083 reg = <0x14650000 0x1000>; 1084 interrupt-parent = <&combiner>; 1085 interrupts = <7 4>; 1086 power-domains = <&pd_disp1>; 1087 clock-names = "sysmmu", "master"; 1088 clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>; 1089 #iommu-cells = <0>; 1090 }; 1091 }; 1092 1093 timer { 1094 compatible = "arm,armv7-timer"; 1095 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1096 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1097 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1098 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1099 /* 1100 * Unfortunately we need this since some versions 1101 * of U-Boot on Exynos don't set the CNTFRQ register, 1102 * so we need the value from DT. 1103 */ 1104 clock-frequency = <24000000>; 1105 }; 1106}; 1107 1108&cpu_thermal { 1109 polling-delay-passive = <0>; 1110 polling-delay = <0>; 1111 thermal-sensors = <&tmu 0>; 1112 1113 cooling-maps { 1114 map0 { 1115 /* Corresponds to 800MHz at freq_table */ 1116 cooling-device = <&cpu0 9 9>, <&cpu1 9 9>; 1117 }; 1118 map1 { 1119 /* Corresponds to 200MHz at freq_table */ 1120 cooling-device = <&cpu0 15 15>, 1121 <&cpu1 15 15>; 1122 }; 1123 }; 1124}; 1125 1126&dp { 1127 power-domains = <&pd_disp1>; 1128 clocks = <&clock CLK_DP>; 1129 clock-names = "dp"; 1130 phys = <&dp_phy>; 1131 phy-names = "dp"; 1132}; 1133 1134&fimd { 1135 power-domains = <&pd_disp1>; 1136 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>; 1137 clock-names = "sclk_fimd", "fimd"; 1138 iommus = <&sysmmu_fimd1>; 1139}; 1140 1141&g2d { 1142 iommus = <&sysmmu_g2d>; 1143 clocks = <&clock CLK_G2D>; 1144 clock-names = "fimg2d"; 1145 status = "okay"; 1146}; 1147 1148&i2c_0 { 1149 clocks = <&clock CLK_I2C0>; 1150 clock-names = "i2c"; 1151 pinctrl-names = "default"; 1152 pinctrl-0 = <&i2c0_bus>; 1153}; 1154 1155&i2c_1 { 1156 clocks = <&clock CLK_I2C1>; 1157 clock-names = "i2c"; 1158 pinctrl-names = "default"; 1159 pinctrl-0 = <&i2c1_bus>; 1160}; 1161 1162&i2c_2 { 1163 clocks = <&clock CLK_I2C2>; 1164 clock-names = "i2c"; 1165 pinctrl-names = "default"; 1166 pinctrl-0 = <&i2c2_bus>; 1167}; 1168 1169&i2c_3 { 1170 clocks = <&clock CLK_I2C3>; 1171 clock-names = "i2c"; 1172 pinctrl-names = "default"; 1173 pinctrl-0 = <&i2c3_bus>; 1174}; 1175 1176&prng { 1177 clocks = <&clock CLK_SSS>; 1178 clock-names = "secss"; 1179}; 1180 1181&pwm { 1182 clocks = <&clock CLK_PWM>; 1183 clock-names = "timers"; 1184}; 1185 1186&rtc { 1187 clocks = <&clock CLK_RTC>; 1188 clock-names = "rtc"; 1189 interrupt-parent = <&pmu_system_controller>; 1190 status = "disabled"; 1191}; 1192 1193&serial_0 { 1194 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; 1195 clock-names = "uart", "clk_uart_baud0"; 1196 dmas = <&pdma0 13>, <&pdma0 14>; 1197 dma-names = "rx", "tx"; 1198}; 1199 1200&serial_1 { 1201 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; 1202 clock-names = "uart", "clk_uart_baud0"; 1203 dmas = <&pdma1 15>, <&pdma1 16>; 1204 dma-names = "rx", "tx"; 1205}; 1206 1207&serial_2 { 1208 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; 1209 clock-names = "uart", "clk_uart_baud0"; 1210 dmas = <&pdma0 15>, <&pdma0 16>; 1211 dma-names = "rx", "tx"; 1212}; 1213 1214&serial_3 { 1215 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; 1216 clock-names = "uart", "clk_uart_baud0"; 1217 dmas = <&pdma1 17>, <&pdma1 18>; 1218 dma-names = "rx", "tx"; 1219}; 1220 1221&sss { 1222 clocks = <&clock CLK_SSS>; 1223 clock-names = "secss"; 1224}; 1225 1226&trng { 1227 clocks = <&clock CLK_SSS>; 1228 clock-names = "secss"; 1229}; 1230 1231#include "exynos5250-pinctrl.dtsi" 1232#include "exynos-syscon-restart.dtsi" 1233