1// SPDX-License-Identifier: GPL-2.0 OR X11 2/* 3 * Copyright 2016 Boundary Devices, Inc. 4 */ 5#include <dt-bindings/gpio/gpio.h> 6#include <dt-bindings/input/input.h> 7 8/ { 9 chosen { 10 stdout-path = &uart2; 11 }; 12 13 memory@10000000 { 14 device_type = "memory"; 15 reg = <0x10000000 0x40000000>; 16 }; 17 18 backlight_lcd: backlight-lcd { 19 compatible = "pwm-backlight"; 20 pwms = <&pwm1 0 5000000>; 21 brightness-levels = <0 4 8 16 32 64 128 255>; 22 default-brightness-level = <7>; 23 power-supply = <®_3p3v>; 24 status = "okay"; 25 }; 26 27 backlight_lvds0: backlight-lvds0 { 28 compatible = "pwm-backlight"; 29 pwms = <&pwm4 0 5000000>; 30 brightness-levels = <0 4 8 16 32 64 128 255>; 31 default-brightness-level = <7>; 32 power-supply = <®_3p3v>; 33 status = "okay"; 34 }; 35 36 backlight_lvds1: backlight-lvds1 { 37 compatible = "gpio-backlight"; 38 pinctrl-names = "default"; 39 pinctrl-0 = <&pinctrl_backlight_lvds1>; 40 gpios = <&gpio2 31 GPIO_ACTIVE_HIGH>; 41 default-on; 42 status = "okay"; 43 }; 44 45 gpio-keys { 46 compatible = "gpio-keys"; 47 pinctrl-names = "default"; 48 pinctrl-0 = <&pinctrl_gpio_keys>; 49 50 power { 51 label = "Power Button"; 52 gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; 53 linux,code = <KEY_POWER>; 54 wakeup-source; 55 }; 56 57 menu { 58 label = "Menu"; 59 gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; 60 linux,code = <KEY_MENU>; 61 }; 62 63 home { 64 label = "Home"; 65 gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; 66 linux,code = <KEY_HOME>; 67 }; 68 69 back { 70 label = "Back"; 71 gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; 72 linux,code = <KEY_BACK>; 73 }; 74 75 volume-up { 76 label = "Volume Up"; 77 gpios = <&gpio7 13 GPIO_ACTIVE_LOW>; 78 linux,code = <KEY_VOLUMEUP>; 79 }; 80 81 volume-down { 82 label = "Volume Down"; 83 gpios = <&gpio7 1 GPIO_ACTIVE_LOW>; 84 linux,code = <KEY_VOLUMEDOWN>; 85 }; 86 }; 87 88 lcd_display: disp0 { 89 compatible = "fsl,imx-parallel-display"; 90 #address-cells = <1>; 91 #size-cells = <0>; 92 interface-pix-fmt = "bgr666"; 93 pinctrl-names = "default"; 94 pinctrl-0 = <&pinctrl_j15>; 95 status = "okay"; 96 97 port@0 { 98 reg = <0>; 99 100 lcd_display_in: endpoint { 101 remote-endpoint = <&ipu1_di0_disp0>; 102 }; 103 }; 104 105 port@1 { 106 reg = <1>; 107 108 lcd_display_out: endpoint { 109 remote-endpoint = <&lcd_panel_in>; 110 }; 111 }; 112 }; 113 114 panel-lcd { 115 compatible = "okaya,rs800480t-7x0gp"; 116 backlight = <&backlight_lcd>; 117 118 port { 119 lcd_panel_in: endpoint { 120 remote-endpoint = <&lcd_display_out>; 121 }; 122 }; 123 }; 124 125 panel-lvds0 { 126 compatible = "hannstar,hsd100pxn1"; 127 backlight = <&backlight_lvds0>; 128 129 port { 130 panel_in_lvds0: endpoint { 131 remote-endpoint = <&lvds0_out>; 132 }; 133 }; 134 }; 135 136 panel-lvds1 { 137 compatible = "hannstar,hsd100pxn1"; 138 backlight = <&backlight_lvds1>; 139 140 port { 141 panel_in_lvds1: endpoint { 142 remote-endpoint = <&lvds1_out>; 143 }; 144 }; 145 }; 146 147 reg_1p8v: regulator-1v8 { 148 compatible = "regulator-fixed"; 149 regulator-name = "1P8V"; 150 regulator-min-microvolt = <1800000>; 151 regulator-max-microvolt = <1800000>; 152 regulator-always-on; 153 }; 154 155 reg_2p5v: regulator-2v5 { 156 compatible = "regulator-fixed"; 157 regulator-name = "2P5V"; 158 regulator-min-microvolt = <2500000>; 159 regulator-max-microvolt = <2500000>; 160 regulator-always-on; 161 }; 162 163 reg_3p3v: regulator-3v3 { 164 compatible = "regulator-fixed"; 165 regulator-name = "3P3V"; 166 regulator-min-microvolt = <3300000>; 167 regulator-max-microvolt = <3300000>; 168 regulator-always-on; 169 }; 170 171 reg_can_xcvr: regulator-can-xcvr { 172 compatible = "regulator-fixed"; 173 regulator-name = "CAN XCVR"; 174 regulator-min-microvolt = <3300000>; 175 regulator-max-microvolt = <3300000>; 176 pinctrl-names = "default"; 177 pinctrl-0 = <&pinctrl_can_xcvr>; 178 gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; 179 }; 180 181 reg_usb_h1_vbus: regulator-usb-h1-vbus { 182 compatible = "regulator-fixed"; 183 pinctrl-names = "default"; 184 pinctrl-0 = <&pinctrl_usbh1>; 185 regulator-name = "usb_h1_vbus"; 186 regulator-min-microvolt = <3300000>; 187 regulator-max-microvolt = <3300000>; 188 gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; 189 enable-active-high; 190 regulator-always-on; 191 }; 192 193 reg_usb_otg_vbus: regulator-usb-otg-vbus { 194 compatible = "regulator-fixed"; 195 regulator-name = "usb_otg_vbus"; 196 regulator-min-microvolt = <5000000>; 197 regulator-max-microvolt = <5000000>; 198 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; 199 enable-active-high; 200 }; 201 202 reg_wlan_vmmc: regulator-wlan-vmmc { 203 compatible = "regulator-fixed"; 204 pinctrl-names = "default"; 205 pinctrl-0 = <&pinctrl_wlan_vmmc>; 206 regulator-name = "reg_wlan_vmmc"; 207 regulator-min-microvolt = <3300000>; 208 regulator-max-microvolt = <3300000>; 209 gpio = <&gpio6 15 GPIO_ACTIVE_HIGH>; 210 startup-delay-us = <70000>; 211 enable-active-high; 212 }; 213 214 sound { 215 compatible = "fsl,imx6q-nitrogen6_som2-sgtl5000", 216 "fsl,imx-audio-sgtl5000"; 217 model = "imx6q-nitrogen6_som2-sgtl5000"; 218 ssi-controller = <&ssi1>; 219 audio-codec = <&codec>; 220 audio-routing = 221 "MIC_IN", "Mic Jack", 222 "Mic Jack", "Mic Bias", 223 "Headphone Jack", "HP_OUT"; 224 mux-int-port = <1>; 225 mux-ext-port = <3>; 226 }; 227}; 228 229&audmux { 230 pinctrl-names = "default"; 231 pinctrl-0 = <&pinctrl_audmux>; 232 status = "okay"; 233}; 234 235&can1 { 236 pinctrl-names = "default"; 237 pinctrl-0 = <&pinctrl_can1>; 238 xceiver-supply = <®_can_xcvr>; 239 status = "okay"; 240}; 241 242&clks { 243 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, 244 <&clks IMX6QDL_CLK_LDB_DI1_SEL>; 245 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, 246 <&clks IMX6QDL_CLK_PLL3_USB_OTG>; 247}; 248 249&ecspi1 { 250 cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; 251 pinctrl-names = "default"; 252 pinctrl-0 = <&pinctrl_ecspi1>; 253 status = "okay"; 254 255 flash: m25p80@0 { 256 compatible = "microchip,sst25vf016b"; 257 spi-max-frequency = <20000000>; 258 reg = <0>; 259 }; 260}; 261 262&fec { 263 pinctrl-names = "default"; 264 pinctrl-0 = <&pinctrl_enet>; 265 phy-mode = "rgmii"; 266 interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, 267 <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; 268 fsl,err006687-workaround-present; 269 status = "okay"; 270}; 271 272&hdmi { 273 ddc-i2c-bus = <&i2c2>; 274 status = "okay"; 275}; 276 277&i2c1 { 278 clock-frequency = <100000>; 279 pinctrl-names = "default"; 280 pinctrl-0 = <&pinctrl_i2c1>; 281 status = "okay"; 282 283 codec: sgtl5000@a { 284 compatible = "fsl,sgtl5000"; 285 pinctrl-names = "default"; 286 pinctrl-0 = <&pinctrl_sgtl5000>; 287 reg = <0x0a>; 288 clocks = <&clks IMX6QDL_CLK_CKO>; 289 VDDA-supply = <®_2p5v>; 290 VDDIO-supply = <®_3p3v>; 291 }; 292 293 rtc@68 { 294 compatible = "microcrystal,rv4162"; 295 pinctrl-names = "default"; 296 pinctrl-0 = <&pinctrl_rv4162>; 297 reg = <0x68>; 298 interrupts-extended = <&gpio6 7 IRQ_TYPE_LEVEL_LOW>; 299 }; 300}; 301 302&i2c2 { 303 clock-frequency = <100000>; 304 pinctrl-names = "default"; 305 pinctrl-0 = <&pinctrl_i2c2>; 306 status = "okay"; 307}; 308 309&i2c3 { 310 clock-frequency = <100000>; 311 pinctrl-names = "default"; 312 pinctrl-0 = <&pinctrl_i2c3>; 313 status = "okay"; 314 315 touchscreen@4 { 316 compatible = "eeti,egalax_ts"; 317 reg = <0x04>; 318 interrupt-parent = <&gpio1>; 319 interrupts = <9 IRQ_TYPE_EDGE_FALLING>; 320 wakeup-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; 321 }; 322 323 touchscreen@38 { 324 compatible = "edt,edt-ft5x06"; 325 reg = <0x38>; 326 interrupt-parent = <&gpio1>; 327 interrupts = <9 IRQ_TYPE_EDGE_FALLING>; 328 wakeup-source; 329 }; 330}; 331 332&iomuxc { 333 pinctrl_audmux: audmuxgrp { 334 fsl,pins = < 335 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 336 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 337 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 338 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 339 >; 340 }; 341 342 pinctrl_backlight_lvds1: backlight-lvds1grp { 343 fsl,pins = < 344 MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x0b0b0 345 >; 346 }; 347 348 pinctrl_can1: can1grp { 349 fsl,pins = < 350 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 351 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 352 >; 353 }; 354 355 pinctrl_can_xcvr: can-xcvrgrp { 356 fsl,pins = < 357 /* Flexcan XCVR enable */ 358 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x0b0b0 359 >; 360 }; 361 362 pinctrl_ecspi1: ecspi1grp { 363 fsl,pins = < 364 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 365 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 366 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 367 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 368 >; 369 }; 370 371 pinctrl_enet: enetgrp { 372 fsl,pins = < 373 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 374 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 375 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0 376 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0 377 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0 378 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0 379 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0 380 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0 381 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 382 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 383 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x130b0 384 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 385 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x130b0 386 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 387 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x130b0 388 MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x030b0 389 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 390 MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 391 >; 392 }; 393 394 pinctrl_gpio_keys: gpio-keysgrp { 395 fsl,pins = < 396 /* Power Button */ 397 MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 398 /* Menu Button */ 399 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 400 /* Home Button */ 401 MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 402 /* Back Button */ 403 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 404 /* Volume Up Button */ 405 MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 406 /* Volume Down Button */ 407 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b0 408 >; 409 }; 410 411 pinctrl_i2c1: i2c1grp { 412 fsl,pins = < 413 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 414 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 415 >; 416 }; 417 418 pinctrl_i2c2: i2c2grp { 419 fsl,pins = < 420 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 421 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 422 >; 423 }; 424 425 pinctrl_i2c3: i2c3grp { 426 fsl,pins = < 427 MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 428 MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 429 MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 430 >; 431 }; 432 433 pinctrl_i2c3mux: i2c3muxgrp { 434 fsl,pins = < 435 /* PCIe I2C enable */ 436 MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x000b0 437 >; 438 }; 439 440 pinctrl_j15: j15grp { 441 fsl,pins = < 442 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 443 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 444 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 445 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 446 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 447 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 448 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 449 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 450 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 451 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 452 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 453 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 454 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 455 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 456 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 457 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 458 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 459 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 460 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 461 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 462 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 463 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 464 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 465 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 466 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 467 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 468 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 469 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 470 >; 471 }; 472 473 pinctrl_pcie: pciegrp { 474 fsl,pins = < 475 /* PCIe reset */ 476 MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x030b0 477 MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x030b0 478 >; 479 }; 480 481 pinctrl_pwm1: pwm1grp { 482 fsl,pins = < 483 MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x030b1 484 >; 485 }; 486 487 pinctrl_pwm3: pwm3grp { 488 fsl,pins = < 489 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x030b1 490 >; 491 }; 492 493 pinctrl_pwm4: pwm4grp { 494 fsl,pins = < 495 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x030b1 496 >; 497 }; 498 499 pinctrl_rv4162: rv4162grp { 500 fsl,pins = < 501 MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0 502 >; 503 }; 504 505 pinctrl_sgtl5000: sgtl5000grp { 506 fsl,pins = < 507 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 508 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x130b0 509 MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x130b0 510 MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x130b0 511 >; 512 }; 513 514 pinctrl_uart1: uart1grp { 515 fsl,pins = < 516 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 517 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 518 >; 519 }; 520 521 pinctrl_uart2: uart2grp { 522 fsl,pins = < 523 MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 524 MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 525 >; 526 }; 527 528 pinctrl_uart3: uart3grp { 529 fsl,pins = < 530 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 531 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 532 MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 533 MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 534 >; 535 }; 536 537 pinctrl_usbh1: usbh1grp { 538 fsl,pins = < 539 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x030b0 540 >; 541 }; 542 543 pinctrl_usbotg: usbotggrp { 544 fsl,pins = < 545 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 546 MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 547 /* power enable, high active */ 548 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x030b0 549 >; 550 }; 551 552 pinctrl_usdhc2: usdhc2grp { 553 fsl,pins = < 554 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071 555 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17071 556 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17071 557 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17071 558 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17071 559 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17071 560 >; 561 }; 562 563 pinctrl_usdhc3: usdhc3grp { 564 fsl,pins = < 565 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10071 566 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17071 567 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17071 568 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17071 569 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17071 570 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17071 571 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 572 >; 573 }; 574 575 pinctrl_usdhc4: usdhc4grp { 576 fsl,pins = < 577 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 578 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 579 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 580 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 581 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 582 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 583 MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 584 MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 585 MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 586 MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 587 >; 588 }; 589 590 pinctrl_wlan_vmmc: wlan-vmmcgrp { 591 fsl,pins = < 592 MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x100b0 593 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x030b0 594 MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x030b0 595 MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x000b0 596 >; 597 }; 598}; 599 600&ipu1_di0_disp0 { 601 remote-endpoint = <&lcd_display_in>; 602}; 603 604&ldb { 605 status = "okay"; 606 607 lvds-channel@0 { 608 status = "okay"; 609 610 port@4 { 611 reg = <4>; 612 613 lvds0_out: endpoint { 614 remote-endpoint = <&panel_in_lvds0>; 615 }; 616 }; 617 }; 618 619 lvds-channel@1 { 620 fsl,data-mapping = "spwg"; 621 fsl,data-width = <18>; 622 status = "okay"; 623 624 port@4 { 625 reg = <4>; 626 627 lvds1_out: endpoint { 628 remote-endpoint = <&panel_in_lvds1>; 629 }; 630 }; 631 }; 632}; 633 634&pcie { 635 pinctrl-names = "default"; 636 pinctrl-0 = <&pinctrl_pcie>; 637 reset-gpio = <&gpio3 0 GPIO_ACTIVE_LOW>; 638 status = "okay"; 639}; 640 641&pwm1 { 642 #pwm-cells = <2>; 643 pinctrl-names = "default"; 644 pinctrl-0 = <&pinctrl_pwm1>; 645 status = "okay"; 646}; 647 648&pwm3 { 649 pinctrl-names = "default"; 650 pinctrl-0 = <&pinctrl_pwm3>; 651 status = "okay"; 652}; 653 654&pwm4 { 655 #pwm-cells = <2>; 656 pinctrl-names = "default"; 657 pinctrl-0 = <&pinctrl_pwm4>; 658 status = "okay"; 659}; 660 661&ssi1 { 662 status = "okay"; 663}; 664 665&uart1 { 666 pinctrl-names = "default"; 667 pinctrl-0 = <&pinctrl_uart1>; 668 status = "okay"; 669}; 670 671&uart2 { 672 pinctrl-names = "default"; 673 pinctrl-0 = <&pinctrl_uart2>; 674 status = "okay"; 675}; 676 677&uart3 { 678 pinctrl-names = "default"; 679 pinctrl-0 = <&pinctrl_uart3>; 680 uart-has-rtscts; 681 status = "okay"; 682}; 683 684&usbh1 { 685 vbus-supply = <®_usb_h1_vbus>; 686 status = "okay"; 687}; 688 689&usbotg { 690 vbus-supply = <®_usb_otg_vbus>; 691 pinctrl-names = "default"; 692 pinctrl-0 = <&pinctrl_usbotg>; 693 disable-over-current; 694 status = "okay"; 695}; 696 697&usdhc2 { 698 pinctrl-names = "default"; 699 pinctrl-0 = <&pinctrl_usdhc2>; 700 bus-width = <4>; 701 non-removable; 702 vmmc-supply = <®_wlan_vmmc>; 703 cap-power-off-card; 704 keep-power-in-suspend; 705 status = "okay"; 706 707 #address-cells = <1>; 708 #size-cells = <0>; 709 wlcore: wlcore@2 { 710 compatible = "ti,wl1271"; 711 reg = <2>; 712 interrupt-parent = <&gpio6>; 713 interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; 714 ref-clock-frequency = <38400000>; 715 }; 716}; 717 718&usdhc3 { 719 pinctrl-names = "default"; 720 pinctrl-0 = <&pinctrl_usdhc3>; 721 cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; 722 bus-width = <4>; 723 vmmc-supply = <®_3p3v>; 724 status = "okay"; 725}; 726 727&usdhc4 { 728 pinctrl-names = "default"; 729 pinctrl-0 = <&pinctrl_usdhc4>; 730 bus-width = <8>; 731 non-removable; 732 vmmc-supply = <®_1p8v>; 733 keep-power-in-suspend; 734 status = "okay"; 735}; 736