1// SPDX-License-Identifier: GPL-2.0+
2//
3// Copyright 2012 Freescale Semiconductor, Inc.
4// Copyright 2011 Linaro Ltd.
5
6#include <dt-bindings/clock/imx6qdl-clock.h>
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/input/input.h>
9
10/ {
11	chosen {
12		stdout-path = &uart1;
13	};
14
15	memory@10000000 {
16		device_type = "memory";
17		reg = <0x10000000 0x40000000>;
18	};
19
20	reg_usb_otg_vbus: regulator-usb-otg-vbus {
21		compatible = "regulator-fixed";
22		regulator-name = "usb_otg_vbus";
23		regulator-min-microvolt = <5000000>;
24		regulator-max-microvolt = <5000000>;
25		gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
26		enable-active-high;
27		vin-supply = <&swbst_reg>;
28	};
29
30	reg_usb_h1_vbus: regulator-usb-h1-vbus {
31		compatible = "regulator-fixed";
32		regulator-name = "usb_h1_vbus";
33		regulator-min-microvolt = <5000000>;
34		regulator-max-microvolt = <5000000>;
35		gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>;
36		enable-active-high;
37		vin-supply = <&swbst_reg>;
38	};
39
40	reg_audio: regulator-audio {
41		compatible = "regulator-fixed";
42		regulator-name = "wm8962-supply";
43		gpio = <&gpio4 10 GPIO_ACTIVE_HIGH>;
44		enable-active-high;
45	};
46
47	reg_pcie: regulator-pcie {
48		compatible = "regulator-fixed";
49		pinctrl-names = "default";
50		pinctrl-0 = <&pinctrl_pcie_reg>;
51		regulator-name = "MPCIE_3V3";
52		regulator-min-microvolt = <3300000>;
53		regulator-max-microvolt = <3300000>;
54		gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>;
55		enable-active-high;
56	};
57
58	reg_sensors: regulator-sensors {
59		compatible = "regulator-fixed";
60		pinctrl-names = "default";
61		pinctrl-0 = <&pinctrl_sensors_reg>;
62		regulator-name = "sensors-supply";
63		regulator-min-microvolt = <3300000>;
64		regulator-max-microvolt = <3300000>;
65		gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>;
66		enable-active-high;
67	};
68
69	gpio-keys {
70		compatible = "gpio-keys";
71		pinctrl-names = "default";
72		pinctrl-0 = <&pinctrl_gpio_keys>;
73
74		power {
75			label = "Power Button";
76			gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
77			wakeup-source;
78			linux,code = <KEY_POWER>;
79		};
80
81		volume-up {
82			label = "Volume Up";
83			gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
84			wakeup-source;
85			linux,code = <KEY_VOLUMEUP>;
86		};
87
88		volume-down {
89			label = "Volume Down";
90			gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
91			wakeup-source;
92			linux,code = <KEY_VOLUMEDOWN>;
93		};
94	};
95
96	sound {
97		compatible = "fsl,imx6q-sabresd-wm8962",
98			   "fsl,imx-audio-wm8962";
99		model = "wm8962-audio";
100		ssi-controller = <&ssi2>;
101		audio-codec = <&codec>;
102		audio-routing =
103			"Headphone Jack", "HPOUTL",
104			"Headphone Jack", "HPOUTR",
105			"Ext Spk", "SPKOUTL",
106			"Ext Spk", "SPKOUTR",
107			"AMIC", "MICBIAS",
108			"IN3R", "AMIC",
109			"DMIC", "MICBIAS",
110			"DMICDAT", "DMIC";
111		mux-int-port = <2>;
112		mux-ext-port = <3>;
113		hp-det-gpio = <&gpio7 8 GPIO_ACTIVE_LOW>;
114		mic-det-gpio = <&gpio1 9 GPIO_ACTIVE_LOW>;
115	};
116
117	backlight_lvds: backlight-lvds {
118		compatible = "pwm-backlight";
119		pwms = <&pwm1 0 5000000>;
120		brightness-levels = <0 4 8 16 32 64 128 255>;
121		default-brightness-level = <7>;
122		status = "okay";
123	};
124
125	leds {
126		compatible = "gpio-leds";
127		pinctrl-names = "default";
128		pinctrl-0 = <&pinctrl_gpio_leds>;
129
130		red {
131			gpios = <&gpio1 2 0>;
132			default-state = "on";
133		};
134	};
135
136	panel {
137		compatible = "hannstar,hsd100pxn1";
138		backlight = <&backlight_lvds>;
139
140		port {
141			panel_in: endpoint {
142				remote-endpoint = <&lvds0_out>;
143			};
144		};
145	};
146};
147
148&ipu1_csi0_from_ipu1_csi0_mux {
149	bus-width = <8>;
150	data-shift = <12>; /* Lines 19:12 used */
151	hsync-active = <1>;
152	vsync-active = <1>;
153};
154
155&ipu1_csi0_mux_from_parallel_sensor {
156	remote-endpoint = <&ov5642_to_ipu1_csi0_mux>;
157};
158
159&ipu1_csi0 {
160	pinctrl-names = "default";
161	pinctrl-0 = <&pinctrl_ipu1_csi0>;
162};
163
164&mipi_csi {
165	status = "okay";
166
167	port@0 {
168		reg = <0>;
169
170		mipi_csi2_in: endpoint {
171			remote-endpoint = <&ov5640_to_mipi_csi2>;
172			clock-lanes = <0>;
173			data-lanes = <1 2>;
174		};
175	};
176};
177
178&audmux {
179	pinctrl-names = "default";
180	pinctrl-0 = <&pinctrl_audmux>;
181	status = "okay";
182};
183
184&clks {
185	assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
186			  <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
187	assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
188				 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
189};
190
191&ecspi1 {
192	cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>;
193	pinctrl-names = "default";
194	pinctrl-0 = <&pinctrl_ecspi1>;
195	status = "okay";
196
197	flash: m25p80@0 {
198		#address-cells = <1>;
199		#size-cells = <1>;
200		compatible = "st,m25p32", "jedec,spi-nor";
201		spi-max-frequency = <20000000>;
202		reg = <0>;
203	};
204};
205
206&fec {
207	pinctrl-names = "default";
208	pinctrl-0 = <&pinctrl_enet>;
209	phy-mode = "rgmii-id";
210	phy-handle = <&phy>;
211	fsl,magic-packet;
212	status = "okay";
213
214	mdio {
215		#address-cells = <1>;
216		#size-cells = <0>;
217
218		phy: ethernet-phy@1 {
219			reg = <1>;
220			qca,clk-out-frequency = <125000000>;
221			reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
222			reset-assert-us = <10000>;
223		};
224	};
225};
226
227&hdmi {
228	pinctrl-names = "default";
229	pinctrl-0 = <&pinctrl_hdmi_cec>;
230	ddc-i2c-bus = <&i2c2>;
231	status = "okay";
232};
233
234&i2c1 {
235	clock-frequency = <100000>;
236	pinctrl-names = "default";
237	pinctrl-0 = <&pinctrl_i2c1>;
238	status = "okay";
239
240	codec: wm8962@1a {
241		compatible = "wlf,wm8962";
242		reg = <0x1a>;
243		clocks = <&clks IMX6QDL_CLK_CKO>;
244		DCVDD-supply = <&reg_audio>;
245		DBVDD-supply = <&reg_audio>;
246		AVDD-supply = <&reg_audio>;
247		CPVDD-supply = <&reg_audio>;
248		MICVDD-supply = <&reg_audio>;
249		PLLVDD-supply = <&reg_audio>;
250		SPKVDD1-supply = <&reg_audio>;
251		SPKVDD2-supply = <&reg_audio>;
252		gpio-cfg = <
253			0x0000 /* 0:Default */
254			0x0000 /* 1:Default */
255			0x0013 /* 2:FN_DMICCLK */
256			0x0000 /* 3:Default */
257			0x8014 /* 4:FN_DMICCDAT */
258			0x0000 /* 5:Default */
259		>;
260	};
261
262	accelerometer@1c {
263		compatible = "fsl,mma8451";
264		reg = <0x1c>;
265		pinctrl-names = "default";
266		pinctrl-0 = <&pinctrl_i2c1_mma8451_int>;
267		interrupt-parent = <&gpio1>;
268		interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
269		vdd-supply = <&reg_sensors>;
270		vddio-supply = <&reg_sensors>;
271	};
272
273	ov5642: camera@3c {
274		compatible = "ovti,ov5642";
275		pinctrl-names = "default";
276		pinctrl-0 = <&pinctrl_ov5642>;
277		clocks = <&clks IMX6QDL_CLK_CKO>;
278		clock-names = "xclk";
279		reg = <0x3c>;
280		DOVDD-supply = <&vgen4_reg>; /* 1.8v */
281		AVDD-supply = <&vgen3_reg>;  /* 2.8v, rev C board is VGEN3
282						rev B board is VGEN5 */
283		DVDD-supply = <&vgen2_reg>;  /* 1.5v*/
284		powerdown-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>;
285		reset-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
286		status = "disabled";
287
288		port {
289			ov5642_to_ipu1_csi0_mux: endpoint {
290				remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
291				bus-width = <8>;
292				hsync-active = <1>;
293				vsync-active = <1>;
294			};
295		};
296	};
297};
298
299&i2c2 {
300	clock-frequency = <100000>;
301	pinctrl-names = "default";
302	pinctrl-0 = <&pinctrl_i2c2>;
303	status = "okay";
304
305	touchscreen@4 {
306		compatible = "eeti,egalax_ts";
307		reg = <0x04>;
308		pinctrl-names = "default";
309		pinctrl-0 = <&pinctrl_i2c2_egalax_int>;
310		interrupt-parent = <&gpio6>;
311		interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
312		wakeup-gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>;
313	};
314
315	ov5640: camera@3c {
316		compatible = "ovti,ov5640";
317		pinctrl-names = "default";
318		pinctrl-0 = <&pinctrl_ov5640>;
319		reg = <0x3c>;
320		clocks = <&clks IMX6QDL_CLK_CKO>;
321		clock-names = "xclk";
322		DOVDD-supply = <&vgen4_reg>; /* 1.8v */
323		AVDD-supply = <&vgen3_reg>;  /* 2.8v, rev C board is VGEN3
324						rev B board is VGEN5 */
325		DVDD-supply = <&vgen2_reg>;  /* 1.5v*/
326		powerdown-gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>;
327		reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
328
329		port {
330			ov5640_to_mipi_csi2: endpoint {
331				remote-endpoint = <&mipi_csi2_in>;
332				clock-lanes = <0>;
333				data-lanes = <1 2>;
334			};
335		};
336	};
337
338	pmic: pfuze100@8 {
339		compatible = "fsl,pfuze100";
340		reg = <0x08>;
341
342		regulators {
343			sw1a_reg: sw1ab {
344				regulator-min-microvolt = <300000>;
345				regulator-max-microvolt = <1875000>;
346				regulator-boot-on;
347				regulator-always-on;
348				regulator-ramp-delay = <6250>;
349			};
350
351			sw1c_reg: sw1c {
352				regulator-min-microvolt = <300000>;
353				regulator-max-microvolt = <1875000>;
354				regulator-boot-on;
355				regulator-always-on;
356				regulator-ramp-delay = <6250>;
357			};
358
359			sw2_reg: sw2 {
360				regulator-min-microvolt = <800000>;
361				regulator-max-microvolt = <3300000>;
362				regulator-boot-on;
363				regulator-always-on;
364				regulator-ramp-delay = <6250>;
365			};
366
367			sw3a_reg: sw3a {
368				regulator-min-microvolt = <400000>;
369				regulator-max-microvolt = <1975000>;
370				regulator-boot-on;
371				regulator-always-on;
372			};
373
374			sw3b_reg: sw3b {
375				regulator-min-microvolt = <400000>;
376				regulator-max-microvolt = <1975000>;
377				regulator-boot-on;
378				regulator-always-on;
379			};
380
381			sw4_reg: sw4 {
382				regulator-min-microvolt = <800000>;
383				regulator-max-microvolt = <3300000>;
384				regulator-always-on;
385			};
386
387			swbst_reg: swbst {
388				regulator-min-microvolt = <5000000>;
389				regulator-max-microvolt = <5150000>;
390			};
391
392			snvs_reg: vsnvs {
393				regulator-min-microvolt = <1000000>;
394				regulator-max-microvolt = <3000000>;
395				regulator-boot-on;
396				regulator-always-on;
397			};
398
399			vref_reg: vrefddr {
400				regulator-boot-on;
401				regulator-always-on;
402			};
403
404			vgen1_reg: vgen1 {
405				regulator-min-microvolt = <800000>;
406				regulator-max-microvolt = <1550000>;
407			};
408
409			vgen2_reg: vgen2 {
410				regulator-min-microvolt = <800000>;
411				regulator-max-microvolt = <1550000>;
412			};
413
414			vgen3_reg: vgen3 {
415				regulator-min-microvolt = <1800000>;
416				regulator-max-microvolt = <3300000>;
417			};
418
419			vgen4_reg: vgen4 {
420				regulator-min-microvolt = <1800000>;
421				regulator-max-microvolt = <3300000>;
422				regulator-always-on;
423			};
424
425			vgen5_reg: vgen5 {
426				regulator-min-microvolt = <1800000>;
427				regulator-max-microvolt = <3300000>;
428				regulator-always-on;
429			};
430
431			vgen6_reg: vgen6 {
432				regulator-min-microvolt = <1800000>;
433				regulator-max-microvolt = <3300000>;
434				regulator-always-on;
435			};
436		};
437	};
438};
439
440&i2c3 {
441	clock-frequency = <100000>;
442	pinctrl-names = "default";
443	pinctrl-0 = <&pinctrl_i2c3>;
444	status = "okay";
445
446	egalax_ts@4 {
447		compatible = "eeti,egalax_ts";
448		reg = <0x04>;
449		interrupt-parent = <&gpio6>;
450		interrupts = <7 2>;
451		wakeup-gpios = <&gpio6 7 0>;
452	};
453
454	magnetometer@e {
455		compatible = "fsl,mag3110";
456		reg = <0x0e>;
457		pinctrl-names = "default";
458		pinctrl-0 = <&pinctrl_i2c3_mag3110_int>;
459		interrupt-parent = <&gpio3>;
460		interrupts = <16 IRQ_TYPE_EDGE_RISING>;
461		vdd-supply = <&reg_sensors>;
462		vddio-supply = <&reg_sensors>;
463	};
464
465	light-sensor@44 {
466		compatible = "isil,isl29023";
467		reg = <0x44>;
468		pinctrl-names = "default";
469		pinctrl-0 = <&pinctrl_i2c3_isl29023_int>;
470		interrupt-parent = <&gpio3>;
471		interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
472		vcc-supply = <&reg_sensors>;
473	};
474};
475
476&iomuxc {
477	pinctrl-names = "default";
478	pinctrl-0 = <&pinctrl_hog>;
479
480	imx6qdl-sabresd {
481		pinctrl_hog: hoggrp {
482			fsl,pins = <
483				MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0
484				MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
485				MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
486				MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
487				MX6QDL_PAD_GPIO_0__CCM_CLKO1    0x130b0
488				MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0
489				MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
490				MX6QDL_PAD_EIM_D22__GPIO3_IO22  0x1b0b0
491				MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0
492			>;
493		};
494
495		pinctrl_audmux: audmuxgrp {
496			fsl,pins = <
497				MX6QDL_PAD_CSI0_DAT7__AUD3_RXD		0x130b0
498				MX6QDL_PAD_CSI0_DAT4__AUD3_TXC		0x130b0
499				MX6QDL_PAD_CSI0_DAT5__AUD3_TXD		0x110b0
500				MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS		0x130b0
501			>;
502		};
503
504		pinctrl_ecspi1: ecspi1grp {
505			fsl,pins = <
506				MX6QDL_PAD_KEY_COL1__ECSPI1_MISO	0x100b1
507				MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI	0x100b1
508				MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK	0x100b1
509				MX6QDL_PAD_KEY_ROW1__GPIO4_IO09		0x1b0b0
510			>;
511		};
512
513		pinctrl_enet: enetgrp {
514			fsl,pins = <
515				MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
516				MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
517				MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b030
518				MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b030
519				MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b030
520				MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b030
521				MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b030
522				MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b030
523				MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
524				MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
525				MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b030
526				MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b030
527				MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
528				MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
529				MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b030
530				MX6QDL_PAD_GPIO_16__ENET_REF_CLK	0x4001b0a8
531			>;
532		};
533
534		pinctrl_gpio_keys: gpio_keysgrp {
535			fsl,pins = <
536				MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0
537				MX6QDL_PAD_GPIO_4__GPIO1_IO04  0x1b0b0
538				MX6QDL_PAD_GPIO_5__GPIO1_IO05  0x1b0b0
539			>;
540		};
541
542		pinctrl_hdmi_cec: hdmicecgrp {
543			fsl,pins = <
544				MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE	0x1f8b0
545			>;
546		};
547
548		pinctrl_i2c1: i2c1grp {
549			fsl,pins = <
550				MX6QDL_PAD_CSI0_DAT8__I2C1_SDA		0x4001b8b1
551				MX6QDL_PAD_CSI0_DAT9__I2C1_SCL		0x4001b8b1
552			>;
553		};
554
555		pinctrl_i2c1_mma8451_int: i2c1mma8451intgrp {
556			fsl,pins = <
557				MX6QDL_PAD_SD1_CMD__GPIO1_IO18		0xb0b1
558			>;
559		};
560
561		pinctrl_i2c2: i2c2grp {
562			fsl,pins = <
563				MX6QDL_PAD_KEY_COL3__I2C2_SCL		0x4001b8b1
564				MX6QDL_PAD_KEY_ROW3__I2C2_SDA		0x4001b8b1
565			>;
566		};
567
568		pinctrl_i2c2_egalax_int: i2c2egalaxintgrp {
569			fsl,pins = <
570				MX6QDL_PAD_NANDF_ALE__GPIO6_IO08	0x1b0b0
571			>;
572		};
573
574		pinctrl_i2c3: i2c3grp {
575			fsl,pins = <
576				MX6QDL_PAD_GPIO_3__I2C3_SCL		0x4001b8b1
577				MX6QDL_PAD_GPIO_6__I2C3_SDA		0x4001b8b1
578			>;
579		};
580
581		pinctrl_i2c3_isl29023_int: i2c3isl29023intgrp {
582			fsl,pins = <
583				MX6QDL_PAD_EIM_DA9__GPIO3_IO09		0xb0b1
584			>;
585		};
586
587		pinctrl_i2c3_mag3110_int: i2c3mag3110intgrp {
588			fsl,pins = <
589				MX6QDL_PAD_EIM_D16__GPIO3_IO16		0xb0b1
590			>;
591		};
592
593		pinctrl_ipu1_csi0: ipu1csi0grp {
594			fsl,pins = <
595				MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12    0x1b0b0
596				MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13    0x1b0b0
597				MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14    0x1b0b0
598				MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15    0x1b0b0
599				MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16    0x1b0b0
600				MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17    0x1b0b0
601				MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18    0x1b0b0
602				MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19    0x1b0b0
603				MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK   0x1b0b0
604				MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC      0x1b0b0
605				MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC     0x1b0b0
606			>;
607		};
608
609		pinctrl_ov5640: ov5640grp {
610			fsl,pins = <
611				MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x1b0b0
612				MX6QDL_PAD_SD1_CLK__GPIO1_IO20  0x1b0b0
613			>;
614		};
615
616		pinctrl_ov5642: ov5642grp {
617			fsl,pins = <
618				MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0
619				MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b0
620			>;
621		};
622
623		pinctrl_pcie: pciegrp {
624			fsl,pins = <
625				MX6QDL_PAD_GPIO_17__GPIO7_IO12	0x1b0b0
626			>;
627		};
628
629		pinctrl_pcie_reg: pciereggrp {
630			fsl,pins = <
631				MX6QDL_PAD_EIM_D19__GPIO3_IO19	0x1b0b0
632			>;
633		};
634
635		pinctrl_pwm1: pwm1grp {
636			fsl,pins = <
637				MX6QDL_PAD_SD1_DAT3__PWM1_OUT		0x1b0b1
638			>;
639		};
640
641		pinctrl_sensors_reg: sensorsreggrp {
642			fsl,pins = <
643				MX6QDL_PAD_EIM_EB3__GPIO2_IO31		0x1b0b0
644			>;
645		};
646
647		pinctrl_uart1: uart1grp {
648			fsl,pins = <
649				MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA	0x1b0b1
650				MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA	0x1b0b1
651			>;
652		};
653
654		pinctrl_usbotg: usbotggrp {
655			fsl,pins = <
656				MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID	0x17059
657			>;
658		};
659
660		pinctrl_usdhc2: usdhc2grp {
661			fsl,pins = <
662				MX6QDL_PAD_SD2_CMD__SD2_CMD		0x17059
663				MX6QDL_PAD_SD2_CLK__SD2_CLK		0x10059
664				MX6QDL_PAD_SD2_DAT0__SD2_DATA0		0x17059
665				MX6QDL_PAD_SD2_DAT1__SD2_DATA1		0x17059
666				MX6QDL_PAD_SD2_DAT2__SD2_DATA2		0x17059
667				MX6QDL_PAD_SD2_DAT3__SD2_DATA3		0x17059
668				MX6QDL_PAD_NANDF_D4__SD2_DATA4		0x17059
669				MX6QDL_PAD_NANDF_D5__SD2_DATA5		0x17059
670				MX6QDL_PAD_NANDF_D6__SD2_DATA6		0x17059
671				MX6QDL_PAD_NANDF_D7__SD2_DATA7		0x17059
672			>;
673		};
674
675		pinctrl_usdhc3: usdhc3grp {
676			fsl,pins = <
677				MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17059
678				MX6QDL_PAD_SD3_CLK__SD3_CLK		0x10059
679				MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x17059
680				MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059
681				MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059
682				MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059
683				MX6QDL_PAD_SD3_DAT4__SD3_DATA4		0x17059
684				MX6QDL_PAD_SD3_DAT5__SD3_DATA5		0x17059
685				MX6QDL_PAD_SD3_DAT6__SD3_DATA6		0x17059
686				MX6QDL_PAD_SD3_DAT7__SD3_DATA7		0x17059
687			>;
688		};
689
690		pinctrl_usdhc4: usdhc4grp {
691			fsl,pins = <
692				MX6QDL_PAD_SD4_CMD__SD4_CMD		0x17059
693				MX6QDL_PAD_SD4_CLK__SD4_CLK		0x10059
694				MX6QDL_PAD_SD4_DAT0__SD4_DATA0		0x17059
695				MX6QDL_PAD_SD4_DAT1__SD4_DATA1		0x17059
696				MX6QDL_PAD_SD4_DAT2__SD4_DATA2		0x17059
697				MX6QDL_PAD_SD4_DAT3__SD4_DATA3		0x17059
698				MX6QDL_PAD_SD4_DAT4__SD4_DATA4		0x17059
699				MX6QDL_PAD_SD4_DAT5__SD4_DATA5		0x17059
700				MX6QDL_PAD_SD4_DAT6__SD4_DATA6		0x17059
701				MX6QDL_PAD_SD4_DAT7__SD4_DATA7		0x17059
702			>;
703		};
704
705		pinctrl_wdog: wdoggrp {
706			fsl,pins = <
707				MX6QDL_PAD_GPIO_1__WDOG2_B		0x1b0b0
708			>;
709		};
710	};
711
712	gpio_leds {
713		pinctrl_gpio_leds: gpioledsgrp {
714			fsl,pins = <
715				MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
716			>;
717		};
718	};
719};
720
721&ldb {
722	status = "okay";
723
724	lvds-channel@1 {
725		fsl,data-mapping = "spwg";
726		fsl,data-width = <18>;
727		status = "okay";
728
729		port@4 {
730			reg = <4>;
731
732			lvds0_out: endpoint {
733				remote-endpoint = <&panel_in>;
734			};
735		};
736	};
737};
738
739&pcie {
740	pinctrl-names = "default";
741	pinctrl-0 = <&pinctrl_pcie>;
742	reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
743	vpcie-supply = <&reg_pcie>;
744	status = "okay";
745};
746
747&pwm1 {
748	#pwm-cells = <2>;
749	pinctrl-names = "default";
750	pinctrl-0 = <&pinctrl_pwm1>;
751	status = "okay";
752};
753
754&reg_arm {
755       vin-supply = <&sw1a_reg>;
756};
757
758&reg_pu {
759       vin-supply = <&sw1c_reg>;
760};
761
762&reg_soc {
763       vin-supply = <&sw1c_reg>;
764};
765
766&reg_vdd1p1 {
767	vin-supply = <&vgen5_reg>;
768};
769
770&reg_vdd2p5 {
771	vin-supply = <&vgen5_reg>;
772};
773
774&snvs_poweroff {
775	status = "okay";
776};
777
778&snvs_pwrkey {
779	status = "okay";
780};
781
782&ssi2 {
783	status = "okay";
784};
785
786&uart1 {
787	pinctrl-names = "default";
788	pinctrl-0 = <&pinctrl_uart1>;
789	status = "okay";
790};
791
792&usbh1 {
793	vbus-supply = <&reg_usb_h1_vbus>;
794	status = "okay";
795};
796
797&usbotg {
798	vbus-supply = <&reg_usb_otg_vbus>;
799	pinctrl-names = "default";
800	pinctrl-0 = <&pinctrl_usbotg>;
801	disable-over-current;
802	status = "okay";
803};
804
805&usdhc2 {
806	pinctrl-names = "default";
807	pinctrl-0 = <&pinctrl_usdhc2>;
808	bus-width = <8>;
809	cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
810	wp-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
811	status = "okay";
812};
813
814&usdhc3 {
815	pinctrl-names = "default";
816	pinctrl-0 = <&pinctrl_usdhc3>;
817	bus-width = <8>;
818	cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
819	wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
820	status = "okay";
821};
822
823&usdhc4 {
824	pinctrl-names = "default";
825	pinctrl-0 = <&pinctrl_usdhc4>;
826	bus-width = <8>;
827	non-removable;
828	no-1-8-v;
829	status = "okay";
830};
831
832&wdog1 {
833	status = "disabled";
834};
835
836&wdog2 {
837	pinctrl-names = "default";
838	pinctrl-0 = <&pinctrl_wdog>;
839	fsl,ext-reset-output;
840	status = "okay";
841};
842