1// SPDX-License-Identifier: GPL-2.0+ OR MIT
2/*
3 * Copyright 2016-2020 Toradex
4 */
5
6/ {
7	bl: backlight {
8		compatible = "pwm-backlight";
9		pinctrl-names = "default";
10		pinctrl-0 = <&pinctrl_gpio_bl_on>;
11		pwms = <&pwm1 0 5000000 0>;
12		enable-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
13	};
14
15	reg_module_3v3: regulator-module-3v3 {
16		compatible = "regulator-fixed";
17		regulator-name = "+V3.3";
18		regulator-min-microvolt = <3300000>;
19		regulator-max-microvolt = <3300000>;
20		regulator-always-on;
21	};
22
23	reg_module_3v3_avdd: regulator-module-3v3-avdd {
24		compatible = "regulator-fixed";
25		regulator-name = "+V3.3_AVDD_AUDIO";
26		regulator-min-microvolt = <3300000>;
27		regulator-max-microvolt = <3300000>;
28		regulator-always-on;
29	};
30
31	sound {
32		compatible = "simple-audio-card";
33		simple-audio-card,name = "imx7-sgtl5000";
34		simple-audio-card,format = "i2s";
35		simple-audio-card,bitclock-master = <&dailink_master>;
36		simple-audio-card,frame-master = <&dailink_master>;
37		simple-audio-card,cpu {
38			sound-dai = <&sai1>;
39		};
40
41		dailink_master: simple-audio-card,codec {
42			sound-dai = <&codec>;
43			clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
44		};
45	};
46};
47
48&adc1 {
49	vref-supply = <&reg_DCDC3>;
50};
51
52&adc2 {
53	vref-supply = <&reg_DCDC3>;
54};
55
56&cpu0 {
57	cpu-supply = <&reg_DCDC2>;
58};
59
60&ecspi3 {
61	pinctrl-names = "default";
62	pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs>;
63	cs-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>;
64};
65
66&fec1 {
67	pinctrl-names = "default", "sleep";
68	pinctrl-0 = <&pinctrl_enet1>;
69	pinctrl-1 = <&pinctrl_enet1_sleep>;
70	clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
71		<&clks IMX7D_ENET_AXI_ROOT_CLK>,
72		<&clks IMX7D_ENET1_TIME_ROOT_CLK>,
73		<&clks IMX7D_PLL_ENET_MAIN_50M_CLK>;
74	clock-names = "ipg", "ahb", "ptp", "enet_clk_ref";
75	assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
76			  <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
77	assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
78	assigned-clock-rates = <0>, <100000000>;
79	phy-mode = "rmii";
80	phy-supply = <&reg_LDO1>;
81	fsl,magic-packet;
82};
83
84&flexcan1 {
85	pinctrl-names = "default";
86	pinctrl-0 = <&pinctrl_flexcan1>;
87	status = "disabled";
88};
89
90&flexcan2 {
91	pinctrl-names = "default";
92	pinctrl-0 = <&pinctrl_flexcan2>;
93	status = "disabled";
94};
95
96&gpio1 {
97	gpio-line-names = "SODIMM_43",
98			  "SODIMM_45",
99			  "SODIMM_135",
100			  "SODIMM_22",
101			  "",
102			  "",
103			  "SODIMM_37",
104			  "SODIMM_29",
105			  "SODIMM_59",
106			  "SODIMM_28",
107			  "SODIMM_30",
108			  "SODIMM_67",
109			  "",
110			  "",
111			  "SODIMM_188",
112			  "SODIMM_178";
113};
114
115&gpio2 {
116	gpio-line-names = "SODIMM_111",
117			  "SODIMM_113",
118			  "SODIMM_115",
119			  "SODIMM_117",
120			  "SODIMM_119",
121			  "SODIMM_121",
122			  "SODIMM_123",
123			  "SODIMM_125",
124			  "SODIMM_91",
125			  "SODIMM_89",
126			  "SODIMM_105",
127			  "SODIMM_152",
128			  "SODIMM_150",
129			  "SODIMM_95",
130			  "SODIMM_126",
131			  "SODIMM_107",
132			  "SODIMM_114",
133			  "SODIMM_116",
134			  "SODIMM_118",
135			  "SODIMM_120",
136			  "SODIMM_122",
137			  "SODIMM_124",
138			  "SODIMM_127",
139			  "SODIMM_130",
140			  "SODIMM_132",
141			  "SODIMM_134",
142			  "SODIMM_133",
143			  "SODIMM_104",
144			  "SODIMM_106",
145			  "SODIMM_110",
146			  "SODIMM_112",
147			  "SODIMM_128";
148};
149
150&gpio3 {
151	gpio-line-names = "SODIMM_56",
152			  "SODIMM_44",
153			  "SODIMM_68",
154			  "SODIMM_82",
155			  "SODIMM_93",
156			  "SODIMM_76",
157			  "SODIMM_70",
158			  "SODIMM_60",
159			  "SODIMM_58",
160			  "SODIMM_78",
161			  "SODIMM_72",
162			  "SODIMM_80",
163			  "SODIMM_46",
164			  "SODIMM_62",
165			  "SODIMM_48",
166			  "SODIMM_74",
167			  "SODIMM_50",
168			  "SODIMM_52",
169			  "SODIMM_54",
170			  "SODIMM_66",
171			  "SODIMM_64",
172			  "SODIMM_57",
173			  "SODIMM_61",
174			  "SODIMM_136",
175			  "SODIMM_138",
176			  "SODIMM_140",
177			  "SODIMM_142",
178			  "SODIMM_144",
179			  "SODIMM_146";
180};
181
182&gpio4 {
183	gpio-line-names = "SODIMM_35",
184			  "SODIMM_33",
185			  "SODIMM_38",
186			  "SODIMM_36",
187			  "SODIMM_21",
188			  "SODIMM_19",
189			  "SODIMM_131",
190			  "SODIMM_129",
191			  "SODIMM_90",
192			  "SODIMM_92",
193			  "SODIMM_88",
194			  "SODIMM_86",
195			  "SODIMM_81",
196			  "SODIMM_94",
197			  "SODIMM_96",
198			  "SODIMM_75",
199			  "SODIMM_101",
200			  "SODIMM_103",
201			  "SODIMM_79",
202			  "SODIMM_97",
203			  "SODIMM_67",
204			  "SODIMM_59",
205			  "SODIMM_85",
206			  "SODIMM_65";
207};
208
209&gpio5 {
210	gpio-line-names = "SODIMM_69",
211			  "SODIMM_71",
212			  "SODIMM_73",
213			  "SODIMM_47",
214			  "SODIMM_190",
215			  "SODIMM_192",
216			  "SODIMM_49",
217			  "SODIMM_51",
218			  "SODIMM_53",
219			  "",
220			  "",
221			  "SODIMM_98",
222			  "SODIMM_184",
223			  "SODIMM_186",
224			  "SODIMM_23",
225			  "SODIMM_31",
226			  "SODIMM_100",
227			  "SODIMM_102";
228};
229
230&gpio6 {
231	gpio-line-names = "",
232			  "",
233			  "",
234			  "",
235			  "",
236			  "",
237			  "",
238			  "",
239			  "",
240			  "",
241			  "",
242			  "",
243			  "SODIMM_169",
244			  "",
245			  "",
246			  "",
247			  "SODIMM_77",
248			  "SODIMM_24",
249			  "",
250			  "SODIMM_25",
251			  "SODIMM_27",
252			  "SODIMM_32",
253			  "SODIMM_34";
254};
255
256&gpio7 {
257	gpio-line-names = "",
258			  "",
259			  "SODIMM_63",
260			  "SODIMM_55",
261			  "",
262			  "",
263			  "",
264			  "",
265			  "SODIMM_196",
266			  "SODIMM_194",
267			  "",
268			  "SODIMM_99",
269			  "",
270			  "",
271			  "SODIMM_137";
272};
273
274&gpmi {
275	pinctrl-names = "default";
276	pinctrl-0 = <&pinctrl_gpmi_nand>;
277	fsl,use-minimum-ecc;
278	nand-on-flash-bbt;
279	nand-ecc-mode = "hw";
280};
281
282&i2c1 {
283	clock-frequency = <100000>;
284	pinctrl-names = "default", "gpio";
285	pinctrl-0 = <&pinctrl_i2c1 &pinctrl_i2c1_int>;
286	pinctrl-1 = <&pinctrl_i2c1_recovery &pinctrl_i2c1_int>;
287	scl-gpios = <&gpio1 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
288	sda-gpios = <&gpio1 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
289
290	status = "okay";
291
292	codec: sgtl5000@a {
293		compatible = "fsl,sgtl5000";
294		#sound-dai-cells = <0>;
295		reg = <0x0a>;
296		clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
297		pinctrl-names = "default";
298		pinctrl-0 = <&pinctrl_sai1_mclk>;
299		VDDA-supply = <&reg_module_3v3_avdd>;
300		VDDIO-supply = <&reg_module_3v3>;
301		VDDD-supply = <&reg_DCDC3>;
302	};
303
304	ad7879@2c {
305		compatible = "adi,ad7879-1";
306		reg = <0x2c>;
307		interrupt-parent = <&gpio1>;
308		interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
309		touchscreen-max-pressure = <4096>;
310		adi,resistance-plate-x = <120>;
311		adi,first-conversion-delay = /bits/ 8 <3>;
312		adi,acquisition-time = /bits/ 8 <1>;
313		adi,median-filter-size = /bits/ 8 <2>;
314		adi,averaging = /bits/ 8 <1>;
315		adi,conversion-interval = /bits/ 8 <255>;
316	};
317
318	pmic@33 {
319		compatible = "ricoh,rn5t567";
320		reg = <0x33>;
321
322		regulators {
323			reg_DCDC1: DCDC1 {  /* V1.0_SOC */
324				regulator-min-microvolt = <1000000>;
325				regulator-max-microvolt = <1100000>;
326				regulator-boot-on;
327				regulator-always-on;
328			};
329
330			reg_DCDC2: DCDC2 { /* V1.1_ARM */
331				regulator-min-microvolt = <975000>;
332				regulator-max-microvolt = <1100000>;
333				regulator-boot-on;
334				regulator-always-on;
335			};
336
337			reg_DCDC3: DCDC3 { /* V1.8 */
338				regulator-min-microvolt = <1800000>;
339				regulator-max-microvolt = <1800000>;
340				regulator-boot-on;
341				regulator-always-on;
342			};
343
344			reg_DCDC4: DCDC4 { /* V1.35_DRAM */
345				regulator-min-microvolt = <1350000>;
346				regulator-max-microvolt = <1350000>;
347				regulator-boot-on;
348				regulator-always-on;
349			};
350
351			reg_LDO1: LDO1 { /* PWR_EN_+V3.3_ETH */
352				regulator-min-microvolt = <1800000>;
353				regulator-max-microvolt = <3300000>;
354				regulator-boot-on;
355			};
356
357			reg_LDO2: LDO2 { /* +V1.8_SD */
358				regulator-min-microvolt = <1800000>;
359				regulator-max-microvolt = <3300000>;
360				regulator-boot-on;
361				regulator-always-on;
362			};
363
364			reg_LDO3: LDO3 { /* PWR_EN_+V3.3_LPSR */
365				regulator-min-microvolt = <3300000>;
366				regulator-max-microvolt = <3300000>;
367				regulator-boot-on;
368				regulator-always-on;
369			};
370
371			reg_LDO4: LDO4 { /* V1.8_LPSR */
372				regulator-min-microvolt = <1800000>;
373				regulator-max-microvolt = <1800000>;
374				regulator-boot-on;
375				regulator-always-on;
376			};
377
378			reg_LDO5: LDO5 { /* PWR_EN_+V3.3 */
379				regulator-min-microvolt = <3300000>;
380				regulator-max-microvolt = <3300000>;
381				regulator-boot-on;
382				regulator-always-on;
383			};
384		};
385	};
386};
387
388&i2c4 {
389	clock-frequency = <100000>;
390	pinctrl-names = "default", "gpio";
391	pinctrl-0 = <&pinctrl_i2c4>;
392	pinctrl-1 = <&pinctrl_i2c4_recovery>;
393	scl-gpios = <&gpio7 8 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
394	sda-gpios = <&gpio7 9 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
395};
396
397&lcdif {
398	pinctrl-names = "default";
399	pinctrl-0 = <&pinctrl_lcdif_dat
400		     &pinctrl_lcdif_ctrl>;
401};
402
403&pwm1 {
404	pinctrl-names = "default";
405	pinctrl-0 = <&pinctrl_pwm1>;
406};
407
408&pwm2 {
409	pinctrl-names = "default";
410	pinctrl-0 = <&pinctrl_pwm2>;
411};
412
413&pwm3 {
414	pinctrl-names = "default";
415	pinctrl-0 = <&pinctrl_pwm3>;
416};
417
418&pwm4 {
419	pinctrl-names = "default";
420	pinctrl-0 = <&pinctrl_pwm4>;
421};
422
423&reg_1p0d {
424	vin-supply = <&reg_DCDC3>;
425};
426
427&sai1 {
428	pinctrl-names = "default";
429	pinctrl-0 = <&pinctrl_sai1>;
430	status = "okay";
431};
432
433&uart1 {
434	pinctrl-names = "default";
435	pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1 &pinctrl_uart1_ctrl2>;
436	assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
437	assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
438	uart-has-rtscts;
439	fsl,dte-mode;
440};
441
442&uart2 {
443	pinctrl-names = "default";
444	pinctrl-0 = <&pinctrl_uart2>;
445	assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>;
446	assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
447	uart-has-rtscts;
448	fsl,dte-mode;
449};
450
451&uart3 {
452	pinctrl-names = "default";
453	pinctrl-0 = <&pinctrl_uart3>;
454	assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>;
455	assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
456	fsl,dte-mode;
457};
458
459&usbotg1 {
460	dr_mode = "host";
461};
462
463&usdhc1 {
464	pinctrl-names = "default";
465	pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_cd_usdhc1>;
466	cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
467	disable-wp;
468	vqmmc-supply = <&reg_LDO2>;
469};
470
471&usdhc3 {
472	pinctrl-names = "default", "state_100mhz", "state_200mhz";
473	pinctrl-0 = <&pinctrl_usdhc3>;
474	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
475	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
476	assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
477	assigned-clock-rates = <400000000>;
478	bus-width = <8>;
479	fsl,tuning-step = <2>;
480	vmmc-supply = <&reg_module_3v3>;
481	vqmmc-supply = <&reg_DCDC3>;
482	non-removable;
483	sdhci-caps-mask = <0x80000000 0x0>;
484};
485
486&iomuxc {
487	pinctrl-names = "default";
488	pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3 &pinctrl_gpio4
489		     &pinctrl_gpio7 &pinctrl_usbc_det>;
490
491	pinctrl_gpio1: gpio1-grp {
492		fsl,pins = <
493			MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16	0x14 /* SODIMM 77 */
494			MX7D_PAD_EPDC_DATA09__GPIO2_IO9		0x14 /* SODIMM 89 */
495			MX7D_PAD_EPDC_DATA08__GPIO2_IO8		0x74 /* SODIMM 91 */
496			MX7D_PAD_LCD_RESET__GPIO3_IO4		0x14 /* SODIMM 93 */
497			MX7D_PAD_EPDC_DATA13__GPIO2_IO13	0x14 /* SODIMM 95 */
498			MX7D_PAD_ENET1_RGMII_TXC__GPIO7_IO11	0x14 /* SODIMM 99 */
499			MX7D_PAD_EPDC_DATA10__GPIO2_IO10	0x74 /* SODIMM 105 */
500			MX7D_PAD_EPDC_DATA00__GPIO2_IO0		0x14 /* SODIMM 111 */
501			MX7D_PAD_EPDC_DATA01__GPIO2_IO1		0x14 /* SODIMM 113 */
502			MX7D_PAD_EPDC_DATA02__GPIO2_IO2		0x14 /* SODIMM 115 */
503			MX7D_PAD_EPDC_DATA03__GPIO2_IO3		0x14 /* SODIMM 117 */
504			MX7D_PAD_EPDC_DATA04__GPIO2_IO4		0x14 /* SODIMM 119 */
505			MX7D_PAD_EPDC_DATA05__GPIO2_IO5		0x14 /* SODIMM 121 */
506			MX7D_PAD_EPDC_DATA06__GPIO2_IO6		0x14 /* SODIMM 123 */
507			MX7D_PAD_EPDC_DATA07__GPIO2_IO7		0x14 /* SODIMM 125 */
508			MX7D_PAD_EPDC_SDCE2__GPIO2_IO22		0x14 /* SODIMM 127 */
509			MX7D_PAD_UART3_RTS_B__GPIO4_IO6		0x14 /* SODIMM 131 */
510			MX7D_PAD_EPDC_GDRL__GPIO2_IO26		0x14 /* SODIMM 133 */
511			MX7D_PAD_SAI1_RX_DATA__GPIO6_IO12	0x14 /* SODIMM 169 */
512			MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17	0x14 /* SODIMM 24 */
513			MX7D_PAD_SD2_DATA2__GPIO5_IO16		0x14 /* SODIMM 100 */
514			MX7D_PAD_SD2_DATA3__GPIO5_IO17		0x14 /* SODIMM 102 */
515			MX7D_PAD_EPDC_GDSP__GPIO2_IO27		0x14 /* SODIMM 104 */
516			MX7D_PAD_EPDC_BDR1__GPIO2_IO29		0x14 /* SODIMM 110 */
517			MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30	0x14 /* SODIMM 112 */
518			MX7D_PAD_EPDC_SDCLK__GPIO2_IO16		0x14 /* SODIMM 114 */
519			MX7D_PAD_EPDC_SDLE__GPIO2_IO17		0x14 /* SODIMM 116 */
520			MX7D_PAD_EPDC_SDOE__GPIO2_IO18		0x14 /* SODIMM 118 */
521			MX7D_PAD_EPDC_SDSHR__GPIO2_IO19		0x14 /* SODIMM 120 */
522			MX7D_PAD_EPDC_SDCE0__GPIO2_IO20		0x14 /* SODIMM 122 */
523			MX7D_PAD_EPDC_SDCE1__GPIO2_IO21		0x14 /* SODIMM 124 */
524			MX7D_PAD_EPDC_DATA14__GPIO2_IO14	0x14 /* SODIMM 126 */
525			MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31	0x14 /* SODIMM 128 */
526			MX7D_PAD_EPDC_SDCE3__GPIO2_IO23		0x14 /* SODIMM 130 */
527			MX7D_PAD_EPDC_GDCLK__GPIO2_IO24		0x14 /* SODIMM 132 */
528			MX7D_PAD_EPDC_GDOE__GPIO2_IO25		0x14 /* SODIMM 134 */
529			MX7D_PAD_EPDC_DATA12__GPIO2_IO12	0x14 /* SODIMM 150 */
530			MX7D_PAD_EPDC_DATA11__GPIO2_IO11	0x14 /* SODIMM 152 */
531			MX7D_PAD_SD2_CLK__GPIO5_IO12		0x14 /* SODIMM 184 */
532			MX7D_PAD_SD2_CMD__GPIO5_IO13		0x14 /* SODIMM 186 */
533		>;
534	};
535
536	pinctrl_gpio2: gpio2-grp { /* On X22 Camera interface */
537		fsl,pins = <
538			MX7D_PAD_ECSPI2_SS0__GPIO4_IO23		0x14 /* SODIMM 65 */
539			MX7D_PAD_SD1_CD_B__GPIO5_IO0		0x74 /* SODIMM 69 */
540			MX7D_PAD_I2C4_SDA__GPIO4_IO15		0x14 /* SODIMM 75 */
541			MX7D_PAD_ECSPI1_MISO__GPIO4_IO18	0x14 /* SODIMM 79 */
542			MX7D_PAD_I2C3_SCL__GPIO4_IO12		0x14 /* SODIMM 81 */
543			MX7D_PAD_ECSPI2_MISO__GPIO4_IO22	0x14 /* SODIMM 85 */
544			MX7D_PAD_ECSPI1_SS0__GPIO4_IO19		0x14 /* SODIMM 97 */
545			MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16	0x14 /* SODIMM 101 */
546			MX7D_PAD_ECSPI1_MOSI__GPIO4_IO17	0x14 /* SODIMM 103 */
547			MX7D_PAD_I2C3_SDA__GPIO4_IO13		0x14 /* SODIMM 94 */
548			MX7D_PAD_I2C4_SCL__GPIO4_IO14		0x14 /* SODIMM 96 */
549			MX7D_PAD_SD2_RESET_B__GPIO5_IO11	0x14 /* SODIMM 98 */
550		>;
551	};
552
553	pinctrl_gpio3: gpio3-grp { /* LCD 18-23 */
554		fsl,pins = <
555			MX7D_PAD_LCD_DATA18__GPIO3_IO23		0x14 /* SODIMM 136 */
556			MX7D_PAD_LCD_DATA19__GPIO3_IO24		0x14 /* SODIMM 138 */
557			MX7D_PAD_LCD_DATA20__GPIO3_IO25		0x14 /* SODIMM 140 */
558			MX7D_PAD_LCD_DATA21__GPIO3_IO26		0x14 /* SODIMM 142 */
559			MX7D_PAD_LCD_DATA22__GPIO3_IO27		0x74 /* SODIMM 144 */
560			MX7D_PAD_LCD_DATA23__GPIO3_IO28		0x74 /* SODIMM 146 */
561		>;
562	};
563
564	pinctrl_gpio4: gpio4-grp { /* Alternatively CAN2 */
565		fsl,pins = <
566			MX7D_PAD_GPIO1_IO15__GPIO1_IO15		0x14 /* SODIMM 178 */
567			MX7D_PAD_GPIO1_IO14__GPIO1_IO14		0x14 /* SODIMM 188 */
568		>;
569	};
570
571	pinctrl_gpio7: gpio7-grp { /* Alternatively CAN1 */
572		fsl,pins = <
573			MX7D_PAD_ENET1_RGMII_RD3__GPIO7_IO3	0x14 /* SODIMM 55 */
574			MX7D_PAD_ENET1_RGMII_RD2__GPIO7_IO2	0x14 /* SODIMM 63 */
575		>;
576	};
577
578	pinctrl_i2c1_int: i2c1-int-grp { /* PMIC / TOUCH */
579		fsl,pins = <
580			MX7D_PAD_GPIO1_IO13__GPIO1_IO13	0x79
581		>;
582	};
583
584	pinctrl_can_int: can-int-grp {
585		fsl,pins = <
586			MX7D_PAD_SD1_RESET_B__GPIO5_IO2		0X14 /* SODIMM 73 */
587		>;
588	};
589
590	pinctrl_enet1: enet1grp {
591		fsl,pins = <
592			MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL	0x73
593			MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0	0x73
594			MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1	0x73
595			MX7D_PAD_ENET1_RGMII_RXC__ENET1_RX_ER		0x73
596
597			MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL	0x73
598			MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0	0x73
599			MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1	0x73
600			MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1		0x73
601			MX7D_PAD_SD2_CD_B__ENET1_MDIO			0x3
602			MX7D_PAD_SD2_WP__ENET1_MDC			0x3
603		>;
604	};
605
606	pinctrl_enet1_sleep: enet1sleepgrp {
607		fsl,pins = <
608			MX7D_PAD_ENET1_RGMII_RX_CTL__GPIO7_IO4		0x0
609			MX7D_PAD_ENET1_RGMII_RD0__GPIO7_IO0		0x0
610			MX7D_PAD_ENET1_RGMII_RD1__GPIO7_IO1		0x0
611			MX7D_PAD_ENET1_RGMII_RXC__GPIO7_IO5		0x0
612
613			MX7D_PAD_ENET1_RGMII_TX_CTL__GPIO7_IO10		0x0
614			MX7D_PAD_ENET1_RGMII_TD0__GPIO7_IO6		0x0
615			MX7D_PAD_ENET1_RGMII_TD1__GPIO7_IO7		0x0
616			MX7D_PAD_GPIO1_IO12__GPIO1_IO12			0x0
617			MX7D_PAD_SD2_CD_B__GPIO5_IO9			0x0
618			MX7D_PAD_SD2_WP__GPIO5_IO10			0x0
619		>;
620	};
621
622	pinctrl_ecspi3_cs: ecspi3-cs-grp {
623		fsl,pins = <
624			MX7D_PAD_I2C2_SDA__GPIO4_IO11		0x14
625		>;
626	};
627
628	pinctrl_ecspi3: ecspi3-grp {
629		fsl,pins = <
630			MX7D_PAD_I2C1_SCL__ECSPI3_MISO		0x2
631			MX7D_PAD_I2C1_SDA__ECSPI3_MOSI		0x2
632			MX7D_PAD_I2C2_SCL__ECSPI3_SCLK		0x2
633		>;
634	};
635
636	pinctrl_flexcan1: flexcan1-grp {
637		fsl,pins = <
638			MX7D_PAD_ENET1_RGMII_RD3__FLEXCAN1_TX	0x79 /* SODIMM 55 */
639			MX7D_PAD_ENET1_RGMII_RD2__FLEXCAN1_RX	0x79 /* SODIMM 63 */
640		>;
641	};
642
643	pinctrl_flexcan2: flexcan2-grp {
644		fsl,pins = <
645			MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX	0x79 /* SODIMM 188 */
646			MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX	0x79 /* SODIMM 178 */
647		>;
648	};
649
650	pinctrl_gpio_bl_on: gpio-bl-on {
651		fsl,pins = <
652			MX7D_PAD_SD1_WP__GPIO5_IO1		0x14 /* SODIMM 71 */
653		>;
654	};
655
656	pinctrl_gpmi_nand: gpmi-nand-grp {
657		fsl,pins = <
658			MX7D_PAD_SD3_CLK__NAND_CLE		0x71
659			MX7D_PAD_SD3_CMD__NAND_ALE		0x71
660			MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B	0x71
661			MX7D_PAD_SAI1_TX_DATA__NAND_READY_B	0x74
662			MX7D_PAD_SD3_STROBE__NAND_RE_B		0x71
663			MX7D_PAD_SD3_RESET_B__NAND_WE_B		0x71
664			MX7D_PAD_SD3_DATA0__NAND_DATA00		0x71
665			MX7D_PAD_SD3_DATA1__NAND_DATA01		0x71
666			MX7D_PAD_SD3_DATA2__NAND_DATA02		0x71
667			MX7D_PAD_SD3_DATA3__NAND_DATA03		0x71
668			MX7D_PAD_SD3_DATA4__NAND_DATA04		0x71
669			MX7D_PAD_SD3_DATA5__NAND_DATA05		0x71
670			MX7D_PAD_SD3_DATA6__NAND_DATA06		0x71
671			MX7D_PAD_SD3_DATA7__NAND_DATA07		0x71
672		>;
673	};
674
675	pinctrl_i2c4: i2c4-grp {
676		fsl,pins = <
677			MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA	0x4000007f
678			MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL	0x4000007f
679		>;
680	};
681
682	pinctrl_i2c4_recovery: i2c4-recoverygrp {
683		fsl,pins = <
684			MX7D_PAD_ENET1_RGMII_TD2__GPIO7_IO8	0x4000007f
685			MX7D_PAD_ENET1_RGMII_TD3__GPIO7_IO9	0x4000007f
686		>;
687	};
688
689	pinctrl_lcdif_dat: lcdif-dat-grp {
690		fsl,pins = <
691			MX7D_PAD_LCD_DATA00__LCD_DATA0		0x79
692			MX7D_PAD_LCD_DATA01__LCD_DATA1		0x79
693			MX7D_PAD_LCD_DATA02__LCD_DATA2		0x79
694			MX7D_PAD_LCD_DATA03__LCD_DATA3		0x79
695			MX7D_PAD_LCD_DATA04__LCD_DATA4		0x79
696			MX7D_PAD_LCD_DATA05__LCD_DATA5		0x79
697			MX7D_PAD_LCD_DATA06__LCD_DATA6		0x79
698			MX7D_PAD_LCD_DATA07__LCD_DATA7		0x79
699			MX7D_PAD_LCD_DATA08__LCD_DATA8		0x79
700			MX7D_PAD_LCD_DATA09__LCD_DATA9		0x79
701			MX7D_PAD_LCD_DATA10__LCD_DATA10		0x79
702			MX7D_PAD_LCD_DATA11__LCD_DATA11		0x79
703			MX7D_PAD_LCD_DATA12__LCD_DATA12		0x79
704			MX7D_PAD_LCD_DATA13__LCD_DATA13		0x79
705			MX7D_PAD_LCD_DATA14__LCD_DATA14		0x79
706			MX7D_PAD_LCD_DATA15__LCD_DATA15		0x79
707			MX7D_PAD_LCD_DATA16__LCD_DATA16		0x79
708			MX7D_PAD_LCD_DATA17__LCD_DATA17		0x79
709		>;
710	};
711
712	pinctrl_lcdif_dat_24: lcdif-dat-24-grp {
713		fsl,pins = <
714			MX7D_PAD_LCD_DATA18__LCD_DATA18		0x79
715			MX7D_PAD_LCD_DATA19__LCD_DATA19		0x79
716			MX7D_PAD_LCD_DATA20__LCD_DATA20		0x79
717			MX7D_PAD_LCD_DATA21__LCD_DATA21		0x79
718			MX7D_PAD_LCD_DATA22__LCD_DATA22		0x79
719			MX7D_PAD_LCD_DATA23__LCD_DATA23		0x79
720		>;
721	};
722
723	pinctrl_lcdif_ctrl: lcdif-ctrl-grp {
724		fsl,pins = <
725			MX7D_PAD_LCD_CLK__LCD_CLK		0x79
726			MX7D_PAD_LCD_ENABLE__LCD_ENABLE		0x79
727			MX7D_PAD_LCD_VSYNC__LCD_VSYNC		0x79
728			MX7D_PAD_LCD_HSYNC__LCD_HSYNC		0x79
729		>;
730	};
731
732	pinctrl_pwm1: pwm1-grp {
733		fsl,pins = <
734			MX7D_PAD_GPIO1_IO08__PWM1_OUT		0x79
735			MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21	0x4
736		>;
737	};
738
739	pinctrl_pwm2: pwm2-grp {
740		fsl,pins = <
741			MX7D_PAD_GPIO1_IO09__PWM2_OUT		0x79
742		>;
743	};
744
745	pinctrl_pwm3: pwm3-grp {
746		fsl,pins = <
747			MX7D_PAD_GPIO1_IO10__PWM3_OUT		0x79
748		>;
749	};
750
751	pinctrl_pwm4: pwm4-grp {
752		fsl,pins = <
753			MX7D_PAD_GPIO1_IO11__PWM4_OUT		0x79
754			MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20	0x4
755		>;
756	};
757
758	pinctrl_uart1: uart1-grp {
759		fsl,pins = <
760			MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX	0x79
761			MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX	0x79
762			MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS	0x79
763			MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS	0x79
764		>;
765	};
766
767	pinctrl_uart1_ctrl1: uart1-ctrl1-grp {
768		fsl,pins = <
769			MX7D_PAD_SD2_DATA1__GPIO5_IO15		0x14 /* DCD */
770			MX7D_PAD_SD2_DATA0__GPIO5_IO14		0x14 /* DTR */
771		>;
772	};
773
774	pinctrl_uart2: uart2-grp {
775		fsl,pins = <
776			MX7D_PAD_UART2_TX_DATA__UART2_DTE_RX 0x79
777			MX7D_PAD_UART2_RX_DATA__UART2_DTE_TX 0x79
778			MX7D_PAD_SAI2_RX_DATA__UART2_DTE_RTS 0x79
779			MX7D_PAD_SAI2_TX_DATA__UART2_DTE_CTS 0x79
780		>;
781	};
782	pinctrl_uart3: uart3-grp {
783		fsl,pins = <
784			MX7D_PAD_UART3_TX_DATA__UART3_DTE_RX 0x79
785			MX7D_PAD_UART3_RX_DATA__UART3_DTE_TX 0x79
786		>;
787	};
788
789	pinctrl_usbc_det: gpio-usbc-det {
790		fsl,pins = <
791			MX7D_PAD_ENET1_CRS__GPIO7_IO14	0x14
792		>;
793	};
794
795	pinctrl_usbh_reg: gpio-usbh-vbus {
796		fsl,pins = <
797			MX7D_PAD_UART3_CTS_B__GPIO4_IO7	0x14 /* SODIMM 129 USBH PEN */
798		>;
799	};
800
801	pinctrl_usdhc1: usdhc1-grp {
802		fsl,pins = <
803			MX7D_PAD_SD1_CMD__SD1_CMD	0x59
804			MX7D_PAD_SD1_CLK__SD1_CLK	0x19
805			MX7D_PAD_SD1_DATA0__SD1_DATA0	0x59
806			MX7D_PAD_SD1_DATA1__SD1_DATA1	0x59
807			MX7D_PAD_SD1_DATA2__SD1_DATA2	0x59
808			MX7D_PAD_SD1_DATA3__SD1_DATA3	0x59
809		>;
810	};
811
812	pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
813		fsl,pins = <
814			MX7D_PAD_SD1_CMD__SD1_CMD	0x5a
815			MX7D_PAD_SD1_CLK__SD1_CLK	0x1a
816			MX7D_PAD_SD1_DATA0__SD1_DATA0	0x5a
817			MX7D_PAD_SD1_DATA1__SD1_DATA1	0x5a
818			MX7D_PAD_SD1_DATA2__SD1_DATA2	0x5a
819			MX7D_PAD_SD1_DATA3__SD1_DATA3	0x5a
820		>;
821	};
822
823	pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
824		fsl,pins = <
825			MX7D_PAD_SD1_CMD__SD1_CMD	0x5b
826			MX7D_PAD_SD1_CLK__SD1_CLK	0x1b
827			MX7D_PAD_SD1_DATA0__SD1_DATA0	0x5b
828			MX7D_PAD_SD1_DATA1__SD1_DATA1	0x5b
829			MX7D_PAD_SD1_DATA2__SD1_DATA2	0x5b
830			MX7D_PAD_SD1_DATA3__SD1_DATA3	0x5b
831		>;
832	};
833
834	pinctrl_usdhc3: usdhc3grp {
835		fsl,pins = <
836			MX7D_PAD_SD3_CMD__SD3_CMD		0x59
837			MX7D_PAD_SD3_CLK__SD3_CLK		0x19
838			MX7D_PAD_SD3_DATA0__SD3_DATA0		0x59
839			MX7D_PAD_SD3_DATA1__SD3_DATA1		0x59
840			MX7D_PAD_SD3_DATA2__SD3_DATA2		0x59
841			MX7D_PAD_SD3_DATA3__SD3_DATA3		0x59
842			MX7D_PAD_SD3_DATA4__SD3_DATA4		0x59
843			MX7D_PAD_SD3_DATA5__SD3_DATA5		0x59
844			MX7D_PAD_SD3_DATA6__SD3_DATA6		0x59
845			MX7D_PAD_SD3_DATA7__SD3_DATA7		0x59
846			MX7D_PAD_SD3_STROBE__SD3_STROBE         0x19
847		>;
848	};
849
850	pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
851		fsl,pins = <
852			MX7D_PAD_SD3_CMD__SD3_CMD		0x5a
853			MX7D_PAD_SD3_CLK__SD3_CLK		0x1a
854			MX7D_PAD_SD3_DATA0__SD3_DATA0		0x5a
855			MX7D_PAD_SD3_DATA1__SD3_DATA1		0x5a
856			MX7D_PAD_SD3_DATA2__SD3_DATA2		0x5a
857			MX7D_PAD_SD3_DATA3__SD3_DATA3		0x5a
858			MX7D_PAD_SD3_DATA4__SD3_DATA4		0x5a
859			MX7D_PAD_SD3_DATA5__SD3_DATA5		0x5a
860			MX7D_PAD_SD3_DATA6__SD3_DATA6		0x5a
861			MX7D_PAD_SD3_DATA7__SD3_DATA7		0x5a
862			MX7D_PAD_SD3_STROBE__SD3_STROBE         0x1a
863		>;
864	};
865
866	pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
867		fsl,pins = <
868			MX7D_PAD_SD3_CMD__SD3_CMD		0x5b
869			MX7D_PAD_SD3_CLK__SD3_CLK		0x1b
870			MX7D_PAD_SD3_DATA0__SD3_DATA0		0x5b
871			MX7D_PAD_SD3_DATA1__SD3_DATA1		0x5b
872			MX7D_PAD_SD3_DATA2__SD3_DATA2		0x5b
873			MX7D_PAD_SD3_DATA3__SD3_DATA3		0x5b
874			MX7D_PAD_SD3_DATA4__SD3_DATA4		0x5b
875			MX7D_PAD_SD3_DATA5__SD3_DATA5		0x5b
876			MX7D_PAD_SD3_DATA6__SD3_DATA6		0x5b
877			MX7D_PAD_SD3_DATA7__SD3_DATA7		0x5b
878			MX7D_PAD_SD3_STROBE__SD3_STROBE         0x1b
879		>;
880	};
881
882	pinctrl_sai1: sai1-grp {
883		fsl,pins = <
884			MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK     0x1f
885			MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC	0x1f
886			MX7D_PAD_ENET1_COL__SAI1_TX_DATA0	0x30
887			MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0	0x1f
888		>;
889	};
890
891	pinctrl_sai1_mclk: sai1grp_mclk {
892		fsl,pins = <
893			MX7D_PAD_SAI1_MCLK__SAI1_MCLK           0x1f
894		>;
895	};
896};
897
898&iomuxc_lpsr {
899	pinctrl-names = "default";
900	pinctrl-0 = <&pinctrl_gpio_lpsr>;
901
902	pinctrl_gpio_lpsr: gpio1-grp {
903		fsl,pins = <
904			MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2	0x59
905			MX7D_PAD_LPSR_GPIO1_IO03__GPIO1_IO3	0x59
906		>;
907	};
908
909	pinctrl_gpiokeys: gpiokeysgrp {
910		fsl,pins = <
911			MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1	0x19
912		>;
913	};
914
915	pinctrl_i2c1: i2c1-grp {
916		fsl,pins = <
917			MX7D_PAD_LPSR_GPIO1_IO05__I2C1_SDA	0x4000007f
918			MX7D_PAD_LPSR_GPIO1_IO04__I2C1_SCL	0x4000007f
919		>;
920	};
921
922	pinctrl_i2c1_recovery: i2c1-recoverygrp {
923		fsl,pins = <
924			MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4	0x4000007f
925			MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5	0x4000007f
926		>;
927	};
928
929	pinctrl_cd_usdhc1: usdhc1-cd-grp {
930		fsl,pins = <
931			MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0	0x59 /* CD */
932		>;
933	};
934
935	pinctrl_uart1_ctrl2: uart1-ctrl2-grp {
936		fsl,pins = <
937			MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7	0x14 /* DSR */
938			MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6	0x14 /* RI */
939		>;
940	};
941};
942