1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2// 3// Copyright 2015 Freescale Semiconductor, Inc. 4// Copyright 2016 Toradex AG 5 6#include <dt-bindings/clock/imx7d-clock.h> 7#include <dt-bindings/power/imx7-power.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/input/input.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/reset/imx7-reset.h> 12#include "imx7d-pinfunc.h" 13 14/ { 15 #address-cells = <1>; 16 #size-cells = <1>; 17 /* 18 * The decompressor and also some bootloaders rely on a 19 * pre-existing /chosen node to be available to insert the 20 * command line and merge other ATAGS info. 21 */ 22 chosen {}; 23 24 aliases { 25 gpio0 = &gpio1; 26 gpio1 = &gpio2; 27 gpio2 = &gpio3; 28 gpio3 = &gpio4; 29 gpio4 = &gpio5; 30 gpio5 = &gpio6; 31 gpio6 = &gpio7; 32 i2c0 = &i2c1; 33 i2c1 = &i2c2; 34 i2c2 = &i2c3; 35 i2c3 = &i2c4; 36 mmc0 = &usdhc1; 37 mmc1 = &usdhc2; 38 mmc2 = &usdhc3; 39 serial0 = &uart1; 40 serial1 = &uart2; 41 serial2 = &uart3; 42 serial3 = &uart4; 43 serial4 = &uart5; 44 serial5 = &uart6; 45 serial6 = &uart7; 46 spi0 = &ecspi1; 47 spi1 = &ecspi2; 48 spi2 = &ecspi3; 49 spi3 = &ecspi4; 50 usb0 = &usbotg1; 51 usb1 = &usbh; 52 }; 53 54 cpus { 55 #address-cells = <1>; 56 #size-cells = <0>; 57 58 idle-states { 59 entry-method = "psci"; 60 61 cpu_sleep_wait: cpu-sleep-wait { 62 compatible = "arm,idle-state"; 63 arm,psci-suspend-param = <0x0010000>; 64 local-timer-stop; 65 entry-latency-us = <100>; 66 exit-latency-us = <50>; 67 min-residency-us = <1000>; 68 }; 69 }; 70 71 cpu0: cpu@0 { 72 compatible = "arm,cortex-a7"; 73 device_type = "cpu"; 74 reg = <0>; 75 clock-frequency = <792000000>; 76 clock-latency = <61036>; /* two CLK32 periods */ 77 clocks = <&clks IMX7D_CLK_ARM>; 78 cpu-idle-states = <&cpu_sleep_wait>; 79 }; 80 }; 81 82 ckil: clock-cki { 83 compatible = "fixed-clock"; 84 #clock-cells = <0>; 85 clock-frequency = <32768>; 86 clock-output-names = "ckil"; 87 }; 88 89 osc: clock-osc { 90 compatible = "fixed-clock"; 91 #clock-cells = <0>; 92 clock-frequency = <24000000>; 93 clock-output-names = "osc"; 94 }; 95 96 usbphynop1: usbphynop1 { 97 compatible = "usb-nop-xceiv"; 98 clocks = <&clks IMX7D_USB_PHY1_CLK>; 99 clock-names = "main_clk"; 100 #phy-cells = <0>; 101 }; 102 103 usbphynop3: usbphynop3 { 104 compatible = "usb-nop-xceiv"; 105 clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>; 106 clock-names = "main_clk"; 107 #phy-cells = <0>; 108 }; 109 110 pmu { 111 compatible = "arm,cortex-a7-pmu"; 112 interrupt-parent = <&gpc>; 113 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 114 interrupt-affinity = <&cpu0>; 115 }; 116 117 replicator { 118 /* 119 * non-configurable replicators don't show up on the 120 * AMBA bus. As such no need to add "arm,primecell" 121 */ 122 compatible = "arm,coresight-static-replicator"; 123 124 out-ports { 125 #address-cells = <1>; 126 #size-cells = <0>; 127 /* replicator output ports */ 128 port@0 { 129 reg = <0>; 130 replicator_out_port0: endpoint { 131 remote-endpoint = <&tpiu_in_port>; 132 }; 133 }; 134 135 port@1 { 136 reg = <1>; 137 replicator_out_port1: endpoint { 138 remote-endpoint = <&etr_in_port>; 139 }; 140 }; 141 }; 142 143 in-ports { 144 port { 145 replicator_in_port0: endpoint { 146 remote-endpoint = <&etf_out_port>; 147 }; 148 }; 149 }; 150 }; 151 152 timer { 153 compatible = "arm,armv7-timer"; 154 arm,cpu-registers-not-fw-configured; 155 interrupt-parent = <&intc>; 156 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 157 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 158 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 159 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 160 }; 161 162 soc { 163 #address-cells = <1>; 164 #size-cells = <1>; 165 compatible = "simple-bus"; 166 interrupt-parent = <&gpc>; 167 ranges; 168 169 funnel@30041000 { 170 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 171 reg = <0x30041000 0x1000>; 172 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 173 clock-names = "apb_pclk"; 174 175 ca_funnel_in_ports: in-ports { 176 port { 177 ca_funnel_in_port0: endpoint { 178 remote-endpoint = <&etm0_out_port>; 179 }; 180 }; 181 182 /* the other input ports are not connect to anything */ 183 }; 184 185 out-ports { 186 port { 187 ca_funnel_out_port0: endpoint { 188 remote-endpoint = <&hugo_funnel_in_port0>; 189 }; 190 }; 191 192 }; 193 }; 194 195 etm@3007c000 { 196 compatible = "arm,coresight-etm3x", "arm,primecell"; 197 reg = <0x3007c000 0x1000>; 198 cpu = <&cpu0>; 199 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 200 clock-names = "apb_pclk"; 201 202 out-ports { 203 port { 204 etm0_out_port: endpoint { 205 remote-endpoint = <&ca_funnel_in_port0>; 206 }; 207 }; 208 }; 209 }; 210 211 funnel@30083000 { 212 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 213 reg = <0x30083000 0x1000>; 214 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 215 clock-names = "apb_pclk"; 216 217 in-ports { 218 #address-cells = <1>; 219 #size-cells = <0>; 220 221 port@0 { 222 reg = <0>; 223 hugo_funnel_in_port0: endpoint { 224 remote-endpoint = <&ca_funnel_out_port0>; 225 }; 226 }; 227 228 port@1 { 229 reg = <1>; 230 hugo_funnel_in_port1: endpoint { 231 /* M4 input */ 232 }; 233 }; 234 /* the other input ports are not connect to anything */ 235 }; 236 237 out-ports { 238 port { 239 hugo_funnel_out_port0: endpoint { 240 remote-endpoint = <&etf_in_port>; 241 }; 242 }; 243 }; 244 }; 245 246 etf@30084000 { 247 compatible = "arm,coresight-tmc", "arm,primecell"; 248 reg = <0x30084000 0x1000>; 249 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 250 clock-names = "apb_pclk"; 251 252 in-ports { 253 port { 254 etf_in_port: endpoint { 255 remote-endpoint = <&hugo_funnel_out_port0>; 256 }; 257 }; 258 }; 259 260 out-ports { 261 port { 262 etf_out_port: endpoint { 263 remote-endpoint = <&replicator_in_port0>; 264 }; 265 }; 266 }; 267 }; 268 269 etr@30086000 { 270 compatible = "arm,coresight-tmc", "arm,primecell"; 271 reg = <0x30086000 0x1000>; 272 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 273 clock-names = "apb_pclk"; 274 275 in-ports { 276 port { 277 etr_in_port: endpoint { 278 remote-endpoint = <&replicator_out_port1>; 279 }; 280 }; 281 }; 282 }; 283 284 tpiu@30087000 { 285 compatible = "arm,coresight-tpiu", "arm,primecell"; 286 reg = <0x30087000 0x1000>; 287 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 288 clock-names = "apb_pclk"; 289 290 in-ports { 291 port { 292 tpiu_in_port: endpoint { 293 remote-endpoint = <&replicator_out_port0>; 294 }; 295 }; 296 }; 297 }; 298 299 intc: interrupt-controller@31001000 { 300 compatible = "arm,cortex-a7-gic"; 301 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; 302 #interrupt-cells = <3>; 303 interrupt-controller; 304 interrupt-parent = <&intc>; 305 reg = <0x31001000 0x1000>, 306 <0x31002000 0x2000>, 307 <0x31004000 0x2000>, 308 <0x31006000 0x2000>; 309 }; 310 311 aips1: bus@30000000 { 312 compatible = "fsl,aips-bus", "simple-bus"; 313 #address-cells = <1>; 314 #size-cells = <1>; 315 reg = <0x30000000 0x400000>; 316 ranges; 317 318 gpio1: gpio@30200000 { 319 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 320 reg = <0x30200000 0x10000>; 321 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* GPIO1_INT15_0 */ 322 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; /* GPIO1_INT31_16 */ 323 gpio-controller; 324 #gpio-cells = <2>; 325 interrupt-controller; 326 #interrupt-cells = <2>; 327 gpio-ranges = <&iomuxc_lpsr 0 0 8>, <&iomuxc 8 5 8>; 328 }; 329 330 gpio2: gpio@30210000 { 331 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 332 reg = <0x30210000 0x10000>; 333 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 334 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 335 gpio-controller; 336 #gpio-cells = <2>; 337 interrupt-controller; 338 #interrupt-cells = <2>; 339 gpio-ranges = <&iomuxc 0 13 32>; 340 }; 341 342 gpio3: gpio@30220000 { 343 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 344 reg = <0x30220000 0x10000>; 345 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 346 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 347 gpio-controller; 348 #gpio-cells = <2>; 349 interrupt-controller; 350 #interrupt-cells = <2>; 351 gpio-ranges = <&iomuxc 0 45 29>; 352 }; 353 354 gpio4: gpio@30230000 { 355 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 356 reg = <0x30230000 0x10000>; 357 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 358 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 359 gpio-controller; 360 #gpio-cells = <2>; 361 interrupt-controller; 362 #interrupt-cells = <2>; 363 gpio-ranges = <&iomuxc 0 74 24>; 364 }; 365 366 gpio5: gpio@30240000 { 367 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 368 reg = <0x30240000 0x10000>; 369 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 370 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 371 gpio-controller; 372 #gpio-cells = <2>; 373 interrupt-controller; 374 #interrupt-cells = <2>; 375 gpio-ranges = <&iomuxc 0 98 18>; 376 }; 377 378 gpio6: gpio@30250000 { 379 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 380 reg = <0x30250000 0x10000>; 381 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 382 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 383 gpio-controller; 384 #gpio-cells = <2>; 385 interrupt-controller; 386 #interrupt-cells = <2>; 387 gpio-ranges = <&iomuxc 0 116 23>; 388 }; 389 390 gpio7: gpio@30260000 { 391 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 392 reg = <0x30260000 0x10000>; 393 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 394 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 395 gpio-controller; 396 #gpio-cells = <2>; 397 interrupt-controller; 398 #interrupt-cells = <2>; 399 gpio-ranges = <&iomuxc 0 139 16>; 400 }; 401 402 wdog1: watchdog@30280000 { 403 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; 404 reg = <0x30280000 0x10000>; 405 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 406 clocks = <&clks IMX7D_WDOG1_ROOT_CLK>; 407 }; 408 409 wdog2: watchdog@30290000 { 410 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; 411 reg = <0x30290000 0x10000>; 412 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 413 clocks = <&clks IMX7D_WDOG2_ROOT_CLK>; 414 status = "disabled"; 415 }; 416 417 wdog3: watchdog@302a0000 { 418 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; 419 reg = <0x302a0000 0x10000>; 420 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 421 clocks = <&clks IMX7D_WDOG3_ROOT_CLK>; 422 status = "disabled"; 423 }; 424 425 wdog4: watchdog@302b0000 { 426 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; 427 reg = <0x302b0000 0x10000>; 428 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 429 clocks = <&clks IMX7D_WDOG4_ROOT_CLK>; 430 status = "disabled"; 431 }; 432 433 iomuxc_lpsr: iomuxc-lpsr@302c0000 { 434 compatible = "fsl,imx7d-iomuxc-lpsr"; 435 reg = <0x302c0000 0x10000>; 436 fsl,input-sel = <&iomuxc>; 437 }; 438 439 gpt1: timer@302d0000 { 440 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; 441 reg = <0x302d0000 0x10000>; 442 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 443 clocks = <&clks IMX7D_GPT1_ROOT_CLK>, 444 <&clks IMX7D_GPT1_ROOT_CLK>; 445 clock-names = "ipg", "per"; 446 }; 447 448 gpt2: timer@302e0000 { 449 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; 450 reg = <0x302e0000 0x10000>; 451 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 452 clocks = <&clks IMX7D_GPT2_ROOT_CLK>, 453 <&clks IMX7D_GPT2_ROOT_CLK>; 454 clock-names = "ipg", "per"; 455 status = "disabled"; 456 }; 457 458 gpt3: timer@302f0000 { 459 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; 460 reg = <0x302f0000 0x10000>; 461 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 462 clocks = <&clks IMX7D_GPT3_ROOT_CLK>, 463 <&clks IMX7D_GPT3_ROOT_CLK>; 464 clock-names = "ipg", "per"; 465 status = "disabled"; 466 }; 467 468 gpt4: timer@30300000 { 469 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; 470 reg = <0x30300000 0x10000>; 471 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 472 clocks = <&clks IMX7D_GPT4_ROOT_CLK>, 473 <&clks IMX7D_GPT4_ROOT_CLK>; 474 clock-names = "ipg", "per"; 475 status = "disabled"; 476 }; 477 478 kpp: keypad@30320000 { 479 compatible = "fsl,imx7d-kpp", "fsl,imx21-kpp"; 480 reg = <0x30320000 0x10000>; 481 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 482 clocks = <&clks IMX7D_KPP_ROOT_CLK>; 483 status = "disabled"; 484 }; 485 486 iomuxc: pinctrl@30330000 { 487 compatible = "fsl,imx7d-iomuxc"; 488 reg = <0x30330000 0x10000>; 489 }; 490 491 gpr: iomuxc-gpr@30340000 { 492 compatible = "fsl,imx7d-iomuxc-gpr", 493 "fsl,imx6q-iomuxc-gpr", "syscon", 494 "simple-mfd"; 495 reg = <0x30340000 0x10000>; 496 497 mux: mux-controller { 498 compatible = "mmio-mux"; 499 #mux-control-cells = <0>; 500 mux-reg-masks = <0x14 0x00000010>; 501 }; 502 503 video_mux: csi-mux { 504 compatible = "video-mux"; 505 mux-controls = <&mux 0>; 506 #address-cells = <1>; 507 #size-cells = <0>; 508 status = "disabled"; 509 510 port@0 { 511 reg = <0>; 512 }; 513 514 port@1 { 515 reg = <1>; 516 517 csi_mux_from_mipi_vc0: endpoint { 518 remote-endpoint = <&mipi_vc0_to_csi_mux>; 519 }; 520 }; 521 522 port@2 { 523 reg = <2>; 524 525 csi_mux_to_csi: endpoint { 526 remote-endpoint = <&csi_from_csi_mux>; 527 }; 528 }; 529 }; 530 }; 531 532 ocotp: efuse@30350000 { 533 #address-cells = <1>; 534 #size-cells = <1>; 535 compatible = "fsl,imx7d-ocotp", "syscon"; 536 reg = <0x30350000 0x10000>; 537 clocks = <&clks IMX7D_OCOTP_CLK>; 538 539 tempmon_calib: calib@3c { 540 reg = <0x3c 0x4>; 541 }; 542 543 fuse_grade: fuse-grade@10 { 544 reg = <0x10 0x4>; 545 }; 546 }; 547 548 anatop: anatop@30360000 { 549 compatible = "fsl,imx7d-anatop", "fsl,imx6q-anatop", 550 "syscon", "simple-mfd"; 551 reg = <0x30360000 0x10000>; 552 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 553 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 554 555 reg_1p0d: regulator-vdd1p0d { 556 compatible = "fsl,anatop-regulator"; 557 regulator-name = "vdd1p0d"; 558 regulator-min-microvolt = <800000>; 559 regulator-max-microvolt = <1200000>; 560 anatop-reg-offset = <0x210>; 561 anatop-vol-bit-shift = <8>; 562 anatop-vol-bit-width = <5>; 563 anatop-min-bit-val = <8>; 564 anatop-min-voltage = <800000>; 565 anatop-max-voltage = <1200000>; 566 anatop-enable-bit = <0>; 567 }; 568 569 reg_1p2: regulator-vdd1p2 { 570 compatible = "fsl,anatop-regulator"; 571 regulator-name = "vdd1p2"; 572 regulator-min-microvolt = <1100000>; 573 regulator-max-microvolt = <1300000>; 574 anatop-reg-offset = <0x220>; 575 anatop-vol-bit-shift = <8>; 576 anatop-vol-bit-width = <5>; 577 anatop-min-bit-val = <0x14>; 578 anatop-min-voltage = <1100000>; 579 anatop-max-voltage = <1300000>; 580 anatop-enable-bit = <0>; 581 }; 582 583 tempmon: tempmon { 584 compatible = "fsl,imx7d-tempmon"; 585 interrupt-parent = <&gpc>; 586 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 587 fsl,tempmon = <&anatop>; 588 nvmem-cells = <&tempmon_calib>, <&fuse_grade>; 589 nvmem-cell-names = "calib", "temp_grade"; 590 clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>; 591 }; 592 }; 593 594 snvs: snvs@30370000 { 595 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; 596 reg = <0x30370000 0x10000>; 597 598 snvs_rtc: snvs-rtc-lp { 599 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 600 regmap = <&snvs>; 601 offset = <0x34>; 602 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 603 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 604 clocks = <&clks IMX7D_SNVS_CLK>; 605 clock-names = "snvs-rtc"; 606 }; 607 608 snvs_pwrkey: snvs-powerkey { 609 compatible = "fsl,sec-v4.0-pwrkey"; 610 regmap = <&snvs>; 611 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 612 clocks = <&clks IMX7D_SNVS_CLK>; 613 clock-names = "snvs-pwrkey"; 614 linux,keycode = <KEY_POWER>; 615 wakeup-source; 616 status = "disabled"; 617 }; 618 }; 619 620 clks: clock-controller@30380000 { 621 compatible = "fsl,imx7d-ccm"; 622 reg = <0x30380000 0x10000>; 623 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 624 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 625 #clock-cells = <1>; 626 clocks = <&ckil>, <&osc>; 627 clock-names = "ckil", "osc"; 628 }; 629 630 src: reset-controller@30390000 { 631 compatible = "fsl,imx7d-src", "syscon"; 632 reg = <0x30390000 0x10000>; 633 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 634 #reset-cells = <1>; 635 }; 636 637 gpc: gpc@303a0000 { 638 compatible = "fsl,imx7d-gpc"; 639 reg = <0x303a0000 0x10000>; 640 interrupt-controller; 641 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 642 #interrupt-cells = <3>; 643 interrupt-parent = <&intc>; 644 #power-domain-cells = <1>; 645 646 pgc { 647 #address-cells = <1>; 648 #size-cells = <0>; 649 650 pgc_mipi_phy: power-domain@0 { 651 #power-domain-cells = <0>; 652 reg = <0>; 653 power-supply = <®_1p0d>; 654 }; 655 656 pgc_pcie_phy: power-domain@1 { 657 #power-domain-cells = <0>; 658 reg = <1>; 659 power-supply = <®_1p0d>; 660 }; 661 662 pgc_hsic_phy: power-domain@2 { 663 #power-domain-cells = <0>; 664 reg = <2>; 665 power-supply = <®_1p2>; 666 }; 667 }; 668 }; 669 }; 670 671 aips2: bus@30400000 { 672 compatible = "fsl,aips-bus", "simple-bus"; 673 #address-cells = <1>; 674 #size-cells = <1>; 675 reg = <0x30400000 0x400000>; 676 ranges; 677 678 adc1: adc@30610000 { 679 compatible = "fsl,imx7d-adc"; 680 reg = <0x30610000 0x10000>; 681 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 682 clocks = <&clks IMX7D_ADC_ROOT_CLK>; 683 clock-names = "adc"; 684 #io-channel-cells = <1>; 685 status = "disabled"; 686 }; 687 688 adc2: adc@30620000 { 689 compatible = "fsl,imx7d-adc"; 690 reg = <0x30620000 0x10000>; 691 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 692 clocks = <&clks IMX7D_ADC_ROOT_CLK>; 693 clock-names = "adc"; 694 #io-channel-cells = <1>; 695 status = "disabled"; 696 }; 697 698 ecspi4: spi@30630000 { 699 #address-cells = <1>; 700 #size-cells = <0>; 701 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; 702 reg = <0x30630000 0x10000>; 703 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 704 clocks = <&clks IMX7D_ECSPI4_ROOT_CLK>, 705 <&clks IMX7D_ECSPI4_ROOT_CLK>; 706 clock-names = "ipg", "per"; 707 status = "disabled"; 708 }; 709 710 pwm1: pwm@30660000 { 711 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; 712 reg = <0x30660000 0x10000>; 713 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 714 clocks = <&clks IMX7D_PWM1_ROOT_CLK>, 715 <&clks IMX7D_PWM1_ROOT_CLK>; 716 clock-names = "ipg", "per"; 717 #pwm-cells = <3>; 718 status = "disabled"; 719 }; 720 721 pwm2: pwm@30670000 { 722 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; 723 reg = <0x30670000 0x10000>; 724 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 725 clocks = <&clks IMX7D_PWM2_ROOT_CLK>, 726 <&clks IMX7D_PWM2_ROOT_CLK>; 727 clock-names = "ipg", "per"; 728 #pwm-cells = <3>; 729 status = "disabled"; 730 }; 731 732 pwm3: pwm@30680000 { 733 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; 734 reg = <0x30680000 0x10000>; 735 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 736 clocks = <&clks IMX7D_PWM3_ROOT_CLK>, 737 <&clks IMX7D_PWM3_ROOT_CLK>; 738 clock-names = "ipg", "per"; 739 #pwm-cells = <3>; 740 status = "disabled"; 741 }; 742 743 pwm4: pwm@30690000 { 744 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; 745 reg = <0x30690000 0x10000>; 746 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 747 clocks = <&clks IMX7D_PWM4_ROOT_CLK>, 748 <&clks IMX7D_PWM4_ROOT_CLK>; 749 clock-names = "ipg", "per"; 750 #pwm-cells = <3>; 751 status = "disabled"; 752 }; 753 754 csi: csi@30710000 { 755 compatible = "fsl,imx7-csi"; 756 reg = <0x30710000 0x10000>; 757 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 758 clocks = <&clks IMX7D_CLK_DUMMY>, 759 <&clks IMX7D_CSI_MCLK_ROOT_CLK>, 760 <&clks IMX7D_CLK_DUMMY>; 761 clock-names = "axi", "mclk", "dcic"; 762 status = "disabled"; 763 764 port { 765 csi_from_csi_mux: endpoint { 766 remote-endpoint = <&csi_mux_to_csi>; 767 }; 768 }; 769 }; 770 771 lcdif: lcdif@30730000 { 772 compatible = "fsl,imx7d-lcdif", "fsl,imx28-lcdif"; 773 reg = <0x30730000 0x10000>; 774 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 775 clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>, 776 <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>; 777 clock-names = "pix", "axi"; 778 status = "disabled"; 779 }; 780 781 mipi_csi: mipi-csi@30750000 { 782 compatible = "fsl,imx7-mipi-csi2"; 783 reg = <0x30750000 0x10000>; 784 #address-cells = <1>; 785 #size-cells = <0>; 786 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 787 clocks = <&clks IMX7D_IPG_ROOT_CLK>, 788 <&clks IMX7D_MIPI_CSI_ROOT_CLK>, 789 <&clks IMX7D_MIPI_DPHY_ROOT_CLK>; 790 clock-names = "pclk", "wrap", "phy"; 791 power-domains = <&pgc_mipi_phy>; 792 phy-supply = <®_1p0d>; 793 resets = <&src IMX7_RESET_MIPI_PHY_MRST>; 794 reset-names = "mrst"; 795 status = "disabled"; 796 797 port@0 { 798 reg = <0>; 799 }; 800 801 port@1 { 802 reg = <1>; 803 804 mipi_vc0_to_csi_mux: endpoint { 805 remote-endpoint = <&csi_mux_from_mipi_vc0>; 806 }; 807 }; 808 }; 809 }; 810 811 aips3: bus@30800000 { 812 compatible = "fsl,aips-bus", "simple-bus"; 813 #address-cells = <1>; 814 #size-cells = <1>; 815 reg = <0x30800000 0x400000>; 816 ranges; 817 818 spba-bus@30800000 { 819 compatible = "fsl,spba-bus", "simple-bus"; 820 #address-cells = <1>; 821 #size-cells = <1>; 822 reg = <0x30800000 0x100000>; 823 ranges; 824 825 ecspi1: spi@30820000 { 826 #address-cells = <1>; 827 #size-cells = <0>; 828 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; 829 reg = <0x30820000 0x10000>; 830 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 831 clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>, 832 <&clks IMX7D_ECSPI1_ROOT_CLK>; 833 clock-names = "ipg", "per"; 834 status = "disabled"; 835 }; 836 837 ecspi2: spi@30830000 { 838 #address-cells = <1>; 839 #size-cells = <0>; 840 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; 841 reg = <0x30830000 0x10000>; 842 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 843 clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>, 844 <&clks IMX7D_ECSPI2_ROOT_CLK>; 845 clock-names = "ipg", "per"; 846 status = "disabled"; 847 }; 848 849 ecspi3: spi@30840000 { 850 #address-cells = <1>; 851 #size-cells = <0>; 852 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; 853 reg = <0x30840000 0x10000>; 854 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 855 clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>, 856 <&clks IMX7D_ECSPI3_ROOT_CLK>; 857 clock-names = "ipg", "per"; 858 status = "disabled"; 859 }; 860 861 uart1: serial@30860000 { 862 compatible = "fsl,imx7d-uart", 863 "fsl,imx6q-uart"; 864 reg = <0x30860000 0x10000>; 865 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 866 clocks = <&clks IMX7D_UART1_ROOT_CLK>, 867 <&clks IMX7D_UART1_ROOT_CLK>; 868 clock-names = "ipg", "per"; 869 status = "disabled"; 870 }; 871 872 uart2: serial@30890000 { 873 compatible = "fsl,imx7d-uart", 874 "fsl,imx6q-uart"; 875 reg = <0x30890000 0x10000>; 876 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 877 clocks = <&clks IMX7D_UART2_ROOT_CLK>, 878 <&clks IMX7D_UART2_ROOT_CLK>; 879 clock-names = "ipg", "per"; 880 status = "disabled"; 881 }; 882 883 uart3: serial@30880000 { 884 compatible = "fsl,imx7d-uart", 885 "fsl,imx6q-uart"; 886 reg = <0x30880000 0x10000>; 887 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 888 clocks = <&clks IMX7D_UART3_ROOT_CLK>, 889 <&clks IMX7D_UART3_ROOT_CLK>; 890 clock-names = "ipg", "per"; 891 status = "disabled"; 892 }; 893 894 sai1: sai@308a0000 { 895 #sound-dai-cells = <0>; 896 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; 897 reg = <0x308a0000 0x10000>; 898 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 899 clocks = <&clks IMX7D_SAI1_IPG_CLK>, 900 <&clks IMX7D_SAI1_ROOT_CLK>, 901 <&clks IMX7D_CLK_DUMMY>, 902 <&clks IMX7D_CLK_DUMMY>; 903 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 904 dma-names = "rx", "tx"; 905 dmas = <&sdma 8 24 0>, <&sdma 9 24 0>; 906 status = "disabled"; 907 }; 908 909 sai2: sai@308b0000 { 910 #sound-dai-cells = <0>; 911 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; 912 reg = <0x308b0000 0x10000>; 913 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 914 clocks = <&clks IMX7D_SAI2_IPG_CLK>, 915 <&clks IMX7D_SAI2_ROOT_CLK>, 916 <&clks IMX7D_CLK_DUMMY>, 917 <&clks IMX7D_CLK_DUMMY>; 918 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 919 dma-names = "rx", "tx"; 920 dmas = <&sdma 10 24 0>, <&sdma 11 24 0>; 921 status = "disabled"; 922 }; 923 924 sai3: sai@308c0000 { 925 #sound-dai-cells = <0>; 926 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; 927 reg = <0x308c0000 0x10000>; 928 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 929 clocks = <&clks IMX7D_SAI3_IPG_CLK>, 930 <&clks IMX7D_SAI3_ROOT_CLK>, 931 <&clks IMX7D_CLK_DUMMY>, 932 <&clks IMX7D_CLK_DUMMY>; 933 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 934 dma-names = "rx", "tx"; 935 dmas = <&sdma 12 24 0>, <&sdma 13 24 0>; 936 status = "disabled"; 937 }; 938 }; 939 940 crypto: crypto@30900000 { 941 compatible = "fsl,sec-v4.0"; 942 #address-cells = <1>; 943 #size-cells = <1>; 944 reg = <0x30900000 0x40000>; 945 ranges = <0 0x30900000 0x40000>; 946 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 947 clocks = <&clks IMX7D_CAAM_CLK>, 948 <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>; 949 clock-names = "ipg", "aclk"; 950 951 sec_jr0: jr@1000 { 952 compatible = "fsl,sec-v4.0-job-ring"; 953 reg = <0x1000 0x1000>; 954 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 955 }; 956 957 sec_jr1: jr@2000 { 958 compatible = "fsl,sec-v4.0-job-ring"; 959 reg = <0x2000 0x1000>; 960 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 961 }; 962 963 sec_jr2: jr@3000 { 964 compatible = "fsl,sec-v4.0-job-ring"; 965 reg = <0x3000 0x1000>; 966 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 967 }; 968 }; 969 970 flexcan1: can@30a00000 { 971 compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan"; 972 reg = <0x30a00000 0x10000>; 973 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 974 clocks = <&clks IMX7D_CLK_DUMMY>, 975 <&clks IMX7D_CAN1_ROOT_CLK>; 976 clock-names = "ipg", "per"; 977 fsl,stop-mode = <&gpr 0x10 1>; 978 status = "disabled"; 979 }; 980 981 flexcan2: can@30a10000 { 982 compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan"; 983 reg = <0x30a10000 0x10000>; 984 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 985 clocks = <&clks IMX7D_CLK_DUMMY>, 986 <&clks IMX7D_CAN2_ROOT_CLK>; 987 clock-names = "ipg", "per"; 988 fsl,stop-mode = <&gpr 0x10 2>; 989 status = "disabled"; 990 }; 991 992 i2c1: i2c@30a20000 { 993 #address-cells = <1>; 994 #size-cells = <0>; 995 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; 996 reg = <0x30a20000 0x10000>; 997 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 998 clocks = <&clks IMX7D_I2C1_ROOT_CLK>; 999 status = "disabled"; 1000 }; 1001 1002 i2c2: i2c@30a30000 { 1003 #address-cells = <1>; 1004 #size-cells = <0>; 1005 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; 1006 reg = <0x30a30000 0x10000>; 1007 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 1008 clocks = <&clks IMX7D_I2C2_ROOT_CLK>; 1009 status = "disabled"; 1010 }; 1011 1012 i2c3: i2c@30a40000 { 1013 #address-cells = <1>; 1014 #size-cells = <0>; 1015 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; 1016 reg = <0x30a40000 0x10000>; 1017 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1018 clocks = <&clks IMX7D_I2C3_ROOT_CLK>; 1019 status = "disabled"; 1020 }; 1021 1022 i2c4: i2c@30a50000 { 1023 #address-cells = <1>; 1024 #size-cells = <0>; 1025 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; 1026 reg = <0x30a50000 0x10000>; 1027 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 1028 clocks = <&clks IMX7D_I2C4_ROOT_CLK>; 1029 status = "disabled"; 1030 }; 1031 1032 uart4: serial@30a60000 { 1033 compatible = "fsl,imx7d-uart", 1034 "fsl,imx6q-uart"; 1035 reg = <0x30a60000 0x10000>; 1036 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 1037 clocks = <&clks IMX7D_UART4_ROOT_CLK>, 1038 <&clks IMX7D_UART4_ROOT_CLK>; 1039 clock-names = "ipg", "per"; 1040 status = "disabled"; 1041 }; 1042 1043 uart5: serial@30a70000 { 1044 compatible = "fsl,imx7d-uart", 1045 "fsl,imx6q-uart"; 1046 reg = <0x30a70000 0x10000>; 1047 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 1048 clocks = <&clks IMX7D_UART5_ROOT_CLK>, 1049 <&clks IMX7D_UART5_ROOT_CLK>; 1050 clock-names = "ipg", "per"; 1051 status = "disabled"; 1052 }; 1053 1054 uart6: serial@30a80000 { 1055 compatible = "fsl,imx7d-uart", 1056 "fsl,imx6q-uart"; 1057 reg = <0x30a80000 0x10000>; 1058 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1059 clocks = <&clks IMX7D_UART6_ROOT_CLK>, 1060 <&clks IMX7D_UART6_ROOT_CLK>; 1061 clock-names = "ipg", "per"; 1062 status = "disabled"; 1063 }; 1064 1065 uart7: serial@30a90000 { 1066 compatible = "fsl,imx7d-uart", 1067 "fsl,imx6q-uart"; 1068 reg = <0x30a90000 0x10000>; 1069 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 1070 clocks = <&clks IMX7D_UART7_ROOT_CLK>, 1071 <&clks IMX7D_UART7_ROOT_CLK>; 1072 clock-names = "ipg", "per"; 1073 status = "disabled"; 1074 }; 1075 1076 mu0a: mailbox@30aa0000 { 1077 compatible = "fsl,imx7s-mu", "fsl,imx6sx-mu"; 1078 reg = <0x30aa0000 0x10000>; 1079 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 1080 clocks = <&clks IMX7D_MU_ROOT_CLK>; 1081 #mbox-cells = <2>; 1082 status = "disabled"; 1083 }; 1084 1085 mu0b: mailbox@30ab0000 { 1086 compatible = "fsl,imx7s-mu", "fsl,imx6sx-mu"; 1087 reg = <0x30ab0000 0x10000>; 1088 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1089 clocks = <&clks IMX7D_MU_ROOT_CLK>; 1090 #mbox-cells = <2>; 1091 fsl,mu-side-b; 1092 status = "disabled"; 1093 }; 1094 1095 usbotg1: usb@30b10000 { 1096 compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; 1097 reg = <0x30b10000 0x200>; 1098 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 1099 clocks = <&clks IMX7D_USB_CTRL_CLK>; 1100 fsl,usbphy = <&usbphynop1>; 1101 fsl,usbmisc = <&usbmisc1 0>; 1102 phy-clkgate-delay-us = <400>; 1103 status = "disabled"; 1104 }; 1105 1106 usbh: usb@30b30000 { 1107 compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; 1108 reg = <0x30b30000 0x200>; 1109 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 1110 power-domains = <&pgc_hsic_phy>; 1111 clocks = <&clks IMX7D_USB_CTRL_CLK>; 1112 fsl,usbphy = <&usbphynop3>; 1113 fsl,usbmisc = <&usbmisc3 0>; 1114 phy_type = "hsic"; 1115 dr_mode = "host"; 1116 phy-clkgate-delay-us = <400>; 1117 status = "disabled"; 1118 }; 1119 1120 usbmisc1: usbmisc@30b10200 { 1121 #index-cells = <1>; 1122 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; 1123 reg = <0x30b10200 0x200>; 1124 }; 1125 1126 usbmisc3: usbmisc@30b30200 { 1127 #index-cells = <1>; 1128 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; 1129 reg = <0x30b30200 0x200>; 1130 }; 1131 1132 usdhc1: mmc@30b40000 { 1133 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; 1134 reg = <0x30b40000 0x10000>; 1135 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1136 clocks = <&clks IMX7D_IPG_ROOT_CLK>, 1137 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>, 1138 <&clks IMX7D_USDHC1_ROOT_CLK>; 1139 clock-names = "ipg", "ahb", "per"; 1140 bus-width = <4>; 1141 status = "disabled"; 1142 }; 1143 1144 usdhc2: mmc@30b50000 { 1145 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; 1146 reg = <0x30b50000 0x10000>; 1147 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1148 clocks = <&clks IMX7D_IPG_ROOT_CLK>, 1149 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>, 1150 <&clks IMX7D_USDHC2_ROOT_CLK>; 1151 clock-names = "ipg", "ahb", "per"; 1152 bus-width = <4>; 1153 status = "disabled"; 1154 }; 1155 1156 usdhc3: mmc@30b60000 { 1157 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; 1158 reg = <0x30b60000 0x10000>; 1159 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 1160 clocks = <&clks IMX7D_IPG_ROOT_CLK>, 1161 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>, 1162 <&clks IMX7D_USDHC3_ROOT_CLK>; 1163 clock-names = "ipg", "ahb", "per"; 1164 bus-width = <4>; 1165 status = "disabled"; 1166 }; 1167 1168 qspi: spi@30bb0000 { 1169 compatible = "fsl,imx7d-qspi"; 1170 reg = <0x30bb0000 0x10000>, <0x60000000 0x10000000>; 1171 reg-names = "QuadSPI", "QuadSPI-memory"; 1172 #address-cells = <1>; 1173 #size-cells = <0>; 1174 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1175 clocks = <&clks IMX7D_QSPI_ROOT_CLK>, 1176 <&clks IMX7D_QSPI_ROOT_CLK>; 1177 clock-names = "qspi_en", "qspi"; 1178 status = "disabled"; 1179 }; 1180 1181 sdma: sdma@30bd0000 { 1182 compatible = "fsl,imx7d-sdma", "fsl,imx35-sdma"; 1183 reg = <0x30bd0000 0x10000>; 1184 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 1185 clocks = <&clks IMX7D_IPG_ROOT_CLK>, 1186 <&clks IMX7D_SDMA_CORE_CLK>; 1187 clock-names = "ipg", "ahb"; 1188 #dma-cells = <3>; 1189 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 1190 }; 1191 1192 fec1: ethernet@30be0000 { 1193 compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec"; 1194 reg = <0x30be0000 0x10000>; 1195 interrupt-names = "int0", "int1", "int2", "pps"; 1196 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1197 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1198 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1199 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 1200 clocks = <&clks IMX7D_ENET1_IPG_ROOT_CLK>, 1201 <&clks IMX7D_ENET_AXI_ROOT_CLK>, 1202 <&clks IMX7D_ENET1_TIME_ROOT_CLK>, 1203 <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>, 1204 <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>; 1205 clock-names = "ipg", "ahb", "ptp", 1206 "enet_clk_ref", "enet_out"; 1207 fsl,num-tx-queues = <3>; 1208 fsl,num-rx-queues = <3>; 1209 fsl,stop-mode = <&gpr 0x10 3>; 1210 status = "disabled"; 1211 }; 1212 }; 1213 1214 dma_apbh: dma-apbh@33000000 { 1215 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; 1216 reg = <0x33000000 0x2000>; 1217 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1218 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1219 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1220 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1221 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; 1222 #dma-cells = <1>; 1223 dma-channels = <4>; 1224 clocks = <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>; 1225 }; 1226 1227 gpmi: nand-controller@33002000{ 1228 compatible = "fsl,imx7d-gpmi-nand"; 1229 #address-cells = <1>; 1230 #size-cells = <1>; 1231 reg = <0x33002000 0x2000>, <0x33004000 0x4000>; 1232 reg-names = "gpmi-nand", "bch"; 1233 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1234 interrupt-names = "bch"; 1235 clocks = <&clks IMX7D_NAND_RAWNAND_CLK>, 1236 <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>; 1237 clock-names = "gpmi_io", "gpmi_bch_apb"; 1238 dmas = <&dma_apbh 0>; 1239 dma-names = "rx-tx"; 1240 status = "disabled"; 1241 assigned-clocks = <&clks IMX7D_NAND_ROOT_SRC>; 1242 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_500M_CLK>; 1243 }; 1244 }; 1245}; 1246