1// SPDX-License-Identifier: GPL-2.0 OR MIT 2/* 3 * Copyright 2015 Endless Mobile, Inc. 4 * Author: Carlo Caione <carlo@endlessm.com> 5 */ 6 7#include <dt-bindings/clock/meson8-ddr-clkc.h> 8#include <dt-bindings/clock/meson8b-clkc.h> 9#include <dt-bindings/gpio/meson8b-gpio.h> 10#include <dt-bindings/power/meson8-power.h> 11#include <dt-bindings/reset/amlogic,meson8b-reset.h> 12#include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h> 13#include <dt-bindings/thermal/thermal.h> 14#include "meson.dtsi" 15 16/ { 17 cpus { 18 #address-cells = <1>; 19 #size-cells = <0>; 20 21 cpu0: cpu@200 { 22 device_type = "cpu"; 23 compatible = "arm,cortex-a5"; 24 next-level-cache = <&L2>; 25 reg = <0x200>; 26 enable-method = "amlogic,meson8b-smp"; 27 resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>; 28 operating-points-v2 = <&cpu_opp_table>; 29 clocks = <&clkc CLKID_CPUCLK>; 30 #cooling-cells = <2>; /* min followed by max */ 31 }; 32 33 cpu1: cpu@201 { 34 device_type = "cpu"; 35 compatible = "arm,cortex-a5"; 36 next-level-cache = <&L2>; 37 reg = <0x201>; 38 enable-method = "amlogic,meson8b-smp"; 39 resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>; 40 operating-points-v2 = <&cpu_opp_table>; 41 clocks = <&clkc CLKID_CPUCLK>; 42 #cooling-cells = <2>; /* min followed by max */ 43 }; 44 45 cpu2: cpu@202 { 46 device_type = "cpu"; 47 compatible = "arm,cortex-a5"; 48 next-level-cache = <&L2>; 49 reg = <0x202>; 50 enable-method = "amlogic,meson8b-smp"; 51 resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>; 52 operating-points-v2 = <&cpu_opp_table>; 53 clocks = <&clkc CLKID_CPUCLK>; 54 #cooling-cells = <2>; /* min followed by max */ 55 }; 56 57 cpu3: cpu@203 { 58 device_type = "cpu"; 59 compatible = "arm,cortex-a5"; 60 next-level-cache = <&L2>; 61 reg = <0x203>; 62 enable-method = "amlogic,meson8b-smp"; 63 resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>; 64 operating-points-v2 = <&cpu_opp_table>; 65 clocks = <&clkc CLKID_CPUCLK>; 66 #cooling-cells = <2>; /* min followed by max */ 67 }; 68 }; 69 70 cpu_opp_table: opp-table { 71 compatible = "operating-points-v2"; 72 opp-shared; 73 74 opp-96000000 { 75 opp-hz = /bits/ 64 <96000000>; 76 opp-microvolt = <860000>; 77 }; 78 opp-192000000 { 79 opp-hz = /bits/ 64 <192000000>; 80 opp-microvolt = <860000>; 81 }; 82 opp-312000000 { 83 opp-hz = /bits/ 64 <312000000>; 84 opp-microvolt = <860000>; 85 }; 86 opp-408000000 { 87 opp-hz = /bits/ 64 <408000000>; 88 opp-microvolt = <860000>; 89 }; 90 opp-504000000 { 91 opp-hz = /bits/ 64 <504000000>; 92 opp-microvolt = <860000>; 93 }; 94 opp-600000000 { 95 opp-hz = /bits/ 64 <600000000>; 96 opp-microvolt = <860000>; 97 }; 98 opp-720000000 { 99 opp-hz = /bits/ 64 <720000000>; 100 opp-microvolt = <860000>; 101 }; 102 opp-816000000 { 103 opp-hz = /bits/ 64 <816000000>; 104 opp-microvolt = <900000>; 105 }; 106 opp-1008000000 { 107 opp-hz = /bits/ 64 <1008000000>; 108 opp-microvolt = <1140000>; 109 }; 110 opp-1200000000 { 111 opp-hz = /bits/ 64 <1200000000>; 112 opp-microvolt = <1140000>; 113 }; 114 opp-1320000000 { 115 opp-hz = /bits/ 64 <1320000000>; 116 opp-microvolt = <1140000>; 117 }; 118 opp-1488000000 { 119 opp-hz = /bits/ 64 <1488000000>; 120 opp-microvolt = <1140000>; 121 }; 122 opp-1536000000 { 123 opp-hz = /bits/ 64 <1536000000>; 124 opp-microvolt = <1140000>; 125 }; 126 }; 127 128 gpu_opp_table: gpu-opp-table { 129 compatible = "operating-points-v2"; 130 131 opp-255000000 { 132 opp-hz = /bits/ 64 <255000000>; 133 opp-microvolt = <1100000>; 134 }; 135 opp-364285714 { 136 opp-hz = /bits/ 64 <364285714>; 137 opp-microvolt = <1100000>; 138 }; 139 opp-425000000 { 140 opp-hz = /bits/ 64 <425000000>; 141 opp-microvolt = <1100000>; 142 }; 143 opp-510000000 { 144 opp-hz = /bits/ 64 <510000000>; 145 opp-microvolt = <1100000>; 146 }; 147 opp-637500000 { 148 opp-hz = /bits/ 64 <637500000>; 149 opp-microvolt = <1100000>; 150 turbo-mode; 151 }; 152 }; 153 154 pmu { 155 compatible = "arm,cortex-a5-pmu"; 156 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 157 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 158 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 159 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 160 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 161 }; 162 163 reserved-memory { 164 #address-cells = <1>; 165 #size-cells = <1>; 166 ranges; 167 168 /* 2 MiB reserved for Hardware ROM Firmware? */ 169 hwrom@0 { 170 reg = <0x0 0x200000>; 171 no-map; 172 }; 173 }; 174 175 thermal-zones { 176 soc { 177 polling-delay-passive = <250>; /* milliseconds */ 178 polling-delay = <1000>; /* milliseconds */ 179 thermal-sensors = <&thermal_sensor>; 180 181 cooling-maps { 182 map0 { 183 trip = <&soc_passive>; 184 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 185 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 186 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 187 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 188 <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 189 }; 190 191 map1 { 192 trip = <&soc_hot>; 193 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 194 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 195 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 196 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 197 <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 198 }; 199 }; 200 201 trips { 202 soc_passive: soc-passive { 203 temperature = <80000>; /* millicelsius */ 204 hysteresis = <2000>; /* millicelsius */ 205 type = "passive"; 206 }; 207 208 soc_hot: soc-hot { 209 temperature = <90000>; /* millicelsius */ 210 hysteresis = <2000>; /* millicelsius */ 211 type = "hot"; 212 }; 213 214 soc_critical: soc-critical { 215 temperature = <110000>; /* millicelsius */ 216 hysteresis = <2000>; /* millicelsius */ 217 type = "critical"; 218 }; 219 }; 220 }; 221 }; 222 223 mmcbus: bus@c8000000 { 224 compatible = "simple-bus"; 225 reg = <0xc8000000 0x8000>; 226 #address-cells = <1>; 227 #size-cells = <1>; 228 ranges = <0x0 0xc8000000 0x8000>; 229 230 ddr_clkc: clock-controller@400 { 231 compatible = "amlogic,meson8b-ddr-clkc"; 232 reg = <0x400 0x20>; 233 clocks = <&xtal>; 234 clock-names = "xtal"; 235 #clock-cells = <1>; 236 }; 237 238 dmcbus: bus@6000 { 239 compatible = "simple-bus"; 240 reg = <0x6000 0x400>; 241 #address-cells = <1>; 242 #size-cells = <1>; 243 ranges = <0x0 0x6000 0x400>; 244 245 canvas: video-lut@48 { 246 compatible = "amlogic,meson8b-canvas", 247 "amlogic,canvas"; 248 reg = <0x48 0x14>; 249 }; 250 }; 251 }; 252 253 apb: bus@d0000000 { 254 compatible = "simple-bus"; 255 reg = <0xd0000000 0x200000>; 256 #address-cells = <1>; 257 #size-cells = <1>; 258 ranges = <0x0 0xd0000000 0x200000>; 259 260 mali: gpu@c0000 { 261 compatible = "amlogic,meson8b-mali", "arm,mali-450"; 262 reg = <0xc0000 0x40000>; 263 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 264 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 265 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 266 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 267 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 268 <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 269 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, 270 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 271 interrupt-names = "gp", "gpmmu", "pp", "pmu", 272 "pp0", "ppmmu0", "pp1", "ppmmu1"; 273 resets = <&reset RESET_MALI>; 274 clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>; 275 clock-names = "bus", "core"; 276 operating-points-v2 = <&gpu_opp_table>; 277 #cooling-cells = <2>; /* min followed by max */ 278 }; 279 }; 280}; /* end of / */ 281 282&aobus { 283 pmu: pmu@e0 { 284 compatible = "amlogic,meson8b-pmu", "syscon"; 285 reg = <0xe0 0x18>; 286 }; 287 288 pinctrl_aobus: pinctrl@84 { 289 compatible = "amlogic,meson8b-aobus-pinctrl"; 290 reg = <0x84 0xc>; 291 #address-cells = <1>; 292 #size-cells = <1>; 293 ranges; 294 295 gpio_ao: ao-bank@14 { 296 reg = <0x14 0x4>, 297 <0x2c 0x4>, 298 <0x24 0x8>; 299 reg-names = "mux", "pull", "gpio"; 300 gpio-controller; 301 #gpio-cells = <2>; 302 gpio-ranges = <&pinctrl_aobus 0 0 16>; 303 }; 304 305 uart_ao_a_pins: uart_ao_a { 306 mux { 307 groups = "uart_tx_ao_a", "uart_rx_ao_a"; 308 function = "uart_ao"; 309 bias-disable; 310 }; 311 }; 312 313 ir_recv_pins: remote { 314 mux { 315 groups = "remote_input"; 316 function = "remote"; 317 bias-disable; 318 }; 319 }; 320 }; 321}; 322 323&ao_arc_rproc { 324 compatible= "amlogic,meson8b-ao-arc", "amlogic,meson-mx-ao-arc"; 325 amlogic,secbus2 = <&secbus2>; 326 sram = <&ao_arc_sram>; 327 resets = <&reset RESET_MEDIA_CPU>; 328 clocks = <&clkc CLKID_AO_MEDIA_CPU>; 329}; 330 331&cbus { 332 reset: reset-controller@4404 { 333 compatible = "amlogic,meson8b-reset"; 334 reg = <0x4404 0x9c>; 335 #reset-cells = <1>; 336 }; 337 338 analog_top: analog-top@81a8 { 339 compatible = "amlogic,meson8b-analog-top", "syscon"; 340 reg = <0x81a8 0x14>; 341 }; 342 343 pwm_ef: pwm@86c0 { 344 compatible = "amlogic,meson8b-pwm"; 345 reg = <0x86c0 0x10>; 346 #pwm-cells = <3>; 347 status = "disabled"; 348 }; 349 350 clock-measure@8758 { 351 compatible = "amlogic,meson8b-clk-measure"; 352 reg = <0x8758 0x1c>; 353 }; 354 355 pinctrl_cbus: pinctrl@9880 { 356 compatible = "amlogic,meson8b-cbus-pinctrl"; 357 reg = <0x9880 0x10>; 358 #address-cells = <1>; 359 #size-cells = <1>; 360 ranges; 361 362 gpio: banks@80b0 { 363 reg = <0x80b0 0x28>, 364 <0x80e8 0x18>, 365 <0x8120 0x18>, 366 <0x8030 0x38>; 367 reg-names = "mux", "pull", "pull-enable", "gpio"; 368 gpio-controller; 369 #gpio-cells = <2>; 370 gpio-ranges = <&pinctrl_cbus 0 0 83>; 371 }; 372 373 eth_rgmii_pins: eth-rgmii { 374 mux { 375 groups = "eth_tx_clk", 376 "eth_tx_en", 377 "eth_txd1_0", 378 "eth_txd0_0", 379 "eth_rx_clk", 380 "eth_rx_dv", 381 "eth_rxd1", 382 "eth_rxd0", 383 "eth_mdio_en", 384 "eth_mdc", 385 "eth_ref_clk", 386 "eth_txd2", 387 "eth_txd3", 388 "eth_rxd3", 389 "eth_rxd2"; 390 function = "ethernet"; 391 bias-disable; 392 }; 393 }; 394 395 eth_rmii_pins: eth-rmii { 396 mux { 397 groups = "eth_tx_en", 398 "eth_txd1_0", 399 "eth_txd0_0", 400 "eth_rx_clk", 401 "eth_rx_dv", 402 "eth_rxd1", 403 "eth_rxd0", 404 "eth_mdio_en", 405 "eth_mdc"; 406 function = "ethernet"; 407 bias-disable; 408 }; 409 }; 410 411 i2c_a_pins: i2c-a { 412 mux { 413 groups = "i2c_sda_a", "i2c_sck_a"; 414 function = "i2c_a"; 415 bias-disable; 416 }; 417 }; 418 419 sd_b_pins: sd-b { 420 mux { 421 groups = "sd_d0_b", "sd_d1_b", "sd_d2_b", 422 "sd_d3_b", "sd_clk_b", "sd_cmd_b"; 423 function = "sd_b"; 424 bias-disable; 425 }; 426 }; 427 428 sdxc_c_pins: sdxc-c { 429 mux { 430 groups = "sdxc_d0_c", "sdxc_d13_c", 431 "sdxc_d47_c", "sdxc_clk_c", 432 "sdxc_cmd_c"; 433 function = "sdxc_c"; 434 bias-pull-up; 435 }; 436 }; 437 438 pwm_c1_pins: pwm-c1 { 439 mux { 440 groups = "pwm_c1"; 441 function = "pwm_c"; 442 bias-disable; 443 }; 444 }; 445 446 pwm_d_pins: pwm-d { 447 mux { 448 groups = "pwm_d"; 449 function = "pwm_d"; 450 bias-disable; 451 }; 452 }; 453 454 uart_b0_pins: uart-b0 { 455 mux { 456 groups = "uart_tx_b0", 457 "uart_rx_b0"; 458 function = "uart_b"; 459 bias-disable; 460 }; 461 }; 462 463 uart_b0_cts_rts_pins: uart-b0-cts-rts { 464 mux { 465 groups = "uart_cts_b0", 466 "uart_rts_b0"; 467 function = "uart_b"; 468 bias-disable; 469 }; 470 }; 471 }; 472}; 473 474&ahb_sram { 475 ao_arc_sram: ao-arc-sram@0 { 476 compatible = "amlogic,meson8b-ao-arc-sram"; 477 reg = <0x0 0x8000>; 478 pool; 479 }; 480 481 smp-sram@1ff80 { 482 compatible = "amlogic,meson8b-smp-sram"; 483 reg = <0x1ff80 0x8>; 484 }; 485}; 486 487 488&efuse { 489 compatible = "amlogic,meson8b-efuse"; 490 clocks = <&clkc CLKID_EFUSE>; 491 clock-names = "core"; 492 493 temperature_calib: calib@1f4 { 494 /* only the upper two bytes are relevant */ 495 reg = <0x1f4 0x4>; 496 }; 497}; 498 499ðmac { 500 compatible = "amlogic,meson8b-dwmac", "snps,dwmac-3.70a", "snps,dwmac"; 501 502 reg = <0xc9410000 0x10000 503 0xc1108140 0x4>; 504 505 clocks = <&clkc CLKID_ETH>, 506 <&clkc CLKID_MPLL2>, 507 <&clkc CLKID_MPLL2>, 508 <&clkc CLKID_FCLK_DIV2>; 509 clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment"; 510 rx-fifo-depth = <4096>; 511 tx-fifo-depth = <2048>; 512 513 resets = <&reset RESET_ETHERNET>; 514 reset-names = "stmmaceth"; 515 516 power-domains = <&pwrc PWRC_MESON8_ETHERNET_MEM_ID>; 517}; 518 519&gpio_intc { 520 compatible = "amlogic,meson-gpio-intc", 521 "amlogic,meson8b-gpio-intc"; 522 status = "okay"; 523}; 524 525&hhi { 526 clkc: clock-controller { 527 compatible = "amlogic,meson8b-clkc"; 528 clocks = <&xtal>, <&ddr_clkc DDR_CLKID_DDR_PLL>; 529 clock-names = "xtal", "ddr_pll"; 530 #clock-cells = <1>; 531 #reset-cells = <1>; 532 }; 533 534 pwrc: power-controller { 535 compatible = "amlogic,meson8b-pwrc"; 536 #power-domain-cells = <1>; 537 amlogic,ao-sysctrl = <&pmu>; 538 resets = <&reset RESET_DBLK>, 539 <&reset RESET_PIC_DC>, 540 <&reset RESET_HDMI_APB>, 541 <&reset RESET_HDMI_SYSTEM_RESET>, 542 <&reset RESET_VENCI>, 543 <&reset RESET_VENCP>, 544 <&reset RESET_VDAC_4>, 545 <&reset RESET_VENCL>, 546 <&reset RESET_VIU>, 547 <&reset RESET_VENC>, 548 <&reset RESET_RDMA>; 549 reset-names = "dblk", "pic_dc", "hdmi_apb", "hdmi_system", 550 "venci", "vencp", "vdac", "vencl", "viu", 551 "venc", "rdma"; 552 clocks = <&clkc CLKID_VPU>; 553 clock-names = "vpu"; 554 assigned-clocks = <&clkc CLKID_VPU>; 555 assigned-clock-rates = <182142857>; 556 }; 557}; 558 559&hwrng { 560 compatible = "amlogic,meson8b-rng", "amlogic,meson-rng"; 561 clocks = <&clkc CLKID_RNG0>; 562 clock-names = "core"; 563}; 564 565&i2c_AO { 566 clocks = <&clkc CLKID_CLK81>; 567}; 568 569&i2c_A { 570 clocks = <&clkc CLKID_I2C>; 571}; 572 573&i2c_B { 574 clocks = <&clkc CLKID_I2C>; 575}; 576 577&L2 { 578 arm,data-latency = <3 3 3>; 579 arm,tag-latency = <2 2 2>; 580 arm,filter-ranges = <0x100000 0xc0000000>; 581 prefetch-data = <1>; 582 prefetch-instr = <1>; 583 arm,shared-override; 584}; 585 586&periph { 587 scu@0 { 588 compatible = "arm,cortex-a5-scu"; 589 reg = <0x0 0x100>; 590 }; 591 592 timer@200 { 593 compatible = "arm,cortex-a5-global-timer"; 594 reg = <0x200 0x20>; 595 interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; 596 clocks = <&clkc CLKID_PERIPH>; 597 598 /* 599 * the arm_global_timer driver currently does not handle clock 600 * rate changes. Keep it disabled for now. 601 */ 602 status = "disabled"; 603 }; 604 605 timer@600 { 606 compatible = "arm,cortex-a5-twd-timer"; 607 reg = <0x600 0x20>; 608 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; 609 clocks = <&clkc CLKID_PERIPH>; 610 }; 611}; 612 613&pwm_ab { 614 compatible = "amlogic,meson8b-pwm"; 615}; 616 617&pwm_cd { 618 compatible = "amlogic,meson8b-pwm"; 619}; 620 621&rtc { 622 compatible = "amlogic,meson8b-rtc"; 623 resets = <&reset RESET_RTC>; 624}; 625 626&saradc { 627 compatible = "amlogic,meson8b-saradc", "amlogic,meson-saradc"; 628 clocks = <&xtal>, <&clkc CLKID_SAR_ADC>; 629 clock-names = "clkin", "core"; 630 amlogic,hhi-sysctrl = <&hhi>; 631 nvmem-cells = <&temperature_calib>; 632 nvmem-cell-names = "temperature_calib"; 633}; 634 635&sdhc { 636 compatible = "amlogic,meson8-sdhc", "amlogic,meson-mx-sdhc"; 637 clocks = <&xtal>, 638 <&clkc CLKID_FCLK_DIV4>, 639 <&clkc CLKID_FCLK_DIV3>, 640 <&clkc CLKID_FCLK_DIV5>, 641 <&clkc CLKID_SDHC>; 642 clock-names = "clkin0", "clkin1", "clkin2", "clkin3", "pclk"; 643}; 644 645&secbus { 646 secbus2: system-controller@4000 { 647 compatible = "amlogic,meson8b-secbus2", "syscon"; 648 reg = <0x4000 0x2000>; 649 }; 650}; 651 652&sdio { 653 compatible = "amlogic,meson8b-sdio", "amlogic,meson-mx-sdio"; 654 clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>; 655 clock-names = "core", "clkin"; 656}; 657 658&timer_abcde { 659 clocks = <&xtal>, <&clkc CLKID_CLK81>; 660 clock-names = "xtal", "pclk"; 661}; 662 663&uart_AO { 664 compatible = "amlogic,meson8b-uart", "amlogic,meson-uart"; 665 clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_CLK81>; 666 clock-names = "baud", "xtal", "pclk"; 667}; 668 669&uart_A { 670 compatible = "amlogic,meson8b-uart", "amlogic,meson-uart"; 671 clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART0>; 672 clock-names = "baud", "xtal", "pclk"; 673}; 674 675&uart_B { 676 compatible = "amlogic,meson8b-uart", "amlogic,meson-uart"; 677 clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART1>; 678 clock-names = "baud", "xtal", "pclk"; 679}; 680 681&uart_C { 682 compatible = "amlogic,meson8b-uart", "amlogic,meson-uart"; 683 clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART2>; 684 clock-names = "baud", "xtal", "pclk"; 685}; 686 687&usb0 { 688 compatible = "amlogic,meson8b-usb", "snps,dwc2"; 689 clocks = <&clkc CLKID_USB0_DDR_BRIDGE>; 690 clock-names = "otg"; 691}; 692 693&usb1 { 694 compatible = "amlogic,meson8b-usb", "snps,dwc2"; 695 clocks = <&clkc CLKID_USB1_DDR_BRIDGE>; 696 clock-names = "otg"; 697}; 698 699&usb0_phy { 700 compatible = "amlogic,meson8b-usb2-phy", "amlogic,meson-mx-usb2-phy"; 701 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>; 702 clock-names = "usb_general", "usb"; 703 resets = <&reset RESET_USB_OTG>; 704}; 705 706&usb1_phy { 707 compatible = "amlogic,meson8b-usb2-phy", "amlogic,meson-mx-usb2-phy"; 708 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>; 709 clock-names = "usb_general", "usb"; 710 resets = <&reset RESET_USB_OTG>; 711}; 712 713&wdt { 714 compatible = "amlogic,meson8b-wdt"; 715}; 716