1// SPDX-License-Identifier: GPL-2.0 2/dts-v1/; 3 4#include <dt-bindings/interconnect/qcom,msm8974.h> 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/clock/qcom,gcc-msm8974.h> 7#include <dt-bindings/clock/qcom,mmcc-msm8974.h> 8#include <dt-bindings/clock/qcom,rpmcc.h> 9#include <dt-bindings/reset/qcom,gcc-msm8974.h> 10#include <dt-bindings/gpio/gpio.h> 11 12/ { 13 #address-cells = <1>; 14 #size-cells = <1>; 15 model = "Qualcomm MSM8974"; 16 compatible = "qcom,msm8974"; 17 interrupt-parent = <&intc>; 18 19 reserved-memory { 20 #address-cells = <1>; 21 #size-cells = <1>; 22 ranges; 23 24 mpss_region: mpss@8000000 { 25 reg = <0x08000000 0x5100000>; 26 no-map; 27 }; 28 29 mba_region: mba@d100000 { 30 reg = <0x0d100000 0x100000>; 31 no-map; 32 }; 33 34 wcnss_region: wcnss@d200000 { 35 reg = <0x0d200000 0xa00000>; 36 no-map; 37 }; 38 39 adsp_region: adsp@dc00000 { 40 reg = <0x0dc00000 0x1900000>; 41 no-map; 42 }; 43 44 venus@f500000 { 45 reg = <0x0f500000 0x500000>; 46 no-map; 47 }; 48 49 smem_region: smem@fa00000 { 50 reg = <0xfa00000 0x200000>; 51 no-map; 52 }; 53 54 tz@fc00000 { 55 reg = <0x0fc00000 0x160000>; 56 no-map; 57 }; 58 59 rfsa@fd60000 { 60 reg = <0x0fd60000 0x20000>; 61 no-map; 62 }; 63 64 rmtfs@fd80000 { 65 compatible = "qcom,rmtfs-mem"; 66 reg = <0x0fd80000 0x180000>; 67 no-map; 68 69 qcom,client-id = <1>; 70 }; 71 }; 72 73 cpus { 74 #address-cells = <1>; 75 #size-cells = <0>; 76 interrupts = <GIC_PPI 9 0xf04>; 77 78 CPU0: cpu@0 { 79 compatible = "qcom,krait"; 80 enable-method = "qcom,kpss-acc-v2"; 81 device_type = "cpu"; 82 reg = <0>; 83 next-level-cache = <&L2>; 84 qcom,acc = <&acc0>; 85 qcom,saw = <&saw0>; 86 cpu-idle-states = <&CPU_SPC>; 87 }; 88 89 CPU1: cpu@1 { 90 compatible = "qcom,krait"; 91 enable-method = "qcom,kpss-acc-v2"; 92 device_type = "cpu"; 93 reg = <1>; 94 next-level-cache = <&L2>; 95 qcom,acc = <&acc1>; 96 qcom,saw = <&saw1>; 97 cpu-idle-states = <&CPU_SPC>; 98 }; 99 100 CPU2: cpu@2 { 101 compatible = "qcom,krait"; 102 enable-method = "qcom,kpss-acc-v2"; 103 device_type = "cpu"; 104 reg = <2>; 105 next-level-cache = <&L2>; 106 qcom,acc = <&acc2>; 107 qcom,saw = <&saw2>; 108 cpu-idle-states = <&CPU_SPC>; 109 }; 110 111 CPU3: cpu@3 { 112 compatible = "qcom,krait"; 113 enable-method = "qcom,kpss-acc-v2"; 114 device_type = "cpu"; 115 reg = <3>; 116 next-level-cache = <&L2>; 117 qcom,acc = <&acc3>; 118 qcom,saw = <&saw3>; 119 cpu-idle-states = <&CPU_SPC>; 120 }; 121 122 L2: l2-cache { 123 compatible = "cache"; 124 cache-level = <2>; 125 qcom,saw = <&saw_l2>; 126 }; 127 128 idle-states { 129 CPU_SPC: spc { 130 compatible = "qcom,idle-state-spc", 131 "arm,idle-state"; 132 entry-latency-us = <150>; 133 exit-latency-us = <200>; 134 min-residency-us = <2000>; 135 }; 136 }; 137 }; 138 139 memory { 140 device_type = "memory"; 141 reg = <0x0 0x0>; 142 }; 143 144 thermal-zones { 145 cpu-thermal0 { 146 polling-delay-passive = <250>; 147 polling-delay = <1000>; 148 149 thermal-sensors = <&tsens 5>; 150 151 trips { 152 cpu_alert0: trip0 { 153 temperature = <75000>; 154 hysteresis = <2000>; 155 type = "passive"; 156 }; 157 cpu_crit0: trip1 { 158 temperature = <110000>; 159 hysteresis = <2000>; 160 type = "critical"; 161 }; 162 }; 163 }; 164 165 cpu-thermal1 { 166 polling-delay-passive = <250>; 167 polling-delay = <1000>; 168 169 thermal-sensors = <&tsens 6>; 170 171 trips { 172 cpu_alert1: trip0 { 173 temperature = <75000>; 174 hysteresis = <2000>; 175 type = "passive"; 176 }; 177 cpu_crit1: trip1 { 178 temperature = <110000>; 179 hysteresis = <2000>; 180 type = "critical"; 181 }; 182 }; 183 }; 184 185 cpu-thermal2 { 186 polling-delay-passive = <250>; 187 polling-delay = <1000>; 188 189 thermal-sensors = <&tsens 7>; 190 191 trips { 192 cpu_alert2: trip0 { 193 temperature = <75000>; 194 hysteresis = <2000>; 195 type = "passive"; 196 }; 197 cpu_crit2: trip1 { 198 temperature = <110000>; 199 hysteresis = <2000>; 200 type = "critical"; 201 }; 202 }; 203 }; 204 205 cpu-thermal3 { 206 polling-delay-passive = <250>; 207 polling-delay = <1000>; 208 209 thermal-sensors = <&tsens 8>; 210 211 trips { 212 cpu_alert3: trip0 { 213 temperature = <75000>; 214 hysteresis = <2000>; 215 type = "passive"; 216 }; 217 cpu_crit3: trip1 { 218 temperature = <110000>; 219 hysteresis = <2000>; 220 type = "critical"; 221 }; 222 }; 223 }; 224 225 q6-dsp-thermal { 226 polling-delay-passive = <250>; 227 polling-delay = <1000>; 228 229 thermal-sensors = <&tsens 1>; 230 231 trips { 232 q6_dsp_alert0: trip-point0 { 233 temperature = <90000>; 234 hysteresis = <2000>; 235 type = "hot"; 236 }; 237 }; 238 }; 239 240 modemtx-thermal { 241 polling-delay-passive = <250>; 242 polling-delay = <1000>; 243 244 thermal-sensors = <&tsens 2>; 245 246 trips { 247 modemtx_alert0: trip-point0 { 248 temperature = <90000>; 249 hysteresis = <2000>; 250 type = "hot"; 251 }; 252 }; 253 }; 254 255 video-thermal { 256 polling-delay-passive = <250>; 257 polling-delay = <1000>; 258 259 thermal-sensors = <&tsens 3>; 260 261 trips { 262 video_alert0: trip-point0 { 263 temperature = <95000>; 264 hysteresis = <2000>; 265 type = "hot"; 266 }; 267 }; 268 }; 269 270 wlan-thermal { 271 polling-delay-passive = <250>; 272 polling-delay = <1000>; 273 274 thermal-sensors = <&tsens 4>; 275 276 trips { 277 wlan_alert0: trip-point0 { 278 temperature = <105000>; 279 hysteresis = <2000>; 280 type = "hot"; 281 }; 282 }; 283 }; 284 285 gpu-thermal-top { 286 polling-delay-passive = <250>; 287 polling-delay = <1000>; 288 289 thermal-sensors = <&tsens 9>; 290 291 trips { 292 gpu1_alert0: trip-point0 { 293 temperature = <90000>; 294 hysteresis = <2000>; 295 type = "hot"; 296 }; 297 }; 298 }; 299 300 gpu-thermal-bottom { 301 polling-delay-passive = <250>; 302 polling-delay = <1000>; 303 304 thermal-sensors = <&tsens 10>; 305 306 trips { 307 gpu2_alert0: trip-point0 { 308 temperature = <90000>; 309 hysteresis = <2000>; 310 type = "hot"; 311 }; 312 }; 313 }; 314 }; 315 316 cpu-pmu { 317 compatible = "qcom,krait-pmu"; 318 interrupts = <GIC_PPI 7 0xf04>; 319 }; 320 321 clocks { 322 xo_board: xo_board { 323 compatible = "fixed-clock"; 324 #clock-cells = <0>; 325 clock-frequency = <19200000>; 326 }; 327 328 sleep_clk: sleep_clk { 329 compatible = "fixed-clock"; 330 #clock-cells = <0>; 331 clock-frequency = <32768>; 332 }; 333 }; 334 335 timer { 336 compatible = "arm,armv7-timer"; 337 interrupts = <GIC_PPI 2 0xf08>, 338 <GIC_PPI 3 0xf08>, 339 <GIC_PPI 4 0xf08>, 340 <GIC_PPI 1 0xf08>; 341 clock-frequency = <19200000>; 342 }; 343 344 adsp-pil { 345 compatible = "qcom,msm8974-adsp-pil"; 346 347 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 348 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 349 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 350 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 351 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 352 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; 353 354 cx-supply = <&pm8841_s2>; 355 356 clocks = <&xo_board>; 357 clock-names = "xo"; 358 359 memory-region = <&adsp_region>; 360 361 qcom,smem-states = <&adsp_smp2p_out 0>; 362 qcom,smem-state-names = "stop"; 363 364 smd-edge { 365 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 366 367 qcom,ipc = <&apcs 8 8>; 368 qcom,smd-edge = <1>; 369 370 label = "lpass"; 371 }; 372 }; 373 374 smem { 375 compatible = "qcom,smem"; 376 377 memory-region = <&smem_region>; 378 qcom,rpm-msg-ram = <&rpm_msg_ram>; 379 380 hwlocks = <&tcsr_mutex 3>; 381 }; 382 383 smp2p-adsp { 384 compatible = "qcom,smp2p"; 385 qcom,smem = <443>, <429>; 386 387 interrupt-parent = <&intc>; 388 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 389 390 qcom,ipc = <&apcs 8 10>; 391 392 qcom,local-pid = <0>; 393 qcom,remote-pid = <2>; 394 395 adsp_smp2p_out: master-kernel { 396 qcom,entry-name = "master-kernel"; 397 #qcom,smem-state-cells = <1>; 398 }; 399 400 adsp_smp2p_in: slave-kernel { 401 qcom,entry-name = "slave-kernel"; 402 403 interrupt-controller; 404 #interrupt-cells = <2>; 405 }; 406 }; 407 408 smp2p-modem { 409 compatible = "qcom,smp2p"; 410 qcom,smem = <435>, <428>; 411 412 interrupt-parent = <&intc>; 413 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>; 414 415 qcom,ipc = <&apcs 8 14>; 416 417 qcom,local-pid = <0>; 418 qcom,remote-pid = <1>; 419 420 modem_smp2p_out: master-kernel { 421 qcom,entry-name = "master-kernel"; 422 #qcom,smem-state-cells = <1>; 423 }; 424 425 modem_smp2p_in: slave-kernel { 426 qcom,entry-name = "slave-kernel"; 427 428 interrupt-controller; 429 #interrupt-cells = <2>; 430 }; 431 }; 432 433 smp2p-wcnss { 434 compatible = "qcom,smp2p"; 435 qcom,smem = <451>, <431>; 436 437 interrupt-parent = <&intc>; 438 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>; 439 440 qcom,ipc = <&apcs 8 18>; 441 442 qcom,local-pid = <0>; 443 qcom,remote-pid = <4>; 444 445 wcnss_smp2p_out: master-kernel { 446 qcom,entry-name = "master-kernel"; 447 448 #qcom,smem-state-cells = <1>; 449 }; 450 451 wcnss_smp2p_in: slave-kernel { 452 qcom,entry-name = "slave-kernel"; 453 454 interrupt-controller; 455 #interrupt-cells = <2>; 456 }; 457 }; 458 459 smsm { 460 compatible = "qcom,smsm"; 461 462 #address-cells = <1>; 463 #size-cells = <0>; 464 465 qcom,ipc-1 = <&apcs 8 13>; 466 qcom,ipc-2 = <&apcs 8 9>; 467 qcom,ipc-3 = <&apcs 8 19>; 468 469 apps_smsm: apps@0 { 470 reg = <0>; 471 472 #qcom,smem-state-cells = <1>; 473 }; 474 475 modem_smsm: modem@1 { 476 reg = <1>; 477 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 478 479 interrupt-controller; 480 #interrupt-cells = <2>; 481 }; 482 483 adsp_smsm: adsp@2 { 484 reg = <2>; 485 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>; 486 487 interrupt-controller; 488 #interrupt-cells = <2>; 489 }; 490 491 wcnss_smsm: wcnss@7 { 492 reg = <7>; 493 interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>; 494 495 interrupt-controller; 496 #interrupt-cells = <2>; 497 }; 498 }; 499 500 firmware { 501 scm { 502 compatible = "qcom,scm"; 503 clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>; 504 clock-names = "core", "bus", "iface"; 505 }; 506 }; 507 508 soc: soc { 509 #address-cells = <1>; 510 #size-cells = <1>; 511 ranges; 512 compatible = "simple-bus"; 513 514 intc: interrupt-controller@f9000000 { 515 compatible = "qcom,msm-qgic2"; 516 interrupt-controller; 517 #interrupt-cells = <3>; 518 reg = <0xf9000000 0x1000>, 519 <0xf9002000 0x1000>; 520 }; 521 522 apcs: syscon@f9011000 { 523 compatible = "syscon"; 524 reg = <0xf9011000 0x1000>; 525 }; 526 527 qfprom: qfprom@fc4bc000 { 528 #address-cells = <1>; 529 #size-cells = <1>; 530 compatible = "qcom,qfprom"; 531 reg = <0xfc4bc000 0x1000>; 532 tsens_calib: calib@d0 { 533 reg = <0xd0 0x18>; 534 }; 535 tsens_backup: backup@440 { 536 reg = <0x440 0x10>; 537 }; 538 }; 539 540 tsens: thermal-sensor@fc4a9000 { 541 compatible = "qcom,msm8974-tsens"; 542 reg = <0xfc4a9000 0x1000>, /* TM */ 543 <0xfc4a8000 0x1000>; /* SROT */ 544 nvmem-cells = <&tsens_calib>, <&tsens_backup>; 545 nvmem-cell-names = "calib", "calib_backup"; 546 #qcom,sensors = <11>; 547 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 548 interrupt-names = "uplow"; 549 #thermal-sensor-cells = <1>; 550 }; 551 552 timer@f9020000 { 553 #address-cells = <1>; 554 #size-cells = <1>; 555 ranges; 556 compatible = "arm,armv7-timer-mem"; 557 reg = <0xf9020000 0x1000>; 558 clock-frequency = <19200000>; 559 560 frame@f9021000 { 561 frame-number = <0>; 562 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 563 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 564 reg = <0xf9021000 0x1000>, 565 <0xf9022000 0x1000>; 566 }; 567 568 frame@f9023000 { 569 frame-number = <1>; 570 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 571 reg = <0xf9023000 0x1000>; 572 status = "disabled"; 573 }; 574 575 frame@f9024000 { 576 frame-number = <2>; 577 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 578 reg = <0xf9024000 0x1000>; 579 status = "disabled"; 580 }; 581 582 frame@f9025000 { 583 frame-number = <3>; 584 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 585 reg = <0xf9025000 0x1000>; 586 status = "disabled"; 587 }; 588 589 frame@f9026000 { 590 frame-number = <4>; 591 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 592 reg = <0xf9026000 0x1000>; 593 status = "disabled"; 594 }; 595 596 frame@f9027000 { 597 frame-number = <5>; 598 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 599 reg = <0xf9027000 0x1000>; 600 status = "disabled"; 601 }; 602 603 frame@f9028000 { 604 frame-number = <6>; 605 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 606 reg = <0xf9028000 0x1000>; 607 status = "disabled"; 608 }; 609 }; 610 611 saw0: power-controller@f9089000 { 612 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; 613 reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>; 614 }; 615 616 saw1: power-controller@f9099000 { 617 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; 618 reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>; 619 }; 620 621 saw2: power-controller@f90a9000 { 622 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; 623 reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>; 624 }; 625 626 saw3: power-controller@f90b9000 { 627 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; 628 reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>; 629 }; 630 631 saw_l2: power-controller@f9012000 { 632 compatible = "qcom,saw2"; 633 reg = <0xf9012000 0x1000>; 634 regulator; 635 }; 636 637 acc0: clock-controller@f9088000 { 638 compatible = "qcom,kpss-acc-v2"; 639 reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>; 640 }; 641 642 acc1: clock-controller@f9098000 { 643 compatible = "qcom,kpss-acc-v2"; 644 reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>; 645 }; 646 647 acc2: clock-controller@f90a8000 { 648 compatible = "qcom,kpss-acc-v2"; 649 reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>; 650 }; 651 652 acc3: clock-controller@f90b8000 { 653 compatible = "qcom,kpss-acc-v2"; 654 reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>; 655 }; 656 657 restart@fc4ab000 { 658 compatible = "qcom,pshold"; 659 reg = <0xfc4ab000 0x4>; 660 }; 661 662 gcc: clock-controller@fc400000 { 663 compatible = "qcom,gcc-msm8974"; 664 #clock-cells = <1>; 665 #reset-cells = <1>; 666 #power-domain-cells = <1>; 667 reg = <0xfc400000 0x4000>; 668 }; 669 670 tcsr: syscon@fd4a0000 { 671 compatible = "syscon"; 672 reg = <0xfd4a0000 0x10000>; 673 }; 674 675 tcsr_mutex_block: syscon@fd484000 { 676 compatible = "syscon"; 677 reg = <0xfd484000 0x2000>; 678 }; 679 680 mmcc: clock-controller@fd8c0000 { 681 compatible = "qcom,mmcc-msm8974"; 682 #clock-cells = <1>; 683 #reset-cells = <1>; 684 #power-domain-cells = <1>; 685 reg = <0xfd8c0000 0x6000>; 686 }; 687 688 tcsr_mutex: tcsr-mutex { 689 compatible = "qcom,tcsr-mutex"; 690 syscon = <&tcsr_mutex_block 0 0x80>; 691 692 #hwlock-cells = <1>; 693 }; 694 695 rpm_msg_ram: memory@fc428000 { 696 compatible = "qcom,rpm-msg-ram"; 697 reg = <0xfc428000 0x4000>; 698 }; 699 700 blsp1_uart1: serial@f991d000 { 701 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 702 reg = <0xf991d000 0x1000>; 703 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 704 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 705 clock-names = "core", "iface"; 706 status = "disabled"; 707 }; 708 709 blsp1_uart2: serial@f991e000 { 710 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 711 reg = <0xf991e000 0x1000>; 712 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 713 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 714 clock-names = "core", "iface"; 715 status = "disabled"; 716 }; 717 718 blsp2_uart8: serial@f995e000 { 719 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 720 reg = <0xf995e000 0x1000>; 721 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 722 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 723 clock-names = "core", "iface"; 724 status = "disabled"; 725 }; 726 727 blsp2_uart10: serial@f9960000 { 728 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 729 reg = <0xf9960000 0x1000>; 730 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 731 clocks = <&gcc GCC_BLSP2_UART4_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 732 clock-names = "core", "iface"; 733 status = "disabled"; 734 }; 735 736 sdhci@f9824900 { 737 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; 738 reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; 739 reg-names = "hc_mem", "core_mem"; 740 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 741 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 742 interrupt-names = "hc_irq", "pwr_irq"; 743 clocks = <&gcc GCC_SDCC1_APPS_CLK>, 744 <&gcc GCC_SDCC1_AHB_CLK>, 745 <&xo_board>; 746 clock-names = "core", "iface", "xo"; 747 status = "disabled"; 748 }; 749 750 sdhci@f9864900 { 751 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; 752 reg = <0xf9864900 0x11c>, <0xf9864000 0x800>; 753 reg-names = "hc_mem", "core_mem"; 754 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 755 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 756 interrupt-names = "hc_irq", "pwr_irq"; 757 clocks = <&gcc GCC_SDCC3_APPS_CLK>, 758 <&gcc GCC_SDCC3_AHB_CLK>, 759 <&xo_board>; 760 clock-names = "core", "iface", "xo"; 761 status = "disabled"; 762 }; 763 764 sdhci@f98a4900 { 765 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; 766 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; 767 reg-names = "hc_mem", "core_mem"; 768 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 769 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 770 interrupt-names = "hc_irq", "pwr_irq"; 771 clocks = <&gcc GCC_SDCC2_APPS_CLK>, 772 <&gcc GCC_SDCC2_AHB_CLK>, 773 <&xo_board>; 774 clock-names = "core", "iface", "xo"; 775 status = "disabled"; 776 }; 777 778 otg: usb@f9a55000 { 779 compatible = "qcom,ci-hdrc"; 780 reg = <0xf9a55000 0x200>, 781 <0xf9a55200 0x200>; 782 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 783 clocks = <&gcc GCC_USB_HS_AHB_CLK>, 784 <&gcc GCC_USB_HS_SYSTEM_CLK>; 785 clock-names = "iface", "core"; 786 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>; 787 assigned-clock-rates = <75000000>; 788 resets = <&gcc GCC_USB_HS_BCR>; 789 reset-names = "core"; 790 phy_type = "ulpi"; 791 dr_mode = "otg"; 792 ahb-burst-config = <0>; 793 phy-names = "usb-phy"; 794 status = "disabled"; 795 #reset-cells = <1>; 796 797 ulpi { 798 usb_hs1_phy: phy@a { 799 compatible = "qcom,usb-hs-phy-msm8974", 800 "qcom,usb-hs-phy"; 801 #phy-cells = <0>; 802 clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>; 803 clock-names = "ref", "sleep"; 804 resets = <&gcc GCC_USB2A_PHY_BCR>, <&otg 0>; 805 reset-names = "phy", "por"; 806 status = "disabled"; 807 }; 808 809 usb_hs2_phy: phy@b { 810 compatible = "qcom,usb-hs-phy-msm8974", 811 "qcom,usb-hs-phy"; 812 #phy-cells = <0>; 813 clocks = <&xo_board>, <&gcc GCC_USB2B_PHY_SLEEP_CLK>; 814 clock-names = "ref", "sleep"; 815 resets = <&gcc GCC_USB2B_PHY_BCR>, <&otg 1>; 816 reset-names = "phy", "por"; 817 status = "disabled"; 818 }; 819 }; 820 }; 821 822 rng@f9bff000 { 823 compatible = "qcom,prng"; 824 reg = <0xf9bff000 0x200>; 825 clocks = <&gcc GCC_PRNG_AHB_CLK>; 826 clock-names = "core"; 827 }; 828 829 remoteproc@fc880000 { 830 compatible = "qcom,msm8974-mss-pil"; 831 reg = <0xfc880000 0x100>, <0xfc820000 0x020>; 832 reg-names = "qdsp6", "rmb"; 833 834 interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>, 835 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 836 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 837 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 838 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 839 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; 840 841 clocks = <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, 842 <&gcc GCC_MSS_CFG_AHB_CLK>, 843 <&gcc GCC_BOOT_ROM_AHB_CLK>, 844 <&xo_board>; 845 clock-names = "iface", "bus", "mem", "xo"; 846 847 resets = <&gcc GCC_MSS_RESTART>; 848 reset-names = "mss_restart"; 849 850 cx-supply = <&pm8841_s2>; 851 mss-supply = <&pm8841_s3>; 852 mx-supply = <&pm8841_s1>; 853 pll-supply = <&pm8941_l12>; 854 855 qcom,halt-regs = <&tcsr_mutex_block 0x1180 0x1200 0x1280>; 856 857 qcom,smem-states = <&modem_smp2p_out 0>; 858 qcom,smem-state-names = "stop"; 859 860 mba { 861 memory-region = <&mba_region>; 862 }; 863 864 mpss { 865 memory-region = <&mpss_region>; 866 }; 867 868 smd-edge { 869 interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>; 870 871 qcom,ipc = <&apcs 8 12>; 872 qcom,smd-edge = <0>; 873 874 label = "modem"; 875 }; 876 }; 877 878 pronto: remoteproc@fb21b000 { 879 compatible = "qcom,pronto-v2-pil", "qcom,pronto"; 880 reg = <0xfb204000 0x2000>, <0xfb202000 0x1000>, <0xfb21b000 0x3000>; 881 reg-names = "ccu", "dxe", "pmu"; 882 883 memory-region = <&wcnss_region>; 884 885 interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>, 886 <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 887 <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 888 <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 889 <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 890 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; 891 892 vddpx-supply = <&pm8941_s3>; 893 894 qcom,smem-states = <&wcnss_smp2p_out 0>; 895 qcom,smem-state-names = "stop"; 896 897 status = "disabled"; 898 899 iris { 900 compatible = "qcom,wcn3680"; 901 902 clocks = <&rpmcc RPM_SMD_CXO_A2>; 903 clock-names = "xo"; 904 905 vddxo-supply = <&pm8941_l6>; 906 vddrfa-supply = <&pm8941_l11>; 907 vddpa-supply = <&pm8941_l19>; 908 vdddig-supply = <&pm8941_s3>; 909 }; 910 911 smd-edge { 912 interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>; 913 914 qcom,ipc = <&apcs 8 17>; 915 qcom,smd-edge = <6>; 916 917 wcnss { 918 compatible = "qcom,wcnss"; 919 qcom,smd-channels = "WCNSS_CTRL"; 920 status = "disabled"; 921 922 qcom,mmio = <&pronto>; 923 924 bt { 925 compatible = "qcom,wcnss-bt"; 926 }; 927 928 wifi { 929 compatible = "qcom,wcnss-wlan"; 930 931 interrupts = <GIC_SPI 145 IRQ_TYPE_EDGE_RISING>, 932 <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>; 933 interrupt-names = "tx", "rx"; 934 935 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>; 936 qcom,smem-state-names = "tx-enable", "tx-rings-empty"; 937 }; 938 }; 939 }; 940 }; 941 942 msmgpio: pinctrl@fd510000 { 943 compatible = "qcom,msm8974-pinctrl"; 944 reg = <0xfd510000 0x4000>; 945 gpio-controller; 946 gpio-ranges = <&msmgpio 0 0 146>; 947 #gpio-cells = <2>; 948 interrupt-controller; 949 #interrupt-cells = <2>; 950 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 951 }; 952 953 i2c@f9923000 { 954 status = "disabled"; 955 compatible = "qcom,i2c-qup-v2.1.1"; 956 reg = <0xf9923000 0x1000>; 957 interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>; 958 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 959 clock-names = "core", "iface"; 960 #address-cells = <1>; 961 #size-cells = <0>; 962 }; 963 964 i2c@f9924000 { 965 status = "disabled"; 966 compatible = "qcom,i2c-qup-v2.1.1"; 967 reg = <0xf9924000 0x1000>; 968 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 969 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 970 clock-names = "core", "iface"; 971 #address-cells = <1>; 972 #size-cells = <0>; 973 }; 974 975 blsp_i2c3: i2c@f9925000 { 976 status = "disabled"; 977 compatible = "qcom,i2c-qup-v2.1.1"; 978 reg = <0xf9925000 0x1000>; 979 interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>; 980 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 981 clock-names = "core", "iface"; 982 #address-cells = <1>; 983 #size-cells = <0>; 984 }; 985 986 blsp_i2c6: i2c@f9928000 { 987 status = "disabled"; 988 compatible = "qcom,i2c-qup-v2.1.1"; 989 reg = <0xf9928000 0x1000>; 990 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 991 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 992 clock-names = "core", "iface"; 993 #address-cells = <1>; 994 #size-cells = <0>; 995 }; 996 997 blsp_i2c8: i2c@f9964000 { 998 status = "disabled"; 999 compatible = "qcom,i2c-qup-v2.1.1"; 1000 reg = <0xf9964000 0x1000>; 1001 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1002 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 1003 clock-names = "core", "iface"; 1004 #address-cells = <1>; 1005 #size-cells = <0>; 1006 }; 1007 1008 blsp_i2c11: i2c@f9967000 { 1009 status = "disabled"; 1010 compatible = "qcom,i2c-qup-v2.1.1"; 1011 reg = <0xf9967000 0x1000>; 1012 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 1013 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 1014 clock-names = "core", "iface"; 1015 #address-cells = <1>; 1016 #size-cells = <0>; 1017 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>; 1018 dma-names = "tx", "rx"; 1019 }; 1020 1021 blsp_i2c12: i2c@f9968000 { 1022 status = "disabled"; 1023 compatible = "qcom,i2c-qup-v2.1.1"; 1024 reg = <0xf9968000 0x1000>; 1025 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; 1026 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 1027 clock-names = "core", "iface"; 1028 #address-cells = <1>; 1029 #size-cells = <0>; 1030 }; 1031 1032 spmi_bus: spmi@fc4cf000 { 1033 compatible = "qcom,spmi-pmic-arb"; 1034 reg-names = "core", "intr", "cnfg"; 1035 reg = <0xfc4cf000 0x1000>, 1036 <0xfc4cb000 0x1000>, 1037 <0xfc4ca000 0x1000>; 1038 interrupt-names = "periph_irq"; 1039 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1040 qcom,ee = <0>; 1041 qcom,channel = <0>; 1042 #address-cells = <2>; 1043 #size-cells = <0>; 1044 interrupt-controller; 1045 #interrupt-cells = <4>; 1046 }; 1047 1048 blsp2_dma: dma-controller@f9944000 { 1049 compatible = "qcom,bam-v1.4.0"; 1050 reg = <0xf9944000 0x19000>; 1051 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 1052 clocks = <&gcc GCC_BLSP2_AHB_CLK>; 1053 clock-names = "bam_clk"; 1054 #dma-cells = <1>; 1055 qcom,ee = <0>; 1056 }; 1057 1058 etr@fc322000 { 1059 compatible = "arm,coresight-tmc", "arm,primecell"; 1060 reg = <0xfc322000 0x1000>; 1061 1062 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1063 clock-names = "apb_pclk", "atclk"; 1064 1065 in-ports { 1066 port { 1067 etr_in: endpoint { 1068 remote-endpoint = <&replicator_out0>; 1069 }; 1070 }; 1071 }; 1072 }; 1073 1074 tpiu@fc318000 { 1075 compatible = "arm,coresight-tpiu", "arm,primecell"; 1076 reg = <0xfc318000 0x1000>; 1077 1078 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1079 clock-names = "apb_pclk", "atclk"; 1080 1081 in-ports { 1082 port { 1083 tpiu_in: endpoint { 1084 remote-endpoint = <&replicator_out1>; 1085 }; 1086 }; 1087 }; 1088 }; 1089 1090 replicator@fc31c000 { 1091 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 1092 reg = <0xfc31c000 0x1000>; 1093 1094 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1095 clock-names = "apb_pclk", "atclk"; 1096 1097 out-ports { 1098 #address-cells = <1>; 1099 #size-cells = <0>; 1100 1101 port@0 { 1102 reg = <0>; 1103 replicator_out0: endpoint { 1104 remote-endpoint = <&etr_in>; 1105 }; 1106 }; 1107 port@1 { 1108 reg = <1>; 1109 replicator_out1: endpoint { 1110 remote-endpoint = <&tpiu_in>; 1111 }; 1112 }; 1113 }; 1114 1115 in-ports { 1116 port { 1117 replicator_in: endpoint { 1118 remote-endpoint = <&etf_out>; 1119 }; 1120 }; 1121 }; 1122 }; 1123 1124 etf@fc307000 { 1125 compatible = "arm,coresight-tmc", "arm,primecell"; 1126 reg = <0xfc307000 0x1000>; 1127 1128 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1129 clock-names = "apb_pclk", "atclk"; 1130 1131 out-ports { 1132 port { 1133 etf_out: endpoint { 1134 remote-endpoint = <&replicator_in>; 1135 }; 1136 }; 1137 }; 1138 1139 in-ports { 1140 port { 1141 etf_in: endpoint { 1142 remote-endpoint = <&merger_out>; 1143 }; 1144 }; 1145 }; 1146 }; 1147 1148 funnel@fc31b000 { 1149 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1150 reg = <0xfc31b000 0x1000>; 1151 1152 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1153 clock-names = "apb_pclk", "atclk"; 1154 1155 in-ports { 1156 #address-cells = <1>; 1157 #size-cells = <0>; 1158 1159 /* 1160 * Not described input ports: 1161 * 0 - connected trought funnel to Audio, Modem and 1162 * Resource and Power Manager CPU's 1163 * 2...7 - not-connected 1164 */ 1165 port@1 { 1166 reg = <1>; 1167 merger_in1: endpoint { 1168 remote-endpoint = <&funnel1_out>; 1169 }; 1170 }; 1171 }; 1172 1173 out-ports { 1174 port { 1175 merger_out: endpoint { 1176 remote-endpoint = <&etf_in>; 1177 }; 1178 }; 1179 }; 1180 }; 1181 1182 funnel@fc31a000 { 1183 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1184 reg = <0xfc31a000 0x1000>; 1185 1186 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1187 clock-names = "apb_pclk", "atclk"; 1188 1189 in-ports { 1190 #address-cells = <1>; 1191 #size-cells = <0>; 1192 1193 /* 1194 * Not described input ports: 1195 * 0 - not-connected 1196 * 1 - connected trought funnel to Multimedia CPU 1197 * 2 - connected to Wireless CPU 1198 * 3 - not-connected 1199 * 4 - not-connected 1200 * 6 - not-connected 1201 * 7 - connected to STM 1202 */ 1203 port@5 { 1204 reg = <5>; 1205 funnel1_in5: endpoint { 1206 remote-endpoint = <&kpss_out>; 1207 }; 1208 }; 1209 }; 1210 1211 out-ports { 1212 port { 1213 funnel1_out: endpoint { 1214 remote-endpoint = <&merger_in1>; 1215 }; 1216 }; 1217 }; 1218 }; 1219 1220 funnel@fc345000 { /* KPSS funnel only 4 inputs are used */ 1221 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1222 reg = <0xfc345000 0x1000>; 1223 1224 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1225 clock-names = "apb_pclk", "atclk"; 1226 1227 in-ports { 1228 #address-cells = <1>; 1229 #size-cells = <0>; 1230 1231 port@0 { 1232 reg = <0>; 1233 kpss_in0: endpoint { 1234 remote-endpoint = <&etm0_out>; 1235 }; 1236 }; 1237 port@1 { 1238 reg = <1>; 1239 kpss_in1: endpoint { 1240 remote-endpoint = <&etm1_out>; 1241 }; 1242 }; 1243 port@2 { 1244 reg = <2>; 1245 kpss_in2: endpoint { 1246 remote-endpoint = <&etm2_out>; 1247 }; 1248 }; 1249 port@3 { 1250 reg = <3>; 1251 kpss_in3: endpoint { 1252 remote-endpoint = <&etm3_out>; 1253 }; 1254 }; 1255 }; 1256 1257 out-ports { 1258 port { 1259 kpss_out: endpoint { 1260 remote-endpoint = <&funnel1_in5>; 1261 }; 1262 }; 1263 }; 1264 }; 1265 1266 etm@fc33c000 { 1267 compatible = "arm,coresight-etm4x", "arm,primecell"; 1268 reg = <0xfc33c000 0x1000>; 1269 1270 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1271 clock-names = "apb_pclk", "atclk"; 1272 1273 cpu = <&CPU0>; 1274 1275 out-ports { 1276 port { 1277 etm0_out: endpoint { 1278 remote-endpoint = <&kpss_in0>; 1279 }; 1280 }; 1281 }; 1282 }; 1283 1284 etm@fc33d000 { 1285 compatible = "arm,coresight-etm4x", "arm,primecell"; 1286 reg = <0xfc33d000 0x1000>; 1287 1288 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1289 clock-names = "apb_pclk", "atclk"; 1290 1291 cpu = <&CPU1>; 1292 1293 out-ports { 1294 port { 1295 etm1_out: endpoint { 1296 remote-endpoint = <&kpss_in1>; 1297 }; 1298 }; 1299 }; 1300 }; 1301 1302 etm@fc33e000 { 1303 compatible = "arm,coresight-etm4x", "arm,primecell"; 1304 reg = <0xfc33e000 0x1000>; 1305 1306 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1307 clock-names = "apb_pclk", "atclk"; 1308 1309 cpu = <&CPU2>; 1310 1311 out-ports { 1312 port { 1313 etm2_out: endpoint { 1314 remote-endpoint = <&kpss_in2>; 1315 }; 1316 }; 1317 }; 1318 }; 1319 1320 etm@fc33f000 { 1321 compatible = "arm,coresight-etm4x", "arm,primecell"; 1322 reg = <0xfc33f000 0x1000>; 1323 1324 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1325 clock-names = "apb_pclk", "atclk"; 1326 1327 cpu = <&CPU3>; 1328 1329 out-ports { 1330 port { 1331 etm3_out: endpoint { 1332 remote-endpoint = <&kpss_in3>; 1333 }; 1334 }; 1335 }; 1336 }; 1337 1338 ocmem@fdd00000 { 1339 compatible = "qcom,msm8974-ocmem"; 1340 reg = <0xfdd00000 0x2000>, 1341 <0xfec00000 0x180000>; 1342 reg-names = "ctrl", 1343 "mem"; 1344 clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>, 1345 <&mmcc OCMEMCX_OCMEMNOC_CLK>; 1346 clock-names = "core", 1347 "iface"; 1348 1349 #address-cells = <1>; 1350 #size-cells = <1>; 1351 1352 gmu_sram: gmu-sram@0 { 1353 reg = <0x0 0x100000>; 1354 }; 1355 }; 1356 1357 bimc: interconnect@fc380000 { 1358 reg = <0xfc380000 0x6a000>; 1359 compatible = "qcom,msm8974-bimc"; 1360 #interconnect-cells = <1>; 1361 clock-names = "bus", "bus_a"; 1362 clocks = <&rpmcc RPM_SMD_BIMC_CLK>, 1363 <&rpmcc RPM_SMD_BIMC_A_CLK>; 1364 }; 1365 1366 snoc: interconnect@fc460000 { 1367 reg = <0xfc460000 0x4000>; 1368 compatible = "qcom,msm8974-snoc"; 1369 #interconnect-cells = <1>; 1370 clock-names = "bus", "bus_a"; 1371 clocks = <&rpmcc RPM_SMD_SNOC_CLK>, 1372 <&rpmcc RPM_SMD_SNOC_A_CLK>; 1373 }; 1374 1375 pnoc: interconnect@fc468000 { 1376 reg = <0xfc468000 0x4000>; 1377 compatible = "qcom,msm8974-pnoc"; 1378 #interconnect-cells = <1>; 1379 clock-names = "bus", "bus_a"; 1380 clocks = <&rpmcc RPM_SMD_PNOC_CLK>, 1381 <&rpmcc RPM_SMD_PNOC_A_CLK>; 1382 }; 1383 1384 ocmemnoc: interconnect@fc470000 { 1385 reg = <0xfc470000 0x4000>; 1386 compatible = "qcom,msm8974-ocmemnoc"; 1387 #interconnect-cells = <1>; 1388 clock-names = "bus", "bus_a"; 1389 clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>, 1390 <&rpmcc RPM_SMD_OCMEMGX_A_CLK>; 1391 }; 1392 1393 mmssnoc: interconnect@fc478000 { 1394 reg = <0xfc478000 0x4000>; 1395 compatible = "qcom,msm8974-mmssnoc"; 1396 #interconnect-cells = <1>; 1397 clock-names = "bus", "bus_a"; 1398 clocks = <&mmcc MMSS_S0_AXI_CLK>, 1399 <&mmcc MMSS_S0_AXI_CLK>; 1400 }; 1401 1402 cnoc: interconnect@fc480000 { 1403 reg = <0xfc480000 0x4000>; 1404 compatible = "qcom,msm8974-cnoc"; 1405 #interconnect-cells = <1>; 1406 clock-names = "bus", "bus_a"; 1407 clocks = <&rpmcc RPM_SMD_CNOC_CLK>, 1408 <&rpmcc RPM_SMD_CNOC_A_CLK>; 1409 }; 1410 1411 gpu: adreno@fdb00000 { 1412 status = "disabled"; 1413 1414 compatible = "qcom,adreno-330.1", 1415 "qcom,adreno"; 1416 reg = <0xfdb00000 0x10000>; 1417 reg-names = "kgsl_3d0_reg_memory"; 1418 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 1419 interrupt-names = "kgsl_3d0_irq"; 1420 clock-names = "core", 1421 "iface", 1422 "mem_iface"; 1423 clocks = <&mmcc OXILI_GFX3D_CLK>, 1424 <&mmcc OXILICX_AHB_CLK>, 1425 <&mmcc OXILICX_AXI_CLK>; 1426 sram = <&gmu_sram>; 1427 power-domains = <&mmcc OXILICX_GDSC>; 1428 operating-points-v2 = <&gpu_opp_table>; 1429 1430 interconnects = <&mmssnoc MNOC_MAS_GRAPHICS_3D &bimc BIMC_SLV_EBI_CH0>, 1431 <&ocmemnoc OCMEM_VNOC_MAS_GFX3D &ocmemnoc OCMEM_SLV_OCMEM>; 1432 interconnect-names = "gfx-mem", 1433 "ocmem"; 1434 1435 // iommus = <&gpu_iommu 0>; 1436 1437 gpu_opp_table: opp_table { 1438 compatible = "operating-points-v2"; 1439 1440 opp-320000000 { 1441 opp-hz = /bits/ 64 <320000000>; 1442 }; 1443 1444 opp-200000000 { 1445 opp-hz = /bits/ 64 <200000000>; 1446 }; 1447 1448 opp-27000000 { 1449 opp-hz = /bits/ 64 <27000000>; 1450 }; 1451 }; 1452 }; 1453 1454 mdss: mdss@fd900000 { 1455 status = "disabled"; 1456 1457 compatible = "qcom,mdss"; 1458 reg = <0xfd900000 0x100>, 1459 <0xfd924000 0x1000>; 1460 reg-names = "mdss_phys", 1461 "vbif_phys"; 1462 1463 power-domains = <&mmcc MDSS_GDSC>; 1464 1465 clocks = <&mmcc MDSS_AHB_CLK>, 1466 <&mmcc MDSS_AXI_CLK>, 1467 <&mmcc MDSS_VSYNC_CLK>; 1468 clock-names = "iface", 1469 "bus", 1470 "vsync"; 1471 1472 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1473 1474 interrupt-controller; 1475 #interrupt-cells = <1>; 1476 1477 #address-cells = <1>; 1478 #size-cells = <1>; 1479 ranges; 1480 1481 mdp: mdp@fd900000 { 1482 status = "disabled"; 1483 1484 compatible = "qcom,mdp5"; 1485 reg = <0xfd900100 0x22000>; 1486 reg-names = "mdp_phys"; 1487 1488 interrupt-parent = <&mdss>; 1489 interrupts = <0 0>; 1490 1491 clocks = <&mmcc MDSS_AHB_CLK>, 1492 <&mmcc MDSS_AXI_CLK>, 1493 <&mmcc MDSS_MDP_CLK>, 1494 <&mmcc MDSS_VSYNC_CLK>; 1495 clock-names = "iface", 1496 "bus", 1497 "core", 1498 "vsync"; 1499 1500 interconnects = <&mmssnoc MNOC_MAS_MDP_PORT0 &bimc BIMC_SLV_EBI_CH0>; 1501 interconnect-names = "mdp0-mem"; 1502 1503 ports { 1504 #address-cells = <1>; 1505 #size-cells = <0>; 1506 1507 port@0 { 1508 reg = <0>; 1509 mdp5_intf1_out: endpoint { 1510 remote-endpoint = <&dsi0_in>; 1511 }; 1512 }; 1513 }; 1514 }; 1515 1516 dsi0: dsi@fd922800 { 1517 status = "disabled"; 1518 1519 compatible = "qcom,mdss-dsi-ctrl"; 1520 reg = <0xfd922800 0x1f8>; 1521 reg-names = "dsi_ctrl"; 1522 1523 interrupt-parent = <&mdss>; 1524 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; 1525 1526 assigned-clocks = <&mmcc BYTE0_CLK_SRC>, 1527 <&mmcc PCLK0_CLK_SRC>; 1528 assigned-clock-parents = <&dsi_phy0 0>, 1529 <&dsi_phy0 1>; 1530 1531 clocks = <&mmcc MDSS_MDP_CLK>, 1532 <&mmcc MDSS_AHB_CLK>, 1533 <&mmcc MDSS_AXI_CLK>, 1534 <&mmcc MDSS_BYTE0_CLK>, 1535 <&mmcc MDSS_PCLK0_CLK>, 1536 <&mmcc MDSS_ESC0_CLK>, 1537 <&mmcc MMSS_MISC_AHB_CLK>; 1538 clock-names = "mdp_core", 1539 "iface", 1540 "bus", 1541 "byte", 1542 "pixel", 1543 "core", 1544 "core_mmss"; 1545 1546 phys = <&dsi_phy0>; 1547 phy-names = "dsi-phy"; 1548 1549 ports { 1550 #address-cells = <1>; 1551 #size-cells = <0>; 1552 1553 port@0 { 1554 reg = <0>; 1555 dsi0_in: endpoint { 1556 remote-endpoint = <&mdp5_intf1_out>; 1557 }; 1558 }; 1559 1560 port@1 { 1561 reg = <1>; 1562 dsi0_out: endpoint { 1563 }; 1564 }; 1565 }; 1566 }; 1567 1568 dsi_phy0: dsi-phy@fd922a00 { 1569 status = "disabled"; 1570 1571 compatible = "qcom,dsi-phy-28nm-hpm"; 1572 reg = <0xfd922a00 0xd4>, 1573 <0xfd922b00 0x280>, 1574 <0xfd922d80 0x30>; 1575 reg-names = "dsi_pll", 1576 "dsi_phy", 1577 "dsi_phy_regulator"; 1578 1579 #clock-cells = <1>; 1580 #phy-cells = <0>; 1581 qcom,dsi-phy-index = <0>; 1582 1583 clocks = <&mmcc MDSS_AHB_CLK>; 1584 clock-names = "iface"; 1585 }; 1586 }; 1587 1588 imem@fe805000 { 1589 status = "disabled"; 1590 compatible = "syscon", "simple-mfd"; 1591 reg = <0xfe805000 0x1000>; 1592 1593 reboot-mode { 1594 compatible = "syscon-reboot-mode"; 1595 offset = <0x65c>; 1596 }; 1597 }; 1598 }; 1599 1600 smd { 1601 compatible = "qcom,smd"; 1602 1603 rpm { 1604 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 1605 qcom,ipc = <&apcs 8 0>; 1606 qcom,smd-edge = <15>; 1607 1608 rpm_requests { 1609 compatible = "qcom,rpm-msm8974"; 1610 qcom,smd-channels = "rpm_requests"; 1611 1612 rpmcc: clock-controller { 1613 compatible = "qcom,rpmcc-msm8974", "qcom,rpmcc"; 1614 #clock-cells = <1>; 1615 }; 1616 1617 pm8841-regulators { 1618 compatible = "qcom,rpm-pm8841-regulators"; 1619 1620 pm8841_s1: s1 {}; 1621 pm8841_s2: s2 {}; 1622 pm8841_s3: s3 {}; 1623 pm8841_s4: s4 {}; 1624 pm8841_s5: s5 {}; 1625 pm8841_s6: s6 {}; 1626 pm8841_s7: s7 {}; 1627 pm8841_s8: s8 {}; 1628 }; 1629 1630 pm8941-regulators { 1631 compatible = "qcom,rpm-pm8941-regulators"; 1632 1633 pm8941_s1: s1 {}; 1634 pm8941_s2: s2 {}; 1635 pm8941_s3: s3 {}; 1636 1637 pm8941_l1: l1 {}; 1638 pm8941_l2: l2 {}; 1639 pm8941_l3: l3 {}; 1640 pm8941_l4: l4 {}; 1641 pm8941_l5: l5 {}; 1642 pm8941_l6: l6 {}; 1643 pm8941_l7: l7 {}; 1644 pm8941_l8: l8 {}; 1645 pm8941_l9: l9 {}; 1646 pm8941_l10: l10 {}; 1647 pm8941_l11: l11 {}; 1648 pm8941_l12: l12 {}; 1649 pm8941_l13: l13 {}; 1650 pm8941_l14: l14 {}; 1651 pm8941_l15: l15 {}; 1652 pm8941_l16: l16 {}; 1653 pm8941_l17: l17 {}; 1654 pm8941_l18: l18 {}; 1655 pm8941_l19: l19 {}; 1656 pm8941_l20: l20 {}; 1657 pm8941_l21: l21 {}; 1658 pm8941_l22: l22 {}; 1659 pm8941_l23: l23 {}; 1660 pm8941_l24: l24 {}; 1661 1662 pm8941_lvs1: lvs1 {}; 1663 pm8941_lvs2: lvs2 {}; 1664 pm8941_lvs3: lvs3 {}; 1665 }; 1666 }; 1667 }; 1668 }; 1669 1670 vreg_boost: vreg-boost { 1671 compatible = "regulator-fixed"; 1672 1673 regulator-name = "vreg-boost"; 1674 regulator-min-microvolt = <3150000>; 1675 regulator-max-microvolt = <3150000>; 1676 1677 regulator-always-on; 1678 regulator-boot-on; 1679 1680 gpio = <&pm8941_gpios 21 GPIO_ACTIVE_HIGH>; 1681 enable-active-high; 1682 1683 pinctrl-names = "default"; 1684 pinctrl-0 = <&boost_bypass_n_pin>; 1685 }; 1686 vreg_vph_pwr: vreg-vph-pwr { 1687 compatible = "regulator-fixed"; 1688 regulator-name = "vph-pwr"; 1689 1690 regulator-min-microvolt = <3600000>; 1691 regulator-max-microvolt = <3600000>; 1692 1693 regulator-always-on; 1694 }; 1695}; 1696