1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 3#include <dt-bindings/gpio/gpio.h> 4#include <dt-bindings/interrupt-controller/irq.h> 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/pinctrl/rockchip.h> 7#include <dt-bindings/clock/rk3228-cru.h> 8#include <dt-bindings/thermal/thermal.h> 9 10/ { 11 #address-cells = <1>; 12 #size-cells = <1>; 13 14 interrupt-parent = <&gic>; 15 16 aliases { 17 serial0 = &uart0; 18 serial1 = &uart1; 19 serial2 = &uart2; 20 spi0 = &spi0; 21 }; 22 23 cpus { 24 #address-cells = <1>; 25 #size-cells = <0>; 26 27 cpu0: cpu@f00 { 28 device_type = "cpu"; 29 compatible = "arm,cortex-a7"; 30 reg = <0xf00>; 31 resets = <&cru SRST_CORE0>; 32 operating-points-v2 = <&cpu0_opp_table>; 33 #cooling-cells = <2>; /* min followed by max */ 34 clock-latency = <40000>; 35 clocks = <&cru ARMCLK>; 36 enable-method = "psci"; 37 }; 38 39 cpu1: cpu@f01 { 40 device_type = "cpu"; 41 compatible = "arm,cortex-a7"; 42 reg = <0xf01>; 43 resets = <&cru SRST_CORE1>; 44 operating-points-v2 = <&cpu0_opp_table>; 45 #cooling-cells = <2>; /* min followed by max */ 46 enable-method = "psci"; 47 }; 48 49 cpu2: cpu@f02 { 50 device_type = "cpu"; 51 compatible = "arm,cortex-a7"; 52 reg = <0xf02>; 53 resets = <&cru SRST_CORE2>; 54 operating-points-v2 = <&cpu0_opp_table>; 55 #cooling-cells = <2>; /* min followed by max */ 56 enable-method = "psci"; 57 }; 58 59 cpu3: cpu@f03 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a7"; 62 reg = <0xf03>; 63 resets = <&cru SRST_CORE3>; 64 operating-points-v2 = <&cpu0_opp_table>; 65 #cooling-cells = <2>; /* min followed by max */ 66 enable-method = "psci"; 67 }; 68 }; 69 70 cpu0_opp_table: opp_table0 { 71 compatible = "operating-points-v2"; 72 opp-shared; 73 74 opp-408000000 { 75 opp-hz = /bits/ 64 <408000000>; 76 opp-microvolt = <950000>; 77 clock-latency-ns = <40000>; 78 opp-suspend; 79 }; 80 opp-600000000 { 81 opp-hz = /bits/ 64 <600000000>; 82 opp-microvolt = <975000>; 83 }; 84 opp-816000000 { 85 opp-hz = /bits/ 64 <816000000>; 86 opp-microvolt = <1000000>; 87 }; 88 opp-1008000000 { 89 opp-hz = /bits/ 64 <1008000000>; 90 opp-microvolt = <1175000>; 91 }; 92 opp-1200000000 { 93 opp-hz = /bits/ 64 <1200000000>; 94 opp-microvolt = <1275000>; 95 }; 96 }; 97 98 arm-pmu { 99 compatible = "arm,cortex-a7-pmu"; 100 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 101 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 102 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 103 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 104 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 105 }; 106 107 psci { 108 compatible = "arm,psci-1.0", "arm,psci-0.2"; 109 method = "smc"; 110 }; 111 112 timer { 113 compatible = "arm,armv7-timer"; 114 arm,cpu-registers-not-fw-configured; 115 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 116 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 117 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 118 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 119 clock-frequency = <24000000>; 120 }; 121 122 xin24m: oscillator { 123 compatible = "fixed-clock"; 124 clock-frequency = <24000000>; 125 clock-output-names = "xin24m"; 126 #clock-cells = <0>; 127 }; 128 129 display_subsystem: display-subsystem { 130 compatible = "rockchip,display-subsystem"; 131 ports = <&vop_out>; 132 }; 133 134 i2s1: i2s1@100b0000 { 135 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; 136 reg = <0x100b0000 0x4000>; 137 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 138 clock-names = "i2s_clk", "i2s_hclk"; 139 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>; 140 dmas = <&pdma 14>, <&pdma 15>; 141 dma-names = "tx", "rx"; 142 pinctrl-names = "default"; 143 pinctrl-0 = <&i2s1_bus>; 144 status = "disabled"; 145 }; 146 147 i2s0: i2s0@100c0000 { 148 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; 149 reg = <0x100c0000 0x4000>; 150 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 151 clock-names = "i2s_clk", "i2s_hclk"; 152 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>; 153 dmas = <&pdma 11>, <&pdma 12>; 154 dma-names = "tx", "rx"; 155 status = "disabled"; 156 }; 157 158 spdif: spdif@100d0000 { 159 compatible = "rockchip,rk3228-spdif"; 160 reg = <0x100d0000 0x1000>; 161 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 162 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>; 163 clock-names = "mclk", "hclk"; 164 dmas = <&pdma 10>; 165 dma-names = "tx"; 166 pinctrl-names = "default"; 167 pinctrl-0 = <&spdif_tx>; 168 status = "disabled"; 169 }; 170 171 i2s2: i2s2@100e0000 { 172 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; 173 reg = <0x100e0000 0x4000>; 174 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 175 clock-names = "i2s_clk", "i2s_hclk"; 176 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>; 177 dmas = <&pdma 0>, <&pdma 1>; 178 dma-names = "tx", "rx"; 179 status = "disabled"; 180 }; 181 182 grf: syscon@11000000 { 183 compatible = "rockchip,rk3228-grf", "syscon", "simple-mfd"; 184 reg = <0x11000000 0x1000>; 185 #address-cells = <1>; 186 #size-cells = <1>; 187 188 io_domains: io-domains { 189 compatible = "rockchip,rk3228-io-voltage-domain"; 190 status = "disabled"; 191 }; 192 193 u2phy0: usb2-phy@760 { 194 compatible = "rockchip,rk3228-usb2phy"; 195 reg = <0x0760 0x0c>; 196 clocks = <&cru SCLK_OTGPHY0>; 197 clock-names = "phyclk"; 198 clock-output-names = "usb480m_phy0"; 199 #clock-cells = <0>; 200 status = "disabled"; 201 202 u2phy0_otg: otg-port { 203 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 204 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 205 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 206 interrupt-names = "otg-bvalid", "otg-id", 207 "linestate"; 208 #phy-cells = <0>; 209 status = "disabled"; 210 }; 211 212 u2phy0_host: host-port { 213 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 214 interrupt-names = "linestate"; 215 #phy-cells = <0>; 216 status = "disabled"; 217 }; 218 }; 219 220 u2phy1: usb2-phy@800 { 221 compatible = "rockchip,rk3228-usb2phy"; 222 reg = <0x0800 0x0c>; 223 clocks = <&cru SCLK_OTGPHY1>; 224 clock-names = "phyclk"; 225 clock-output-names = "usb480m_phy1"; 226 #clock-cells = <0>; 227 status = "disabled"; 228 229 u2phy1_otg: otg-port { 230 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 231 interrupt-names = "linestate"; 232 #phy-cells = <0>; 233 status = "disabled"; 234 }; 235 236 u2phy1_host: host-port { 237 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 238 interrupt-names = "linestate"; 239 #phy-cells = <0>; 240 status = "disabled"; 241 }; 242 }; 243 }; 244 245 uart0: serial@11010000 { 246 compatible = "snps,dw-apb-uart"; 247 reg = <0x11010000 0x100>; 248 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 249 clock-frequency = <24000000>; 250 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 251 clock-names = "baudclk", "apb_pclk"; 252 pinctrl-names = "default"; 253 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 254 reg-shift = <2>; 255 reg-io-width = <4>; 256 status = "disabled"; 257 }; 258 259 uart1: serial@11020000 { 260 compatible = "snps,dw-apb-uart"; 261 reg = <0x11020000 0x100>; 262 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 263 clock-frequency = <24000000>; 264 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 265 clock-names = "baudclk", "apb_pclk"; 266 pinctrl-names = "default"; 267 pinctrl-0 = <&uart1_xfer>; 268 reg-shift = <2>; 269 reg-io-width = <4>; 270 status = "disabled"; 271 }; 272 273 uart2: serial@11030000 { 274 compatible = "snps,dw-apb-uart"; 275 reg = <0x11030000 0x100>; 276 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 277 clock-frequency = <24000000>; 278 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 279 clock-names = "baudclk", "apb_pclk"; 280 pinctrl-names = "default"; 281 pinctrl-0 = <&uart2_xfer>; 282 reg-shift = <2>; 283 reg-io-width = <4>; 284 status = "disabled"; 285 }; 286 287 efuse: efuse@11040000 { 288 compatible = "rockchip,rk3228-efuse"; 289 reg = <0x11040000 0x20>; 290 clocks = <&cru PCLK_EFUSE_256>; 291 clock-names = "pclk_efuse"; 292 #address-cells = <1>; 293 #size-cells = <1>; 294 295 /* Data cells */ 296 efuse_id: id@7 { 297 reg = <0x7 0x10>; 298 }; 299 cpu_leakage: cpu_leakage@17 { 300 reg = <0x17 0x1>; 301 }; 302 }; 303 304 i2c0: i2c@11050000 { 305 compatible = "rockchip,rk3228-i2c"; 306 reg = <0x11050000 0x1000>; 307 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 308 #address-cells = <1>; 309 #size-cells = <0>; 310 clock-names = "i2c"; 311 clocks = <&cru PCLK_I2C0>; 312 pinctrl-names = "default"; 313 pinctrl-0 = <&i2c0_xfer>; 314 status = "disabled"; 315 }; 316 317 i2c1: i2c@11060000 { 318 compatible = "rockchip,rk3228-i2c"; 319 reg = <0x11060000 0x1000>; 320 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 321 #address-cells = <1>; 322 #size-cells = <0>; 323 clock-names = "i2c"; 324 clocks = <&cru PCLK_I2C1>; 325 pinctrl-names = "default"; 326 pinctrl-0 = <&i2c1_xfer>; 327 status = "disabled"; 328 }; 329 330 i2c2: i2c@11070000 { 331 compatible = "rockchip,rk3228-i2c"; 332 reg = <0x11070000 0x1000>; 333 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 334 #address-cells = <1>; 335 #size-cells = <0>; 336 clock-names = "i2c"; 337 clocks = <&cru PCLK_I2C2>; 338 pinctrl-names = "default"; 339 pinctrl-0 = <&i2c2_xfer>; 340 status = "disabled"; 341 }; 342 343 i2c3: i2c@11080000 { 344 compatible = "rockchip,rk3228-i2c"; 345 reg = <0x11080000 0x1000>; 346 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 347 #address-cells = <1>; 348 #size-cells = <0>; 349 clock-names = "i2c"; 350 clocks = <&cru PCLK_I2C3>; 351 pinctrl-names = "default"; 352 pinctrl-0 = <&i2c3_xfer>; 353 status = "disabled"; 354 }; 355 356 spi0: spi@11090000 { 357 compatible = "rockchip,rk3228-spi"; 358 reg = <0x11090000 0x1000>; 359 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 360 #address-cells = <1>; 361 #size-cells = <0>; 362 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 363 clock-names = "spiclk", "apb_pclk"; 364 pinctrl-names = "default"; 365 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>; 366 status = "disabled"; 367 }; 368 369 wdt: watchdog@110a0000 { 370 compatible = "rockchip,rk3228-wdt", "snps,dw-wdt"; 371 reg = <0x110a0000 0x100>; 372 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 373 clocks = <&cru PCLK_CPU>; 374 status = "disabled"; 375 }; 376 377 pwm0: pwm@110b0000 { 378 compatible = "rockchip,rk3288-pwm"; 379 reg = <0x110b0000 0x10>; 380 #pwm-cells = <3>; 381 clocks = <&cru PCLK_PWM>; 382 clock-names = "pwm"; 383 pinctrl-names = "default"; 384 pinctrl-0 = <&pwm0_pin>; 385 status = "disabled"; 386 }; 387 388 pwm1: pwm@110b0010 { 389 compatible = "rockchip,rk3288-pwm"; 390 reg = <0x110b0010 0x10>; 391 #pwm-cells = <3>; 392 clocks = <&cru PCLK_PWM>; 393 clock-names = "pwm"; 394 pinctrl-names = "default"; 395 pinctrl-0 = <&pwm1_pin>; 396 status = "disabled"; 397 }; 398 399 pwm2: pwm@110b0020 { 400 compatible = "rockchip,rk3288-pwm"; 401 reg = <0x110b0020 0x10>; 402 #pwm-cells = <3>; 403 clocks = <&cru PCLK_PWM>; 404 clock-names = "pwm"; 405 pinctrl-names = "default"; 406 pinctrl-0 = <&pwm2_pin>; 407 status = "disabled"; 408 }; 409 410 pwm3: pwm@110b0030 { 411 compatible = "rockchip,rk3288-pwm"; 412 reg = <0x110b0030 0x10>; 413 #pwm-cells = <2>; 414 clocks = <&cru PCLK_PWM>; 415 clock-names = "pwm"; 416 pinctrl-names = "default"; 417 pinctrl-0 = <&pwm3_pin>; 418 status = "disabled"; 419 }; 420 421 timer: timer@110c0000 { 422 compatible = "rockchip,rk3228-timer", "rockchip,rk3288-timer"; 423 reg = <0x110c0000 0x20>; 424 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 425 clocks = <&xin24m>, <&cru PCLK_TIMER>; 426 clock-names = "timer", "pclk"; 427 }; 428 429 cru: clock-controller@110e0000 { 430 compatible = "rockchip,rk3228-cru"; 431 reg = <0x110e0000 0x1000>; 432 rockchip,grf = <&grf>; 433 #clock-cells = <1>; 434 #reset-cells = <1>; 435 assigned-clocks = 436 <&cru PLL_GPLL>, <&cru ARMCLK>, 437 <&cru PLL_CPLL>, <&cru ACLK_PERI>, 438 <&cru HCLK_PERI>, <&cru PCLK_PERI>, 439 <&cru ACLK_CPU>, <&cru HCLK_CPU>, 440 <&cru PCLK_CPU>; 441 assigned-clock-rates = 442 <594000000>, <816000000>, 443 <500000000>, <150000000>, 444 <150000000>, <75000000>, 445 <150000000>, <150000000>, 446 <75000000>; 447 }; 448 449 pdma: pdma@110f0000 { 450 compatible = "arm,pl330", "arm,primecell"; 451 reg = <0x110f0000 0x4000>; 452 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 453 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 454 #dma-cells = <1>; 455 arm,pl330-periph-burst; 456 clocks = <&cru ACLK_DMAC>; 457 clock-names = "apb_pclk"; 458 }; 459 460 thermal-zones { 461 cpu_thermal: cpu-thermal { 462 polling-delay-passive = <100>; /* milliseconds */ 463 polling-delay = <5000>; /* milliseconds */ 464 465 thermal-sensors = <&tsadc 0>; 466 467 trips { 468 cpu_alert0: cpu_alert0 { 469 temperature = <70000>; /* millicelsius */ 470 hysteresis = <2000>; /* millicelsius */ 471 type = "passive"; 472 }; 473 cpu_alert1: cpu_alert1 { 474 temperature = <75000>; /* millicelsius */ 475 hysteresis = <2000>; /* millicelsius */ 476 type = "passive"; 477 }; 478 cpu_crit: cpu_crit { 479 temperature = <90000>; /* millicelsius */ 480 hysteresis = <2000>; /* millicelsius */ 481 type = "critical"; 482 }; 483 }; 484 485 cooling-maps { 486 map0 { 487 trip = <&cpu_alert0>; 488 cooling-device = 489 <&cpu0 THERMAL_NO_LIMIT 6>, 490 <&cpu1 THERMAL_NO_LIMIT 6>, 491 <&cpu2 THERMAL_NO_LIMIT 6>, 492 <&cpu3 THERMAL_NO_LIMIT 6>; 493 }; 494 map1 { 495 trip = <&cpu_alert1>; 496 cooling-device = 497 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 498 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 499 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 500 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 501 }; 502 }; 503 }; 504 }; 505 506 tsadc: tsadc@11150000 { 507 compatible = "rockchip,rk3228-tsadc"; 508 reg = <0x11150000 0x100>; 509 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 510 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 511 clock-names = "tsadc", "apb_pclk"; 512 assigned-clocks = <&cru SCLK_TSADC>; 513 assigned-clock-rates = <32768>; 514 resets = <&cru SRST_TSADC>; 515 reset-names = "tsadc-apb"; 516 pinctrl-names = "init", "default", "sleep"; 517 pinctrl-0 = <&otp_pin>; 518 pinctrl-1 = <&otp_out>; 519 pinctrl-2 = <&otp_pin>; 520 #thermal-sensor-cells = <0>; 521 rockchip,hw-tshut-temp = <95000>; 522 status = "disabled"; 523 }; 524 525 hdmi_phy: hdmi-phy@12030000 { 526 compatible = "rockchip,rk3228-hdmi-phy"; 527 reg = <0x12030000 0x10000>; 528 clocks = <&cru PCLK_HDMI_PHY>, <&xin24m>, <&cru DCLK_HDMI_PHY>; 529 clock-names = "sysclk", "refoclk", "refpclk"; 530 #clock-cells = <0>; 531 clock-output-names = "hdmiphy_phy"; 532 #phy-cells = <0>; 533 status = "disabled"; 534 }; 535 536 gpu: gpu@20000000 { 537 compatible = "rockchip,rk3228-mali", "arm,mali-400"; 538 reg = <0x20000000 0x10000>; 539 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 540 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 541 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 542 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 543 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 544 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 545 interrupt-names = "gp", 546 "gpmmu", 547 "pp0", 548 "ppmmu0", 549 "pp1", 550 "ppmmu1"; 551 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; 552 clock-names = "bus", "core"; 553 resets = <&cru SRST_GPU_A>; 554 status = "disabled"; 555 }; 556 557 vpu_mmu: iommu@20020800 { 558 compatible = "rockchip,iommu"; 559 reg = <0x20020800 0x100>; 560 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 561 interrupt-names = "vpu_mmu"; 562 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 563 clock-names = "aclk", "iface"; 564 iommu-cells = <0>; 565 status = "disabled"; 566 }; 567 568 vdec_mmu: iommu@20030480 { 569 compatible = "rockchip,iommu"; 570 reg = <0x20030480 0x40>, <0x200304c0 0x40>; 571 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 572 interrupt-names = "vdec_mmu"; 573 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>; 574 clock-names = "aclk", "iface"; 575 iommu-cells = <0>; 576 status = "disabled"; 577 }; 578 579 vop: vop@20050000 { 580 compatible = "rockchip,rk3228-vop"; 581 reg = <0x20050000 0x1ffc>; 582 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 583 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>; 584 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 585 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>; 586 reset-names = "axi", "ahb", "dclk"; 587 iommus = <&vop_mmu>; 588 status = "disabled"; 589 590 vop_out: port { 591 #address-cells = <1>; 592 #size-cells = <0>; 593 594 vop_out_hdmi: endpoint@0 { 595 reg = <0>; 596 remote-endpoint = <&hdmi_in_vop>; 597 }; 598 }; 599 }; 600 601 vop_mmu: iommu@20053f00 { 602 compatible = "rockchip,iommu"; 603 reg = <0x20053f00 0x100>; 604 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 605 interrupt-names = "vop_mmu"; 606 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; 607 clock-names = "aclk", "iface"; 608 #iommu-cells = <0>; 609 status = "disabled"; 610 }; 611 612 rga: rga@20060000 { 613 compatible = "rockchip,rk3228-rga", "rockchip,rk3288-rga"; 614 reg = <0x20060000 0x1000>; 615 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 616 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>; 617 clock-names = "aclk", "hclk", "sclk"; 618 resets = <&cru SRST_RGA>, <&cru SRST_RGA_A>, <&cru SRST_RGA_H>; 619 reset-names = "core", "axi", "ahb"; 620 }; 621 622 iep_mmu: iommu@20070800 { 623 compatible = "rockchip,iommu"; 624 reg = <0x20070800 0x100>; 625 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 626 interrupt-names = "iep_mmu"; 627 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; 628 clock-names = "aclk", "iface"; 629 iommu-cells = <0>; 630 status = "disabled"; 631 }; 632 633 hdmi: hdmi@200a0000 { 634 compatible = "rockchip,rk3228-dw-hdmi"; 635 reg = <0x200a0000 0x20000>; 636 reg-io-width = <4>; 637 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 638 assigned-clocks = <&cru SCLK_HDMI_PHY>; 639 assigned-clock-parents = <&hdmi_phy>; 640 clocks = <&cru SCLK_HDMI_HDCP>, <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_CEC>; 641 clock-names = "isfr", "iahb", "cec"; 642 pinctrl-names = "default"; 643 pinctrl-0 = <&hdmii2c_xfer &hdmi_hpd &hdmi_cec>; 644 resets = <&cru SRST_HDMI_P>; 645 reset-names = "hdmi"; 646 phys = <&hdmi_phy>; 647 phy-names = "hdmi"; 648 rockchip,grf = <&grf>; 649 status = "disabled"; 650 651 ports { 652 hdmi_in: port { 653 #address-cells = <1>; 654 #size-cells = <0>; 655 hdmi_in_vop: endpoint@0 { 656 reg = <0>; 657 remote-endpoint = <&vop_out_hdmi>; 658 }; 659 }; 660 }; 661 }; 662 663 sdmmc: mmc@30000000 { 664 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc"; 665 reg = <0x30000000 0x4000>; 666 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 667 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 668 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 669 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 670 fifo-depth = <0x100>; 671 pinctrl-names = "default"; 672 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; 673 status = "disabled"; 674 }; 675 676 sdio: mmc@30010000 { 677 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc"; 678 reg = <0x30010000 0x4000>; 679 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 680 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 681 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 682 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 683 fifo-depth = <0x100>; 684 pinctrl-names = "default"; 685 pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>; 686 status = "disabled"; 687 }; 688 689 emmc: mmc@30020000 { 690 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc"; 691 reg = <0x30020000 0x4000>; 692 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 693 clock-frequency = <37500000>; 694 max-frequency = <37500000>; 695 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 696 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 697 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 698 bus-width = <8>; 699 rockchip,default-sample-phase = <158>; 700 fifo-depth = <0x100>; 701 pinctrl-names = "default"; 702 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; 703 resets = <&cru SRST_EMMC>; 704 reset-names = "reset"; 705 status = "disabled"; 706 }; 707 708 usb_otg: usb@30040000 { 709 compatible = "rockchip,rk3228-usb", "rockchip,rk3066-usb", 710 "snps,dwc2"; 711 reg = <0x30040000 0x40000>; 712 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 713 clocks = <&cru HCLK_OTG>; 714 clock-names = "otg"; 715 dr_mode = "otg"; 716 g-np-tx-fifo-size = <16>; 717 g-rx-fifo-size = <280>; 718 g-tx-fifo-size = <256 128 128 64 32 16>; 719 phys = <&u2phy0_otg>; 720 phy-names = "usb2-phy"; 721 status = "disabled"; 722 }; 723 724 usb_host0_ehci: usb@30080000 { 725 compatible = "generic-ehci"; 726 reg = <0x30080000 0x20000>; 727 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 728 clocks = <&cru HCLK_HOST0>, <&u2phy0>; 729 phys = <&u2phy0_host>; 730 phy-names = "usb"; 731 status = "disabled"; 732 }; 733 734 usb_host0_ohci: usb@300a0000 { 735 compatible = "generic-ohci"; 736 reg = <0x300a0000 0x20000>; 737 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 738 clocks = <&cru HCLK_HOST0>, <&u2phy0>; 739 phys = <&u2phy0_host>; 740 phy-names = "usb"; 741 status = "disabled"; 742 }; 743 744 usb_host1_ehci: usb@300c0000 { 745 compatible = "generic-ehci"; 746 reg = <0x300c0000 0x20000>; 747 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 748 clocks = <&cru HCLK_HOST1>, <&u2phy1>; 749 phys = <&u2phy1_otg>; 750 phy-names = "usb"; 751 status = "disabled"; 752 }; 753 754 usb_host1_ohci: usb@300e0000 { 755 compatible = "generic-ohci"; 756 reg = <0x300e0000 0x20000>; 757 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 758 clocks = <&cru HCLK_HOST1>, <&u2phy1>; 759 phys = <&u2phy1_otg>; 760 phy-names = "usb"; 761 status = "disabled"; 762 }; 763 764 usb_host2_ehci: usb@30100000 { 765 compatible = "generic-ehci"; 766 reg = <0x30100000 0x20000>; 767 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 768 clocks = <&cru HCLK_HOST2>, <&u2phy1>; 769 phys = <&u2phy1_host>; 770 phy-names = "usb"; 771 status = "disabled"; 772 }; 773 774 usb_host2_ohci: usb@30120000 { 775 compatible = "generic-ohci"; 776 reg = <0x30120000 0x20000>; 777 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 778 clocks = <&cru HCLK_HOST2>, <&u2phy1>; 779 phys = <&u2phy1_host>; 780 phy-names = "usb"; 781 status = "disabled"; 782 }; 783 784 gmac: ethernet@30200000 { 785 compatible = "rockchip,rk3228-gmac"; 786 reg = <0x30200000 0x10000>; 787 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 788 interrupt-names = "macirq"; 789 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>, 790 <&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>, 791 <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>, 792 <&cru PCLK_GMAC>; 793 clock-names = "stmmaceth", "mac_clk_rx", 794 "mac_clk_tx", "clk_mac_ref", 795 "clk_mac_refout", "aclk_mac", 796 "pclk_mac"; 797 resets = <&cru SRST_GMAC>; 798 reset-names = "stmmaceth"; 799 rockchip,grf = <&grf>; 800 status = "disabled"; 801 }; 802 803 gic: interrupt-controller@32010000 { 804 compatible = "arm,gic-400"; 805 interrupt-controller; 806 #interrupt-cells = <3>; 807 #address-cells = <0>; 808 809 reg = <0x32011000 0x1000>, 810 <0x32012000 0x2000>, 811 <0x32014000 0x2000>, 812 <0x32016000 0x2000>; 813 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 814 }; 815 816 pinctrl: pinctrl { 817 compatible = "rockchip,rk3228-pinctrl"; 818 rockchip,grf = <&grf>; 819 #address-cells = <1>; 820 #size-cells = <1>; 821 ranges; 822 823 gpio0: gpio0@11110000 { 824 compatible = "rockchip,gpio-bank"; 825 reg = <0x11110000 0x100>; 826 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 827 clocks = <&cru PCLK_GPIO0>; 828 829 gpio-controller; 830 #gpio-cells = <2>; 831 832 interrupt-controller; 833 #interrupt-cells = <2>; 834 }; 835 836 gpio1: gpio1@11120000 { 837 compatible = "rockchip,gpio-bank"; 838 reg = <0x11120000 0x100>; 839 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 840 clocks = <&cru PCLK_GPIO1>; 841 842 gpio-controller; 843 #gpio-cells = <2>; 844 845 interrupt-controller; 846 #interrupt-cells = <2>; 847 }; 848 849 gpio2: gpio2@11130000 { 850 compatible = "rockchip,gpio-bank"; 851 reg = <0x11130000 0x100>; 852 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 853 clocks = <&cru PCLK_GPIO2>; 854 855 gpio-controller; 856 #gpio-cells = <2>; 857 858 interrupt-controller; 859 #interrupt-cells = <2>; 860 }; 861 862 gpio3: gpio3@11140000 { 863 compatible = "rockchip,gpio-bank"; 864 reg = <0x11140000 0x100>; 865 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 866 clocks = <&cru PCLK_GPIO3>; 867 868 gpio-controller; 869 #gpio-cells = <2>; 870 871 interrupt-controller; 872 #interrupt-cells = <2>; 873 }; 874 875 pcfg_pull_up: pcfg-pull-up { 876 bias-pull-up; 877 }; 878 879 pcfg_pull_down: pcfg-pull-down { 880 bias-pull-down; 881 }; 882 883 pcfg_pull_none: pcfg-pull-none { 884 bias-disable; 885 }; 886 887 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma { 888 drive-strength = <12>; 889 }; 890 891 sdmmc { 892 sdmmc_clk: sdmmc-clk { 893 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none_drv_12ma>; 894 }; 895 896 sdmmc_cmd: sdmmc-cmd { 897 rockchip,pins = <1 RK_PB7 1 &pcfg_pull_none_drv_12ma>; 898 }; 899 900 sdmmc_bus4: sdmmc-bus4 { 901 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_none_drv_12ma>, 902 <1 RK_PC3 1 &pcfg_pull_none_drv_12ma>, 903 <1 RK_PC4 1 &pcfg_pull_none_drv_12ma>, 904 <1 RK_PC5 1 &pcfg_pull_none_drv_12ma>; 905 }; 906 }; 907 908 sdio { 909 sdio_clk: sdio-clk { 910 rockchip,pins = <3 RK_PA0 1 &pcfg_pull_none_drv_12ma>; 911 }; 912 913 sdio_cmd: sdio-cmd { 914 rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none_drv_12ma>; 915 }; 916 917 sdio_bus4: sdio-bus4 { 918 rockchip,pins = <3 RK_PA2 1 &pcfg_pull_none_drv_12ma>, 919 <3 RK_PA3 1 &pcfg_pull_none_drv_12ma>, 920 <3 RK_PA4 1 &pcfg_pull_none_drv_12ma>, 921 <3 RK_PA5 1 &pcfg_pull_none_drv_12ma>; 922 }; 923 }; 924 925 emmc { 926 emmc_clk: emmc-clk { 927 rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>; 928 }; 929 930 emmc_cmd: emmc-cmd { 931 rockchip,pins = <1 RK_PC6 2 &pcfg_pull_none>; 932 }; 933 934 emmc_bus8: emmc-bus8 { 935 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_none>, 936 <1 RK_PD1 2 &pcfg_pull_none>, 937 <1 RK_PD2 2 &pcfg_pull_none>, 938 <1 RK_PD3 2 &pcfg_pull_none>, 939 <1 RK_PD4 2 &pcfg_pull_none>, 940 <1 RK_PD5 2 &pcfg_pull_none>, 941 <1 RK_PD6 2 &pcfg_pull_none>, 942 <1 RK_PD7 2 &pcfg_pull_none>; 943 }; 944 }; 945 946 gmac { 947 rgmii_pins: rgmii-pins { 948 rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none>, 949 <2 RK_PB4 1 &pcfg_pull_none>, 950 <2 RK_PD1 1 &pcfg_pull_none>, 951 <2 RK_PC3 1 &pcfg_pull_none_drv_12ma>, 952 <2 RK_PC2 1 &pcfg_pull_none_drv_12ma>, 953 <2 RK_PC6 1 &pcfg_pull_none_drv_12ma>, 954 <2 RK_PC7 1 &pcfg_pull_none_drv_12ma>, 955 <2 RK_PB1 1 &pcfg_pull_none_drv_12ma>, 956 <2 RK_PB5 1 &pcfg_pull_none_drv_12ma>, 957 <2 RK_PC1 1 &pcfg_pull_none>, 958 <2 RK_PC0 1 &pcfg_pull_none>, 959 <2 RK_PC5 2 &pcfg_pull_none>, 960 <2 RK_PC4 2 &pcfg_pull_none>, 961 <2 RK_PB3 1 &pcfg_pull_none>, 962 <2 RK_PB0 1 &pcfg_pull_none>; 963 }; 964 965 rmii_pins: rmii-pins { 966 rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none>, 967 <2 RK_PB4 1 &pcfg_pull_none>, 968 <2 RK_PD1 1 &pcfg_pull_none>, 969 <2 RK_PC3 1 &pcfg_pull_none_drv_12ma>, 970 <2 RK_PC2 1 &pcfg_pull_none_drv_12ma>, 971 <2 RK_PB5 1 &pcfg_pull_none_drv_12ma>, 972 <2 RK_PC1 1 &pcfg_pull_none>, 973 <2 RK_PC0 1 &pcfg_pull_none>, 974 <2 RK_PB0 1 &pcfg_pull_none>, 975 <2 RK_PB7 1 &pcfg_pull_none>; 976 }; 977 978 phy_pins: phy-pins { 979 rockchip,pins = <2 RK_PB6 2 &pcfg_pull_none>, 980 <2 RK_PB0 2 &pcfg_pull_none>; 981 }; 982 }; 983 984 hdmi { 985 hdmi_hpd: hdmi-hpd { 986 rockchip,pins = <0 RK_PB7 1 &pcfg_pull_down>; 987 }; 988 989 hdmii2c_xfer: hdmii2c-xfer { 990 rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>, 991 <0 RK_PA7 2 &pcfg_pull_none>; 992 }; 993 994 hdmi_cec: hdmi-cec { 995 rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>; 996 }; 997 }; 998 999 i2c0 { 1000 i2c0_xfer: i2c0-xfer { 1001 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>, 1002 <0 RK_PA1 1 &pcfg_pull_none>; 1003 }; 1004 }; 1005 1006 i2c1 { 1007 i2c1_xfer: i2c1-xfer { 1008 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>, 1009 <0 RK_PA3 1 &pcfg_pull_none>; 1010 }; 1011 }; 1012 1013 i2c2 { 1014 i2c2_xfer: i2c2-xfer { 1015 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>, 1016 <2 RK_PC5 1 &pcfg_pull_none>; 1017 }; 1018 }; 1019 1020 i2c3 { 1021 i2c3_xfer: i2c3-xfer { 1022 rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>, 1023 <0 RK_PA7 1 &pcfg_pull_none>; 1024 }; 1025 }; 1026 1027 spi0 { 1028 spi0_clk: spi0-clk { 1029 rockchip,pins = <0 RK_PB1 2 &pcfg_pull_up>; 1030 }; 1031 spi0_cs0: spi0-cs0 { 1032 rockchip,pins = <0 RK_PB6 2 &pcfg_pull_up>; 1033 }; 1034 spi0_tx: spi0-tx { 1035 rockchip,pins = <0 RK_PB3 2 &pcfg_pull_up>; 1036 }; 1037 spi0_rx: spi0-rx { 1038 rockchip,pins = <0 RK_PB5 2 &pcfg_pull_up>; 1039 }; 1040 spi0_cs1: spi0-cs1 { 1041 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_up>; 1042 }; 1043 }; 1044 1045 spi1 { 1046 spi1_clk: spi1-clk { 1047 rockchip,pins = <0 RK_PC7 2 &pcfg_pull_up>; 1048 }; 1049 spi1_cs0: spi1-cs0 { 1050 rockchip,pins = <2 RK_PA2 2 &pcfg_pull_up>; 1051 }; 1052 spi1_rx: spi1-rx { 1053 rockchip,pins = <2 RK_PA0 2 &pcfg_pull_up>; 1054 }; 1055 spi1_tx: spi1-tx { 1056 rockchip,pins = <2 RK_PA1 2 &pcfg_pull_up>; 1057 }; 1058 spi1_cs1: spi1-cs1 { 1059 rockchip,pins = <2 RK_PA3 2 &pcfg_pull_up>; 1060 }; 1061 }; 1062 1063 i2s1 { 1064 i2s1_bus: i2s1-bus { 1065 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>, 1066 <0 RK_PB1 1 &pcfg_pull_none>, 1067 <0 RK_PB3 1 &pcfg_pull_none>, 1068 <0 RK_PB4 1 &pcfg_pull_none>, 1069 <0 RK_PB5 1 &pcfg_pull_none>, 1070 <0 RK_PB6 1 &pcfg_pull_none>, 1071 <1 RK_PA2 2 &pcfg_pull_none>, 1072 <1 RK_PA4 2 &pcfg_pull_none>, 1073 <1 RK_PA5 2 &pcfg_pull_none>; 1074 }; 1075 }; 1076 1077 pwm0 { 1078 pwm0_pin: pwm0-pin { 1079 rockchip,pins = <3 RK_PC5 1 &pcfg_pull_none>; 1080 }; 1081 }; 1082 1083 pwm1 { 1084 pwm1_pin: pwm1-pin { 1085 rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>; 1086 }; 1087 }; 1088 1089 pwm2 { 1090 pwm2_pin: pwm2-pin { 1091 rockchip,pins = <1 RK_PB4 2 &pcfg_pull_none>; 1092 }; 1093 }; 1094 1095 pwm3 { 1096 pwm3_pin: pwm3-pin { 1097 rockchip,pins = <1 RK_PB3 2 &pcfg_pull_none>; 1098 }; 1099 }; 1100 1101 spdif { 1102 spdif_tx: spdif-tx { 1103 rockchip,pins = <3 RK_PD7 2 &pcfg_pull_none>; 1104 }; 1105 }; 1106 1107 tsadc { 1108 otp_pin: otp-pin { 1109 rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; 1110 }; 1111 1112 otp_out: otp-out { 1113 rockchip,pins = <0 RK_PD0 2 &pcfg_pull_none>; 1114 }; 1115 }; 1116 1117 uart0 { 1118 uart0_xfer: uart0-xfer { 1119 rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>, 1120 <2 RK_PD3 1 &pcfg_pull_none>; 1121 }; 1122 1123 uart0_cts: uart0-cts { 1124 rockchip,pins = <2 RK_PD5 1 &pcfg_pull_none>; 1125 }; 1126 1127 uart0_rts: uart0-rts { 1128 rockchip,pins = <0 RK_PC1 1 &pcfg_pull_none>; 1129 }; 1130 }; 1131 1132 uart1 { 1133 uart1_xfer: uart1-xfer { 1134 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_none>, 1135 <1 RK_PB2 1 &pcfg_pull_none>; 1136 }; 1137 1138 uart1_cts: uart1-cts { 1139 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_none>; 1140 }; 1141 1142 uart1_rts: uart1-rts { 1143 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>; 1144 }; 1145 }; 1146 1147 uart2 { 1148 uart2_xfer: uart2-xfer { 1149 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>, 1150 <1 RK_PC3 2 &pcfg_pull_none>; 1151 }; 1152 1153 uart21_xfer: uart21-xfer { 1154 rockchip,pins = <1 RK_PB2 2 &pcfg_pull_up>, 1155 <1 RK_PB1 2 &pcfg_pull_none>; 1156 }; 1157 1158 uart2_cts: uart2-cts { 1159 rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>; 1160 }; 1161 1162 uart2_rts: uart2-rts { 1163 rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>; 1164 }; 1165 }; 1166 }; 1167}; 1168