1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2013 MundoReader S.L. 4 * Author: Heiko Stuebner <heiko@sntech.de> 5 */ 6 7#include <dt-bindings/interrupt-controller/irq.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/soc/rockchip,boot-mode.h> 10 11/ { 12 #address-cells = <1>; 13 #size-cells = <1>; 14 15 interrupt-parent = <&gic>; 16 17 aliases { 18 ethernet0 = &emac; 19 i2c0 = &i2c0; 20 i2c1 = &i2c1; 21 i2c2 = &i2c2; 22 i2c3 = &i2c3; 23 i2c4 = &i2c4; 24 mshc0 = &emmc; 25 mshc1 = &mmc0; 26 mshc2 = &mmc1; 27 serial0 = &uart0; 28 serial1 = &uart1; 29 serial2 = &uart2; 30 serial3 = &uart3; 31 spi0 = &spi0; 32 spi1 = &spi1; 33 }; 34 35 xin24m: oscillator { 36 compatible = "fixed-clock"; 37 clock-frequency = <24000000>; 38 #clock-cells = <0>; 39 clock-output-names = "xin24m"; 40 }; 41 42 gpu: gpu@10090000 { 43 compatible = "arm,mali-400"; 44 reg = <0x10090000 0x10000>; 45 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; 46 clock-names = "bus", "core"; 47 assigned-clocks = <&cru ACLK_GPU>; 48 assigned-clock-rates = <100000000>; 49 resets = <&cru SRST_GPU>; 50 status = "disabled"; 51 }; 52 53 L2: cache-controller@10138000 { 54 compatible = "arm,pl310-cache"; 55 reg = <0x10138000 0x1000>; 56 cache-unified; 57 cache-level = <2>; 58 }; 59 60 scu@1013c000 { 61 compatible = "arm,cortex-a9-scu"; 62 reg = <0x1013c000 0x100>; 63 }; 64 65 global_timer: global-timer@1013c200 { 66 compatible = "arm,cortex-a9-global-timer"; 67 reg = <0x1013c200 0x20>; 68 interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>; 69 clocks = <&cru CORE_PERI>; 70 }; 71 72 local_timer: local-timer@1013c600 { 73 compatible = "arm,cortex-a9-twd-timer"; 74 reg = <0x1013c600 0x20>; 75 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>; 76 clocks = <&cru CORE_PERI>; 77 }; 78 79 gic: interrupt-controller@1013d000 { 80 compatible = "arm,cortex-a9-gic"; 81 interrupt-controller; 82 #interrupt-cells = <3>; 83 reg = <0x1013d000 0x1000>, 84 <0x1013c100 0x0100>; 85 }; 86 87 uart0: serial@10124000 { 88 compatible = "snps,dw-apb-uart"; 89 reg = <0x10124000 0x400>; 90 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 91 reg-shift = <2>; 92 reg-io-width = <1>; 93 clock-names = "baudclk", "apb_pclk"; 94 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 95 status = "disabled"; 96 }; 97 98 uart1: serial@10126000 { 99 compatible = "snps,dw-apb-uart"; 100 reg = <0x10126000 0x400>; 101 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 102 reg-shift = <2>; 103 reg-io-width = <1>; 104 clock-names = "baudclk", "apb_pclk"; 105 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 106 status = "disabled"; 107 }; 108 109 qos_gpu: qos@1012d000 { 110 compatible = "rockchip,rk3066-qos", "syscon"; 111 reg = <0x1012d000 0x20>; 112 }; 113 114 qos_vpu: qos@1012e000 { 115 compatible = "rockchip,rk3066-qos", "syscon"; 116 reg = <0x1012e000 0x20>; 117 }; 118 119 qos_lcdc0: qos@1012f000 { 120 compatible = "rockchip,rk3066-qos", "syscon"; 121 reg = <0x1012f000 0x20>; 122 }; 123 124 qos_cif0: qos@1012f080 { 125 compatible = "rockchip,rk3066-qos", "syscon"; 126 reg = <0x1012f080 0x20>; 127 }; 128 129 qos_ipp: qos@1012f100 { 130 compatible = "rockchip,rk3066-qos", "syscon"; 131 reg = <0x1012f100 0x20>; 132 }; 133 134 qos_lcdc1: qos@1012f180 { 135 compatible = "rockchip,rk3066-qos", "syscon"; 136 reg = <0x1012f180 0x20>; 137 }; 138 139 qos_cif1: qos@1012f200 { 140 compatible = "rockchip,rk3066-qos", "syscon"; 141 reg = <0x1012f200 0x20>; 142 }; 143 144 qos_rga: qos@1012f280 { 145 compatible = "rockchip,rk3066-qos", "syscon"; 146 reg = <0x1012f280 0x20>; 147 }; 148 149 usb_otg: usb@10180000 { 150 compatible = "rockchip,rk3066-usb", "snps,dwc2"; 151 reg = <0x10180000 0x40000>; 152 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 153 clocks = <&cru HCLK_OTG0>; 154 clock-names = "otg"; 155 dr_mode = "otg"; 156 g-np-tx-fifo-size = <16>; 157 g-rx-fifo-size = <275>; 158 g-tx-fifo-size = <256 128 128 64 64 32>; 159 phys = <&usbphy0>; 160 phy-names = "usb2-phy"; 161 status = "disabled"; 162 }; 163 164 usb_host: usb@101c0000 { 165 compatible = "snps,dwc2"; 166 reg = <0x101c0000 0x40000>; 167 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 168 clocks = <&cru HCLK_OTG1>; 169 clock-names = "otg"; 170 dr_mode = "host"; 171 phys = <&usbphy1>; 172 phy-names = "usb2-phy"; 173 status = "disabled"; 174 }; 175 176 emac: ethernet@10204000 { 177 compatible = "snps,arc-emac"; 178 reg = <0x10204000 0x3c>; 179 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 180 #address-cells = <1>; 181 #size-cells = <0>; 182 183 rockchip,grf = <&grf>; 184 185 clocks = <&cru HCLK_EMAC>, <&cru SCLK_MAC>; 186 clock-names = "hclk", "macref"; 187 max-speed = <100>; 188 phy-mode = "rmii"; 189 190 status = "disabled"; 191 }; 192 193 mmc0: mmc@10214000 { 194 compatible = "rockchip,rk2928-dw-mshc"; 195 reg = <0x10214000 0x1000>; 196 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 197 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; 198 clock-names = "biu", "ciu"; 199 dmas = <&dmac2 1>; 200 dma-names = "rx-tx"; 201 fifo-depth = <256>; 202 resets = <&cru SRST_SDMMC>; 203 reset-names = "reset"; 204 status = "disabled"; 205 }; 206 207 mmc1: mmc@10218000 { 208 compatible = "rockchip,rk2928-dw-mshc"; 209 reg = <0x10218000 0x1000>; 210 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 211 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>; 212 clock-names = "biu", "ciu"; 213 dmas = <&dmac2 3>; 214 dma-names = "rx-tx"; 215 fifo-depth = <256>; 216 resets = <&cru SRST_SDIO>; 217 reset-names = "reset"; 218 status = "disabled"; 219 }; 220 221 emmc: mmc@1021c000 { 222 compatible = "rockchip,rk2928-dw-mshc"; 223 reg = <0x1021c000 0x1000>; 224 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 225 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>; 226 clock-names = "biu", "ciu"; 227 dmas = <&dmac2 4>; 228 dma-names = "rx-tx"; 229 fifo-depth = <256>; 230 resets = <&cru SRST_EMMC>; 231 reset-names = "reset"; 232 status = "disabled"; 233 }; 234 235 nfc: nand-controller@10500000 { 236 compatible = "rockchip,rk2928-nfc"; 237 reg = <0x10500000 0x4000>; 238 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 239 clocks = <&cru HCLK_NANDC0>; 240 clock-names = "ahb"; 241 status = "disabled"; 242 }; 243 244 pmu: pmu@20004000 { 245 compatible = "rockchip,rk3066-pmu", "syscon", "simple-mfd"; 246 reg = <0x20004000 0x100>; 247 248 reboot-mode { 249 compatible = "syscon-reboot-mode"; 250 offset = <0x40>; 251 mode-normal = <BOOT_NORMAL>; 252 mode-recovery = <BOOT_RECOVERY>; 253 mode-bootloader = <BOOT_FASTBOOT>; 254 mode-loader = <BOOT_BL_DOWNLOAD>; 255 }; 256 }; 257 258 grf: grf@20008000 { 259 compatible = "syscon"; 260 reg = <0x20008000 0x200>; 261 }; 262 263 dmac1_s: dma-controller@20018000 { 264 compatible = "arm,pl330", "arm,primecell"; 265 reg = <0x20018000 0x4000>; 266 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 267 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 268 #dma-cells = <1>; 269 arm,pl330-broken-no-flushp; 270 arm,pl330-periph-burst; 271 clocks = <&cru ACLK_DMA1>; 272 clock-names = "apb_pclk"; 273 }; 274 275 dmac1_ns: dma-controller@2001c000 { 276 compatible = "arm,pl330", "arm,primecell"; 277 reg = <0x2001c000 0x4000>; 278 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 279 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 280 #dma-cells = <1>; 281 arm,pl330-broken-no-flushp; 282 arm,pl330-periph-burst; 283 clocks = <&cru ACLK_DMA1>; 284 clock-names = "apb_pclk"; 285 status = "disabled"; 286 }; 287 288 i2c0: i2c@2002d000 { 289 compatible = "rockchip,rk3066-i2c"; 290 reg = <0x2002d000 0x1000>; 291 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 292 #address-cells = <1>; 293 #size-cells = <0>; 294 295 rockchip,grf = <&grf>; 296 297 clock-names = "i2c"; 298 clocks = <&cru PCLK_I2C0>; 299 300 status = "disabled"; 301 }; 302 303 i2c1: i2c@2002f000 { 304 compatible = "rockchip,rk3066-i2c"; 305 reg = <0x2002f000 0x1000>; 306 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 307 #address-cells = <1>; 308 #size-cells = <0>; 309 310 rockchip,grf = <&grf>; 311 312 clocks = <&cru PCLK_I2C1>; 313 clock-names = "i2c"; 314 315 status = "disabled"; 316 }; 317 318 pwm0: pwm@20030000 { 319 compatible = "rockchip,rk2928-pwm"; 320 reg = <0x20030000 0x10>; 321 #pwm-cells = <2>; 322 clocks = <&cru PCLK_PWM01>; 323 status = "disabled"; 324 }; 325 326 pwm1: pwm@20030010 { 327 compatible = "rockchip,rk2928-pwm"; 328 reg = <0x20030010 0x10>; 329 #pwm-cells = <2>; 330 clocks = <&cru PCLK_PWM01>; 331 status = "disabled"; 332 }; 333 334 wdt: watchdog@2004c000 { 335 compatible = "snps,dw-wdt"; 336 reg = <0x2004c000 0x100>; 337 clocks = <&cru PCLK_WDT>; 338 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 339 status = "disabled"; 340 }; 341 342 pwm2: pwm@20050020 { 343 compatible = "rockchip,rk2928-pwm"; 344 reg = <0x20050020 0x10>; 345 #pwm-cells = <2>; 346 clocks = <&cru PCLK_PWM23>; 347 status = "disabled"; 348 }; 349 350 pwm3: pwm@20050030 { 351 compatible = "rockchip,rk2928-pwm"; 352 reg = <0x20050030 0x10>; 353 #pwm-cells = <2>; 354 clocks = <&cru PCLK_PWM23>; 355 status = "disabled"; 356 }; 357 358 i2c2: i2c@20056000 { 359 compatible = "rockchip,rk3066-i2c"; 360 reg = <0x20056000 0x1000>; 361 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 362 #address-cells = <1>; 363 #size-cells = <0>; 364 365 rockchip,grf = <&grf>; 366 367 clocks = <&cru PCLK_I2C2>; 368 clock-names = "i2c"; 369 370 status = "disabled"; 371 }; 372 373 i2c3: i2c@2005a000 { 374 compatible = "rockchip,rk3066-i2c"; 375 reg = <0x2005a000 0x1000>; 376 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 377 #address-cells = <1>; 378 #size-cells = <0>; 379 380 rockchip,grf = <&grf>; 381 382 clocks = <&cru PCLK_I2C3>; 383 clock-names = "i2c"; 384 385 status = "disabled"; 386 }; 387 388 i2c4: i2c@2005e000 { 389 compatible = "rockchip,rk3066-i2c"; 390 reg = <0x2005e000 0x1000>; 391 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 392 #address-cells = <1>; 393 #size-cells = <0>; 394 395 rockchip,grf = <&grf>; 396 397 clocks = <&cru PCLK_I2C4>; 398 clock-names = "i2c"; 399 400 status = "disabled"; 401 }; 402 403 uart2: serial@20064000 { 404 compatible = "snps,dw-apb-uart"; 405 reg = <0x20064000 0x400>; 406 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 407 reg-shift = <2>; 408 reg-io-width = <1>; 409 clock-names = "baudclk", "apb_pclk"; 410 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 411 status = "disabled"; 412 }; 413 414 uart3: serial@20068000 { 415 compatible = "snps,dw-apb-uart"; 416 reg = <0x20068000 0x400>; 417 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 418 reg-shift = <2>; 419 reg-io-width = <1>; 420 clock-names = "baudclk", "apb_pclk"; 421 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 422 status = "disabled"; 423 }; 424 425 saradc: saradc@2006c000 { 426 compatible = "rockchip,saradc"; 427 reg = <0x2006c000 0x100>; 428 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 429 #io-channel-cells = <1>; 430 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 431 clock-names = "saradc", "apb_pclk"; 432 resets = <&cru SRST_SARADC>; 433 reset-names = "saradc-apb"; 434 status = "disabled"; 435 }; 436 437 spi0: spi@20070000 { 438 compatible = "rockchip,rk3066-spi"; 439 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 440 clock-names = "spiclk", "apb_pclk"; 441 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 442 reg = <0x20070000 0x1000>; 443 #address-cells = <1>; 444 #size-cells = <0>; 445 dmas = <&dmac2 10>, <&dmac2 11>; 446 dma-names = "tx", "rx"; 447 status = "disabled"; 448 }; 449 450 spi1: spi@20074000 { 451 compatible = "rockchip,rk3066-spi"; 452 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 453 clock-names = "spiclk", "apb_pclk"; 454 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 455 reg = <0x20074000 0x1000>; 456 #address-cells = <1>; 457 #size-cells = <0>; 458 dmas = <&dmac2 12>, <&dmac2 13>; 459 dma-names = "tx", "rx"; 460 status = "disabled"; 461 }; 462 463 dmac2: dma-controller@20078000 { 464 compatible = "arm,pl330", "arm,primecell"; 465 reg = <0x20078000 0x4000>; 466 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 467 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 468 #dma-cells = <1>; 469 arm,pl330-broken-no-flushp; 470 arm,pl330-periph-burst; 471 clocks = <&cru ACLK_DMA2>; 472 clock-names = "apb_pclk"; 473 }; 474}; 475