1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2014 STMicroelectronics Limited.
4 * Author: Peter Griffin <peter.griffin@linaro.org>
5 */
6#include "stih418-clock.dtsi"
7#include "stih407-family.dtsi"
8#include "stih410-pinctrl.dtsi"
9/ {
10	cpus {
11		#address-cells = <1>;
12		#size-cells = <0>;
13		cpu@2 {
14			device_type = "cpu";
15			compatible = "arm,cortex-a9";
16			reg = <2>;
17			/* u-boot puts hpen in SBC dmem at 0xa4 offset */
18			cpu-release-addr = <0x94100A4>;
19		};
20		cpu@3 {
21			device_type = "cpu";
22			compatible = "arm,cortex-a9";
23			reg = <3>;
24			/* u-boot puts hpen in SBC dmem at 0xa4 offset */
25			cpu-release-addr = <0x94100A4>;
26		};
27	};
28
29	soc {
30		usb2_picophy1: phy2@0 {
31			compatible = "st,stih407-usb2-phy";
32			reg = <0 0>;
33			#phy-cells = <0>;
34			st,syscfg = <&syscfg_core 0xf8 0xf4>;
35			resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
36				 <&picophyreset STIH407_PICOPHY0_RESET>;
37			reset-names = "global", "port";
38		};
39
40		usb2_picophy2: phy3@0 {
41			compatible = "st,stih407-usb2-phy";
42			reg = <0 0>;
43			#phy-cells = <0>;
44			st,syscfg = <&syscfg_core 0xfc 0xf4>;
45			resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
46				 <&picophyreset STIH407_PICOPHY1_RESET>;
47			reset-names = "global", "port";
48		};
49
50		ohci0: usb@9a03c00 {
51			compatible = "st,st-ohci-300x";
52			reg = <0x9a03c00 0x100>;
53			interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
54			clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
55			resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
56				 <&softreset STIH407_USB2_PORT0_SOFTRESET>;
57			reset-names = "power", "softreset";
58			phys = <&usb2_picophy1>;
59			phy-names = "usb";
60		};
61
62		ehci0: usb@9a03e00 {
63			compatible = "st,st-ehci-300x";
64			reg = <0x9a03e00 0x100>;
65			interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
66			pinctrl-names = "default";
67			pinctrl-0 = <&pinctrl_usb0>;
68			clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
69			resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
70				 <&softreset STIH407_USB2_PORT0_SOFTRESET>;
71			reset-names = "power", "softreset";
72			phys = <&usb2_picophy1>;
73			phy-names = "usb";
74		};
75
76		ohci1: usb@9a83c00 {
77			compatible = "st,st-ohci-300x";
78			reg = <0x9a83c00 0x100>;
79			interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
80			clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
81			resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
82				 <&softreset STIH407_USB2_PORT1_SOFTRESET>;
83			reset-names = "power", "softreset";
84			phys = <&usb2_picophy2>;
85			phy-names = "usb";
86		};
87
88		ehci1: usb@9a83e00 {
89			compatible = "st,st-ehci-300x";
90			reg = <0x9a83e00 0x100>;
91			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
92			pinctrl-names = "default";
93			pinctrl-0 = <&pinctrl_usb1>;
94			clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
95			resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
96				 <&softreset STIH407_USB2_PORT1_SOFTRESET>;
97			reset-names = "power", "softreset";
98			phys = <&usb2_picophy2>;
99			phy-names = "usb";
100		};
101
102		mmc0: sdhci@9060000 {
103			assigned-clocks = <&clk_s_c0_flexgen CLK_MMC_0>;
104			assigned-clock-parents = <&clk_s_c0_pll1 0>;
105			assigned-clock-rates = <200000000>;
106		};
107	};
108};
109