1/* 2 * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz> 3 * 4 * This file is dual-licensed: you can use it either under the terms 5 * of the GPL or the X11 license, at your option. Note that this dual 6 * licensing only applies to this file, and not this project as a 7 * whole. 8 * 9 * a) This file is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of the 12 * License, or (at your option) any later version. 13 * 14 * This file is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * Or, alternatively, 20 * 21 * b) Permission is hereby granted, free of charge, to any person 22 * obtaining a copy of this software and associated documentation 23 * files (the "Software"), to deal in the Software without 24 * restriction, including without limitation the rights to use, 25 * copy, modify, merge, publish, distribute, sublicense, and/or 26 * sell copies of the Software, and to permit persons to whom the 27 * Software is furnished to do so, subject to the following 28 * conditions: 29 * 30 * The above copyright notice and this permission notice shall be 31 * included in all copies or substantial portions of the Software. 32 * 33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 40 * OTHER DEALINGS IN THE SOFTWARE. 41 */ 42 43#include <dt-bindings/interrupt-controller/arm-gic.h> 44#include <dt-bindings/clock/sun8i-v3s-ccu.h> 45#include <dt-bindings/reset/sun8i-v3s-ccu.h> 46#include <dt-bindings/clock/sun8i-de2.h> 47 48/ { 49 #address-cells = <1>; 50 #size-cells = <1>; 51 interrupt-parent = <&gic>; 52 53 chosen { 54 #address-cells = <1>; 55 #size-cells = <1>; 56 ranges; 57 58 framebuffer-lcd { 59 compatible = "allwinner,simple-framebuffer", 60 "simple-framebuffer"; 61 allwinner,pipeline = "mixer0-lcd0"; 62 clocks = <&display_clocks CLK_MIXER0>, 63 <&ccu CLK_TCON0>; 64 status = "disabled"; 65 }; 66 }; 67 68 cpus { 69 #address-cells = <1>; 70 #size-cells = <0>; 71 72 cpu@0 { 73 compatible = "arm,cortex-a7"; 74 device_type = "cpu"; 75 reg = <0>; 76 clocks = <&ccu CLK_CPU>; 77 }; 78 }; 79 80 de: display-engine { 81 compatible = "allwinner,sun8i-v3s-display-engine"; 82 allwinner,pipelines = <&mixer0>; 83 status = "disabled"; 84 }; 85 86 timer { 87 compatible = "arm,armv7-timer"; 88 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 89 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 90 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 91 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 92 }; 93 94 clocks { 95 #address-cells = <1>; 96 #size-cells = <1>; 97 ranges; 98 99 osc24M: osc24M_clk { 100 #clock-cells = <0>; 101 compatible = "fixed-clock"; 102 clock-frequency = <24000000>; 103 clock-accuracy = <50000>; 104 clock-output-names = "osc24M"; 105 }; 106 107 osc32k: osc32k_clk { 108 #clock-cells = <0>; 109 compatible = "fixed-clock"; 110 clock-frequency = <32768>; 111 clock-accuracy = <50000>; 112 clock-output-names = "ext-osc32k"; 113 }; 114 }; 115 116 soc { 117 compatible = "simple-bus"; 118 #address-cells = <1>; 119 #size-cells = <1>; 120 ranges; 121 122 display_clocks: clock@1000000 { 123 compatible = "allwinner,sun8i-v3s-de2-clk"; 124 reg = <0x01000000 0x10000>; 125 clocks = <&ccu CLK_BUS_DE>, 126 <&ccu CLK_DE>; 127 clock-names = "bus", 128 "mod"; 129 resets = <&ccu RST_BUS_DE>; 130 #clock-cells = <1>; 131 #reset-cells = <1>; 132 }; 133 134 mixer0: mixer@1100000 { 135 compatible = "allwinner,sun8i-v3s-de2-mixer"; 136 reg = <0x01100000 0x100000>; 137 clocks = <&display_clocks 0>, 138 <&display_clocks 6>; 139 clock-names = "bus", 140 "mod"; 141 resets = <&display_clocks 0>; 142 143 ports { 144 #address-cells = <1>; 145 #size-cells = <0>; 146 147 mixer0_out: port@1 { 148 reg = <1>; 149 150 mixer0_out_tcon0: endpoint { 151 remote-endpoint = <&tcon0_in_mixer0>; 152 }; 153 }; 154 }; 155 }; 156 157 syscon: system-control@1c00000 { 158 compatible = "allwinner,sun8i-v3s-system-control", 159 "allwinner,sun8i-h3-system-control"; 160 reg = <0x01c00000 0xd0>; 161 #address-cells = <1>; 162 #size-cells = <1>; 163 ranges; 164 }; 165 166 nmi_intc: interrupt-controller@1c000d0 { 167 compatible = "allwinner,sun8i-v3s-nmi", 168 "allwinner,sun9i-a80-nmi"; 169 interrupt-controller; 170 #interrupt-cells = <2>; 171 reg = <0x01c000d0 0x0c>; 172 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 173 }; 174 175 tcon0: lcd-controller@1c0c000 { 176 compatible = "allwinner,sun8i-v3s-tcon"; 177 reg = <0x01c0c000 0x1000>; 178 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 179 clocks = <&ccu CLK_BUS_TCON0>, 180 <&ccu CLK_TCON0>; 181 clock-names = "ahb", 182 "tcon-ch0"; 183 clock-output-names = "tcon-pixel-clock"; 184 #clock-cells = <0>; 185 resets = <&ccu RST_BUS_TCON0>; 186 reset-names = "lcd"; 187 status = "disabled"; 188 189 ports { 190 #address-cells = <1>; 191 #size-cells = <0>; 192 193 tcon0_in: port@0 { 194 reg = <0>; 195 196 tcon0_in_mixer0: endpoint { 197 remote-endpoint = <&mixer0_out_tcon0>; 198 }; 199 }; 200 201 tcon0_out: port@1 { 202 #address-cells = <1>; 203 #size-cells = <0>; 204 reg = <1>; 205 }; 206 }; 207 }; 208 209 210 mmc0: mmc@1c0f000 { 211 compatible = "allwinner,sun7i-a20-mmc"; 212 reg = <0x01c0f000 0x1000>; 213 clocks = <&ccu CLK_BUS_MMC0>, 214 <&ccu CLK_MMC0>, 215 <&ccu CLK_MMC0_OUTPUT>, 216 <&ccu CLK_MMC0_SAMPLE>; 217 clock-names = "ahb", 218 "mmc", 219 "output", 220 "sample"; 221 resets = <&ccu RST_BUS_MMC0>; 222 reset-names = "ahb"; 223 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 224 pinctrl-names = "default"; 225 pinctrl-0 = <&mmc0_pins>; 226 status = "disabled"; 227 #address-cells = <1>; 228 #size-cells = <0>; 229 }; 230 231 mmc1: mmc@1c10000 { 232 compatible = "allwinner,sun7i-a20-mmc"; 233 reg = <0x01c10000 0x1000>; 234 clocks = <&ccu CLK_BUS_MMC1>, 235 <&ccu CLK_MMC1>, 236 <&ccu CLK_MMC1_OUTPUT>, 237 <&ccu CLK_MMC1_SAMPLE>; 238 clock-names = "ahb", 239 "mmc", 240 "output", 241 "sample"; 242 resets = <&ccu RST_BUS_MMC1>; 243 reset-names = "ahb"; 244 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 245 pinctrl-names = "default"; 246 pinctrl-0 = <&mmc1_pins>; 247 status = "disabled"; 248 #address-cells = <1>; 249 #size-cells = <0>; 250 }; 251 252 mmc2: mmc@1c11000 { 253 compatible = "allwinner,sun7i-a20-mmc"; 254 reg = <0x01c11000 0x1000>; 255 clocks = <&ccu CLK_BUS_MMC2>, 256 <&ccu CLK_MMC2>, 257 <&ccu CLK_MMC2_OUTPUT>, 258 <&ccu CLK_MMC2_SAMPLE>; 259 clock-names = "ahb", 260 "mmc", 261 "output", 262 "sample"; 263 resets = <&ccu RST_BUS_MMC2>; 264 reset-names = "ahb"; 265 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 266 status = "disabled"; 267 #address-cells = <1>; 268 #size-cells = <0>; 269 }; 270 271 crypto@1c15000 { 272 compatible = "allwinner,sun8i-v3s-crypto", 273 "allwinner,sun8i-a33-crypto"; 274 reg = <0x01c15000 0x1000>; 275 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 276 clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>; 277 clock-names = "ahb", "mod"; 278 resets = <&ccu RST_BUS_CE>; 279 reset-names = "ahb"; 280 }; 281 282 usb_otg: usb@1c19000 { 283 compatible = "allwinner,sun8i-h3-musb"; 284 reg = <0x01c19000 0x0400>; 285 clocks = <&ccu CLK_BUS_OTG>; 286 resets = <&ccu RST_BUS_OTG>; 287 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 288 interrupt-names = "mc"; 289 phys = <&usbphy 0>; 290 phy-names = "usb"; 291 extcon = <&usbphy 0>; 292 status = "disabled"; 293 }; 294 295 usbphy: phy@1c19400 { 296 compatible = "allwinner,sun8i-v3s-usb-phy"; 297 reg = <0x01c19400 0x2c>, 298 <0x01c1a800 0x4>; 299 reg-names = "phy_ctrl", 300 "pmu0"; 301 clocks = <&ccu CLK_USB_PHY0>; 302 clock-names = "usb0_phy"; 303 resets = <&ccu RST_USB_PHY0>; 304 reset-names = "usb0_reset"; 305 status = "disabled"; 306 #phy-cells = <1>; 307 }; 308 309 ccu: clock@1c20000 { 310 compatible = "allwinner,sun8i-v3s-ccu"; 311 reg = <0x01c20000 0x400>; 312 clocks = <&osc24M>, <&rtc 0>; 313 clock-names = "hosc", "losc"; 314 #clock-cells = <1>; 315 #reset-cells = <1>; 316 }; 317 318 rtc: rtc@1c20400 { 319 #clock-cells = <1>; 320 compatible = "allwinner,sun8i-v3-rtc"; 321 reg = <0x01c20400 0x54>; 322 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 323 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 324 clocks = <&osc32k>; 325 clock-output-names = "osc32k", "osc32k-out"; 326 }; 327 328 pio: pinctrl@1c20800 { 329 compatible = "allwinner,sun8i-v3s-pinctrl"; 330 reg = <0x01c20800 0x400>; 331 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 332 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 333 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>; 334 clock-names = "apb", "hosc", "losc"; 335 gpio-controller; 336 #gpio-cells = <3>; 337 interrupt-controller; 338 #interrupt-cells = <3>; 339 340 /omit-if-no-ref/ 341 csi0_mclk_pin: csi0-mclk-pin { 342 pins = "PE20"; 343 function = "csi_mipi"; 344 }; 345 346 /omit-if-no-ref/ 347 csi1_8bit_pins: csi1-8bit-pins { 348 pins = "PE0", "PE2", "PE3", "PE8", "PE9", 349 "PE10", "PE11", "PE12", "PE13", "PE14", 350 "PE15"; 351 function = "csi"; 352 }; 353 354 /omit-if-no-ref/ 355 csi1_mclk_pin: csi1-mclk-pin { 356 pins = "PE1"; 357 function = "csi"; 358 }; 359 360 i2c0_pins: i2c0-pins { 361 pins = "PB6", "PB7"; 362 function = "i2c0"; 363 }; 364 365 /omit-if-no-ref/ 366 i2c1_pb_pins: i2c1-pb-pins { 367 pins = "PB8", "PB9"; 368 function = "i2c1"; 369 }; 370 371 /omit-if-no-ref/ 372 i2c1_pe_pins: i2c1-pe-pins { 373 pins = "PE21", "PE22"; 374 function = "i2c1"; 375 }; 376 377 uart0_pb_pins: uart0-pb-pins { 378 pins = "PB8", "PB9"; 379 function = "uart0"; 380 }; 381 382 uart2_pins: uart2-pins { 383 pins = "PB0", "PB1"; 384 function = "uart2"; 385 }; 386 387 mmc0_pins: mmc0-pins { 388 pins = "PF0", "PF1", "PF2", "PF3", 389 "PF4", "PF5"; 390 function = "mmc0"; 391 drive-strength = <30>; 392 bias-pull-up; 393 }; 394 395 mmc1_pins: mmc1-pins { 396 pins = "PG0", "PG1", "PG2", "PG3", 397 "PG4", "PG5"; 398 function = "mmc1"; 399 drive-strength = <30>; 400 bias-pull-up; 401 }; 402 403 spi0_pins: spi0-pins { 404 pins = "PC0", "PC1", "PC2", "PC3"; 405 function = "spi0"; 406 }; 407 }; 408 409 timer@1c20c00 { 410 compatible = "allwinner,sun8i-v3s-timer"; 411 reg = <0x01c20c00 0xa0>; 412 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 413 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 414 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 415 clocks = <&osc24M>; 416 }; 417 418 wdt0: watchdog@1c20ca0 { 419 compatible = "allwinner,sun6i-a31-wdt"; 420 reg = <0x01c20ca0 0x20>; 421 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 422 clocks = <&osc24M>; 423 }; 424 425 lradc: lradc@1c22800 { 426 compatible = "allwinner,sun4i-a10-lradc-keys"; 427 reg = <0x01c22800 0x400>; 428 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 429 status = "disabled"; 430 }; 431 432 uart0: serial@1c28000 { 433 compatible = "snps,dw-apb-uart"; 434 reg = <0x01c28000 0x400>; 435 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 436 reg-shift = <2>; 437 reg-io-width = <4>; 438 clocks = <&ccu CLK_BUS_UART0>; 439 resets = <&ccu RST_BUS_UART0>; 440 status = "disabled"; 441 }; 442 443 uart1: serial@1c28400 { 444 compatible = "snps,dw-apb-uart"; 445 reg = <0x01c28400 0x400>; 446 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 447 reg-shift = <2>; 448 reg-io-width = <4>; 449 clocks = <&ccu CLK_BUS_UART1>; 450 resets = <&ccu RST_BUS_UART1>; 451 status = "disabled"; 452 }; 453 454 uart2: serial@1c28800 { 455 compatible = "snps,dw-apb-uart"; 456 reg = <0x01c28800 0x400>; 457 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 458 reg-shift = <2>; 459 reg-io-width = <4>; 460 clocks = <&ccu CLK_BUS_UART2>; 461 resets = <&ccu RST_BUS_UART2>; 462 pinctrl-0 = <&uart2_pins>; 463 pinctrl-names = "default"; 464 status = "disabled"; 465 }; 466 467 i2c0: i2c@1c2ac00 { 468 compatible = "allwinner,sun6i-a31-i2c"; 469 reg = <0x01c2ac00 0x400>; 470 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 471 clocks = <&ccu CLK_BUS_I2C0>; 472 resets = <&ccu RST_BUS_I2C0>; 473 pinctrl-names = "default"; 474 pinctrl-0 = <&i2c0_pins>; 475 status = "disabled"; 476 #address-cells = <1>; 477 #size-cells = <0>; 478 }; 479 480 i2c1: i2c@1c2b000 { 481 compatible = "allwinner,sun6i-a31-i2c"; 482 reg = <0x01c2b000 0x400>; 483 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 484 clocks = <&ccu CLK_BUS_I2C1>; 485 resets = <&ccu RST_BUS_I2C1>; 486 status = "disabled"; 487 #address-cells = <1>; 488 #size-cells = <0>; 489 }; 490 491 emac: ethernet@1c30000 { 492 compatible = "allwinner,sun8i-v3s-emac"; 493 syscon = <&syscon>; 494 reg = <0x01c30000 0x10000>; 495 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 496 interrupt-names = "macirq"; 497 resets = <&ccu RST_BUS_EMAC>; 498 reset-names = "stmmaceth"; 499 clocks = <&ccu CLK_BUS_EMAC>; 500 clock-names = "stmmaceth"; 501 phy-handle = <&int_mii_phy>; 502 phy-mode = "mii"; 503 status = "disabled"; 504 505 mdio: mdio { 506 #address-cells = <1>; 507 #size-cells = <0>; 508 compatible = "snps,dwmac-mdio"; 509 }; 510 511 mdio_mux: mdio-mux { 512 compatible = "allwinner,sun8i-h3-mdio-mux"; 513 #address-cells = <1>; 514 #size-cells = <0>; 515 516 mdio-parent-bus = <&mdio>; 517 /* Only one MDIO is usable at the time */ 518 internal_mdio: mdio@1 { 519 compatible = "allwinner,sun8i-h3-mdio-internal"; 520 reg = <1>; 521 #address-cells = <1>; 522 #size-cells = <0>; 523 524 int_mii_phy: ethernet-phy@1 { 525 compatible = "ethernet-phy-ieee802.3-c22"; 526 reg = <1>; 527 clocks = <&ccu CLK_BUS_EPHY>; 528 resets = <&ccu RST_BUS_EPHY>; 529 }; 530 }; 531 }; 532 }; 533 534 spi0: spi@1c68000 { 535 compatible = "allwinner,sun8i-h3-spi"; 536 reg = <0x01c68000 0x1000>; 537 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 538 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 539 clock-names = "ahb", "mod"; 540 pinctrl-names = "default"; 541 pinctrl-0 = <&spi0_pins>; 542 resets = <&ccu RST_BUS_SPI0>; 543 status = "disabled"; 544 #address-cells = <1>; 545 #size-cells = <0>; 546 }; 547 548 csi1: camera@1cb4000 { 549 compatible = "allwinner,sun8i-v3s-csi"; 550 reg = <0x01cb4000 0x3000>; 551 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 552 clocks = <&ccu CLK_BUS_CSI>, 553 <&ccu CLK_CSI1_SCLK>, 554 <&ccu CLK_DRAM_CSI>; 555 clock-names = "bus", "mod", "ram"; 556 resets = <&ccu RST_BUS_CSI>; 557 status = "disabled"; 558 }; 559 560 gic: interrupt-controller@1c81000 { 561 compatible = "arm,gic-400"; 562 reg = <0x01c81000 0x1000>, 563 <0x01c82000 0x2000>, 564 <0x01c84000 0x2000>, 565 <0x01c86000 0x2000>; 566 interrupt-controller; 567 #interrupt-cells = <3>; 568 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 569 }; 570 }; 571}; 572