1// SPDX-License-Identifier: GPL-2.0 OR MIT 2/* 3 * Copyright 2016-2018 Toradex AG 4 */ 5 6#include "tegra124.dtsi" 7#include "tegra124-apalis-emc.dtsi" 8 9/* 10 * Toradex Apalis TK1 Module Device Tree 11 * Compatible for Revisions 2GB: V1.2A 12 */ 13/ { 14 memory@80000000 { 15 reg = <0x0 0x80000000 0x0 0x80000000>; 16 }; 17 18 pcie@1003000 { 19 status = "okay"; 20 21 avddio-pex-supply = <®_1v05_vdd>; 22 avdd-pex-pll-supply = <®_1v05_vdd>; 23 avdd-pll-erefe-supply = <®_1v05_avdd>; 24 dvddio-pex-supply = <®_1v05_vdd>; 25 hvdd-pex-pll-e-supply = <®_module_3v3>; 26 hvdd-pex-supply = <®_module_3v3>; 27 vddio-pex-ctl-supply = <®_module_3v3>; 28 29 /* Apalis PCIe (additional lane Apalis type specific) */ 30 pci@1,0 { 31 /* PCIE1_RX/TX and TS_DIFF1/2 */ 32 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>, 33 <&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>; 34 phy-names = "pcie-0", "pcie-1"; 35 }; 36 37 /* I210 Gigabit Ethernet Controller (On-module) */ 38 pci@2,0 { 39 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>; 40 phy-names = "pcie-0"; 41 status = "okay"; 42 43 ethernet@0,0 { 44 reg = <0 0 0 0 0>; 45 local-mac-address = [00 00 00 00 00 00]; 46 }; 47 }; 48 }; 49 50 host1x@50000000 { 51 hdmi@54280000 { 52 nvidia,ddc-i2c-bus = <&hdmi_ddc>; 53 nvidia,hpd-gpio = 54 <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; 55 pll-supply = <®_1v05_avdd_hdmi_pll>; 56 vdd-supply = <®_3v3_avdd_hdmi>; 57 }; 58 }; 59 60 gpu@0,57000000 { 61 /* 62 * Node left disabled on purpose - the bootloader will enable 63 * it after having set the VPR up 64 */ 65 vdd-supply = <®_vdd_gpu>; 66 }; 67 68 pinmux@70000868 { 69 pinctrl-names = "default"; 70 pinctrl-0 = <&state_default>; 71 72 state_default: pinmux { 73 /* Analogue Audio (On-module) */ 74 dap3-fs-pp0 { 75 nvidia,pins = "dap3_fs_pp0"; 76 nvidia,function = "i2s2"; 77 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 78 nvidia,tristate = <TEGRA_PIN_DISABLE>; 79 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 80 }; 81 dap3-din-pp1 { 82 nvidia,pins = "dap3_din_pp1"; 83 nvidia,function = "i2s2"; 84 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 85 nvidia,tristate = <TEGRA_PIN_ENABLE>; 86 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 87 }; 88 dap3-dout-pp2 { 89 nvidia,pins = "dap3_dout_pp2"; 90 nvidia,function = "i2s2"; 91 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 92 nvidia,tristate = <TEGRA_PIN_DISABLE>; 93 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 94 }; 95 dap3-sclk-pp3 { 96 nvidia,pins = "dap3_sclk_pp3"; 97 nvidia,function = "i2s2"; 98 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 99 nvidia,tristate = <TEGRA_PIN_DISABLE>; 100 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 101 }; 102 dap-mclk1-pw4 { 103 nvidia,pins = "dap_mclk1_pw4"; 104 nvidia,function = "extperiph1"; 105 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 106 nvidia,tristate = <TEGRA_PIN_DISABLE>; 107 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 108 }; 109 110 /* Apalis BKL1_ON */ 111 pbb5 { 112 nvidia,pins = "pbb5"; 113 nvidia,function = "vgp5"; 114 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 115 nvidia,tristate = <TEGRA_PIN_DISABLE>; 116 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 117 }; 118 119 /* Apalis BKL1_PWM */ 120 pu6 { 121 nvidia,pins = "pu6"; 122 nvidia,function = "pwm3"; 123 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 124 nvidia,tristate = <TEGRA_PIN_DISABLE>; 125 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 126 }; 127 128 /* Apalis CAM1_MCLK */ 129 cam-mclk-pcc0 { 130 nvidia,pins = "cam_mclk_pcc0"; 131 nvidia,function = "vi_alt3"; 132 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 133 nvidia,tristate = <TEGRA_PIN_DISABLE>; 134 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 135 }; 136 137 /* Apalis Digital Audio */ 138 dap2-fs-pa2 { 139 nvidia,pins = "dap2_fs_pa2"; 140 nvidia,function = "hda"; 141 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 142 nvidia,tristate = <TEGRA_PIN_DISABLE>; 143 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 144 }; 145 dap2-sclk-pa3 { 146 nvidia,pins = "dap2_sclk_pa3"; 147 nvidia,function = "hda"; 148 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 149 nvidia,tristate = <TEGRA_PIN_DISABLE>; 150 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 151 }; 152 dap2-din-pa4 { 153 nvidia,pins = "dap2_din_pa4"; 154 nvidia,function = "hda"; 155 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 156 nvidia,tristate = <TEGRA_PIN_ENABLE>; 157 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 158 }; 159 dap2-dout-pa5 { 160 nvidia,pins = "dap2_dout_pa5"; 161 nvidia,function = "hda"; 162 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 163 nvidia,tristate = <TEGRA_PIN_DISABLE>; 164 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 165 }; 166 pbb3 { /* DAP1_RESET */ 167 nvidia,pins = "pbb3"; 168 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 169 nvidia,tristate = <TEGRA_PIN_DISABLE>; 170 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 171 }; 172 clk3-out-pee0 { 173 nvidia,pins = "clk3_out_pee0"; 174 nvidia,function = "extperiph3"; 175 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 176 nvidia,tristate = <TEGRA_PIN_DISABLE>; 177 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 178 }; 179 180 /* Apalis GPIO */ 181 usb-vbus-en0-pn4 { 182 nvidia,pins = "usb_vbus_en0_pn4"; 183 nvidia,function = "rsvd2"; 184 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 185 nvidia,tristate = <TEGRA_PIN_DISABLE>; 186 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 187 nvidia,open-drain = <TEGRA_PIN_DISABLE>; 188 }; 189 usb-vbus-en1-pn5 { 190 nvidia,pins = "usb_vbus_en1_pn5"; 191 nvidia,function = "rsvd2"; 192 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 193 nvidia,tristate = <TEGRA_PIN_DISABLE>; 194 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 195 nvidia,open-drain = <TEGRA_PIN_DISABLE>; 196 }; 197 pex-l0-rst-n-pdd1 { 198 nvidia,pins = "pex_l0_rst_n_pdd1"; 199 nvidia,function = "rsvd2"; 200 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 201 nvidia,tristate = <TEGRA_PIN_DISABLE>; 202 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 203 }; 204 pex-l0-clkreq-n-pdd2 { 205 nvidia,pins = "pex_l0_clkreq_n_pdd2"; 206 nvidia,function = "rsvd2"; 207 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 208 nvidia,tristate = <TEGRA_PIN_DISABLE>; 209 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 210 }; 211 pex-l1-rst-n-pdd5 { 212 nvidia,pins = "pex_l1_rst_n_pdd5"; 213 nvidia,function = "rsvd2"; 214 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 215 nvidia,tristate = <TEGRA_PIN_DISABLE>; 216 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 217 }; 218 pex-l1-clkreq-n-pdd6 { 219 nvidia,pins = "pex_l1_clkreq_n_pdd6"; 220 nvidia,function = "rsvd2"; 221 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 222 nvidia,tristate = <TEGRA_PIN_DISABLE>; 223 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 224 }; 225 dp-hpd-pff0 { 226 nvidia,pins = "dp_hpd_pff0"; 227 nvidia,function = "dp"; 228 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 229 nvidia,tristate = <TEGRA_PIN_DISABLE>; 230 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 231 }; 232 pff2 { 233 nvidia,pins = "pff2"; 234 nvidia,function = "rsvd2"; 235 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 236 nvidia,tristate = <TEGRA_PIN_DISABLE>; 237 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 238 }; 239 owr { /* PEX_L1_CLKREQ_N multiplexed GPIO6 */ 240 nvidia,pins = "owr"; 241 nvidia,function = "rsvd2"; 242 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 243 nvidia,tristate = <TEGRA_PIN_ENABLE>; 244 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 245 nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; 246 }; 247 248 /* Apalis HDMI1_CEC */ 249 hdmi-cec-pee3 { 250 nvidia,pins = "hdmi_cec_pee3"; 251 nvidia,function = "cec"; 252 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 253 nvidia,tristate = <TEGRA_PIN_DISABLE>; 254 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 255 nvidia,open-drain = <TEGRA_PIN_DISABLE>; 256 }; 257 258 /* Apalis HDMI1_HPD */ 259 hdmi-int-pn7 { 260 nvidia,pins = "hdmi_int_pn7"; 261 nvidia,function = "rsvd1"; 262 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 263 nvidia,tristate = <TEGRA_PIN_ENABLE>; 264 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 265 nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; 266 }; 267 268 /* Apalis I2C1 */ 269 gen1-i2c-scl-pc4 { 270 nvidia,pins = "gen1_i2c_scl_pc4"; 271 nvidia,function = "i2c1"; 272 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 273 nvidia,tristate = <TEGRA_PIN_DISABLE>; 274 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 275 nvidia,open-drain = <TEGRA_PIN_ENABLE>; 276 }; 277 gen1-i2c-sda-pc5 { 278 nvidia,pins = "gen1_i2c_sda_pc5"; 279 nvidia,function = "i2c1"; 280 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 281 nvidia,tristate = <TEGRA_PIN_DISABLE>; 282 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 283 nvidia,open-drain = <TEGRA_PIN_ENABLE>; 284 }; 285 286 /* Apalis I2C3 (CAM) */ 287 cam-i2c-scl-pbb1 { 288 nvidia,pins = "cam_i2c_scl_pbb1"; 289 nvidia,function = "i2c3"; 290 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 291 nvidia,tristate = <TEGRA_PIN_DISABLE>; 292 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 293 nvidia,open-drain = <TEGRA_PIN_ENABLE>; 294 }; 295 cam-i2c-sda-pbb2 { 296 nvidia,pins = "cam_i2c_sda_pbb2"; 297 nvidia,function = "i2c3"; 298 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 299 nvidia,tristate = <TEGRA_PIN_DISABLE>; 300 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 301 nvidia,open-drain = <TEGRA_PIN_ENABLE>; 302 }; 303 304 /* Apalis I2C4 (DDC) */ 305 ddc-scl-pv4 { 306 nvidia,pins = "ddc_scl_pv4"; 307 nvidia,function = "i2c4"; 308 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 309 nvidia,tristate = <TEGRA_PIN_DISABLE>; 310 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 311 nvidia,rcv-sel = <TEGRA_PIN_ENABLE>; 312 }; 313 ddc-sda-pv5 { 314 nvidia,pins = "ddc_sda_pv5"; 315 nvidia,function = "i2c4"; 316 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 317 nvidia,tristate = <TEGRA_PIN_DISABLE>; 318 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 319 nvidia,rcv-sel = <TEGRA_PIN_ENABLE>; 320 }; 321 322 /* Apalis MMC1 */ 323 sdmmc1-cd-n-pv3 { /* CD# GPIO */ 324 nvidia,pins = "sdmmc1_wp_n_pv3"; 325 nvidia,function = "sdmmc1"; 326 nvidia,pull = <TEGRA_PIN_PULL_UP>; 327 nvidia,tristate = <TEGRA_PIN_ENABLE>; 328 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 329 }; 330 clk2-out-pw5 { /* D5 GPIO */ 331 nvidia,pins = "clk2_out_pw5"; 332 nvidia,function = "rsvd2"; 333 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 334 nvidia,tristate = <TEGRA_PIN_DISABLE>; 335 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 336 }; 337 sdmmc1-dat3-py4 { 338 nvidia,pins = "sdmmc1_dat3_py4"; 339 nvidia,function = "sdmmc1"; 340 nvidia,pull = <TEGRA_PIN_PULL_UP>; 341 nvidia,tristate = <TEGRA_PIN_DISABLE>; 342 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 343 }; 344 sdmmc1-dat2-py5 { 345 nvidia,pins = "sdmmc1_dat2_py5"; 346 nvidia,function = "sdmmc1"; 347 nvidia,pull = <TEGRA_PIN_PULL_UP>; 348 nvidia,tristate = <TEGRA_PIN_DISABLE>; 349 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 350 }; 351 sdmmc1-dat1-py6 { 352 nvidia,pins = "sdmmc1_dat1_py6"; 353 nvidia,function = "sdmmc1"; 354 nvidia,pull = <TEGRA_PIN_PULL_UP>; 355 nvidia,tristate = <TEGRA_PIN_DISABLE>; 356 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 357 }; 358 sdmmc1-dat0-py7 { 359 nvidia,pins = "sdmmc1_dat0_py7"; 360 nvidia,function = "sdmmc1"; 361 nvidia,pull = <TEGRA_PIN_PULL_UP>; 362 nvidia,tristate = <TEGRA_PIN_DISABLE>; 363 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 364 }; 365 sdmmc1-clk-pz0 { 366 nvidia,pins = "sdmmc1_clk_pz0"; 367 nvidia,function = "sdmmc1"; 368 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 369 nvidia,tristate = <TEGRA_PIN_DISABLE>; 370 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 371 }; 372 sdmmc1-cmd-pz1 { 373 nvidia,pins = "sdmmc1_cmd_pz1"; 374 nvidia,function = "sdmmc1"; 375 nvidia,pull = <TEGRA_PIN_PULL_UP>; 376 nvidia,tristate = <TEGRA_PIN_DISABLE>; 377 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 378 }; 379 clk2-req-pcc5 { /* D4 GPIO */ 380 nvidia,pins = "clk2_req_pcc5"; 381 nvidia,function = "rsvd2"; 382 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 383 nvidia,tristate = <TEGRA_PIN_DISABLE>; 384 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 385 }; 386 sdmmc3-clk-lb-in-pee5 { /* D6 GPIO */ 387 nvidia,pins = "sdmmc3_clk_lb_in_pee5"; 388 nvidia,function = "rsvd2"; 389 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 390 nvidia,tristate = <TEGRA_PIN_DISABLE>; 391 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 392 }; 393 usb-vbus-en2-pff1 { /* D7 GPIO */ 394 nvidia,pins = "usb_vbus_en2_pff1"; 395 nvidia,function = "rsvd2"; 396 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 397 nvidia,tristate = <TEGRA_PIN_DISABLE>; 398 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 399 }; 400 401 /* Apalis PWM */ 402 ph0 { 403 nvidia,pins = "ph0"; 404 nvidia,function = "pwm0"; 405 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 406 nvidia,tristate = <TEGRA_PIN_DISABLE>; 407 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 408 }; 409 ph1 { 410 nvidia,pins = "ph1"; 411 nvidia,function = "pwm1"; 412 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 413 nvidia,tristate = <TEGRA_PIN_DISABLE>; 414 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 415 }; 416 ph2 { 417 nvidia,pins = "ph2"; 418 nvidia,function = "pwm2"; 419 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 420 nvidia,tristate = <TEGRA_PIN_DISABLE>; 421 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 422 }; 423 /* PWM3 active on pu6 being Apalis BKL1_PWM as well */ 424 ph3 { 425 nvidia,pins = "ph3"; 426 nvidia,function = "pwm3"; 427 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 428 nvidia,tristate = <TEGRA_PIN_DISABLE>; 429 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 430 }; 431 432 /* Apalis SATA1_ACT# */ 433 dap1-dout-pn2 { 434 nvidia,pins = "dap1_dout_pn2"; 435 nvidia,function = "gmi"; 436 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 437 nvidia,tristate = <TEGRA_PIN_DISABLE>; 438 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 439 }; 440 441 /* Apalis SD1 */ 442 sdmmc3-clk-pa6 { 443 nvidia,pins = "sdmmc3_clk_pa6"; 444 nvidia,function = "sdmmc3"; 445 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 446 nvidia,tristate = <TEGRA_PIN_DISABLE>; 447 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 448 }; 449 sdmmc3-cmd-pa7 { 450 nvidia,pins = "sdmmc3_cmd_pa7"; 451 nvidia,function = "sdmmc3"; 452 nvidia,pull = <TEGRA_PIN_PULL_UP>; 453 nvidia,tristate = <TEGRA_PIN_DISABLE>; 454 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 455 }; 456 sdmmc3-dat3-pb4 { 457 nvidia,pins = "sdmmc3_dat3_pb4"; 458 nvidia,function = "sdmmc3"; 459 nvidia,pull = <TEGRA_PIN_PULL_UP>; 460 nvidia,tristate = <TEGRA_PIN_DISABLE>; 461 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 462 }; 463 sdmmc3-dat2-pb5 { 464 nvidia,pins = "sdmmc3_dat2_pb5"; 465 nvidia,function = "sdmmc3"; 466 nvidia,pull = <TEGRA_PIN_PULL_UP>; 467 nvidia,tristate = <TEGRA_PIN_DISABLE>; 468 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 469 }; 470 sdmmc3-dat1-pb6 { 471 nvidia,pins = "sdmmc3_dat1_pb6"; 472 nvidia,function = "sdmmc3"; 473 nvidia,pull = <TEGRA_PIN_PULL_UP>; 474 nvidia,tristate = <TEGRA_PIN_DISABLE>; 475 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 476 }; 477 sdmmc3-dat0-pb7 { 478 nvidia,pins = "sdmmc3_dat0_pb7"; 479 nvidia,function = "sdmmc3"; 480 nvidia,pull = <TEGRA_PIN_PULL_UP>; 481 nvidia,tristate = <TEGRA_PIN_DISABLE>; 482 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 483 }; 484 sdmmc3-cd-n-pv2 { /* CD# GPIO */ 485 nvidia,pins = "sdmmc3_cd_n_pv2"; 486 nvidia,function = "rsvd3"; 487 nvidia,pull = <TEGRA_PIN_PULL_UP>; 488 nvidia,tristate = <TEGRA_PIN_ENABLE>; 489 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 490 }; 491 492 /* Apalis SPDIF */ 493 spdif-out-pk5 { 494 nvidia,pins = "spdif_out_pk5"; 495 nvidia,function = "spdif"; 496 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 497 nvidia,tristate = <TEGRA_PIN_DISABLE>; 498 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 499 }; 500 spdif-in-pk6 { 501 nvidia,pins = "spdif_in_pk6"; 502 nvidia,function = "spdif"; 503 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 504 nvidia,tristate = <TEGRA_PIN_ENABLE>; 505 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 506 }; 507 508 /* Apalis SPI1 */ 509 ulpi-clk-py0 { 510 nvidia,pins = "ulpi_clk_py0"; 511 nvidia,function = "spi1"; 512 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 513 nvidia,tristate = <TEGRA_PIN_DISABLE>; 514 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 515 }; 516 ulpi-dir-py1 { 517 nvidia,pins = "ulpi_dir_py1"; 518 nvidia,function = "spi1"; 519 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 520 nvidia,tristate = <TEGRA_PIN_ENABLE>; 521 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 522 }; 523 ulpi-nxt-py2 { 524 nvidia,pins = "ulpi_nxt_py2"; 525 nvidia,function = "spi1"; 526 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 527 nvidia,tristate = <TEGRA_PIN_DISABLE>; 528 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 529 }; 530 ulpi-stp-py3 { 531 nvidia,pins = "ulpi_stp_py3"; 532 nvidia,function = "spi1"; 533 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 534 nvidia,tristate = <TEGRA_PIN_DISABLE>; 535 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 536 }; 537 538 /* Apalis SPI2 */ 539 pg5 { 540 nvidia,pins = "pg5"; 541 nvidia,function = "spi4"; 542 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 543 nvidia,tristate = <TEGRA_PIN_DISABLE>; 544 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 545 }; 546 pg6 { 547 nvidia,pins = "pg6"; 548 nvidia,function = "spi4"; 549 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 550 nvidia,tristate = <TEGRA_PIN_DISABLE>; 551 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 552 }; 553 pg7 { 554 nvidia,pins = "pg7"; 555 nvidia,function = "spi4"; 556 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 557 nvidia,tristate = <TEGRA_PIN_ENABLE>; 558 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 559 }; 560 pi3 { 561 nvidia,pins = "pi3"; 562 nvidia,function = "spi4"; 563 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 564 nvidia,tristate = <TEGRA_PIN_DISABLE>; 565 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 566 }; 567 568 /* Apalis UART1 */ 569 pb1 { /* DCD GPIO */ 570 nvidia,pins = "pb1"; 571 nvidia,function = "rsvd2"; 572 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 573 nvidia,tristate = <TEGRA_PIN_ENABLE>; 574 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 575 }; 576 pk7 { /* RI GPIO */ 577 nvidia,pins = "pk7"; 578 nvidia,function = "rsvd2"; 579 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 580 nvidia,tristate = <TEGRA_PIN_ENABLE>; 581 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 582 }; 583 uart1-txd-pu0 { 584 nvidia,pins = "pu0"; 585 nvidia,function = "uarta"; 586 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 587 nvidia,tristate = <TEGRA_PIN_DISABLE>; 588 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 589 }; 590 uart1-rxd-pu1 { 591 nvidia,pins = "pu1"; 592 nvidia,function = "uarta"; 593 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 594 nvidia,tristate = <TEGRA_PIN_ENABLE>; 595 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 596 }; 597 uart1-cts-n-pu2 { 598 nvidia,pins = "pu2"; 599 nvidia,function = "uarta"; 600 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 601 nvidia,tristate = <TEGRA_PIN_ENABLE>; 602 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 603 }; 604 uart1-rts-n-pu3 { 605 nvidia,pins = "pu3"; 606 nvidia,function = "uarta"; 607 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 608 nvidia,tristate = <TEGRA_PIN_DISABLE>; 609 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 610 }; 611 uart3-cts-n-pa1 { /* DSR GPIO */ 612 nvidia,pins = "uart3_cts_n_pa1"; 613 nvidia,function = "gmi"; 614 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 615 nvidia,tristate = <TEGRA_PIN_ENABLE>; 616 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 617 }; 618 uart3-rts-n-pc0 { /* DTR GPIO */ 619 nvidia,pins = "uart3_rts_n_pc0"; 620 nvidia,function = "gmi"; 621 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 622 nvidia,tristate = <TEGRA_PIN_DISABLE>; 623 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 624 }; 625 626 /* Apalis UART2 */ 627 uart2-txd-pc2 { 628 nvidia,pins = "uart2_txd_pc2"; 629 nvidia,function = "irda"; 630 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 631 nvidia,tristate = <TEGRA_PIN_DISABLE>; 632 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 633 }; 634 uart2-rxd-pc3 { 635 nvidia,pins = "uart2_rxd_pc3"; 636 nvidia,function = "irda"; 637 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 638 nvidia,tristate = <TEGRA_PIN_ENABLE>; 639 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 640 }; 641 uart2-cts-n-pj5 { 642 nvidia,pins = "uart2_cts_n_pj5"; 643 nvidia,function = "uartb"; 644 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 645 nvidia,tristate = <TEGRA_PIN_ENABLE>; 646 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 647 }; 648 uart2-rts-n-pj6 { 649 nvidia,pins = "uart2_rts_n_pj6"; 650 nvidia,function = "uartb"; 651 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 652 nvidia,tristate = <TEGRA_PIN_DISABLE>; 653 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 654 }; 655 656 /* Apalis UART3 */ 657 uart3-txd-pw6 { 658 nvidia,pins = "uart3_txd_pw6"; 659 nvidia,function = "uartc"; 660 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 661 nvidia,tristate = <TEGRA_PIN_DISABLE>; 662 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 663 }; 664 uart3-rxd-pw7 { 665 nvidia,pins = "uart3_rxd_pw7"; 666 nvidia,function = "uartc"; 667 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 668 nvidia,tristate = <TEGRA_PIN_ENABLE>; 669 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 670 }; 671 672 /* Apalis UART4 */ 673 uart4-rxd-pb0 { 674 nvidia,pins = "pb0"; 675 nvidia,function = "uartd"; 676 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 677 nvidia,tristate = <TEGRA_PIN_ENABLE>; 678 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 679 }; 680 uart4-txd-pj7 { 681 nvidia,pins = "pj7"; 682 nvidia,function = "uartd"; 683 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 684 nvidia,tristate = <TEGRA_PIN_DISABLE>; 685 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 686 }; 687 688 /* Apalis USBH_EN */ 689 gen2-i2c-sda-pt6 { 690 nvidia,pins = "gen2_i2c_sda_pt6"; 691 nvidia,function = "rsvd2"; 692 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 693 nvidia,tristate = <TEGRA_PIN_DISABLE>; 694 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 695 nvidia,open-drain = <TEGRA_PIN_DISABLE>; 696 }; 697 698 /* Apalis USBH_OC# */ 699 pbb0 { 700 nvidia,pins = "pbb0"; 701 nvidia,function = "vgp6"; 702 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 703 nvidia,tristate = <TEGRA_PIN_ENABLE>; 704 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 705 }; 706 707 /* Apalis USBO1_EN */ 708 gen2-i2c-scl-pt5 { 709 nvidia,pins = "gen2_i2c_scl_pt5"; 710 nvidia,function = "rsvd2"; 711 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 712 nvidia,tristate = <TEGRA_PIN_DISABLE>; 713 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 714 nvidia,open-drain = <TEGRA_PIN_DISABLE>; 715 }; 716 717 /* Apalis USBO1_OC# */ 718 pbb4 { 719 nvidia,pins = "pbb4"; 720 nvidia,function = "vgp4"; 721 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 722 nvidia,tristate = <TEGRA_PIN_ENABLE>; 723 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 724 }; 725 726 /* Apalis WAKE1_MICO */ 727 pex-wake-n-pdd3 { 728 nvidia,pins = "pex_wake_n_pdd3"; 729 nvidia,function = "rsvd2"; 730 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 731 nvidia,tristate = <TEGRA_PIN_ENABLE>; 732 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 733 }; 734 735 /* CORE_PWR_REQ */ 736 core-pwr-req { 737 nvidia,pins = "core_pwr_req"; 738 nvidia,function = "pwron"; 739 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 740 nvidia,tristate = <TEGRA_PIN_DISABLE>; 741 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 742 }; 743 744 /* CPU_PWR_REQ */ 745 cpu-pwr-req { 746 nvidia,pins = "cpu_pwr_req"; 747 nvidia,function = "cpu"; 748 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 749 nvidia,tristate = <TEGRA_PIN_DISABLE>; 750 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 751 }; 752 753 /* DVFS */ 754 dvfs-pwm-px0 { 755 nvidia,pins = "dvfs_pwm_px0"; 756 nvidia,function = "cldvfs"; 757 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 758 nvidia,tristate = <TEGRA_PIN_DISABLE>; 759 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 760 }; 761 dvfs-clk-px2 { 762 nvidia,pins = "dvfs_clk_px2"; 763 nvidia,function = "cldvfs"; 764 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 765 nvidia,tristate = <TEGRA_PIN_DISABLE>; 766 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 767 }; 768 769 /* eMMC */ 770 sdmmc4-dat0-paa0 { 771 nvidia,pins = "sdmmc4_dat0_paa0"; 772 nvidia,function = "sdmmc4"; 773 nvidia,pull = <TEGRA_PIN_PULL_UP>; 774 nvidia,tristate = <TEGRA_PIN_DISABLE>; 775 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 776 }; 777 sdmmc4-dat1-paa1 { 778 nvidia,pins = "sdmmc4_dat1_paa1"; 779 nvidia,function = "sdmmc4"; 780 nvidia,pull = <TEGRA_PIN_PULL_UP>; 781 nvidia,tristate = <TEGRA_PIN_DISABLE>; 782 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 783 }; 784 sdmmc4-dat2-paa2 { 785 nvidia,pins = "sdmmc4_dat2_paa2"; 786 nvidia,function = "sdmmc4"; 787 nvidia,pull = <TEGRA_PIN_PULL_UP>; 788 nvidia,tristate = <TEGRA_PIN_DISABLE>; 789 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 790 }; 791 sdmmc4-dat3-paa3 { 792 nvidia,pins = "sdmmc4_dat3_paa3"; 793 nvidia,function = "sdmmc4"; 794 nvidia,pull = <TEGRA_PIN_PULL_UP>; 795 nvidia,tristate = <TEGRA_PIN_DISABLE>; 796 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 797 }; 798 sdmmc4-dat4-paa4 { 799 nvidia,pins = "sdmmc4_dat4_paa4"; 800 nvidia,function = "sdmmc4"; 801 nvidia,pull = <TEGRA_PIN_PULL_UP>; 802 nvidia,tristate = <TEGRA_PIN_DISABLE>; 803 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 804 }; 805 sdmmc4-dat5-paa5 { 806 nvidia,pins = "sdmmc4_dat5_paa5"; 807 nvidia,function = "sdmmc4"; 808 nvidia,pull = <TEGRA_PIN_PULL_UP>; 809 nvidia,tristate = <TEGRA_PIN_DISABLE>; 810 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 811 }; 812 sdmmc4-dat6-paa6 { 813 nvidia,pins = "sdmmc4_dat6_paa6"; 814 nvidia,function = "sdmmc4"; 815 nvidia,pull = <TEGRA_PIN_PULL_UP>; 816 nvidia,tristate = <TEGRA_PIN_DISABLE>; 817 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 818 }; 819 sdmmc4-dat7-paa7 { 820 nvidia,pins = "sdmmc4_dat7_paa7"; 821 nvidia,function = "sdmmc4"; 822 nvidia,pull = <TEGRA_PIN_PULL_UP>; 823 nvidia,tristate = <TEGRA_PIN_DISABLE>; 824 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 825 }; 826 sdmmc4-clk-pcc4 { 827 nvidia,pins = "sdmmc4_clk_pcc4"; 828 nvidia,function = "sdmmc4"; 829 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 830 nvidia,tristate = <TEGRA_PIN_DISABLE>; 831 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 832 }; 833 sdmmc4-cmd-pt7 { 834 nvidia,pins = "sdmmc4_cmd_pt7"; 835 nvidia,function = "sdmmc4"; 836 nvidia,pull = <TEGRA_PIN_PULL_UP>; 837 nvidia,tristate = <TEGRA_PIN_DISABLE>; 838 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 839 }; 840 841 /* JTAG_RTCK */ 842 jtag-rtck { 843 nvidia,pins = "jtag_rtck"; 844 nvidia,function = "rtck"; 845 nvidia,pull = <TEGRA_PIN_PULL_UP>; 846 nvidia,tristate = <TEGRA_PIN_DISABLE>; 847 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 848 }; 849 850 /* LAN_DEV_OFF# */ 851 ulpi-data5-po6 { 852 nvidia,pins = "ulpi_data5_po6"; 853 nvidia,function = "ulpi"; 854 nvidia,pull = <TEGRA_PIN_PULL_UP>; 855 nvidia,tristate = <TEGRA_PIN_DISABLE>; 856 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 857 }; 858 859 /* LAN_RESET# */ 860 kb-row10-ps2 { 861 nvidia,pins = "kb_row10_ps2"; 862 nvidia,function = "rsvd2"; 863 nvidia,pull = <TEGRA_PIN_PULL_UP>; 864 nvidia,tristate = <TEGRA_PIN_DISABLE>; 865 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 866 }; 867 868 /* LAN_WAKE# */ 869 ulpi-data4-po5 { 870 nvidia,pins = "ulpi_data4_po5"; 871 nvidia,function = "ulpi"; 872 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 873 nvidia,tristate = <TEGRA_PIN_ENABLE>; 874 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 875 }; 876 877 /* MCU_INT1# */ 878 pk2 { 879 nvidia,pins = "pk2"; 880 nvidia,function = "rsvd1"; 881 nvidia,pull = <TEGRA_PIN_PULL_UP>; 882 nvidia,tristate = <TEGRA_PIN_ENABLE>; 883 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 884 }; 885 886 /* MCU_INT2# */ 887 pj2 { 888 nvidia,pins = "pj2"; 889 nvidia,function = "rsvd1"; 890 nvidia,pull = <TEGRA_PIN_PULL_UP>; 891 nvidia,tristate = <TEGRA_PIN_ENABLE>; 892 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 893 }; 894 895 /* MCU_INT3# */ 896 pi5 { 897 nvidia,pins = "pi5"; 898 nvidia,function = "rsvd2"; 899 nvidia,pull = <TEGRA_PIN_PULL_UP>; 900 nvidia,tristate = <TEGRA_PIN_ENABLE>; 901 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 902 }; 903 904 /* MCU_INT4# */ 905 pj0 { 906 nvidia,pins = "pj0"; 907 nvidia,function = "rsvd1"; 908 nvidia,pull = <TEGRA_PIN_PULL_UP>; 909 nvidia,tristate = <TEGRA_PIN_ENABLE>; 910 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 911 }; 912 913 /* MCU_RESET */ 914 pbb6 { 915 nvidia,pins = "pbb6"; 916 nvidia,function = "rsvd2"; 917 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 918 nvidia,tristate = <TEGRA_PIN_DISABLE>; 919 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 920 }; 921 922 /* MCU SPI */ 923 gpio-x4-aud-px4 { 924 nvidia,pins = "gpio_x4_aud_px4"; 925 nvidia,function = "spi2"; 926 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 927 nvidia,tristate = <TEGRA_PIN_DISABLE>; 928 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 929 }; 930 gpio-x5-aud-px5 { 931 nvidia,pins = "gpio_x5_aud_px5"; 932 nvidia,function = "spi2"; 933 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 934 nvidia,tristate = <TEGRA_PIN_DISABLE>; 935 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 936 }; 937 gpio-x6-aud-px6 { /* MCU_CS */ 938 nvidia,pins = "gpio_x6_aud_px6"; 939 nvidia,function = "spi2"; 940 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 941 nvidia,tristate = <TEGRA_PIN_DISABLE>; 942 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 943 }; 944 gpio-x7-aud-px7 { 945 nvidia,pins = "gpio_x7_aud_px7"; 946 nvidia,function = "spi2"; 947 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 948 nvidia,tristate = <TEGRA_PIN_ENABLE>; 949 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 950 }; 951 gpio-w2-aud-pw2 { /* MCU_CSEZP */ 952 nvidia,pins = "gpio_w2_aud_pw2"; 953 nvidia,function = "spi2"; 954 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 955 nvidia,tristate = <TEGRA_PIN_DISABLE>; 956 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 957 }; 958 959 /* PMIC_CLK_32K */ 960 clk-32k-in { 961 nvidia,pins = "clk_32k_in"; 962 nvidia,function = "clk"; 963 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 964 nvidia,tristate = <TEGRA_PIN_ENABLE>; 965 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 966 }; 967 968 /* PMIC_CPU_OC_INT */ 969 clk-32k-out-pa0 { 970 nvidia,pins = "clk_32k_out_pa0"; 971 nvidia,function = "soc"; 972 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 973 nvidia,tristate = <TEGRA_PIN_ENABLE>; 974 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 975 }; 976 977 /* PWR_I2C */ 978 pwr-i2c-scl-pz6 { 979 nvidia,pins = "pwr_i2c_scl_pz6"; 980 nvidia,function = "i2cpwr"; 981 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 982 nvidia,tristate = <TEGRA_PIN_DISABLE>; 983 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 984 nvidia,open-drain = <TEGRA_PIN_ENABLE>; 985 }; 986 pwr-i2c-sda-pz7 { 987 nvidia,pins = "pwr_i2c_sda_pz7"; 988 nvidia,function = "i2cpwr"; 989 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 990 nvidia,tristate = <TEGRA_PIN_DISABLE>; 991 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 992 nvidia,open-drain = <TEGRA_PIN_ENABLE>; 993 }; 994 995 /* PWR_INT_N */ 996 pwr-int-n { 997 nvidia,pins = "pwr_int_n"; 998 nvidia,function = "pmi"; 999 nvidia,pull = <TEGRA_PIN_PULL_UP>; 1000 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1001 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1002 }; 1003 1004 /* RESET_MOCI_CTRL */ 1005 pu4 { 1006 nvidia,pins = "pu4"; 1007 nvidia,function = "gmi"; 1008 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1009 nvidia,tristate = <TEGRA_PIN_DISABLE>; 1010 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1011 }; 1012 1013 /* RESET_OUT_N */ 1014 reset-out-n { 1015 nvidia,pins = "reset_out_n"; 1016 nvidia,function = "reset_out_n"; 1017 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1018 nvidia,tristate = <TEGRA_PIN_DISABLE>; 1019 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1020 }; 1021 1022 /* SHIFT_CTRL_DIR_IN */ 1023 kb-row0-pr0 { 1024 nvidia,pins = "kb_row0_pr0"; 1025 nvidia,function = "rsvd2"; 1026 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1027 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1028 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1029 }; 1030 kb-row1-pr1 { 1031 nvidia,pins = "kb_row1_pr1"; 1032 nvidia,function = "rsvd2"; 1033 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1034 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1035 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1036 }; 1037 1038 /* Configure level-shifter as output for HDA */ 1039 kb-row11-ps3 { 1040 nvidia,pins = "kb_row11_ps3"; 1041 nvidia,function = "rsvd2"; 1042 nvidia,pull = <TEGRA_PIN_PULL_UP>; 1043 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1044 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1045 }; 1046 1047 /* SHIFT_CTRL_DIR_OUT */ 1048 kb-col5-pq5 { 1049 nvidia,pins = "kb_col5_pq5"; 1050 nvidia,function = "rsvd2"; 1051 nvidia,pull = <TEGRA_PIN_PULL_UP>; 1052 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1053 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1054 }; 1055 kb-col6-pq6 { 1056 nvidia,pins = "kb_col6_pq6"; 1057 nvidia,function = "rsvd2"; 1058 nvidia,pull = <TEGRA_PIN_PULL_UP>; 1059 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1060 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1061 }; 1062 kb-col7-pq7 { 1063 nvidia,pins = "kb_col7_pq7"; 1064 nvidia,function = "rsvd2"; 1065 nvidia,pull = <TEGRA_PIN_PULL_UP>; 1066 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1067 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1068 }; 1069 1070 /* SHIFT_CTRL_OE */ 1071 kb-col0-pq0 { 1072 nvidia,pins = "kb_col0_pq0"; 1073 nvidia,function = "rsvd2"; 1074 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1075 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1076 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1077 }; 1078 kb-col1-pq1 { 1079 nvidia,pins = "kb_col1_pq1"; 1080 nvidia,function = "rsvd2"; 1081 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1082 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1083 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1084 }; 1085 kb-col2-pq2 { 1086 nvidia,pins = "kb_col2_pq2"; 1087 nvidia,function = "rsvd2"; 1088 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1089 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1090 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1091 }; 1092 kb-col4-pq4 { 1093 nvidia,pins = "kb_col4_pq4"; 1094 nvidia,function = "kbc"; 1095 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1096 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1097 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1098 }; 1099 kb-row2-pr2 { 1100 nvidia,pins = "kb_row2_pr2"; 1101 nvidia,function = "rsvd2"; 1102 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1103 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1104 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1105 }; 1106 1107 /* GPIO_PI6 aka TMP451 ALERT#/THERM2# */ 1108 pi6 { 1109 nvidia,pins = "pi6"; 1110 nvidia,function = "rsvd1"; 1111 nvidia,pull = <TEGRA_PIN_PULL_UP>; 1112 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1113 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1114 }; 1115 1116 /* TOUCH_INT */ 1117 gpio-w3-aud-pw3 { 1118 nvidia,pins = "gpio_w3_aud_pw3"; 1119 nvidia,function = "spi6"; 1120 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1121 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1122 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1123 }; 1124 1125 pc7 { /* NC */ 1126 nvidia,pins = "pc7"; 1127 nvidia,function = "rsvd1"; 1128 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1129 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1130 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1131 }; 1132 pg0 { /* NC */ 1133 nvidia,pins = "pg0"; 1134 nvidia,function = "rsvd1"; 1135 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1136 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1137 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1138 }; 1139 pg1 { /* NC */ 1140 nvidia,pins = "pg1"; 1141 nvidia,function = "rsvd1"; 1142 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1143 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1144 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1145 }; 1146 pg2 { /* NC */ 1147 nvidia,pins = "pg2"; 1148 nvidia,function = "rsvd1"; 1149 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1150 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1151 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1152 }; 1153 pg3 { /* NC */ 1154 nvidia,pins = "pg3"; 1155 nvidia,function = "rsvd1"; 1156 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1157 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1158 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1159 }; 1160 pg4 { /* NC */ 1161 nvidia,pins = "pg4"; 1162 nvidia,function = "rsvd1"; 1163 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1164 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1165 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1166 }; 1167 ph4 { /* NC */ 1168 nvidia,pins = "ph4"; 1169 nvidia,function = "rsvd2"; 1170 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1171 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1172 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1173 }; 1174 ph5 { /* NC */ 1175 nvidia,pins = "ph5"; 1176 nvidia,function = "rsvd2"; 1177 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1178 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1179 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1180 }; 1181 ph6 { /* NC */ 1182 nvidia,pins = "ph6"; 1183 nvidia,function = "gmi"; 1184 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1185 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1186 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1187 }; 1188 ph7 { /* NC */ 1189 nvidia,pins = "ph7"; 1190 nvidia,function = "gmi"; 1191 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1192 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1193 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1194 }; 1195 pi0 { /* NC */ 1196 nvidia,pins = "pi0"; 1197 nvidia,function = "rsvd1"; 1198 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1199 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1200 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1201 }; 1202 pi1 { /* NC */ 1203 nvidia,pins = "pi1"; 1204 nvidia,function = "rsvd1"; 1205 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1206 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1207 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1208 }; 1209 pi2 { /* NC */ 1210 nvidia,pins = "pi2"; 1211 nvidia,function = "rsvd4"; 1212 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1213 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1214 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1215 }; 1216 pi4 { /* NC */ 1217 nvidia,pins = "pi4"; 1218 nvidia,function = "gmi"; 1219 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1220 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1221 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1222 }; 1223 pi7 { /* NC */ 1224 nvidia,pins = "pi7"; 1225 nvidia,function = "rsvd1"; 1226 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1227 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1228 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1229 }; 1230 pk0 { /* NC */ 1231 nvidia,pins = "pk0"; 1232 nvidia,function = "rsvd1"; 1233 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1234 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1235 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1236 }; 1237 pk1 { /* NC */ 1238 nvidia,pins = "pk1"; 1239 nvidia,function = "rsvd4"; 1240 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1241 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1242 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1243 }; 1244 pk3 { /* NC */ 1245 nvidia,pins = "pk3"; 1246 nvidia,function = "gmi"; 1247 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1248 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1249 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1250 }; 1251 pk4 { /* NC */ 1252 nvidia,pins = "pk4"; 1253 nvidia,function = "rsvd2"; 1254 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1255 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1256 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1257 }; 1258 dap1-fs-pn0 { /* NC */ 1259 nvidia,pins = "dap1_fs_pn0"; 1260 nvidia,function = "rsvd4"; 1261 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1262 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1263 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1264 }; 1265 dap1-din-pn1 { /* NC */ 1266 nvidia,pins = "dap1_din_pn1"; 1267 nvidia,function = "rsvd4"; 1268 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1269 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1270 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1271 }; 1272 dap1-sclk-pn3 { /* NC */ 1273 nvidia,pins = "dap1_sclk_pn3"; 1274 nvidia,function = "rsvd4"; 1275 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1276 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1277 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1278 }; 1279 ulpi-data7-po0 { /* NC */ 1280 nvidia,pins = "ulpi_data7_po0"; 1281 nvidia,function = "ulpi"; 1282 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1283 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1284 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1285 }; 1286 ulpi-data0-po1 { /* NC */ 1287 nvidia,pins = "ulpi_data0_po1"; 1288 nvidia,function = "ulpi"; 1289 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1290 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1291 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1292 }; 1293 ulpi-data1-po2 { /* NC */ 1294 nvidia,pins = "ulpi_data1_po2"; 1295 nvidia,function = "ulpi"; 1296 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1297 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1298 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1299 }; 1300 ulpi-data2-po3 { /* NC */ 1301 nvidia,pins = "ulpi_data2_po3"; 1302 nvidia,function = "ulpi"; 1303 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1304 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1305 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1306 }; 1307 ulpi-data3-po4 { /* NC */ 1308 nvidia,pins = "ulpi_data3_po4"; 1309 nvidia,function = "ulpi"; 1310 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1311 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1312 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1313 }; 1314 ulpi-data6-po7 { /* NC */ 1315 nvidia,pins = "ulpi_data6_po7"; 1316 nvidia,function = "ulpi"; 1317 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1318 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1319 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1320 }; 1321 dap4-fs-pp4 { /* NC */ 1322 nvidia,pins = "dap4_fs_pp4"; 1323 nvidia,function = "rsvd4"; 1324 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1325 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1326 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1327 }; 1328 dap4-din-pp5 { /* NC */ 1329 nvidia,pins = "dap4_din_pp5"; 1330 nvidia,function = "rsvd3"; 1331 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1332 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1333 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1334 }; 1335 dap4-dout-pp6 { /* NC */ 1336 nvidia,pins = "dap4_dout_pp6"; 1337 nvidia,function = "rsvd4"; 1338 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1339 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1340 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1341 }; 1342 dap4-sclk-pp7 { /* NC */ 1343 nvidia,pins = "dap4_sclk_pp7"; 1344 nvidia,function = "rsvd3"; 1345 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1346 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1347 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1348 }; 1349 kb-col3-pq3 { /* NC */ 1350 nvidia,pins = "kb_col3_pq3"; 1351 nvidia,function = "kbc"; 1352 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1353 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1354 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1355 }; 1356 kb-row3-pr3 { /* NC */ 1357 nvidia,pins = "kb_row3_pr3"; 1358 nvidia,function = "kbc"; 1359 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1360 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1361 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1362 }; 1363 kb-row4-pr4 { /* NC */ 1364 nvidia,pins = "kb_row4_pr4"; 1365 nvidia,function = "rsvd3"; 1366 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1367 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1368 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1369 }; 1370 kb-row5-pr5 { /* NC */ 1371 nvidia,pins = "kb_row5_pr5"; 1372 nvidia,function = "rsvd3"; 1373 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1374 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1375 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1376 }; 1377 kb-row6-pr6 { /* NC */ 1378 nvidia,pins = "kb_row6_pr6"; 1379 nvidia,function = "kbc"; 1380 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1381 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1382 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1383 }; 1384 kb-row7-pr7 { /* NC */ 1385 nvidia,pins = "kb_row7_pr7"; 1386 nvidia,function = "rsvd2"; 1387 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1388 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1389 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1390 }; 1391 kb-row8-ps0 { /* NC */ 1392 nvidia,pins = "kb_row8_ps0"; 1393 nvidia,function = "rsvd2"; 1394 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1395 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1396 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1397 }; 1398 kb-row9-ps1 { /* NC */ 1399 nvidia,pins = "kb_row9_ps1"; 1400 nvidia,function = "rsvd2"; 1401 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1402 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1403 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1404 }; 1405 kb-row12-ps4 { /* NC */ 1406 nvidia,pins = "kb_row12_ps4"; 1407 nvidia,function = "rsvd2"; 1408 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1409 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1410 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1411 }; 1412 kb-row13-ps5 { /* NC */ 1413 nvidia,pins = "kb_row13_ps5"; 1414 nvidia,function = "rsvd2"; 1415 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1416 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1417 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1418 }; 1419 kb-row14-ps6 { /* NC */ 1420 nvidia,pins = "kb_row14_ps6"; 1421 nvidia,function = "rsvd2"; 1422 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1423 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1424 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1425 }; 1426 kb-row15-ps7 { /* NC */ 1427 nvidia,pins = "kb_row15_ps7"; 1428 nvidia,function = "rsvd3"; 1429 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1430 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1431 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1432 }; 1433 kb-row16-pt0 { /* NC */ 1434 nvidia,pins = "kb_row16_pt0"; 1435 nvidia,function = "rsvd2"; 1436 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1437 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1438 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1439 }; 1440 kb-row17-pt1 { /* NC */ 1441 nvidia,pins = "kb_row17_pt1"; 1442 nvidia,function = "rsvd2"; 1443 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1444 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1445 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1446 }; 1447 pu5 { /* NC */ 1448 nvidia,pins = "pu5"; 1449 nvidia,function = "gmi"; 1450 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1451 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1452 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1453 }; 1454 /* 1455 * PCB Version Indication: V1.2 and later have GPIO_PV0 1456 * wired to GND, was NC before 1457 */ 1458 pv0 { 1459 nvidia,pins = "pv0"; 1460 nvidia,function = "rsvd1"; 1461 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1462 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1463 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1464 }; 1465 pv1 { /* NC */ 1466 nvidia,pins = "pv1"; 1467 nvidia,function = "rsvd1"; 1468 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1469 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1470 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1471 }; 1472 gpio-x1-aud-px1 { /* NC */ 1473 nvidia,pins = "gpio_x1_aud_px1"; 1474 nvidia,function = "rsvd2"; 1475 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1476 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1477 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1478 }; 1479 gpio-x3-aud-px3 { /* NC */ 1480 nvidia,pins = "gpio_x3_aud_px3"; 1481 nvidia,function = "rsvd4"; 1482 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1483 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1484 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1485 }; 1486 pbb7 { /* NC */ 1487 nvidia,pins = "pbb7"; 1488 nvidia,function = "rsvd2"; 1489 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1490 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1491 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1492 }; 1493 pcc1 { /* NC */ 1494 nvidia,pins = "pcc1"; 1495 nvidia,function = "rsvd2"; 1496 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1497 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1498 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1499 }; 1500 pcc2 { /* NC */ 1501 nvidia,pins = "pcc2"; 1502 nvidia,function = "rsvd2"; 1503 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1504 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1505 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1506 }; 1507 clk3-req-pee1 { /* NC */ 1508 nvidia,pins = "clk3_req_pee1"; 1509 nvidia,function = "rsvd2"; 1510 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1511 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1512 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1513 }; 1514 dap-mclk1-req-pee2 { /* NC */ 1515 nvidia,pins = "dap_mclk1_req_pee2"; 1516 nvidia,function = "rsvd4"; 1517 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1518 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1519 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1520 }; 1521 /* 1522 * Leave SDMMC3_CLK_LB_OUT muxed as SDMMC3 with output 1523 * driver enabled aka not tristated and input driver 1524 * enabled as well as it features some magic properties 1525 * even though the external loopback is disabled and the 1526 * internal loopback used as per 1527 * SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1 1528 * bits being set to 0xfffd according to the TRM! 1529 */ 1530 sdmmc3-clk-lb-out-pee4 { /* NC */ 1531 nvidia,pins = "sdmmc3_clk_lb_out_pee4"; 1532 nvidia,function = "sdmmc3"; 1533 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1534 nvidia,tristate = <TEGRA_PIN_DISABLE>; 1535 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1536 }; 1537 }; 1538 }; 1539 1540 serial@70006040 { 1541 compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; 1542 }; 1543 1544 serial@70006200 { 1545 compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; 1546 }; 1547 1548 serial@70006300 { 1549 compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; 1550 }; 1551 1552 hdmi_ddc: i2c@7000c700 { 1553 clock-frequency = <10000>; 1554 }; 1555 1556 /* PWR_I2C: power I2C to audio codec, PMIC and temperature sensor */ 1557 i2c@7000d000 { 1558 status = "okay"; 1559 clock-frequency = <400000>; 1560 1561 /* SGTL5000 audio codec */ 1562 sgtl5000: codec@a { 1563 compatible = "fsl,sgtl5000"; 1564 reg = <0x0a>; 1565 #sound-dai-cells = <0>; 1566 VDDA-supply = <®_module_3v3_audio>; 1567 VDDD-supply = <®_1v8_vddio>; 1568 VDDIO-supply = <®_1v8_vddio>; 1569 clocks = <&tegra_car TEGRA124_CLK_EXTERN1>; 1570 }; 1571 1572 pmic: pmic@40 { 1573 compatible = "ams,as3722"; 1574 reg = <0x40>; 1575 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; 1576 ams,system-power-controller; 1577 #interrupt-cells = <2>; 1578 interrupt-controller; 1579 gpio-controller; 1580 #gpio-cells = <2>; 1581 pinctrl-names = "default"; 1582 pinctrl-0 = <&as3722_default>; 1583 1584 as3722_default: pinmux { 1585 gpio2-7 { 1586 pins = "gpio2", /* PWR_EN_+V3.3 */ 1587 "gpio7"; /* +V1.6_LPO */ 1588 function = "gpio"; 1589 bias-pull-up; 1590 }; 1591 1592 gpio0-1-3-4-5-6 { 1593 pins = "gpio0", "gpio1", "gpio3", 1594 "gpio4", "gpio5", "gpio6"; 1595 bias-high-impedance; 1596 }; 1597 }; 1598 1599 regulators { 1600 vsup-sd2-supply = <®_module_3v3>; 1601 vsup-sd3-supply = <®_module_3v3>; 1602 vsup-sd4-supply = <®_module_3v3>; 1603 vsup-sd5-supply = <®_module_3v3>; 1604 vin-ldo0-supply = <®_1v35_vddio_ddr>; 1605 vin-ldo1-6-supply = <®_module_3v3>; 1606 vin-ldo2-5-7-supply = <®_1v8_vddio>; 1607 vin-ldo3-4-supply = <®_module_3v3>; 1608 vin-ldo9-10-supply = <®_module_3v3>; 1609 vin-ldo11-supply = <®_module_3v3>; 1610 1611 reg_vdd_cpu: sd0 { 1612 regulator-name = "+VDD_CPU_AP"; 1613 regulator-min-microvolt = <700000>; 1614 regulator-max-microvolt = <1400000>; 1615 regulator-min-microamp = <3500000>; 1616 regulator-max-microamp = <3500000>; 1617 regulator-always-on; 1618 regulator-boot-on; 1619 ams,ext-control = <2>; 1620 }; 1621 1622 sd1 { 1623 regulator-name = "+VDD_CORE"; 1624 regulator-min-microvolt = <700000>; 1625 regulator-max-microvolt = <1350000>; 1626 regulator-min-microamp = <2500000>; 1627 regulator-max-microamp = <4000000>; 1628 regulator-always-on; 1629 regulator-boot-on; 1630 ams,ext-control = <1>; 1631 }; 1632 1633 reg_1v35_vddio_ddr: sd2 { 1634 regulator-name = 1635 "+V1.35_VDDIO_DDR(sd2)"; 1636 regulator-min-microvolt = <1350000>; 1637 regulator-max-microvolt = <1350000>; 1638 regulator-always-on; 1639 regulator-boot-on; 1640 }; 1641 1642 sd3 { 1643 regulator-name = 1644 "+V1.35_VDDIO_DDR(sd3)"; 1645 regulator-min-microvolt = <1350000>; 1646 regulator-max-microvolt = <1350000>; 1647 regulator-always-on; 1648 regulator-boot-on; 1649 }; 1650 1651 reg_1v05_vdd: sd4 { 1652 regulator-name = "+V1.05"; 1653 regulator-min-microvolt = <1050000>; 1654 regulator-max-microvolt = <1050000>; 1655 }; 1656 1657 reg_1v8_vddio: sd5 { 1658 regulator-name = "+V1.8"; 1659 regulator-min-microvolt = <1800000>; 1660 regulator-max-microvolt = <1800000>; 1661 regulator-boot-on; 1662 regulator-always-on; 1663 }; 1664 1665 reg_vdd_gpu: sd6 { 1666 regulator-name = "+VDD_GPU_AP"; 1667 regulator-min-microvolt = <650000>; 1668 regulator-max-microvolt = <1200000>; 1669 regulator-min-microamp = <3500000>; 1670 regulator-max-microamp = <3500000>; 1671 regulator-boot-on; 1672 regulator-always-on; 1673 }; 1674 1675 reg_1v05_avdd: ldo0 { 1676 regulator-name = "+V1.05_AVDD"; 1677 regulator-min-microvolt = <1050000>; 1678 regulator-max-microvolt = <1050000>; 1679 regulator-boot-on; 1680 regulator-always-on; 1681 ams,ext-control = <1>; 1682 }; 1683 1684 vddio_sdmmc1: ldo1 { 1685 regulator-name = "VDDIO_SDMMC1"; 1686 regulator-min-microvolt = <1800000>; 1687 regulator-max-microvolt = <3300000>; 1688 }; 1689 1690 ldo2 { 1691 regulator-name = "+V1.2"; 1692 regulator-min-microvolt = <1200000>; 1693 regulator-max-microvolt = <1200000>; 1694 regulator-boot-on; 1695 regulator-always-on; 1696 }; 1697 1698 ldo3 { 1699 regulator-name = "+V1.05_RTC"; 1700 regulator-min-microvolt = <1000000>; 1701 regulator-max-microvolt = <1000000>; 1702 regulator-boot-on; 1703 regulator-always-on; 1704 ams,enable-tracking; 1705 }; 1706 1707 /* 1.8V for LVDS, 3.3V for eDP */ 1708 ldo4 { 1709 regulator-name = "AVDD_LVDS0_PLL"; 1710 regulator-min-microvolt = <1800000>; 1711 regulator-max-microvolt = <1800000>; 1712 }; 1713 1714 /* LDO5 not used */ 1715 1716 vddio_sdmmc3: ldo6 { 1717 regulator-name = "VDDIO_SDMMC3"; 1718 regulator-min-microvolt = <1800000>; 1719 regulator-max-microvolt = <3300000>; 1720 }; 1721 1722 /* LDO7 not used */ 1723 1724 ldo9 { 1725 regulator-name = "+V3.3_ETH(ldo9)"; 1726 regulator-min-microvolt = <3300000>; 1727 regulator-max-microvolt = <3300000>; 1728 regulator-always-on; 1729 }; 1730 1731 ldo10 { 1732 regulator-name = "+V3.3_ETH(ldo10)"; 1733 regulator-min-microvolt = <3300000>; 1734 regulator-max-microvolt = <3300000>; 1735 regulator-always-on; 1736 }; 1737 1738 ldo11 { 1739 regulator-name = "+V1.8_VPP_FUSE"; 1740 regulator-min-microvolt = <1800000>; 1741 regulator-max-microvolt = <1800000>; 1742 }; 1743 }; 1744 }; 1745 1746 /* 1747 * TMP451 temperature sensor 1748 * Note: THERM_N directly connected to AS3722 PMIC THERM 1749 */ 1750 temp-sensor@4c { 1751 compatible = "ti,tmp451"; 1752 reg = <0x4c>; 1753 interrupt-parent = <&gpio>; 1754 interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_LEVEL_LOW>; 1755 #thermal-sensor-cells = <1>; 1756 vcc-supply = <®_module_3v3>; 1757 }; 1758 }; 1759 1760 /* SPI2: MCU SPI */ 1761 spi@7000d600 { 1762 status = "okay"; 1763 spi-max-frequency = <25000000>; 1764 }; 1765 1766 pmc@7000e400 { 1767 nvidia,invert-interrupt; 1768 nvidia,suspend-mode = <1>; 1769 nvidia,cpu-pwr-good-time = <500>; 1770 nvidia,cpu-pwr-off-time = <300>; 1771 nvidia,core-pwr-good-time = <641 3845>; 1772 nvidia,core-pwr-off-time = <61036>; 1773 nvidia,core-power-req-active-high; 1774 nvidia,sys-clock-req-active-high; 1775 1776 /* Set power_off bit in ResetControl register of AS3722 PMIC */ 1777 i2c-thermtrip { 1778 nvidia,i2c-controller-id = <4>; 1779 nvidia,bus-addr = <0x40>; 1780 nvidia,reg-addr = <0x36>; 1781 nvidia,reg-data = <0x2>; 1782 }; 1783 }; 1784 1785 sata@70020000 { 1786 phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>; 1787 phy-names = "sata-0"; 1788 avdd-supply = <®_1v05_vdd>; 1789 hvdd-supply = <®_module_3v3>; 1790 vddio-supply = <®_1v05_vdd>; 1791 }; 1792 1793 usb@70090000 { 1794 /* USBO1, USBO1 (SS), USBH2, USBH4 and USBH4 (SS) */ 1795 phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, 1796 <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>, 1797 <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>, 1798 <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, 1799 <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>; 1800 phy-names = "usb2-0", "usb3-1", "usb2-1", "usb2-2", "usb3-0"; 1801 1802 avddio-pex-supply = <®_1v05_vdd>; 1803 avdd-pll-erefe-supply = <®_1v05_avdd>; 1804 avdd-pll-utmip-supply = <®_1v8_vddio>; 1805 avdd-usb-ss-pll-supply = <®_1v05_vdd>; 1806 avdd-usb-supply = <®_module_3v3>; 1807 dvddio-pex-supply = <®_1v05_vdd>; 1808 hvdd-usb-ss-pll-e-supply = <®_module_3v3>; 1809 hvdd-usb-ss-supply = <®_module_3v3>; 1810 }; 1811 1812 padctl@7009f000 { 1813 avdd-pll-utmip-supply = <®_1v8_vddio>; 1814 avdd-pll-erefe-supply = <®_1v05_avdd>; 1815 avdd-pex-pll-supply = <®_1v05_vdd>; 1816 hvdd-pex-pll-e-supply = <®_module_3v3>; 1817 1818 pads { 1819 usb2 { 1820 status = "okay"; 1821 1822 lanes { 1823 usb2-0 { 1824 status = "okay"; 1825 nvidia,function = "xusb"; 1826 }; 1827 1828 usb2-1 { 1829 status = "okay"; 1830 nvidia,function = "xusb"; 1831 }; 1832 1833 usb2-2 { 1834 status = "okay"; 1835 nvidia,function = "xusb"; 1836 }; 1837 }; 1838 }; 1839 1840 pcie { 1841 status = "okay"; 1842 1843 lanes { 1844 pcie-0 { 1845 status = "okay"; 1846 nvidia,function = "usb3-ss"; 1847 }; 1848 1849 pcie-1 { 1850 status = "okay"; 1851 nvidia,function = "usb3-ss"; 1852 }; 1853 1854 pcie-2 { 1855 status = "okay"; 1856 nvidia,function = "pcie"; 1857 }; 1858 1859 pcie-3 { 1860 status = "okay"; 1861 nvidia,function = "pcie"; 1862 }; 1863 1864 pcie-4 { 1865 status = "okay"; 1866 nvidia,function = "pcie"; 1867 }; 1868 }; 1869 }; 1870 1871 sata { 1872 status = "okay"; 1873 1874 lanes { 1875 sata-0 { 1876 status = "okay"; 1877 nvidia,function = "sata"; 1878 }; 1879 }; 1880 }; 1881 }; 1882 1883 ports { 1884 /* USBO1 */ 1885 usb2-0 { 1886 status = "okay"; 1887 mode = "otg"; 1888 vbus-supply = <®_usbo1_vbus>; 1889 }; 1890 1891 /* USBH2 */ 1892 usb2-1 { 1893 status = "okay"; 1894 mode = "host"; 1895 vbus-supply = <®_usbh_vbus>; 1896 }; 1897 1898 /* USBH4 */ 1899 usb2-2 { 1900 status = "okay"; 1901 mode = "host"; 1902 vbus-supply = <®_usbh_vbus>; 1903 }; 1904 1905 usb3-0 { 1906 status = "okay"; 1907 nvidia,usb2-companion = <2>; 1908 vbus-supply = <®_usbh_vbus>; 1909 }; 1910 1911 usb3-1 { 1912 status = "okay"; 1913 nvidia,usb2-companion = <0>; 1914 vbus-supply = <®_usbo1_vbus>; 1915 }; 1916 }; 1917 }; 1918 1919 /* eMMC */ 1920 mmc@700b0600 { 1921 status = "okay"; 1922 bus-width = <8>; 1923 non-removable; 1924 vmmc-supply = <®_module_3v3>; /* VCC */ 1925 vqmmc-supply = <®_1v8_vddio>; /* VCCQ */ 1926 mmc-ddr-1_8v; 1927 }; 1928 1929 /* CPU DFLL clock */ 1930 clock@70110000 { 1931 status = "okay"; 1932 nvidia,i2c-fs-rate = <400000>; 1933 vdd-cpu-supply = <®_vdd_cpu>; 1934 }; 1935 1936 ahub@70300000 { 1937 i2s@70301200 { 1938 status = "okay"; 1939 }; 1940 }; 1941 1942 clk32k_in: osc3 { 1943 compatible = "fixed-clock"; 1944 #clock-cells = <0>; 1945 clock-frequency = <32768>; 1946 }; 1947 1948 cpus { 1949 cpu@0 { 1950 vdd-cpu-supply = <®_vdd_cpu>; 1951 }; 1952 }; 1953 1954 reg_1v05_avdd_hdmi_pll: regulator-1v05-avdd-hdmi-pll { 1955 compatible = "regulator-fixed"; 1956 regulator-name = "+V1.05_AVDD_HDMI_PLL"; 1957 regulator-min-microvolt = <1050000>; 1958 regulator-max-microvolt = <1050000>; 1959 gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; 1960 vin-supply = <®_1v05_vdd>; 1961 }; 1962 1963 reg_3v3_mxm: regulator-3v3-mxm { 1964 compatible = "regulator-fixed"; 1965 regulator-name = "+V3.3_MXM"; 1966 regulator-min-microvolt = <3300000>; 1967 regulator-max-microvolt = <3300000>; 1968 regulator-always-on; 1969 regulator-boot-on; 1970 }; 1971 1972 reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi { 1973 compatible = "regulator-fixed"; 1974 regulator-name = "+V3.3_AVDD_HDMI"; 1975 regulator-min-microvolt = <3300000>; 1976 regulator-max-microvolt = <3300000>; 1977 vin-supply = <®_1v05_vdd>; 1978 }; 1979 1980 reg_module_3v3: regulator-module-3v3 { 1981 compatible = "regulator-fixed"; 1982 regulator-name = "+V3.3"; 1983 regulator-min-microvolt = <3300000>; 1984 regulator-max-microvolt = <3300000>; 1985 regulator-always-on; 1986 regulator-boot-on; 1987 /* PWR_EN_+V3.3 */ 1988 gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; 1989 enable-active-high; 1990 vin-supply = <®_3v3_mxm>; 1991 }; 1992 1993 reg_module_3v3_audio: regulator-module-3v3-audio { 1994 compatible = "regulator-fixed"; 1995 regulator-name = "+V3.3_AUDIO_AVDD_S"; 1996 regulator-min-microvolt = <3300000>; 1997 regulator-max-microvolt = <3300000>; 1998 regulator-always-on; 1999 }; 2000 2001 sound { 2002 compatible = "toradex,tegra-audio-sgtl5000-apalis_tk1", 2003 "nvidia,tegra-audio-sgtl5000"; 2004 nvidia,model = "Toradex Apalis TK1"; 2005 nvidia,audio-routing = 2006 "Headphone Jack", "HP_OUT", 2007 "LINE_IN", "Line In Jack", 2008 "MIC_IN", "Mic Jack"; 2009 nvidia,i2s-controller = <&tegra_i2s2>; 2010 nvidia,audio-codec = <&sgtl5000>; 2011 clocks = <&tegra_car TEGRA124_CLK_PLL_A>, 2012 <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, 2013 <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; 2014 clock-names = "pll_a", "pll_a_out0", "mclk"; 2015 2016 assigned-clocks = <&tegra_car TEGRA124_CLK_EXTERN1>, 2017 <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; 2018 2019 assigned-clock-parents = <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, 2020 <&tegra_car TEGRA124_CLK_EXTERN1>; 2021 }; 2022 2023 thermal-zones { 2024 cpu { 2025 trips { 2026 cpu-shutdown-trip { 2027 temperature = <101000>; 2028 hysteresis = <0>; 2029 type = "critical"; 2030 }; 2031 }; 2032 }; 2033 2034 mem { 2035 trips { 2036 mem-shutdown-trip { 2037 temperature = <101000>; 2038 hysteresis = <0>; 2039 type = "critical"; 2040 }; 2041 }; 2042 }; 2043 2044 gpu { 2045 trips { 2046 gpu-shutdown-trip { 2047 temperature = <101000>; 2048 hysteresis = <0>; 2049 type = "critical"; 2050 }; 2051 }; 2052 }; 2053 }; 2054}; 2055 2056&gpio { 2057 /* I210 Gigabit Ethernet Controller Reset */ 2058 lan-reset-n { 2059 gpio-hog; 2060 gpios = <TEGRA_GPIO(S, 2) GPIO_ACTIVE_HIGH>; 2061 output-high; 2062 line-name = "LAN_RESET_N"; 2063 }; 2064 2065 /* Control MXM3 pin 26 Reset Module Output Carrier Input */ 2066 reset-moci-ctrl { 2067 gpio-hog; 2068 gpios = <TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>; 2069 output-high; 2070 line-name = "RESET_MOCI_CTRL"; 2071 }; 2072}; 2073