1// SPDX-License-Identifier: GPL-2.0
2/dts-v1/;
3
4#include <dt-bindings/input/input.h>
5#include "tegra20.dtsi"
6#include "tegra20-cpu-opp.dtsi"
7#include "tegra20-cpu-opp-microvolt.dtsi"
8
9/ {
10	model = "Toshiba AC100 / Dynabook AZ";
11	compatible = "compal,paz00", "nvidia,tegra20";
12
13	aliases {
14		rtc0 = "/i2c@7000d000/tps6586x@34";
15		rtc1 = "/rtc@7000e000";
16		serial0 = &uarta;
17		serial1 = &uartc;
18	};
19
20	chosen {
21		stdout-path = "serial0:115200n8";
22	};
23
24	memory@0 {
25		reg = <0x00000000 0x20000000>;
26	};
27
28	host1x@50000000 {
29		dc@54200000 {
30			rgb {
31				status = "okay";
32
33				nvidia,panel = <&panel>;
34			};
35		};
36
37		hdmi@54280000 {
38			status = "okay";
39
40			vdd-supply = <&hdmi_vdd_reg>;
41			pll-supply = <&hdmi_pll_reg>;
42
43			nvidia,ddc-i2c-bus = <&hdmi_ddc>;
44			nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
45				GPIO_ACTIVE_HIGH>;
46		};
47	};
48
49	pinmux@70000014 {
50		pinctrl-names = "default";
51		pinctrl-0 = <&state_default>;
52
53		state_default: pinmux {
54			ata {
55				nvidia,pins = "ata", "atc", "atd", "ate",
56					"dap2", "gmb", "gmc", "gmd", "spia",
57					"spib", "spic", "spid", "spie";
58				nvidia,function = "gmi";
59			};
60			atb {
61				nvidia,pins = "atb", "gma", "gme";
62				nvidia,function = "sdio4";
63			};
64			cdev1 {
65				nvidia,pins = "cdev1";
66				nvidia,function = "plla_out";
67			};
68			cdev2 {
69				nvidia,pins = "cdev2";
70				nvidia,function = "pllp_out4";
71			};
72			crtp {
73				nvidia,pins = "crtp";
74				nvidia,function = "crt";
75			};
76			csus {
77				nvidia,pins = "csus";
78				nvidia,function = "pllc_out1";
79			};
80			dap1 {
81				nvidia,pins = "dap1";
82				nvidia,function = "dap1";
83			};
84			dap3 {
85				nvidia,pins = "dap3";
86				nvidia,function = "dap3";
87			};
88			dap4 {
89				nvidia,pins = "dap4";
90				nvidia,function = "dap4";
91			};
92			ddc {
93				nvidia,pins = "ddc";
94				nvidia,function = "i2c2";
95			};
96			dta {
97				nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
98				nvidia,function = "rsvd1";
99			};
100			dtf {
101				nvidia,pins = "dtf";
102				nvidia,function = "i2c3";
103			};
104			gpu {
105				nvidia,pins = "gpu", "sdb", "sdd";
106				nvidia,function = "pwm";
107			};
108			gpu7 {
109				nvidia,pins = "gpu7";
110				nvidia,function = "rtck";
111			};
112			gpv {
113				nvidia,pins = "gpv", "slxa", "slxk";
114				nvidia,function = "pcie";
115			};
116			hdint {
117				nvidia,pins = "hdint", "pta";
118				nvidia,function = "hdmi";
119			};
120			i2cp {
121				nvidia,pins = "i2cp";
122				nvidia,function = "i2cp";
123			};
124			irrx {
125				nvidia,pins = "irrx", "irtx";
126				nvidia,function = "uarta";
127			};
128			kbca {
129				nvidia,pins = "kbca", "kbcc", "kbce", "kbcf";
130				nvidia,function = "kbc";
131			};
132			kbcb {
133				nvidia,pins = "kbcb", "kbcd";
134				nvidia,function = "sdio2";
135			};
136			lcsn {
137				nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
138					"ld3", "ld4", "ld5", "ld6", "ld7",
139					"ld8", "ld9", "ld10", "ld11", "ld12",
140					"ld13", "ld14", "ld15", "ld16", "ld17",
141					"ldc", "ldi", "lhp0", "lhp1", "lhp2",
142					"lhs", "lm0", "lm1", "lpp", "lpw0",
143					"lpw1", "lpw2", "lsc0", "lsc1", "lsck",
144					"lsda", "lsdi", "lspi", "lvp0", "lvp1",
145					"lvs";
146				nvidia,function = "displaya";
147			};
148			owc {
149				nvidia,pins = "owc";
150				nvidia,function = "owr";
151			};
152			pmc {
153				nvidia,pins = "pmc";
154				nvidia,function = "pwr_on";
155			};
156			rm {
157				nvidia,pins = "rm";
158				nvidia,function = "i2c1";
159			};
160			sdc {
161				nvidia,pins = "sdc";
162				nvidia,function = "twc";
163			};
164			sdio1 {
165				nvidia,pins = "sdio1";
166				nvidia,function = "sdio1";
167			};
168			slxc {
169				nvidia,pins = "slxc", "slxd";
170				nvidia,function = "spi4";
171			};
172			spdi {
173				nvidia,pins = "spdi", "spdo";
174				nvidia,function = "rsvd2";
175			};
176			spif {
177				nvidia,pins = "spif", "uac";
178				nvidia,function = "rsvd4";
179			};
180			spig {
181				nvidia,pins = "spig", "spih";
182				nvidia,function = "spi2_alt";
183			};
184			uaa {
185				nvidia,pins = "uaa", "uab", "uda";
186				nvidia,function = "ulpi";
187			};
188			uad {
189				nvidia,pins = "uad";
190				nvidia,function = "spdif";
191			};
192			uca {
193				nvidia,pins = "uca", "ucb";
194				nvidia,function = "uartc";
195			};
196			conf_ata {
197				nvidia,pins = "ata", "atb", "atc", "atd", "ate",
198					"cdev1", "cdev2", "dap1", "dap2", "dtf",
199					"gma", "gmb", "gmc", "gmd", "gme",
200					"gpu", "gpu7", "gpv", "i2cp", "pta",
201					"rm", "sdio1", "slxk", "spdo", "uac",
202					"uda";
203				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
204				nvidia,tristate = <TEGRA_PIN_DISABLE>;
205			};
206			conf_ck32 {
207				nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
208					"pmcc", "pmcd", "pmce", "xm2c", "xm2d";
209				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
210			};
211			conf_crtp {
212				nvidia,pins = "crtp", "dap3", "dap4", "dtb",
213					"dtc", "dte", "slxa", "slxc", "slxd",
214					"spdi";
215				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
216				nvidia,tristate = <TEGRA_PIN_ENABLE>;
217			};
218			conf_csus {
219				nvidia,pins = "csus", "spia", "spib", "spid",
220					"spif";
221				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
222				nvidia,tristate = <TEGRA_PIN_ENABLE>;
223			};
224			conf_ddc {
225				nvidia,pins = "ddc", "irrx", "irtx", "kbca",
226					"kbcb", "kbcc", "kbcd", "kbce", "kbcf",
227					"spic", "spig", "uaa", "uab";
228				nvidia,pull = <TEGRA_PIN_PULL_UP>;
229				nvidia,tristate = <TEGRA_PIN_DISABLE>;
230			};
231			conf_dta {
232				nvidia,pins = "dta", "dtd", "owc", "sdc", "sdd",
233					"spie", "spih", "uad", "uca", "ucb";
234				nvidia,pull = <TEGRA_PIN_PULL_UP>;
235				nvidia,tristate = <TEGRA_PIN_ENABLE>;
236			};
237			conf_hdint {
238				nvidia,pins = "hdint", "ld0", "ld1", "ld2",
239					"ld3", "ld4", "ld5", "ld6", "ld7",
240					"ld8", "ld9", "ld10", "ld11", "ld12",
241					"ld13", "ld14", "ld15", "ld16", "ld17",
242					"ldc", "ldi", "lhs", "lsc0", "lspi",
243					"lvs", "pmc";
244				nvidia,tristate = <TEGRA_PIN_DISABLE>;
245			};
246			conf_lc {
247				nvidia,pins = "lc", "ls";
248				nvidia,pull = <TEGRA_PIN_PULL_UP>;
249			};
250			conf_lcsn {
251				nvidia,pins = "lcsn", "lhp0", "lhp1", "lhp2",
252					"lm0", "lm1", "lpp", "lpw0", "lpw1",
253					"lpw2", "lsc1", "lsck", "lsda", "lsdi",
254					"lvp0", "lvp1", "sdb";
255				nvidia,tristate = <TEGRA_PIN_ENABLE>;
256			};
257			conf_ld17_0 {
258				nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
259					"ld23_22";
260				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
261			};
262		};
263	};
264
265	i2s@70002800 {
266		status = "okay";
267	};
268
269	serial@70006000 {
270		status = "okay";
271	};
272
273	serial@70006200 {
274		status = "okay";
275	};
276
277	pwm: pwm@7000a000 {
278		status = "okay";
279	};
280
281	lvds_ddc: i2c@7000c000 {
282		status = "okay";
283		clock-frequency = <400000>;
284
285		alc5632: alc5632@1e {
286			compatible = "realtek,alc5632";
287			reg = <0x1e>;
288			gpio-controller;
289			#gpio-cells = <2>;
290		};
291	};
292
293	hdmi_ddc: i2c@7000c400 {
294		status = "okay";
295		clock-frequency = <100000>;
296	};
297
298	nvec@7000c500 {
299		compatible = "nvidia,nvec";
300		reg = <0x7000c500 0x100>;
301		interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
302		#address-cells = <1>;
303		#size-cells = <0>;
304		clock-frequency = <80000>;
305		request-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
306		slave-addr = <138>;
307		clocks = <&tegra_car TEGRA20_CLK_I2C3>,
308			 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
309		clock-names = "div-clk", "fast-clk";
310		resets = <&tegra_car 67>;
311		reset-names = "i2c";
312	};
313
314	memory-controller@7000f400 {
315		nvidia,use-ram-code;
316
317		emc-tables@0 {
318			nvidia,ram-code = <0x0>;
319			#address-cells = <1>;
320			#size-cells = <0>;
321
322			emc-table@166500 {
323				reg = <166500>;
324				compatible = "nvidia,tegra20-emc-table";
325				clock-frequency = <166500>;
326				nvidia,emc-registers = <0x0000000a 0x00000016
327					0x00000008 0x00000003 0x00000004 0x00000004
328					0x00000002 0x0000000c 0x00000003 0x00000003
329					0x00000002 0x00000001 0x00000004 0x00000005
330					0x00000004 0x00000009 0x0000000d 0x000004df
331					0x00000000 0x00000003 0x00000003 0x00000003
332					0x00000003 0x00000001 0x0000000a 0x000000c8
333					0x00000003 0x00000006 0x00000004 0x00000008
334					0x00000002 0x00000000 0x00000000 0x00000002
335					0x00000000 0x00000000 0x00000083 0xe03b0323
336					0x007fe010 0x00001414 0x00000000 0x00000000
337					0x00000000 0x00000000 0x00000000 0x00000000>;
338			};
339
340			emc-table@333000 {
341				reg = <333000>;
342				compatible = "nvidia,tegra20-emc-table";
343				clock-frequency = <333000>;
344				nvidia,emc-registers = <0x00000018 0x00000033
345					0x00000012 0x00000004 0x00000004 0x00000005
346					0x00000003 0x0000000c 0x00000006 0x00000006
347					0x00000003 0x00000001 0x00000004 0x00000005
348					0x00000004 0x00000009 0x0000000d 0x00000bff
349					0x00000000 0x00000003 0x00000003 0x00000006
350					0x00000006 0x00000001 0x00000011 0x000000c8
351					0x00000003 0x0000000e 0x00000007 0x00000008
352					0x00000002 0x00000000 0x00000000 0x00000002
353					0x00000000 0x00000000 0x00000083 0xf0440303
354					0x007fe010 0x00001414 0x00000000 0x00000000
355					0x00000000 0x00000000 0x00000000 0x00000000>;
356			};
357		};
358	};
359
360	i2c@7000d000 {
361		status = "okay";
362		clock-frequency = <400000>;
363
364		pmic: tps6586x@34 {
365			compatible = "ti,tps6586x";
366			reg = <0x34>;
367			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
368
369			#gpio-cells = <2>;
370			gpio-controller;
371
372			sys-supply = <&p5valw_reg>;
373			vin-sm0-supply = <&sys_reg>;
374			vin-sm1-supply = <&sys_reg>;
375			vin-sm2-supply = <&sys_reg>;
376			vinldo01-supply = <&sm2_reg>;
377			vinldo23-supply = <&sm2_reg>;
378			vinldo4-supply = <&sm2_reg>;
379			vinldo678-supply = <&sm2_reg>;
380			vinldo9-supply = <&sm2_reg>;
381
382			regulators {
383				sys_reg: sys {
384					regulator-name = "vdd_sys";
385					regulator-always-on;
386				};
387
388				core_vdd_reg: sm0 {
389					regulator-name = "+1.2vs_sm0,vdd_core";
390					regulator-min-microvolt = <950000>;
391					regulator-max-microvolt = <1300000>;
392					regulator-coupled-with = <&rtc_vdd_reg &cpu_vdd_reg>;
393					regulator-coupled-max-spread = <170000 550000>;
394					regulator-always-on;
395
396					nvidia,tegra-core-regulator;
397				};
398
399				cpu_vdd_reg: sm1 {
400					regulator-name = "+1.0vs_sm1,vdd_cpu";
401					regulator-min-microvolt = <750000>;
402					regulator-max-microvolt = <1100000>;
403					regulator-coupled-with = <&core_vdd_reg &rtc_vdd_reg>;
404					regulator-coupled-max-spread = <550000 550000>;
405					regulator-always-on;
406
407					nvidia,tegra-cpu-regulator;
408				};
409
410				sm2_reg: sm2 {
411					regulator-name = "+3.7vs_sm2,vin_ldo*";
412					regulator-min-microvolt = <3700000>;
413					regulator-max-microvolt = <3700000>;
414					regulator-always-on;
415				};
416
417				/* LDO0 is not connected to anything */
418
419				ldo1 {
420					regulator-name = "+1.1vs_ldo1,avdd_pll*";
421					regulator-min-microvolt = <1100000>;
422					regulator-max-microvolt = <1100000>;
423					regulator-always-on;
424				};
425
426				rtc_vdd_reg: ldo2 {
427					regulator-name = "+1.2vs_ldo2,vdd_rtc";
428					regulator-min-microvolt = <950000>;
429					regulator-max-microvolt = <1300000>;
430					regulator-coupled-with = <&core_vdd_reg &cpu_vdd_reg>;
431					regulator-coupled-max-spread = <170000 550000>;
432					regulator-always-on;
433
434					nvidia,tegra-rtc-regulator;
435				};
436
437				ldo3 {
438					regulator-name = "+3.3vs_ldo3,avdd_usb*";
439					regulator-min-microvolt = <3300000>;
440					regulator-max-microvolt = <3300000>;
441					regulator-always-on;
442				};
443
444				ldo4 {
445					regulator-name = "+1.8vs_ldo4,avdd_osc,vddio_sys";
446					regulator-min-microvolt = <1800000>;
447					regulator-max-microvolt = <1800000>;
448					regulator-always-on;
449				};
450
451				ldo5 {
452					regulator-name = "+2.85vs_ldo5,vcore_mmc";
453					regulator-min-microvolt = <2850000>;
454					regulator-max-microvolt = <2850000>;
455					regulator-always-on;
456				};
457
458				ldo6 {
459					/*
460					 * Research indicates this should be
461					 * 1.8v; other boards that use this
462					 * rail for the same purpose need it
463					 * set to 1.8v. The schematic signal
464					 * name is incorrect; perhaps copied
465					 * from an incorrect NVIDIA reference.
466					 */
467					regulator-name = "+2.85vs_ldo6,avdd_vdac";
468					regulator-min-microvolt = <1800000>;
469					regulator-max-microvolt = <1800000>;
470				};
471
472				hdmi_vdd_reg: ldo7 {
473					regulator-name = "+3.3vs_ldo7,avdd_hdmi";
474					regulator-min-microvolt = <3300000>;
475					regulator-max-microvolt = <3300000>;
476				};
477
478				hdmi_pll_reg: ldo8 {
479					regulator-name = "+1.8vs_ldo8,avdd_hdmi_pll";
480					regulator-min-microvolt = <1800000>;
481					regulator-max-microvolt = <1800000>;
482				};
483
484				ldo9 {
485					regulator-name = "+2.85vs_ldo9,vdd_ddr_rx";
486					regulator-min-microvolt = <2850000>;
487					regulator-max-microvolt = <2850000>;
488					regulator-always-on;
489				};
490
491				ldo_rtc {
492					regulator-name = "+3.3vs_rtc";
493					regulator-min-microvolt = <3300000>;
494					regulator-max-microvolt = <3300000>;
495					regulator-always-on;
496				};
497			};
498		};
499
500		adt7461@4c {
501			compatible = "adi,adt7461";
502			reg = <0x4c>;
503		};
504	};
505
506	pmc@7000e400 {
507		nvidia,invert-interrupt;
508		nvidia,suspend-mode = <1>;
509		nvidia,cpu-pwr-good-time = <2000>;
510		nvidia,cpu-pwr-off-time = <0>;
511		nvidia,core-pwr-good-time = <3845 3845>;
512		nvidia,core-pwr-off-time = <0>;
513		nvidia,sys-clock-req-active-high;
514	};
515
516	usb@c5000000 {
517		compatible = "nvidia,tegra20-udc";
518		status = "okay";
519		dr_mode = "peripheral";
520	};
521
522	usb-phy@c5000000 {
523		status = "okay";
524	};
525
526	usb@c5004000 {
527		status = "okay";
528		nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
529			GPIO_ACTIVE_LOW>;
530	};
531
532	usb-phy@c5004000 {
533		status = "okay";
534		nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
535			GPIO_ACTIVE_LOW>;
536	};
537
538	usb@c5008000 {
539		status = "okay";
540	};
541
542	usb-phy@c5008000 {
543		status = "okay";
544	};
545
546	mmc@c8000000 {
547		status = "okay";
548		cd-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_LOW>;
549		wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
550		power-gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>;
551		bus-width = <4>;
552	};
553
554	mmc@c8000600 {
555		status = "okay";
556		bus-width = <8>;
557		non-removable;
558	};
559
560	backlight: backlight {
561		compatible = "pwm-backlight";
562
563		enable-gpios = <&gpio TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>;
564		pwms = <&pwm 0 5000000>;
565
566		brightness-levels = <0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 255>;
567		default-brightness-level = <10>;
568
569		backlight-boot-off;
570	};
571
572	clk32k_in: clock@0 {
573		compatible = "fixed-clock";
574		clock-frequency = <32768>;
575		#clock-cells = <0>;
576	};
577
578	gpio-keys {
579		compatible = "gpio-keys";
580
581		wakeup {
582			label = "Wakeup";
583			gpios = <&gpio TEGRA_GPIO(J, 7) GPIO_ACTIVE_LOW>;
584			linux,code = <KEY_WAKEUP>;
585			wakeup-source;
586		};
587	};
588
589	gpio-leds {
590		compatible = "gpio-leds";
591
592		led-0 {
593			label = "wifi-led";
594			gpios = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
595			linux,default-trigger = "rfkill0";
596		};
597	};
598
599	panel: panel {
600		compatible = "samsung,ltn101nt05";
601
602		ddc-i2c-bus = <&lvds_ddc>;
603		power-supply = <&vdd_pnl_reg>;
604		enable-gpios = <&gpio TEGRA_GPIO(M, 6) GPIO_ACTIVE_HIGH>;
605
606		backlight = <&backlight>;
607	};
608
609	p5valw_reg: regulator@0 {
610		compatible = "regulator-fixed";
611		regulator-name = "+5valw";
612		regulator-min-microvolt = <5000000>;
613		regulator-max-microvolt = <5000000>;
614		regulator-always-on;
615	};
616
617	vdd_pnl_reg: regulator@1 {
618		compatible = "regulator-fixed";
619		regulator-name = "+3VS,vdd_pnl";
620		regulator-min-microvolt = <3300000>;
621		regulator-max-microvolt = <3300000>;
622		regulator-boot-on;
623		gpio = <&gpio TEGRA_GPIO(A, 4) GPIO_ACTIVE_HIGH>;
624		enable-active-high;
625	};
626
627	sound {
628		compatible = "nvidia,tegra-audio-alc5632-paz00",
629			"nvidia,tegra-audio-alc5632";
630
631		nvidia,model = "Compal PAZ00";
632
633		nvidia,audio-routing =
634			"Int Spk", "SPKOUT",
635			"Int Spk", "SPKOUTN",
636			"Headset Mic", "MICBIAS1",
637			"MIC1", "Headset Mic",
638			"Headset Stereophone", "HPR",
639			"Headset Stereophone", "HPL",
640			"DMICDAT", "Digital Mic";
641
642		nvidia,audio-codec = <&alc5632>;
643		nvidia,i2s-controller = <&tegra_i2s1>;
644		nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
645			GPIO_ACTIVE_HIGH>;
646
647		clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
648			 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
649			 <&tegra_car TEGRA20_CLK_CDEV1>;
650		clock-names = "pll_a", "pll_a_out0", "mclk";
651	};
652
653	cpus {
654		cpu0: cpu@0 {
655			cpu-supply = <&cpu_vdd_reg>;
656			operating-points-v2 = <&cpu0_opp_table>;
657		};
658
659		cpu@1 {
660			cpu-supply = <&cpu_vdd_reg>;
661			operating-points-v2 = <&cpu0_opp_table>;
662		};
663	};
664};
665
666&emc_icc_dvfs_opp_table {
667	/delete-node/ opp@760000000;
668};
669