1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra30-car.h> 3#include <dt-bindings/gpio/tegra-gpio.h> 4#include <dt-bindings/memory/tegra30-mc.h> 5#include <dt-bindings/pinctrl/pinctrl-tegra.h> 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/soc/tegra-pmc.h> 8 9#include "tegra30-peripherals-opp.dtsi" 10 11/ { 12 compatible = "nvidia,tegra30"; 13 interrupt-parent = <&lic>; 14 #address-cells = <1>; 15 #size-cells = <1>; 16 17 memory@80000000 { 18 device_type = "memory"; 19 reg = <0x80000000 0x0>; 20 }; 21 22 pcie@3000 { 23 compatible = "nvidia,tegra30-pcie"; 24 device_type = "pci"; 25 reg = <0x00003000 0x00000800>, /* PADS registers */ 26 <0x00003800 0x00000200>, /* AFI registers */ 27 <0x10000000 0x10000000>; /* configuration space */ 28 reg-names = "pads", "afi", "cs"; 29 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 30 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 31 interrupt-names = "intr", "msi"; 32 33 #interrupt-cells = <1>; 34 interrupt-map-mask = <0 0 0 0>; 35 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 36 37 bus-range = <0x00 0xff>; 38 #address-cells = <3>; 39 #size-cells = <2>; 40 41 ranges = <0x02000000 0 0x00000000 0x00000000 0 0x00001000>, /* port 0 configuration space */ 42 <0x02000000 0 0x00001000 0x00001000 0 0x00001000>, /* port 1 configuration space */ 43 <0x02000000 0 0x00004000 0x00004000 0 0x00001000>, /* port 2 configuration space */ 44 <0x01000000 0 0 0x02000000 0 0x00010000>, /* downstream I/O */ 45 <0x02000000 0 0x20000000 0x20000000 0 0x08000000>, /* non-prefetchable memory */ 46 <0x42000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */ 47 48 clocks = <&tegra_car TEGRA30_CLK_PCIE>, 49 <&tegra_car TEGRA30_CLK_AFI>, 50 <&tegra_car TEGRA30_CLK_PLL_E>, 51 <&tegra_car TEGRA30_CLK_CML0>; 52 clock-names = "pex", "afi", "pll_e", "cml"; 53 resets = <&tegra_car 70>, 54 <&tegra_car 72>, 55 <&tegra_car 74>; 56 reset-names = "pex", "afi", "pcie_x"; 57 status = "disabled"; 58 59 pci@1,0 { 60 device_type = "pci"; 61 assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>; 62 reg = <0x000800 0 0 0 0>; 63 bus-range = <0x00 0xff>; 64 status = "disabled"; 65 66 #address-cells = <3>; 67 #size-cells = <2>; 68 ranges; 69 70 nvidia,num-lanes = <2>; 71 }; 72 73 pci@2,0 { 74 device_type = "pci"; 75 assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>; 76 reg = <0x001000 0 0 0 0>; 77 bus-range = <0x00 0xff>; 78 status = "disabled"; 79 80 #address-cells = <3>; 81 #size-cells = <2>; 82 ranges; 83 84 nvidia,num-lanes = <2>; 85 }; 86 87 pci@3,0 { 88 device_type = "pci"; 89 assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>; 90 reg = <0x001800 0 0 0 0>; 91 bus-range = <0x00 0xff>; 92 status = "disabled"; 93 94 #address-cells = <3>; 95 #size-cells = <2>; 96 ranges; 97 98 nvidia,num-lanes = <2>; 99 }; 100 }; 101 102 sram@40000000 { 103 compatible = "mmio-sram"; 104 reg = <0x40000000 0x40000>; 105 #address-cells = <1>; 106 #size-cells = <1>; 107 ranges = <0 0x40000000 0x40000>; 108 109 vde_pool: sram@400 { 110 reg = <0x400 0x3fc00>; 111 pool; 112 }; 113 }; 114 115 host1x@50000000 { 116 compatible = "nvidia,tegra30-host1x"; 117 reg = <0x50000000 0x00024000>; 118 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 119 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 120 interrupt-names = "syncpt", "host1x"; 121 clocks = <&tegra_car TEGRA30_CLK_HOST1X>; 122 clock-names = "host1x"; 123 resets = <&tegra_car 28>; 124 reset-names = "host1x"; 125 iommus = <&mc TEGRA_SWGROUP_HC>; 126 127 #address-cells = <1>; 128 #size-cells = <1>; 129 130 ranges = <0x54000000 0x54000000 0x04000000>; 131 132 mpe@54040000 { 133 compatible = "nvidia,tegra30-mpe"; 134 reg = <0x54040000 0x00040000>; 135 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 136 clocks = <&tegra_car TEGRA30_CLK_MPE>; 137 resets = <&tegra_car 60>; 138 reset-names = "mpe"; 139 140 iommus = <&mc TEGRA_SWGROUP_MPE>; 141 }; 142 143 vi@54080000 { 144 compatible = "nvidia,tegra30-vi"; 145 reg = <0x54080000 0x00040000>; 146 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 147 clocks = <&tegra_car TEGRA30_CLK_VI>; 148 resets = <&tegra_car 20>; 149 reset-names = "vi"; 150 151 iommus = <&mc TEGRA_SWGROUP_VI>; 152 }; 153 154 epp@540c0000 { 155 compatible = "nvidia,tegra30-epp"; 156 reg = <0x540c0000 0x00040000>; 157 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 158 clocks = <&tegra_car TEGRA30_CLK_EPP>; 159 resets = <&tegra_car 19>; 160 reset-names = "epp"; 161 162 iommus = <&mc TEGRA_SWGROUP_EPP>; 163 }; 164 165 isp@54100000 { 166 compatible = "nvidia,tegra30-isp"; 167 reg = <0x54100000 0x00040000>; 168 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 169 clocks = <&tegra_car TEGRA30_CLK_ISP>; 170 resets = <&tegra_car 23>; 171 reset-names = "isp"; 172 173 iommus = <&mc TEGRA_SWGROUP_ISP>; 174 }; 175 176 gr2d@54140000 { 177 compatible = "nvidia,tegra30-gr2d"; 178 reg = <0x54140000 0x00040000>; 179 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 180 clocks = <&tegra_car TEGRA30_CLK_GR2D>; 181 resets = <&tegra_car 21>; 182 reset-names = "2d"; 183 184 iommus = <&mc TEGRA_SWGROUP_G2>; 185 }; 186 187 gr3d@54180000 { 188 compatible = "nvidia,tegra30-gr3d"; 189 reg = <0x54180000 0x00040000>; 190 clocks = <&tegra_car TEGRA30_CLK_GR3D>, 191 <&tegra_car TEGRA30_CLK_GR3D2>; 192 clock-names = "3d", "3d2"; 193 resets = <&tegra_car 24>, 194 <&tegra_car 98>; 195 reset-names = "3d", "3d2"; 196 197 iommus = <&mc TEGRA_SWGROUP_NV>, 198 <&mc TEGRA_SWGROUP_NV2>; 199 }; 200 201 dc@54200000 { 202 compatible = "nvidia,tegra30-dc"; 203 reg = <0x54200000 0x00040000>; 204 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 205 clocks = <&tegra_car TEGRA30_CLK_DISP1>, 206 <&tegra_car TEGRA30_CLK_PLL_P>; 207 clock-names = "dc", "parent"; 208 resets = <&tegra_car 27>; 209 reset-names = "dc"; 210 211 iommus = <&mc TEGRA_SWGROUP_DC>; 212 213 nvidia,head = <0>; 214 215 interconnects = <&mc TEGRA30_MC_DISPLAY0A &emc>, 216 <&mc TEGRA30_MC_DISPLAY0B &emc>, 217 <&mc TEGRA30_MC_DISPLAY1B &emc>, 218 <&mc TEGRA30_MC_DISPLAY0C &emc>, 219 <&mc TEGRA30_MC_DISPLAYHC &emc>; 220 interconnect-names = "wina", 221 "winb", 222 "winb-vfilter", 223 "winc", 224 "cursor"; 225 226 rgb { 227 status = "disabled"; 228 }; 229 }; 230 231 dc@54240000 { 232 compatible = "nvidia,tegra30-dc"; 233 reg = <0x54240000 0x00040000>; 234 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 235 clocks = <&tegra_car TEGRA30_CLK_DISP2>, 236 <&tegra_car TEGRA30_CLK_PLL_P>; 237 clock-names = "dc", "parent"; 238 resets = <&tegra_car 26>; 239 reset-names = "dc"; 240 241 iommus = <&mc TEGRA_SWGROUP_DCB>; 242 243 nvidia,head = <1>; 244 245 interconnects = <&mc TEGRA30_MC_DISPLAY0AB &emc>, 246 <&mc TEGRA30_MC_DISPLAY0BB &emc>, 247 <&mc TEGRA30_MC_DISPLAY1BB &emc>, 248 <&mc TEGRA30_MC_DISPLAY0CB &emc>, 249 <&mc TEGRA30_MC_DISPLAYHCB &emc>; 250 interconnect-names = "wina", 251 "winb", 252 "winb-vfilter", 253 "winc", 254 "cursor"; 255 256 rgb { 257 status = "disabled"; 258 }; 259 }; 260 261 hdmi@54280000 { 262 compatible = "nvidia,tegra30-hdmi"; 263 reg = <0x54280000 0x00040000>; 264 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 265 clocks = <&tegra_car TEGRA30_CLK_HDMI>, 266 <&tegra_car TEGRA30_CLK_PLL_D2_OUT0>; 267 clock-names = "hdmi", "parent"; 268 resets = <&tegra_car 51>; 269 reset-names = "hdmi"; 270 status = "disabled"; 271 }; 272 273 tvo@542c0000 { 274 compatible = "nvidia,tegra30-tvo"; 275 reg = <0x542c0000 0x00040000>; 276 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 277 clocks = <&tegra_car TEGRA30_CLK_TVO>; 278 status = "disabled"; 279 }; 280 281 dsi@54300000 { 282 compatible = "nvidia,tegra30-dsi"; 283 reg = <0x54300000 0x00040000>; 284 clocks = <&tegra_car TEGRA30_CLK_DSIA>, 285 <&tegra_car TEGRA30_CLK_PLL_D_OUT0>; 286 clock-names = "dsi", "parent"; 287 resets = <&tegra_car 48>; 288 reset-names = "dsi"; 289 status = "disabled"; 290 }; 291 292 dsi@54400000 { 293 compatible = "nvidia,tegra30-dsi"; 294 reg = <0x54400000 0x00040000>; 295 clocks = <&tegra_car TEGRA30_CLK_DSIB>, 296 <&tegra_car TEGRA30_CLK_PLL_D_OUT0>; 297 clock-names = "dsi", "parent"; 298 resets = <&tegra_car 84>; 299 reset-names = "dsi"; 300 status = "disabled"; 301 }; 302 }; 303 304 timer@50040600 { 305 compatible = "arm,cortex-a9-twd-timer"; 306 reg = <0x50040600 0x20>; 307 interrupt-parent = <&intc>; 308 interrupts = <GIC_PPI 13 309 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; 310 clocks = <&tegra_car TEGRA30_CLK_TWD>; 311 }; 312 313 intc: interrupt-controller@50041000 { 314 compatible = "arm,cortex-a9-gic"; 315 reg = <0x50041000 0x1000>, 316 <0x50040100 0x0100>; 317 interrupt-controller; 318 #interrupt-cells = <3>; 319 interrupt-parent = <&intc>; 320 }; 321 322 cache-controller@50043000 { 323 compatible = "arm,pl310-cache"; 324 reg = <0x50043000 0x1000>; 325 arm,data-latency = <6 6 2>; 326 arm,tag-latency = <5 5 2>; 327 cache-unified; 328 cache-level = <2>; 329 }; 330 331 lic: interrupt-controller@60004000 { 332 compatible = "nvidia,tegra30-ictlr"; 333 reg = <0x60004000 0x100>, 334 <0x60004100 0x50>, 335 <0x60004200 0x50>, 336 <0x60004300 0x50>, 337 <0x60004400 0x50>; 338 interrupt-controller; 339 #interrupt-cells = <3>; 340 interrupt-parent = <&intc>; 341 }; 342 343 timer@60005000 { 344 compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer"; 345 reg = <0x60005000 0x400>; 346 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 347 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 348 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 349 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 350 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 351 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 352 clocks = <&tegra_car TEGRA30_CLK_TIMER>; 353 }; 354 355 tegra_car: clock@60006000 { 356 compatible = "nvidia,tegra30-car"; 357 reg = <0x60006000 0x1000>; 358 #clock-cells = <1>; 359 #reset-cells = <1>; 360 }; 361 362 flow-controller@60007000 { 363 compatible = "nvidia,tegra30-flowctrl"; 364 reg = <0x60007000 0x1000>; 365 }; 366 367 apbdma: dma@6000a000 { 368 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma"; 369 reg = <0x6000a000 0x1400>; 370 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 371 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 372 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 373 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 374 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 375 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 376 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 377 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 378 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 379 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 380 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 381 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 382 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 383 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 384 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 385 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 386 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 387 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 388 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 389 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 390 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 391 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 392 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 393 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 394 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 395 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 396 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 397 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 398 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 399 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 400 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 401 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 402 clocks = <&tegra_car TEGRA30_CLK_APBDMA>; 403 resets = <&tegra_car 34>; 404 reset-names = "dma"; 405 #dma-cells = <1>; 406 }; 407 408 ahb: ahb@6000c000 { 409 compatible = "nvidia,tegra30-ahb"; 410 reg = <0x6000c000 0x150>; /* AHB Arbitration + Gizmo Controller */ 411 }; 412 413 actmon@6000c800 { 414 compatible = "nvidia,tegra30-actmon"; 415 reg = <0x6000c800 0x400>; 416 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 417 clocks = <&tegra_car TEGRA30_CLK_ACTMON>, 418 <&tegra_car TEGRA30_CLK_EMC>; 419 clock-names = "actmon", "emc"; 420 resets = <&tegra_car TEGRA30_CLK_ACTMON>; 421 reset-names = "actmon"; 422 operating-points-v2 = <&emc_bw_dfs_opp_table>; 423 interconnects = <&mc TEGRA30_MC_MPCORER &emc>; 424 interconnect-names = "cpu-read"; 425 }; 426 427 gpio: gpio@6000d000 { 428 compatible = "nvidia,tegra30-gpio"; 429 reg = <0x6000d000 0x1000>; 430 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 431 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 432 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 433 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 434 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 435 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 436 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 437 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 438 #gpio-cells = <2>; 439 gpio-controller; 440 #interrupt-cells = <2>; 441 interrupt-controller; 442 /* 443 gpio-ranges = <&pinmux 0 0 248>; 444 */ 445 }; 446 447 vde@6001a000 { 448 compatible = "nvidia,tegra30-vde", "nvidia,tegra20-vde"; 449 reg = <0x6001a000 0x1000>, /* Syntax Engine */ 450 <0x6001b000 0x1000>, /* Video Bitstream Engine */ 451 <0x6001c000 0x100>, /* Macroblock Engine */ 452 <0x6001c200 0x100>, /* Post-processing Engine */ 453 <0x6001c400 0x100>, /* Motion Compensation Engine */ 454 <0x6001c600 0x100>, /* Transform Engine */ 455 <0x6001c800 0x100>, /* Pixel prediction block */ 456 <0x6001ca00 0x100>, /* Video DMA */ 457 <0x6001d800 0x400>; /* Video frame controls */ 458 reg-names = "sxe", "bsev", "mbe", "ppe", "mce", 459 "tfe", "ppb", "vdma", "frameid"; 460 iram = <&vde_pool>; /* IRAM region */ 461 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, /* Sync token interrupt */ 462 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */ 463 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /* SXE interrupt */ 464 interrupt-names = "sync-token", "bsev", "sxe"; 465 clocks = <&tegra_car TEGRA30_CLK_VDE>; 466 reset-names = "vde", "mc"; 467 resets = <&tegra_car 61>, <&mc TEGRA30_MC_RESET_VDE>; 468 iommus = <&mc TEGRA_SWGROUP_VDE>; 469 }; 470 471 apbmisc@70000800 { 472 compatible = "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc"; 473 reg = <0x70000800 0x64>, /* Chip revision */ 474 <0x70000008 0x04>; /* Strapping options */ 475 }; 476 477 pinmux: pinmux@70000868 { 478 compatible = "nvidia,tegra30-pinmux"; 479 reg = <0x70000868 0x0d4>, /* Pad control registers */ 480 <0x70003000 0x3e4>; /* Mux registers */ 481 }; 482 483 /* 484 * There are two serial driver i.e. 8250 based simple serial 485 * driver and APB DMA based serial driver for higher baudrate 486 * and performace. To enable the 8250 based driver, the compatible 487 * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable 488 * the APB DMA based serial driver, the compatible is 489 * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart". 490 */ 491 uarta: serial@70006000 { 492 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; 493 reg = <0x70006000 0x40>; 494 reg-shift = <2>; 495 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 496 clocks = <&tegra_car TEGRA30_CLK_UARTA>; 497 resets = <&tegra_car 6>; 498 reset-names = "serial"; 499 dmas = <&apbdma 8>, <&apbdma 8>; 500 dma-names = "rx", "tx"; 501 status = "disabled"; 502 }; 503 504 uartb: serial@70006040 { 505 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; 506 reg = <0x70006040 0x40>; 507 reg-shift = <2>; 508 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 509 clocks = <&tegra_car TEGRA30_CLK_UARTB>; 510 resets = <&tegra_car 7>; 511 reset-names = "serial"; 512 dmas = <&apbdma 9>, <&apbdma 9>; 513 dma-names = "rx", "tx"; 514 status = "disabled"; 515 }; 516 517 uartc: serial@70006200 { 518 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; 519 reg = <0x70006200 0x100>; 520 reg-shift = <2>; 521 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 522 clocks = <&tegra_car TEGRA30_CLK_UARTC>; 523 resets = <&tegra_car 55>; 524 reset-names = "serial"; 525 dmas = <&apbdma 10>, <&apbdma 10>; 526 dma-names = "rx", "tx"; 527 status = "disabled"; 528 }; 529 530 uartd: serial@70006300 { 531 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; 532 reg = <0x70006300 0x100>; 533 reg-shift = <2>; 534 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 535 clocks = <&tegra_car TEGRA30_CLK_UARTD>; 536 resets = <&tegra_car 65>; 537 reset-names = "serial"; 538 dmas = <&apbdma 19>, <&apbdma 19>; 539 dma-names = "rx", "tx"; 540 status = "disabled"; 541 }; 542 543 uarte: serial@70006400 { 544 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; 545 reg = <0x70006400 0x100>; 546 reg-shift = <2>; 547 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 548 clocks = <&tegra_car TEGRA30_CLK_UARTE>; 549 resets = <&tegra_car 66>; 550 reset-names = "serial"; 551 dmas = <&apbdma 20>, <&apbdma 20>; 552 dma-names = "rx", "tx"; 553 status = "disabled"; 554 }; 555 556 gmi@70009000 { 557 compatible = "nvidia,tegra30-gmi"; 558 reg = <0x70009000 0x1000>; 559 #address-cells = <2>; 560 #size-cells = <1>; 561 ranges = <0 0 0x48000000 0x7ffffff>; 562 clocks = <&tegra_car TEGRA30_CLK_NOR>; 563 clock-names = "gmi"; 564 resets = <&tegra_car 42>; 565 reset-names = "gmi"; 566 status = "disabled"; 567 }; 568 569 pwm: pwm@7000a000 { 570 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm"; 571 reg = <0x7000a000 0x100>; 572 #pwm-cells = <2>; 573 clocks = <&tegra_car TEGRA30_CLK_PWM>; 574 resets = <&tegra_car 17>; 575 reset-names = "pwm"; 576 status = "disabled"; 577 }; 578 579 rtc@7000e000 { 580 compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc"; 581 reg = <0x7000e000 0x100>; 582 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 583 clocks = <&tegra_car TEGRA30_CLK_RTC>; 584 }; 585 586 i2c@7000c000 { 587 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; 588 reg = <0x7000c000 0x100>; 589 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 590 #address-cells = <1>; 591 #size-cells = <0>; 592 clocks = <&tegra_car TEGRA30_CLK_I2C1>, 593 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; 594 clock-names = "div-clk", "fast-clk"; 595 resets = <&tegra_car 12>; 596 reset-names = "i2c"; 597 dmas = <&apbdma 21>, <&apbdma 21>; 598 dma-names = "rx", "tx"; 599 status = "disabled"; 600 }; 601 602 i2c@7000c400 { 603 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; 604 reg = <0x7000c400 0x100>; 605 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 606 #address-cells = <1>; 607 #size-cells = <0>; 608 clocks = <&tegra_car TEGRA30_CLK_I2C2>, 609 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; 610 clock-names = "div-clk", "fast-clk"; 611 resets = <&tegra_car 54>; 612 reset-names = "i2c"; 613 dmas = <&apbdma 22>, <&apbdma 22>; 614 dma-names = "rx", "tx"; 615 status = "disabled"; 616 }; 617 618 i2c@7000c500 { 619 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; 620 reg = <0x7000c500 0x100>; 621 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 622 #address-cells = <1>; 623 #size-cells = <0>; 624 clocks = <&tegra_car TEGRA30_CLK_I2C3>, 625 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; 626 clock-names = "div-clk", "fast-clk"; 627 resets = <&tegra_car 67>; 628 reset-names = "i2c"; 629 dmas = <&apbdma 23>, <&apbdma 23>; 630 dma-names = "rx", "tx"; 631 status = "disabled"; 632 }; 633 634 i2c@7000c700 { 635 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; 636 reg = <0x7000c700 0x100>; 637 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 638 #address-cells = <1>; 639 #size-cells = <0>; 640 clocks = <&tegra_car TEGRA30_CLK_I2C4>, 641 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; 642 resets = <&tegra_car 103>; 643 reset-names = "i2c"; 644 clock-names = "div-clk", "fast-clk"; 645 dmas = <&apbdma 26>, <&apbdma 26>; 646 dma-names = "rx", "tx"; 647 status = "disabled"; 648 }; 649 650 i2c@7000d000 { 651 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; 652 reg = <0x7000d000 0x100>; 653 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 654 #address-cells = <1>; 655 #size-cells = <0>; 656 clocks = <&tegra_car TEGRA30_CLK_I2C5>, 657 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; 658 clock-names = "div-clk", "fast-clk"; 659 resets = <&tegra_car 47>; 660 reset-names = "i2c"; 661 dmas = <&apbdma 24>, <&apbdma 24>; 662 dma-names = "rx", "tx"; 663 status = "disabled"; 664 }; 665 666 spi@7000d400 { 667 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; 668 reg = <0x7000d400 0x200>; 669 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 670 #address-cells = <1>; 671 #size-cells = <0>; 672 clocks = <&tegra_car TEGRA30_CLK_SBC1>; 673 resets = <&tegra_car 41>; 674 reset-names = "spi"; 675 dmas = <&apbdma 15>, <&apbdma 15>; 676 dma-names = "rx", "tx"; 677 status = "disabled"; 678 }; 679 680 spi@7000d600 { 681 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; 682 reg = <0x7000d600 0x200>; 683 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 684 #address-cells = <1>; 685 #size-cells = <0>; 686 clocks = <&tegra_car TEGRA30_CLK_SBC2>; 687 resets = <&tegra_car 44>; 688 reset-names = "spi"; 689 dmas = <&apbdma 16>, <&apbdma 16>; 690 dma-names = "rx", "tx"; 691 status = "disabled"; 692 }; 693 694 spi@7000d800 { 695 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; 696 reg = <0x7000d800 0x200>; 697 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 698 #address-cells = <1>; 699 #size-cells = <0>; 700 clocks = <&tegra_car TEGRA30_CLK_SBC3>; 701 resets = <&tegra_car 46>; 702 reset-names = "spi"; 703 dmas = <&apbdma 17>, <&apbdma 17>; 704 dma-names = "rx", "tx"; 705 status = "disabled"; 706 }; 707 708 spi@7000da00 { 709 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; 710 reg = <0x7000da00 0x200>; 711 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 712 #address-cells = <1>; 713 #size-cells = <0>; 714 clocks = <&tegra_car TEGRA30_CLK_SBC4>; 715 resets = <&tegra_car 68>; 716 reset-names = "spi"; 717 dmas = <&apbdma 18>, <&apbdma 18>; 718 dma-names = "rx", "tx"; 719 status = "disabled"; 720 }; 721 722 spi@7000dc00 { 723 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; 724 reg = <0x7000dc00 0x200>; 725 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 726 #address-cells = <1>; 727 #size-cells = <0>; 728 clocks = <&tegra_car TEGRA30_CLK_SBC5>; 729 resets = <&tegra_car 104>; 730 reset-names = "spi"; 731 dmas = <&apbdma 27>, <&apbdma 27>; 732 dma-names = "rx", "tx"; 733 status = "disabled"; 734 }; 735 736 spi@7000de00 { 737 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; 738 reg = <0x7000de00 0x200>; 739 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 740 #address-cells = <1>; 741 #size-cells = <0>; 742 clocks = <&tegra_car TEGRA30_CLK_SBC6>; 743 resets = <&tegra_car 106>; 744 reset-names = "spi"; 745 dmas = <&apbdma 28>, <&apbdma 28>; 746 dma-names = "rx", "tx"; 747 status = "disabled"; 748 }; 749 750 kbc@7000e200 { 751 compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc"; 752 reg = <0x7000e200 0x100>; 753 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 754 clocks = <&tegra_car TEGRA30_CLK_KBC>; 755 resets = <&tegra_car 36>; 756 reset-names = "kbc"; 757 status = "disabled"; 758 }; 759 760 tegra_pmc: pmc@7000e400 { 761 compatible = "nvidia,tegra30-pmc"; 762 reg = <0x7000e400 0x400>; 763 clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>; 764 clock-names = "pclk", "clk32k_in"; 765 #clock-cells = <1>; 766 }; 767 768 mc: memory-controller@7000f000 { 769 compatible = "nvidia,tegra30-mc"; 770 reg = <0x7000f000 0x400>; 771 clocks = <&tegra_car TEGRA30_CLK_MC>; 772 clock-names = "mc"; 773 774 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 775 776 #iommu-cells = <1>; 777 #reset-cells = <1>; 778 #interconnect-cells = <1>; 779 }; 780 781 emc: memory-controller@7000f400 { 782 compatible = "nvidia,tegra30-emc"; 783 reg = <0x7000f400 0x400>; 784 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 785 clocks = <&tegra_car TEGRA30_CLK_EMC>; 786 787 nvidia,memory-controller = <&mc>; 788 operating-points-v2 = <&emc_icc_dvfs_opp_table>; 789 790 #interconnect-cells = <0>; 791 }; 792 793 fuse@7000f800 { 794 compatible = "nvidia,tegra30-efuse"; 795 reg = <0x7000f800 0x400>; 796 clocks = <&tegra_car TEGRA30_CLK_FUSE>; 797 clock-names = "fuse"; 798 resets = <&tegra_car 39>; 799 reset-names = "fuse"; 800 }; 801 802 hda@70030000 { 803 compatible = "nvidia,tegra30-hda"; 804 reg = <0x70030000 0x10000>; 805 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 806 clocks = <&tegra_car TEGRA30_CLK_HDA>, 807 <&tegra_car TEGRA30_CLK_HDA2HDMI>, 808 <&tegra_car TEGRA30_CLK_HDA2CODEC_2X>; 809 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 810 resets = <&tegra_car 125>, /* hda */ 811 <&tegra_car 128>, /* hda2hdmi */ 812 <&tegra_car 111>; /* hda2codec_2x */ 813 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 814 status = "disabled"; 815 }; 816 817 ahub@70080000 { 818 compatible = "nvidia,tegra30-ahub"; 819 reg = <0x70080000 0x200>, 820 <0x70080200 0x100>; 821 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 822 clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>, 823 <&tegra_car TEGRA30_CLK_APBIF>; 824 clock-names = "d_audio", "apbif"; 825 resets = <&tegra_car 106>, /* d_audio */ 826 <&tegra_car 107>, /* apbif */ 827 <&tegra_car 30>, /* i2s0 */ 828 <&tegra_car 11>, /* i2s1 */ 829 <&tegra_car 18>, /* i2s2 */ 830 <&tegra_car 101>, /* i2s3 */ 831 <&tegra_car 102>, /* i2s4 */ 832 <&tegra_car 108>, /* dam0 */ 833 <&tegra_car 109>, /* dam1 */ 834 <&tegra_car 110>, /* dam2 */ 835 <&tegra_car 10>; /* spdif */ 836 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", 837 "i2s3", "i2s4", "dam0", "dam1", "dam2", 838 "spdif"; 839 dmas = <&apbdma 1>, <&apbdma 1>, 840 <&apbdma 2>, <&apbdma 2>, 841 <&apbdma 3>, <&apbdma 3>, 842 <&apbdma 4>, <&apbdma 4>; 843 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", 844 "rx3", "tx3"; 845 ranges; 846 #address-cells = <1>; 847 #size-cells = <1>; 848 849 tegra_i2s0: i2s@70080300 { 850 compatible = "nvidia,tegra30-i2s"; 851 reg = <0x70080300 0x100>; 852 nvidia,ahub-cif-ids = <4 4>; 853 clocks = <&tegra_car TEGRA30_CLK_I2S0>; 854 resets = <&tegra_car 30>; 855 reset-names = "i2s"; 856 status = "disabled"; 857 }; 858 859 tegra_i2s1: i2s@70080400 { 860 compatible = "nvidia,tegra30-i2s"; 861 reg = <0x70080400 0x100>; 862 nvidia,ahub-cif-ids = <5 5>; 863 clocks = <&tegra_car TEGRA30_CLK_I2S1>; 864 resets = <&tegra_car 11>; 865 reset-names = "i2s"; 866 status = "disabled"; 867 }; 868 869 tegra_i2s2: i2s@70080500 { 870 compatible = "nvidia,tegra30-i2s"; 871 reg = <0x70080500 0x100>; 872 nvidia,ahub-cif-ids = <6 6>; 873 clocks = <&tegra_car TEGRA30_CLK_I2S2>; 874 resets = <&tegra_car 18>; 875 reset-names = "i2s"; 876 status = "disabled"; 877 }; 878 879 tegra_i2s3: i2s@70080600 { 880 compatible = "nvidia,tegra30-i2s"; 881 reg = <0x70080600 0x100>; 882 nvidia,ahub-cif-ids = <7 7>; 883 clocks = <&tegra_car TEGRA30_CLK_I2S3>; 884 resets = <&tegra_car 101>; 885 reset-names = "i2s"; 886 status = "disabled"; 887 }; 888 889 tegra_i2s4: i2s@70080700 { 890 compatible = "nvidia,tegra30-i2s"; 891 reg = <0x70080700 0x100>; 892 nvidia,ahub-cif-ids = <8 8>; 893 clocks = <&tegra_car TEGRA30_CLK_I2S4>; 894 resets = <&tegra_car 102>; 895 reset-names = "i2s"; 896 status = "disabled"; 897 }; 898 }; 899 900 mmc@78000000 { 901 compatible = "nvidia,tegra30-sdhci"; 902 reg = <0x78000000 0x200>; 903 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 904 clocks = <&tegra_car TEGRA30_CLK_SDMMC1>; 905 clock-names = "sdhci"; 906 resets = <&tegra_car 14>; 907 reset-names = "sdhci"; 908 status = "disabled"; 909 }; 910 911 mmc@78000200 { 912 compatible = "nvidia,tegra30-sdhci"; 913 reg = <0x78000200 0x200>; 914 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 915 clocks = <&tegra_car TEGRA30_CLK_SDMMC2>; 916 clock-names = "sdhci"; 917 resets = <&tegra_car 9>; 918 reset-names = "sdhci"; 919 status = "disabled"; 920 }; 921 922 mmc@78000400 { 923 compatible = "nvidia,tegra30-sdhci"; 924 reg = <0x78000400 0x200>; 925 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 926 clocks = <&tegra_car TEGRA30_CLK_SDMMC3>; 927 clock-names = "sdhci"; 928 resets = <&tegra_car 69>; 929 reset-names = "sdhci"; 930 status = "disabled"; 931 }; 932 933 mmc@78000600 { 934 compatible = "nvidia,tegra30-sdhci"; 935 reg = <0x78000600 0x200>; 936 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 937 clocks = <&tegra_car TEGRA30_CLK_SDMMC4>; 938 clock-names = "sdhci"; 939 resets = <&tegra_car 15>; 940 reset-names = "sdhci"; 941 status = "disabled"; 942 }; 943 944 usb@7d000000 { 945 compatible = "nvidia,tegra30-ehci", "usb-ehci"; 946 reg = <0x7d000000 0x4000>; 947 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 948 phy_type = "utmi"; 949 clocks = <&tegra_car TEGRA30_CLK_USBD>; 950 resets = <&tegra_car 22>; 951 reset-names = "usb"; 952 nvidia,needs-double-reset; 953 nvidia,phy = <&phy1>; 954 status = "disabled"; 955 }; 956 957 phy1: usb-phy@7d000000 { 958 compatible = "nvidia,tegra30-usb-phy"; 959 reg = <0x7d000000 0x4000>, 960 <0x7d000000 0x4000>; 961 phy_type = "utmi"; 962 clocks = <&tegra_car TEGRA30_CLK_USBD>, 963 <&tegra_car TEGRA30_CLK_PLL_U>, 964 <&tegra_car TEGRA30_CLK_USBD>; 965 clock-names = "reg", "pll_u", "utmi-pads"; 966 resets = <&tegra_car 22>, <&tegra_car 22>; 967 reset-names = "usb", "utmi-pads"; 968 #phy-cells = <0>; 969 nvidia,hssync-start-delay = <9>; 970 nvidia,idle-wait-delay = <17>; 971 nvidia,elastic-limit = <16>; 972 nvidia,term-range-adj = <6>; 973 nvidia,xcvr-setup = <51>; 974 nvidia,xcvr-setup-use-fuses; 975 nvidia,xcvr-lsfslew = <1>; 976 nvidia,xcvr-lsrslew = <1>; 977 nvidia,xcvr-hsslew = <32>; 978 nvidia,hssquelch-level = <2>; 979 nvidia,hsdiscon-level = <5>; 980 nvidia,has-utmi-pad-registers; 981 status = "disabled"; 982 }; 983 984 usb@7d004000 { 985 compatible = "nvidia,tegra30-ehci", "usb-ehci"; 986 reg = <0x7d004000 0x4000>; 987 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 988 phy_type = "utmi"; 989 clocks = <&tegra_car TEGRA30_CLK_USB2>; 990 resets = <&tegra_car 58>; 991 reset-names = "usb"; 992 nvidia,phy = <&phy2>; 993 status = "disabled"; 994 }; 995 996 phy2: usb-phy@7d004000 { 997 compatible = "nvidia,tegra30-usb-phy"; 998 reg = <0x7d004000 0x4000>, 999 <0x7d000000 0x4000>; 1000 phy_type = "utmi"; 1001 clocks = <&tegra_car TEGRA30_CLK_USB2>, 1002 <&tegra_car TEGRA30_CLK_PLL_U>, 1003 <&tegra_car TEGRA30_CLK_USBD>; 1004 clock-names = "reg", "pll_u", "utmi-pads"; 1005 resets = <&tegra_car 58>, <&tegra_car 22>; 1006 reset-names = "usb", "utmi-pads"; 1007 #phy-cells = <0>; 1008 nvidia,hssync-start-delay = <9>; 1009 nvidia,idle-wait-delay = <17>; 1010 nvidia,elastic-limit = <16>; 1011 nvidia,term-range-adj = <6>; 1012 nvidia,xcvr-setup = <51>; 1013 nvidia,xcvr-setup-use-fuses; 1014 nvidia,xcvr-lsfslew = <2>; 1015 nvidia,xcvr-lsrslew = <2>; 1016 nvidia,xcvr-hsslew = <32>; 1017 nvidia,hssquelch-level = <2>; 1018 nvidia,hsdiscon-level = <5>; 1019 status = "disabled"; 1020 }; 1021 1022 usb@7d008000 { 1023 compatible = "nvidia,tegra30-ehci", "usb-ehci"; 1024 reg = <0x7d008000 0x4000>; 1025 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1026 phy_type = "utmi"; 1027 clocks = <&tegra_car TEGRA30_CLK_USB3>; 1028 resets = <&tegra_car 59>; 1029 reset-names = "usb"; 1030 nvidia,phy = <&phy3>; 1031 status = "disabled"; 1032 }; 1033 1034 phy3: usb-phy@7d008000 { 1035 compatible = "nvidia,tegra30-usb-phy"; 1036 reg = <0x7d008000 0x4000>, 1037 <0x7d000000 0x4000>; 1038 phy_type = "utmi"; 1039 clocks = <&tegra_car TEGRA30_CLK_USB3>, 1040 <&tegra_car TEGRA30_CLK_PLL_U>, 1041 <&tegra_car TEGRA30_CLK_USBD>; 1042 clock-names = "reg", "pll_u", "utmi-pads"; 1043 resets = <&tegra_car 59>, <&tegra_car 22>; 1044 reset-names = "usb", "utmi-pads"; 1045 #phy-cells = <0>; 1046 nvidia,hssync-start-delay = <0>; 1047 nvidia,idle-wait-delay = <17>; 1048 nvidia,elastic-limit = <16>; 1049 nvidia,term-range-adj = <6>; 1050 nvidia,xcvr-setup = <51>; 1051 nvidia,xcvr-setup-use-fuses; 1052 nvidia,xcvr-lsfslew = <2>; 1053 nvidia,xcvr-lsrslew = <2>; 1054 nvidia,xcvr-hsslew = <32>; 1055 nvidia,hssquelch-level = <2>; 1056 nvidia,hsdiscon-level = <5>; 1057 status = "disabled"; 1058 }; 1059 1060 cpus { 1061 #address-cells = <1>; 1062 #size-cells = <0>; 1063 1064 cpu@0 { 1065 device_type = "cpu"; 1066 compatible = "arm,cortex-a9"; 1067 reg = <0>; 1068 clocks = <&tegra_car TEGRA30_CLK_CCLK_G>; 1069 }; 1070 1071 cpu@1 { 1072 device_type = "cpu"; 1073 compatible = "arm,cortex-a9"; 1074 reg = <1>; 1075 clocks = <&tegra_car TEGRA30_CLK_CCLK_G>; 1076 }; 1077 1078 cpu@2 { 1079 device_type = "cpu"; 1080 compatible = "arm,cortex-a9"; 1081 reg = <2>; 1082 clocks = <&tegra_car TEGRA30_CLK_CCLK_G>; 1083 }; 1084 1085 cpu@3 { 1086 device_type = "cpu"; 1087 compatible = "arm,cortex-a9"; 1088 reg = <3>; 1089 clocks = <&tegra_car TEGRA30_CLK_CCLK_G>; 1090 }; 1091 }; 1092 1093 pmu { 1094 compatible = "arm,cortex-a9-pmu"; 1095 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1096 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1097 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1098 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 1099 interrupt-affinity = <&{/cpus/cpu@0}>, 1100 <&{/cpus/cpu@1}>, 1101 <&{/cpus/cpu@2}>, 1102 <&{/cpus/cpu@3}>; 1103 }; 1104}; 1105