1// SPDX-License-Identifier: GPL-2.0
2/*
3 * ARM Ltd. Versatile Express
4 *
5 * Motherboard Express uATX
6 * V2M-P1
7 *
8 * HBI-0190D
9 *
10 * Original memory map ("Legacy memory map" in the board's
11 * Technical Reference Manual)
12 *
13 * WARNING! The hardware described in this file is independent from the
14 * RS1 variant (vexpress-v2m-rs1.dtsi), but there is a strong
15 * correspondence between the two configurations.
16 *
17 * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT
18 * CHANGES TO vexpress-v2m-rs1.dtsi!
19 */
20
21/ {
22	bus@4000000 {
23		motherboard {
24			model = "V2M-P1";
25			arm,hbi = <0x190>;
26			arm,vexpress,site = <0>;
27			compatible = "arm,vexpress,v2m-p1", "simple-bus";
28			#address-cells = <2>; /* SMB chipselect number and offset */
29			#size-cells = <1>;
30			#interrupt-cells = <1>;
31			ranges;
32
33			flash@0,00000000 {
34				compatible = "arm,vexpress-flash", "cfi-flash";
35				reg = <0 0x00000000 0x04000000>,
36				      <1 0x00000000 0x04000000>;
37				bank-width = <4>;
38				partitions {
39					compatible = "arm,arm-firmware-suite";
40				};
41			};
42
43			psram@2,00000000 {
44				compatible = "arm,vexpress-psram", "mtd-ram";
45				reg = <2 0x00000000 0x02000000>;
46				bank-width = <4>;
47			};
48
49			ethernet@3,02000000 {
50				compatible = "smsc,lan9118", "smsc,lan9115";
51				reg = <3 0x02000000 0x10000>;
52				interrupts = <15>;
53				phy-mode = "mii";
54				reg-io-width = <4>;
55				smsc,irq-active-high;
56				smsc,irq-push-pull;
57				vdd33a-supply = <&v2m_fixed_3v3>;
58				vddvario-supply = <&v2m_fixed_3v3>;
59			};
60
61			usb@3,03000000 {
62				compatible = "nxp,usb-isp1761";
63				reg = <3 0x03000000 0x20000>;
64				interrupts = <16>;
65				port1-otg;
66			};
67
68			iofpga@7,00000000 {
69				compatible = "simple-bus";
70				#address-cells = <1>;
71				#size-cells = <1>;
72				ranges = <0 7 0 0x20000>;
73
74				v2m_sysreg: sysreg@0 {
75					compatible = "arm,vexpress-sysreg";
76					reg = <0x00000 0x1000>;
77					#address-cells = <1>;
78					#size-cells = <1>;
79					ranges = <0 0 0x1000>;
80
81					v2m_led_gpios: gpio@8 {
82						compatible = "arm,vexpress-sysreg,sys_led";
83						reg = <0x008 4>;
84						gpio-controller;
85						#gpio-cells = <2>;
86					};
87
88					v2m_mmc_gpios: gpio@48 {
89						compatible = "arm,vexpress-sysreg,sys_mci";
90						reg = <0x048 4>;
91						gpio-controller;
92						#gpio-cells = <2>;
93					};
94
95					v2m_flash_gpios: gpio@4c {
96						compatible = "arm,vexpress-sysreg,sys_flash";
97						reg = <0x04c 4>;
98						gpio-controller;
99						#gpio-cells = <2>;
100					};
101				};
102
103				v2m_sysctl: sysctl@1000 {
104					compatible = "arm,sp810", "arm,primecell";
105					reg = <0x01000 0x1000>;
106					clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>;
107					clock-names = "refclk", "timclk", "apb_pclk";
108					#clock-cells = <1>;
109					clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
110					assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>;
111					assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>;
112				};
113
114				/* PCI-E I2C bus */
115				v2m_i2c_pcie: i2c@2000 {
116					compatible = "arm,versatile-i2c";
117					reg = <0x02000 0x1000>;
118
119					#address-cells = <1>;
120					#size-cells = <0>;
121
122					pcie-switch@60 {
123						compatible = "idt,89hpes32h8";
124						reg = <0x60>;
125					};
126				};
127
128				aaci@4000 {
129					compatible = "arm,pl041", "arm,primecell";
130					reg = <0x04000 0x1000>;
131					interrupts = <11>;
132					clocks = <&smbclk>;
133					clock-names = "apb_pclk";
134				};
135
136				mmci@5000 {
137					compatible = "arm,pl180", "arm,primecell";
138					reg = <0x05000 0x1000>;
139					interrupts = <9>, <10>;
140					cd-gpios = <&v2m_mmc_gpios 0 0>;
141					wp-gpios = <&v2m_mmc_gpios 1 0>;
142					max-frequency = <12000000>;
143					vmmc-supply = <&v2m_fixed_3v3>;
144					clocks = <&v2m_clk24mhz>, <&smbclk>;
145					clock-names = "mclk", "apb_pclk";
146				};
147
148				kmi@6000 {
149					compatible = "arm,pl050", "arm,primecell";
150					reg = <0x06000 0x1000>;
151					interrupts = <12>;
152					clocks = <&v2m_clk24mhz>, <&smbclk>;
153					clock-names = "KMIREFCLK", "apb_pclk";
154				};
155
156				kmi@7000 {
157					compatible = "arm,pl050", "arm,primecell";
158					reg = <0x07000 0x1000>;
159					interrupts = <13>;
160					clocks = <&v2m_clk24mhz>, <&smbclk>;
161					clock-names = "KMIREFCLK", "apb_pclk";
162				};
163
164				v2m_serial0: uart@9000 {
165					compatible = "arm,pl011", "arm,primecell";
166					reg = <0x09000 0x1000>;
167					interrupts = <5>;
168					clocks = <&v2m_oscclk2>, <&smbclk>;
169					clock-names = "uartclk", "apb_pclk";
170				};
171
172				v2m_serial1: uart@a000 {
173					compatible = "arm,pl011", "arm,primecell";
174					reg = <0x0a000 0x1000>;
175					interrupts = <6>;
176					clocks = <&v2m_oscclk2>, <&smbclk>;
177					clock-names = "uartclk", "apb_pclk";
178				};
179
180				v2m_serial2: uart@b000 {
181					compatible = "arm,pl011", "arm,primecell";
182					reg = <0x0b000 0x1000>;
183					interrupts = <7>;
184					clocks = <&v2m_oscclk2>, <&smbclk>;
185					clock-names = "uartclk", "apb_pclk";
186				};
187
188				v2m_serial3: uart@c000 {
189					compatible = "arm,pl011", "arm,primecell";
190					reg = <0x0c000 0x1000>;
191					interrupts = <8>;
192					clocks = <&v2m_oscclk2>, <&smbclk>;
193					clock-names = "uartclk", "apb_pclk";
194				};
195
196				wdt@f000 {
197					compatible = "arm,sp805", "arm,primecell";
198					reg = <0x0f000 0x1000>;
199					interrupts = <0>;
200					clocks = <&v2m_refclk32khz>, <&smbclk>;
201					clock-names = "wdog_clk", "apb_pclk";
202				};
203
204				v2m_timer01: timer@11000 {
205					compatible = "arm,sp804", "arm,primecell";
206					reg = <0x11000 0x1000>;
207					interrupts = <2>;
208					clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>;
209					clock-names = "timclken1", "timclken2", "apb_pclk";
210				};
211
212				v2m_timer23: timer@12000 {
213					compatible = "arm,sp804", "arm,primecell";
214					reg = <0x12000 0x1000>;
215					interrupts = <3>;
216					clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>;
217					clock-names = "timclken1", "timclken2", "apb_pclk";
218				};
219
220				/* DVI I2C bus */
221				v2m_i2c_dvi: i2c@16000 {
222					compatible = "arm,versatile-i2c";
223					reg = <0x16000 0x1000>;
224					#address-cells = <1>;
225					#size-cells = <0>;
226
227					dvi-transmitter@39 {
228						compatible = "sil,sii9022-tpi", "sil,sii9022";
229						reg = <0x39>;
230
231						ports {
232							#address-cells = <1>;
233							#size-cells = <0>;
234
235							/*
236							 * Both the core tile and the motherboard routes their output
237							 * pads to this transmitter. The motherboard system controller
238							 * can select one of them as input using a mux register in
239							 * "arm,vexpress-muxfpga". The Vexpress with the CA9 core tile is
240							 * the only platform with this specific set-up.
241							 */
242							port@0 {
243								reg = <0>;
244								dvi_bridge_in_ct: endpoint {
245									remote-endpoint = <&clcd_pads_ct>;
246								};
247							};
248							port@1 {
249								reg = <1>;
250								dvi_bridge_in_mb: endpoint {
251									remote-endpoint = <&clcd_pads_mb>;
252								};
253							};
254						};
255					};
256
257					dvi-transmitter@60 {
258						compatible = "sil,sii9022-cpi", "sil,sii9022";
259						reg = <0x60>;
260					};
261				};
262
263				rtc@17000 {
264					compatible = "arm,pl031", "arm,primecell";
265					reg = <0x17000 0x1000>;
266					interrupts = <4>;
267					clocks = <&smbclk>;
268					clock-names = "apb_pclk";
269				};
270
271				compact-flash@1a000 {
272					compatible = "arm,vexpress-cf", "ata-generic";
273					reg = <0x1a000 0x100
274					       0x1a100 0xf00>;
275					reg-shift = <2>;
276				};
277
278
279				clcd@1f000 {
280					compatible = "arm,pl111", "arm,primecell";
281					reg = <0x1f000 0x1000>;
282					interrupt-names = "combined";
283					interrupts = <14>;
284					clocks = <&v2m_oscclk1>, <&smbclk>;
285					clock-names = "clcdclk", "apb_pclk";
286					/* 800x600 16bpp @36MHz works fine */
287					max-memory-bandwidth = <54000000>;
288					memory-region = <&vram>;
289
290					port {
291						clcd_pads_mb: endpoint {
292							remote-endpoint = <&dvi_bridge_in_mb>;
293							arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
294						};
295					};
296				};
297			};
298
299			v2m_fixed_3v3: fixed-regulator-0 {
300				compatible = "regulator-fixed";
301				regulator-name = "3V3";
302				regulator-min-microvolt = <3300000>;
303				regulator-max-microvolt = <3300000>;
304				regulator-always-on;
305			};
306
307			v2m_clk24mhz: clk24mhz {
308				compatible = "fixed-clock";
309				#clock-cells = <0>;
310				clock-frequency = <24000000>;
311				clock-output-names = "v2m:clk24mhz";
312			};
313
314			v2m_refclk1mhz: refclk1mhz {
315				compatible = "fixed-clock";
316				#clock-cells = <0>;
317				clock-frequency = <1000000>;
318				clock-output-names = "v2m:refclk1mhz";
319			};
320
321			v2m_refclk32khz: refclk32khz {
322				compatible = "fixed-clock";
323				#clock-cells = <0>;
324				clock-frequency = <32768>;
325				clock-output-names = "v2m:refclk32khz";
326			};
327
328			leds {
329				compatible = "gpio-leds";
330
331				user1 {
332					label = "v2m:green:user1";
333					gpios = <&v2m_led_gpios 0 0>;
334					linux,default-trigger = "heartbeat";
335				};
336
337				user2 {
338					label = "v2m:green:user2";
339					gpios = <&v2m_led_gpios 1 0>;
340					linux,default-trigger = "mmc0";
341				};
342
343				user3 {
344					label = "v2m:green:user3";
345					gpios = <&v2m_led_gpios 2 0>;
346					linux,default-trigger = "cpu0";
347				};
348
349				user4 {
350					label = "v2m:green:user4";
351					gpios = <&v2m_led_gpios 3 0>;
352					linux,default-trigger = "cpu1";
353				};
354
355				user5 {
356					label = "v2m:green:user5";
357					gpios = <&v2m_led_gpios 4 0>;
358					linux,default-trigger = "cpu2";
359				};
360
361				user6 {
362					label = "v2m:green:user6";
363					gpios = <&v2m_led_gpios 5 0>;
364					linux,default-trigger = "cpu3";
365				};
366
367				user7 {
368					label = "v2m:green:user7";
369					gpios = <&v2m_led_gpios 6 0>;
370					linux,default-trigger = "cpu4";
371				};
372
373				user8 {
374					label = "v2m:green:user8";
375					gpios = <&v2m_led_gpios 7 0>;
376					linux,default-trigger = "cpu5";
377				};
378			};
379
380			mcc {
381				compatible = "arm,vexpress,config-bus";
382				arm,vexpress,config-bridge = <&v2m_sysreg>;
383
384				oscclk0 {
385					/* MCC static memory clock */
386					compatible = "arm,vexpress-osc";
387					arm,vexpress-sysreg,func = <1 0>;
388					freq-range = <25000000 60000000>;
389					#clock-cells = <0>;
390					clock-output-names = "v2m:oscclk0";
391				};
392
393				v2m_oscclk1: oscclk1 {
394					/* CLCD clock */
395					compatible = "arm,vexpress-osc";
396					arm,vexpress-sysreg,func = <1 1>;
397					freq-range = <23750000 65000000>;
398					#clock-cells = <0>;
399					clock-output-names = "v2m:oscclk1";
400				};
401
402				v2m_oscclk2: oscclk2 {
403					/* IO FPGA peripheral clock */
404					compatible = "arm,vexpress-osc";
405					arm,vexpress-sysreg,func = <1 2>;
406					freq-range = <24000000 24000000>;
407					#clock-cells = <0>;
408					clock-output-names = "v2m:oscclk2";
409				};
410
411				volt-vio {
412					/* Logic level voltage */
413					compatible = "arm,vexpress-volt";
414					arm,vexpress-sysreg,func = <2 0>;
415					regulator-name = "VIO";
416					regulator-always-on;
417					label = "VIO";
418				};
419
420				temp-mcc {
421					/* MCC internal operating temperature */
422					compatible = "arm,vexpress-temp";
423					arm,vexpress-sysreg,func = <4 0>;
424					label = "MCC";
425				};
426
427				reset {
428					compatible = "arm,vexpress-reset";
429					arm,vexpress-sysreg,func = <5 0>;
430				};
431
432				muxfpga {
433					compatible = "arm,vexpress-muxfpga";
434					arm,vexpress-sysreg,func = <7 0>;
435				};
436
437				shutdown {
438					compatible = "arm,vexpress-shutdown";
439					arm,vexpress-sysreg,func = <8 0>;
440				};
441
442				reboot {
443					compatible = "arm,vexpress-reboot";
444					arm,vexpress-sysreg,func = <9 0>;
445				};
446
447				dvimode {
448					compatible = "arm,vexpress-dvimode";
449					arm,vexpress-sysreg,func = <11 0>;
450				};
451			};
452		};
453	};
454};
455