1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
3 */
4
5 #include <linux/kernel.h>
6 #include <linux/init.h>
7 #include <linux/err.h>
8 #include <linux/ctype.h>
9 #include <linux/io.h>
10 #include <linux/of.h>
11 #include <linux/platform_device.h>
12 #include <linux/module.h>
13 #include <linux/regmap.h>
14
15 #include <dt-bindings/clock/qcom,gcc-msm8994.h>
16
17 #include "common.h"
18 #include "clk-regmap.h"
19 #include "clk-alpha-pll.h"
20 #include "clk-rcg.h"
21 #include "clk-branch.h"
22 #include "reset.h"
23 #include "gdsc.h"
24
25 enum {
26 P_XO,
27 P_GPLL0,
28 P_GPLL4,
29 };
30
31 static const struct parent_map gcc_xo_gpll0_map[] = {
32 { P_XO, 0 },
33 { P_GPLL0, 1 },
34 };
35
36 static const char * const gcc_xo_gpll0[] = {
37 "xo",
38 "gpll0",
39 };
40
41 static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
42 { P_XO, 0 },
43 { P_GPLL0, 1 },
44 { P_GPLL4, 5 },
45 };
46
47 static const char * const gcc_xo_gpll0_gpll4[] = {
48 "xo",
49 "gpll0",
50 "gpll4",
51 };
52
53 static struct clk_fixed_factor xo = {
54 .mult = 1,
55 .div = 1,
56 .hw.init = &(struct clk_init_data)
57 {
58 .name = "xo",
59 .parent_names = (const char *[]) { "xo_board" },
60 .num_parents = 1,
61 .ops = &clk_fixed_factor_ops,
62 },
63 };
64
65 static struct clk_alpha_pll gpll0_early = {
66 .offset = 0x00000,
67 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
68 .clkr = {
69 .enable_reg = 0x1480,
70 .enable_mask = BIT(0),
71 .hw.init = &(struct clk_init_data)
72 {
73 .name = "gpll0_early",
74 .parent_names = (const char *[]) { "xo" },
75 .num_parents = 1,
76 .ops = &clk_alpha_pll_ops,
77 },
78 },
79 };
80
81 static struct clk_alpha_pll_postdiv gpll0 = {
82 .offset = 0x00000,
83 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
84 .clkr.hw.init = &(struct clk_init_data)
85 {
86 .name = "gpll0",
87 .parent_names = (const char *[]) { "gpll0_early" },
88 .num_parents = 1,
89 .ops = &clk_alpha_pll_postdiv_ops,
90 },
91 };
92
93 static struct clk_alpha_pll gpll4_early = {
94 .offset = 0x1dc0,
95 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
96 .clkr = {
97 .enable_reg = 0x1480,
98 .enable_mask = BIT(4),
99 .hw.init = &(struct clk_init_data)
100 {
101 .name = "gpll4_early",
102 .parent_names = (const char *[]) { "xo" },
103 .num_parents = 1,
104 .ops = &clk_alpha_pll_ops,
105 },
106 },
107 };
108
109 static struct clk_alpha_pll_postdiv gpll4 = {
110 .offset = 0x1dc0,
111 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
112 .clkr.hw.init = &(struct clk_init_data)
113 {
114 .name = "gpll4",
115 .parent_names = (const char *[]) { "gpll4_early" },
116 .num_parents = 1,
117 .ops = &clk_alpha_pll_postdiv_ops,
118 },
119 };
120
121 static struct freq_tbl ftbl_ufs_axi_clk_src[] = {
122 F(50000000, P_GPLL0, 12, 0, 0),
123 F(100000000, P_GPLL0, 6, 0, 0),
124 F(150000000, P_GPLL0, 4, 0, 0),
125 F(171430000, P_GPLL0, 3.5, 0, 0),
126 F(200000000, P_GPLL0, 3, 0, 0),
127 F(240000000, P_GPLL0, 2.5, 0, 0),
128 { }
129 };
130
131 static struct clk_rcg2 ufs_axi_clk_src = {
132 .cmd_rcgr = 0x1d68,
133 .mnd_width = 8,
134 .hid_width = 5,
135 .parent_map = gcc_xo_gpll0_map,
136 .freq_tbl = ftbl_ufs_axi_clk_src,
137 .clkr.hw.init = &(struct clk_init_data)
138 {
139 .name = "ufs_axi_clk_src",
140 .parent_names = gcc_xo_gpll0,
141 .num_parents = 2,
142 .ops = &clk_rcg2_ops,
143 },
144 };
145
146 static struct freq_tbl ftbl_usb30_master_clk_src[] = {
147 F(19200000, P_XO, 1, 0, 0),
148 F(125000000, P_GPLL0, 1, 5, 24),
149 { }
150 };
151
152 static struct clk_rcg2 usb30_master_clk_src = {
153 .cmd_rcgr = 0x03d4,
154 .mnd_width = 8,
155 .hid_width = 5,
156 .parent_map = gcc_xo_gpll0_map,
157 .freq_tbl = ftbl_usb30_master_clk_src,
158 .clkr.hw.init = &(struct clk_init_data)
159 {
160 .name = "usb30_master_clk_src",
161 .parent_names = gcc_xo_gpll0,
162 .num_parents = 2,
163 .ops = &clk_rcg2_ops,
164 },
165 };
166
167 static struct freq_tbl ftbl_blsp_i2c_apps_clk_src[] = {
168 F(19200000, P_XO, 1, 0, 0),
169 F(50000000, P_GPLL0, 12, 0, 0),
170 { }
171 };
172
173 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
174 .cmd_rcgr = 0x0660,
175 .hid_width = 5,
176 .parent_map = gcc_xo_gpll0_map,
177 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
178 .clkr.hw.init = &(struct clk_init_data)
179 {
180 .name = "blsp1_qup1_i2c_apps_clk_src",
181 .parent_names = gcc_xo_gpll0,
182 .num_parents = 2,
183 .ops = &clk_rcg2_ops,
184 },
185 };
186
187 static struct freq_tbl ftbl_blspqup_spi_apps_clk_src[] = {
188 F(960000, P_XO, 10, 1, 2),
189 F(4800000, P_XO, 4, 0, 0),
190 F(9600000, P_XO, 2, 0, 0),
191 F(15000000, P_GPLL0, 10, 1, 4),
192 F(19200000, P_XO, 1, 0, 0),
193 F(24000000, P_GPLL0, 12.5, 1, 2),
194 F(25000000, P_GPLL0, 12, 1, 2),
195 F(48000000, P_GPLL0, 12.5, 0, 0),
196 F(50000000, P_GPLL0, 12, 0, 0),
197 { }
198 };
199
200 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
201 .cmd_rcgr = 0x064c,
202 .mnd_width = 8,
203 .hid_width = 5,
204 .parent_map = gcc_xo_gpll0_map,
205 .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
206 .clkr.hw.init = &(struct clk_init_data)
207 {
208 .name = "blsp1_qup1_spi_apps_clk_src",
209 .parent_names = gcc_xo_gpll0,
210 .num_parents = 2,
211 .ops = &clk_rcg2_ops,
212 },
213 };
214
215 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
216 .cmd_rcgr = 0x06e0,
217 .hid_width = 5,
218 .parent_map = gcc_xo_gpll0_map,
219 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
220 .clkr.hw.init = &(struct clk_init_data)
221 {
222 .name = "blsp1_qup2_i2c_apps_clk_src",
223 .parent_names = gcc_xo_gpll0,
224 .num_parents = 2,
225 .ops = &clk_rcg2_ops,
226 },
227 };
228
229 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
230 .cmd_rcgr = 0x06cc,
231 .mnd_width = 8,
232 .hid_width = 5,
233 .parent_map = gcc_xo_gpll0_map,
234 .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
235 .clkr.hw.init = &(struct clk_init_data)
236 {
237 .name = "blsp1_qup2_spi_apps_clk_src",
238 .parent_names = gcc_xo_gpll0,
239 .num_parents = 2,
240 .ops = &clk_rcg2_ops,
241 },
242 };
243
244 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
245 .cmd_rcgr = 0x0760,
246 .hid_width = 5,
247 .parent_map = gcc_xo_gpll0_map,
248 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
249 .clkr.hw.init = &(struct clk_init_data)
250 {
251 .name = "blsp1_qup3_i2c_apps_clk_src",
252 .parent_names = gcc_xo_gpll0,
253 .num_parents = 2,
254 .ops = &clk_rcg2_ops,
255 },
256 };
257
258 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
259 .cmd_rcgr = 0x074c,
260 .mnd_width = 8,
261 .hid_width = 5,
262 .parent_map = gcc_xo_gpll0_map,
263 .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
264 .clkr.hw.init = &(struct clk_init_data)
265 {
266 .name = "blsp1_qup3_spi_apps_clk_src",
267 .parent_names = gcc_xo_gpll0,
268 .num_parents = 2,
269 .ops = &clk_rcg2_ops,
270 },
271 };
272
273 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
274 .cmd_rcgr = 0x07e0,
275 .hid_width = 5,
276 .parent_map = gcc_xo_gpll0_map,
277 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
278 .clkr.hw.init = &(struct clk_init_data)
279 {
280 .name = "blsp1_qup4_i2c_apps_clk_src",
281 .parent_names = gcc_xo_gpll0,
282 .num_parents = 2,
283 .ops = &clk_rcg2_ops,
284 },
285 };
286
287 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
288 .cmd_rcgr = 0x07cc,
289 .mnd_width = 8,
290 .hid_width = 5,
291 .parent_map = gcc_xo_gpll0_map,
292 .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
293 .clkr.hw.init = &(struct clk_init_data)
294 {
295 .name = "blsp1_qup4_spi_apps_clk_src",
296 .parent_names = gcc_xo_gpll0,
297 .num_parents = 2,
298 .ops = &clk_rcg2_ops,
299 },
300 };
301
302 static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
303 .cmd_rcgr = 0x0860,
304 .hid_width = 5,
305 .parent_map = gcc_xo_gpll0_map,
306 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
307 .clkr.hw.init = &(struct clk_init_data)
308 {
309 .name = "blsp1_qup5_i2c_apps_clk_src",
310 .parent_names = gcc_xo_gpll0,
311 .num_parents = 2,
312 .ops = &clk_rcg2_ops,
313 },
314 };
315
316 static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
317 .cmd_rcgr = 0x084c,
318 .mnd_width = 8,
319 .hid_width = 5,
320 .parent_map = gcc_xo_gpll0_map,
321 .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
322 .clkr.hw.init = &(struct clk_init_data)
323 {
324 .name = "blsp1_qup5_spi_apps_clk_src",
325 .parent_names = gcc_xo_gpll0,
326 .num_parents = 2,
327 .ops = &clk_rcg2_ops,
328 },
329 };
330
331 static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
332 .cmd_rcgr = 0x08e0,
333 .hid_width = 5,
334 .parent_map = gcc_xo_gpll0_map,
335 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
336 .clkr.hw.init = &(struct clk_init_data)
337 {
338 .name = "blsp1_qup6_i2c_apps_clk_src",
339 .parent_names = gcc_xo_gpll0,
340 .num_parents = 2,
341 .ops = &clk_rcg2_ops,
342 },
343 };
344
345 static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
346 .cmd_rcgr = 0x08cc,
347 .mnd_width = 8,
348 .hid_width = 5,
349 .parent_map = gcc_xo_gpll0_map,
350 .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
351 .clkr.hw.init = &(struct clk_init_data)
352 {
353 .name = "blsp1_qup6_spi_apps_clk_src",
354 .parent_names = gcc_xo_gpll0,
355 .num_parents = 2,
356 .ops = &clk_rcg2_ops,
357 },
358 };
359
360 static struct freq_tbl ftbl_blsp_uart_apps_clk_src[] = {
361 F(3686400, P_GPLL0, 1, 96, 15625),
362 F(7372800, P_GPLL0, 1, 192, 15625),
363 F(14745600, P_GPLL0, 1, 384, 15625),
364 F(16000000, P_GPLL0, 5, 2, 15),
365 F(19200000, P_XO, 1, 0, 0),
366 F(24000000, P_GPLL0, 5, 1, 5),
367 F(32000000, P_GPLL0, 1, 4, 75),
368 F(40000000, P_GPLL0, 15, 0, 0),
369 F(46400000, P_GPLL0, 1, 29, 375),
370 F(48000000, P_GPLL0, 12.5, 0, 0),
371 F(51200000, P_GPLL0, 1, 32, 375),
372 F(56000000, P_GPLL0, 1, 7, 75),
373 F(58982400, P_GPLL0, 1, 1536, 15625),
374 F(60000000, P_GPLL0, 10, 0, 0),
375 F(63160000, P_GPLL0, 9.5, 0, 0),
376 { }
377 };
378
379 static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
380 .cmd_rcgr = 0x068c,
381 .mnd_width = 16,
382 .hid_width = 5,
383 .parent_map = gcc_xo_gpll0_map,
384 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
385 .clkr.hw.init = &(struct clk_init_data)
386 {
387 .name = "blsp1_uart1_apps_clk_src",
388 .parent_names = gcc_xo_gpll0,
389 .num_parents = 2,
390 .ops = &clk_rcg2_ops,
391 },
392 };
393
394 static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
395 .cmd_rcgr = 0x070c,
396 .mnd_width = 16,
397 .hid_width = 5,
398 .parent_map = gcc_xo_gpll0_map,
399 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
400 .clkr.hw.init = &(struct clk_init_data)
401 {
402 .name = "blsp1_uart2_apps_clk_src",
403 .parent_names = gcc_xo_gpll0,
404 .num_parents = 2,
405 .ops = &clk_rcg2_ops,
406 },
407 };
408
409 static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
410 .cmd_rcgr = 0x078c,
411 .mnd_width = 16,
412 .hid_width = 5,
413 .parent_map = gcc_xo_gpll0_map,
414 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
415 .clkr.hw.init = &(struct clk_init_data)
416 {
417 .name = "blsp1_uart3_apps_clk_src",
418 .parent_names = gcc_xo_gpll0,
419 .num_parents = 2,
420 .ops = &clk_rcg2_ops,
421 },
422 };
423
424 static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
425 .cmd_rcgr = 0x080c,
426 .mnd_width = 16,
427 .hid_width = 5,
428 .parent_map = gcc_xo_gpll0_map,
429 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
430 .clkr.hw.init = &(struct clk_init_data)
431 {
432 .name = "blsp1_uart4_apps_clk_src",
433 .parent_names = gcc_xo_gpll0,
434 .num_parents = 2,
435 .ops = &clk_rcg2_ops,
436 },
437 };
438
439 static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
440 .cmd_rcgr = 0x088c,
441 .mnd_width = 16,
442 .hid_width = 5,
443 .parent_map = gcc_xo_gpll0_map,
444 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
445 .clkr.hw.init = &(struct clk_init_data)
446 {
447 .name = "blsp1_uart5_apps_clk_src",
448 .parent_names = gcc_xo_gpll0,
449 .num_parents = 2,
450 .ops = &clk_rcg2_ops,
451 },
452 };
453
454 static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
455 .cmd_rcgr = 0x090c,
456 .mnd_width = 16,
457 .hid_width = 5,
458 .parent_map = gcc_xo_gpll0_map,
459 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
460 .clkr.hw.init = &(struct clk_init_data)
461 {
462 .name = "blsp1_uart6_apps_clk_src",
463 .parent_names = gcc_xo_gpll0,
464 .num_parents = 2,
465 .ops = &clk_rcg2_ops,
466 },
467 };
468
469 static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
470 .cmd_rcgr = 0x09a0,
471 .hid_width = 5,
472 .parent_map = gcc_xo_gpll0_map,
473 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
474 .clkr.hw.init = &(struct clk_init_data)
475 {
476 .name = "blsp2_qup1_i2c_apps_clk_src",
477 .parent_names = gcc_xo_gpll0,
478 .num_parents = 2,
479 .ops = &clk_rcg2_ops,
480 },
481 };
482
483 static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
484 .cmd_rcgr = 0x098c,
485 .mnd_width = 8,
486 .hid_width = 5,
487 .parent_map = gcc_xo_gpll0_map,
488 .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
489 .clkr.hw.init = &(struct clk_init_data)
490 {
491 .name = "blsp2_qup1_spi_apps_clk_src",
492 .parent_names = gcc_xo_gpll0,
493 .num_parents = 2,
494 .ops = &clk_rcg2_ops,
495 },
496 };
497
498 static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
499 .cmd_rcgr = 0x0a20,
500 .hid_width = 5,
501 .parent_map = gcc_xo_gpll0_map,
502 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
503 .clkr.hw.init = &(struct clk_init_data)
504 {
505 .name = "blsp2_qup2_i2c_apps_clk_src",
506 .parent_names = gcc_xo_gpll0,
507 .num_parents = 2,
508 .ops = &clk_rcg2_ops,
509 },
510 };
511
512 static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
513 .cmd_rcgr = 0x0a0c,
514 .mnd_width = 8,
515 .hid_width = 5,
516 .parent_map = gcc_xo_gpll0_map,
517 .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
518 .clkr.hw.init = &(struct clk_init_data)
519 {
520 .name = "blsp2_qup2_spi_apps_clk_src",
521 .parent_names = gcc_xo_gpll0,
522 .num_parents = 2,
523 .ops = &clk_rcg2_ops,
524 },
525 };
526
527 static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
528 .cmd_rcgr = 0x0aa0,
529 .hid_width = 5,
530 .parent_map = gcc_xo_gpll0_map,
531 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
532 .clkr.hw.init = &(struct clk_init_data)
533 {
534 .name = "blsp2_qup3_i2c_apps_clk_src",
535 .parent_names = gcc_xo_gpll0,
536 .num_parents = 2,
537 .ops = &clk_rcg2_ops,
538 },
539 };
540
541 static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
542 .cmd_rcgr = 0x0a8c,
543 .mnd_width = 8,
544 .hid_width = 5,
545 .parent_map = gcc_xo_gpll0_map,
546 .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
547 .clkr.hw.init = &(struct clk_init_data)
548 {
549 .name = "blsp2_qup3_spi_apps_clk_src",
550 .parent_names = gcc_xo_gpll0,
551 .num_parents = 2,
552 .ops = &clk_rcg2_ops,
553 },
554 };
555
556 static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
557 .cmd_rcgr = 0x0b20,
558 .hid_width = 5,
559 .parent_map = gcc_xo_gpll0_map,
560 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
561 .clkr.hw.init = &(struct clk_init_data)
562 {
563 .name = "blsp2_qup4_i2c_apps_clk_src",
564 .parent_names = gcc_xo_gpll0,
565 .num_parents = 2,
566 .ops = &clk_rcg2_ops,
567 },
568 };
569
570 static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
571 .cmd_rcgr = 0x0b0c,
572 .mnd_width = 8,
573 .hid_width = 5,
574 .parent_map = gcc_xo_gpll0_map,
575 .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
576 .clkr.hw.init = &(struct clk_init_data)
577 {
578 .name = "blsp2_qup4_spi_apps_clk_src",
579 .parent_names = gcc_xo_gpll0,
580 .num_parents = 2,
581 .ops = &clk_rcg2_ops,
582 },
583 };
584
585 static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
586 .cmd_rcgr = 0x0ba0,
587 .hid_width = 5,
588 .parent_map = gcc_xo_gpll0_map,
589 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
590 .clkr.hw.init = &(struct clk_init_data)
591 {
592 .name = "blsp2_qup5_i2c_apps_clk_src",
593 .parent_names = gcc_xo_gpll0,
594 .num_parents = 2,
595 .ops = &clk_rcg2_ops,
596 },
597 };
598
599 static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
600 .cmd_rcgr = 0x0b8c,
601 .mnd_width = 8,
602 .hid_width = 5,
603 .parent_map = gcc_xo_gpll0_map,
604 .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
605 .clkr.hw.init = &(struct clk_init_data)
606 {
607 .name = "blsp2_qup5_spi_apps_clk_src",
608 .parent_names = gcc_xo_gpll0,
609 .num_parents = 2,
610 .ops = &clk_rcg2_ops,
611 },
612 };
613
614 static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
615 .cmd_rcgr = 0x0c20,
616 .hid_width = 5,
617 .parent_map = gcc_xo_gpll0_map,
618 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
619 .clkr.hw.init = &(struct clk_init_data)
620 {
621 .name = "blsp2_qup6_i2c_apps_clk_src",
622 .parent_names = gcc_xo_gpll0,
623 .num_parents = 2,
624 .ops = &clk_rcg2_ops,
625 },
626 };
627
628 static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
629 .cmd_rcgr = 0x0c0c,
630 .mnd_width = 8,
631 .hid_width = 5,
632 .parent_map = gcc_xo_gpll0_map,
633 .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
634 .clkr.hw.init = &(struct clk_init_data)
635 {
636 .name = "blsp2_qup6_spi_apps_clk_src",
637 .parent_names = gcc_xo_gpll0,
638 .num_parents = 2,
639 .ops = &clk_rcg2_ops,
640 },
641 };
642
643 static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
644 .cmd_rcgr = 0x09cc,
645 .mnd_width = 16,
646 .hid_width = 5,
647 .parent_map = gcc_xo_gpll0_map,
648 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
649 .clkr.hw.init = &(struct clk_init_data)
650 {
651 .name = "blsp2_uart1_apps_clk_src",
652 .parent_names = gcc_xo_gpll0,
653 .num_parents = 2,
654 .ops = &clk_rcg2_ops,
655 },
656 };
657
658 static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
659 .cmd_rcgr = 0x0a4c,
660 .mnd_width = 16,
661 .hid_width = 5,
662 .parent_map = gcc_xo_gpll0_map,
663 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
664 .clkr.hw.init = &(struct clk_init_data)
665 {
666 .name = "blsp2_uart2_apps_clk_src",
667 .parent_names = gcc_xo_gpll0,
668 .num_parents = 2,
669 .ops = &clk_rcg2_ops,
670 },
671 };
672
673 static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
674 .cmd_rcgr = 0x0acc,
675 .mnd_width = 16,
676 .hid_width = 5,
677 .parent_map = gcc_xo_gpll0_map,
678 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
679 .clkr.hw.init = &(struct clk_init_data)
680 {
681 .name = "blsp2_uart3_apps_clk_src",
682 .parent_names = gcc_xo_gpll0,
683 .num_parents = 2,
684 .ops = &clk_rcg2_ops,
685 },
686 };
687
688 static struct clk_rcg2 blsp2_uart4_apps_clk_src = {
689 .cmd_rcgr = 0x0b4c,
690 .mnd_width = 16,
691 .hid_width = 5,
692 .parent_map = gcc_xo_gpll0_map,
693 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
694 .clkr.hw.init = &(struct clk_init_data)
695 {
696 .name = "blsp2_uart4_apps_clk_src",
697 .parent_names = gcc_xo_gpll0,
698 .num_parents = 2,
699 .ops = &clk_rcg2_ops,
700 },
701 };
702
703 static struct clk_rcg2 blsp2_uart5_apps_clk_src = {
704 .cmd_rcgr = 0x0bcc,
705 .mnd_width = 16,
706 .hid_width = 5,
707 .parent_map = gcc_xo_gpll0_map,
708 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
709 .clkr.hw.init = &(struct clk_init_data)
710 {
711 .name = "blsp2_uart5_apps_clk_src",
712 .parent_names = gcc_xo_gpll0,
713 .num_parents = 2,
714 .ops = &clk_rcg2_ops,
715 },
716 };
717
718 static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
719 .cmd_rcgr = 0x0c4c,
720 .mnd_width = 16,
721 .hid_width = 5,
722 .parent_map = gcc_xo_gpll0_map,
723 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
724 .clkr.hw.init = &(struct clk_init_data)
725 {
726 .name = "blsp2_uart6_apps_clk_src",
727 .parent_names = gcc_xo_gpll0,
728 .num_parents = 2,
729 .ops = &clk_rcg2_ops,
730 },
731 };
732
733 static struct freq_tbl ftbl_gp1_clk_src[] = {
734 F(19200000, P_XO, 1, 0, 0),
735 F(100000000, P_GPLL0, 6, 0, 0),
736 F(200000000, P_GPLL0, 3, 0, 0),
737 { }
738 };
739
740 static struct clk_rcg2 gp1_clk_src = {
741 .cmd_rcgr = 0x1904,
742 .mnd_width = 8,
743 .hid_width = 5,
744 .parent_map = gcc_xo_gpll0_map,
745 .freq_tbl = ftbl_gp1_clk_src,
746 .clkr.hw.init = &(struct clk_init_data)
747 {
748 .name = "gp1_clk_src",
749 .parent_names = gcc_xo_gpll0,
750 .num_parents = 2,
751 .ops = &clk_rcg2_ops,
752 },
753 };
754
755 static struct freq_tbl ftbl_gp2_clk_src[] = {
756 F(19200000, P_XO, 1, 0, 0),
757 F(100000000, P_GPLL0, 6, 0, 0),
758 F(200000000, P_GPLL0, 3, 0, 0),
759 { }
760 };
761
762 static struct clk_rcg2 gp2_clk_src = {
763 .cmd_rcgr = 0x1944,
764 .mnd_width = 8,
765 .hid_width = 5,
766 .parent_map = gcc_xo_gpll0_map,
767 .freq_tbl = ftbl_gp2_clk_src,
768 .clkr.hw.init = &(struct clk_init_data)
769 {
770 .name = "gp2_clk_src",
771 .parent_names = gcc_xo_gpll0,
772 .num_parents = 2,
773 .ops = &clk_rcg2_ops,
774 },
775 };
776
777 static struct freq_tbl ftbl_gp3_clk_src[] = {
778 F(19200000, P_XO, 1, 0, 0),
779 F(100000000, P_GPLL0, 6, 0, 0),
780 F(200000000, P_GPLL0, 3, 0, 0),
781 { }
782 };
783
784 static struct clk_rcg2 gp3_clk_src = {
785 .cmd_rcgr = 0x1984,
786 .mnd_width = 8,
787 .hid_width = 5,
788 .parent_map = gcc_xo_gpll0_map,
789 .freq_tbl = ftbl_gp3_clk_src,
790 .clkr.hw.init = &(struct clk_init_data)
791 {
792 .name = "gp3_clk_src",
793 .parent_names = gcc_xo_gpll0,
794 .num_parents = 2,
795 .ops = &clk_rcg2_ops,
796 },
797 };
798
799 static struct freq_tbl ftbl_pcie_0_aux_clk_src[] = {
800 F(1011000, P_XO, 1, 1, 19),
801 { }
802 };
803
804 static struct clk_rcg2 pcie_0_aux_clk_src = {
805 .cmd_rcgr = 0x1b00,
806 .mnd_width = 8,
807 .hid_width = 5,
808 .freq_tbl = ftbl_pcie_0_aux_clk_src,
809 .clkr.hw.init = &(struct clk_init_data)
810 {
811 .name = "pcie_0_aux_clk_src",
812 .parent_names = (const char *[]) { "xo" },
813 .num_parents = 1,
814 .ops = &clk_rcg2_ops,
815 },
816 };
817
818 static struct freq_tbl ftbl_pcie_pipe_clk_src[] = {
819 F(125000000, P_XO, 1, 0, 0),
820 { }
821 };
822
823 static struct clk_rcg2 pcie_0_pipe_clk_src = {
824 .cmd_rcgr = 0x1adc,
825 .hid_width = 5,
826 .freq_tbl = ftbl_pcie_pipe_clk_src,
827 .clkr.hw.init = &(struct clk_init_data)
828 {
829 .name = "pcie_0_pipe_clk_src",
830 .parent_names = (const char *[]) { "xo" },
831 .num_parents = 1,
832 .ops = &clk_rcg2_ops,
833 },
834 };
835
836 static struct freq_tbl ftbl_pcie_1_aux_clk_src[] = {
837 F(1011000, P_XO, 1, 1, 19),
838 { }
839 };
840
841 static struct clk_rcg2 pcie_1_aux_clk_src = {
842 .cmd_rcgr = 0x1b80,
843 .mnd_width = 8,
844 .hid_width = 5,
845 .freq_tbl = ftbl_pcie_1_aux_clk_src,
846 .clkr.hw.init = &(struct clk_init_data)
847 {
848 .name = "pcie_1_aux_clk_src",
849 .parent_names = (const char *[]) { "xo" },
850 .num_parents = 1,
851 .ops = &clk_rcg2_ops,
852 },
853 };
854
855 static struct clk_rcg2 pcie_1_pipe_clk_src = {
856 .cmd_rcgr = 0x1b5c,
857 .hid_width = 5,
858 .freq_tbl = ftbl_pcie_pipe_clk_src,
859 .clkr.hw.init = &(struct clk_init_data)
860 {
861 .name = "pcie_1_pipe_clk_src",
862 .parent_names = (const char *[]) { "xo" },
863 .num_parents = 1,
864 .ops = &clk_rcg2_ops,
865 },
866 };
867
868 static struct freq_tbl ftbl_pdm2_clk_src[] = {
869 F(60000000, P_GPLL0, 10, 0, 0),
870 { }
871 };
872
873 static struct clk_rcg2 pdm2_clk_src = {
874 .cmd_rcgr = 0x0cd0,
875 .hid_width = 5,
876 .parent_map = gcc_xo_gpll0_map,
877 .freq_tbl = ftbl_pdm2_clk_src,
878 .clkr.hw.init = &(struct clk_init_data)
879 {
880 .name = "pdm2_clk_src",
881 .parent_names = gcc_xo_gpll0,
882 .num_parents = 2,
883 .ops = &clk_rcg2_ops,
884 },
885 };
886
887 static struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
888 F(144000, P_XO, 16, 3, 25),
889 F(400000, P_XO, 12, 1, 4),
890 F(20000000, P_GPLL0, 15, 1, 2),
891 F(25000000, P_GPLL0, 12, 1, 2),
892 F(50000000, P_GPLL0, 12, 0, 0),
893 F(100000000, P_GPLL0, 6, 0, 0),
894 F(192000000, P_GPLL4, 2, 0, 0),
895 F(384000000, P_GPLL4, 1, 0, 0),
896 { }
897 };
898
899 static struct clk_rcg2 sdcc1_apps_clk_src = {
900 .cmd_rcgr = 0x04d0,
901 .mnd_width = 8,
902 .hid_width = 5,
903 .parent_map = gcc_xo_gpll0_gpll4_map,
904 .freq_tbl = ftbl_sdcc1_apps_clk_src,
905 .clkr.hw.init = &(struct clk_init_data)
906 {
907 .name = "sdcc1_apps_clk_src",
908 .parent_names = gcc_xo_gpll0_gpll4,
909 .num_parents = 3,
910 .ops = &clk_rcg2_floor_ops,
911 },
912 };
913
914 static struct freq_tbl ftbl_sdcc2_4_apps_clk_src[] = {
915 F(144000, P_XO, 16, 3, 25),
916 F(400000, P_XO, 12, 1, 4),
917 F(20000000, P_GPLL0, 15, 1, 2),
918 F(25000000, P_GPLL0, 12, 1, 2),
919 F(50000000, P_GPLL0, 12, 0, 0),
920 F(100000000, P_GPLL0, 6, 0, 0),
921 F(200000000, P_GPLL0, 3, 0, 0),
922 { }
923 };
924
925 static struct clk_rcg2 sdcc2_apps_clk_src = {
926 .cmd_rcgr = 0x0510,
927 .mnd_width = 8,
928 .hid_width = 5,
929 .parent_map = gcc_xo_gpll0_map,
930 .freq_tbl = ftbl_sdcc2_4_apps_clk_src,
931 .clkr.hw.init = &(struct clk_init_data)
932 {
933 .name = "sdcc2_apps_clk_src",
934 .parent_names = gcc_xo_gpll0,
935 .num_parents = 2,
936 .ops = &clk_rcg2_floor_ops,
937 },
938 };
939
940 static struct clk_rcg2 sdcc3_apps_clk_src = {
941 .cmd_rcgr = 0x0550,
942 .mnd_width = 8,
943 .hid_width = 5,
944 .parent_map = gcc_xo_gpll0_map,
945 .freq_tbl = ftbl_sdcc2_4_apps_clk_src,
946 .clkr.hw.init = &(struct clk_init_data)
947 {
948 .name = "sdcc3_apps_clk_src",
949 .parent_names = gcc_xo_gpll0,
950 .num_parents = 2,
951 .ops = &clk_rcg2_floor_ops,
952 },
953 };
954
955 static struct clk_rcg2 sdcc4_apps_clk_src = {
956 .cmd_rcgr = 0x0590,
957 .mnd_width = 8,
958 .hid_width = 5,
959 .parent_map = gcc_xo_gpll0_map,
960 .freq_tbl = ftbl_sdcc2_4_apps_clk_src,
961 .clkr.hw.init = &(struct clk_init_data)
962 {
963 .name = "sdcc4_apps_clk_src",
964 .parent_names = gcc_xo_gpll0,
965 .num_parents = 2,
966 .ops = &clk_rcg2_floor_ops,
967 },
968 };
969
970 static struct freq_tbl ftbl_tsif_ref_clk_src[] = {
971 F(105500, P_XO, 1, 1, 182),
972 { }
973 };
974
975 static struct clk_rcg2 tsif_ref_clk_src = {
976 .cmd_rcgr = 0x0d90,
977 .mnd_width = 8,
978 .hid_width = 5,
979 .freq_tbl = ftbl_tsif_ref_clk_src,
980 .clkr.hw.init = &(struct clk_init_data)
981 {
982 .name = "tsif_ref_clk_src",
983 .parent_names = (const char *[]) { "xo" },
984 .num_parents = 1,
985 .ops = &clk_rcg2_ops,
986 },
987 };
988
989 static struct freq_tbl ftbl_usb30_mock_utmi_clk_src[] = {
990 F(19200000, P_XO, 1, 0, 0),
991 F(60000000, P_GPLL0, 10, 0, 0),
992 { }
993 };
994
995 static struct clk_rcg2 usb30_mock_utmi_clk_src = {
996 .cmd_rcgr = 0x03e8,
997 .hid_width = 5,
998 .parent_map = gcc_xo_gpll0_map,
999 .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
1000 .clkr.hw.init = &(struct clk_init_data)
1001 {
1002 .name = "usb30_mock_utmi_clk_src",
1003 .parent_names = gcc_xo_gpll0,
1004 .num_parents = 2,
1005 .ops = &clk_rcg2_ops,
1006 },
1007 };
1008
1009 static struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = {
1010 F(1200000, P_XO, 16, 0, 0),
1011 { }
1012 };
1013
1014 static struct clk_rcg2 usb3_phy_aux_clk_src = {
1015 .cmd_rcgr = 0x1414,
1016 .hid_width = 5,
1017 .freq_tbl = ftbl_usb3_phy_aux_clk_src,
1018 .clkr.hw.init = &(struct clk_init_data)
1019 {
1020 .name = "usb3_phy_aux_clk_src",
1021 .parent_names = (const char *[]) { "xo" },
1022 .num_parents = 1,
1023 .ops = &clk_rcg2_ops,
1024 },
1025 };
1026
1027 static struct freq_tbl ftbl_usb_hs_system_clk_src[] = {
1028 F(75000000, P_GPLL0, 8, 0, 0),
1029 { }
1030 };
1031
1032 static struct clk_rcg2 usb_hs_system_clk_src = {
1033 .cmd_rcgr = 0x0490,
1034 .hid_width = 5,
1035 .parent_map = gcc_xo_gpll0_map,
1036 .freq_tbl = ftbl_usb_hs_system_clk_src,
1037 .clkr.hw.init = &(struct clk_init_data)
1038 {
1039 .name = "usb_hs_system_clk_src",
1040 .parent_names = gcc_xo_gpll0,
1041 .num_parents = 2,
1042 .ops = &clk_rcg2_ops,
1043 },
1044 };
1045
1046 static struct clk_branch gcc_blsp1_ahb_clk = {
1047 .halt_reg = 0x05c4,
1048 .halt_check = BRANCH_HALT_VOTED,
1049 .clkr = {
1050 .enable_reg = 0x1484,
1051 .enable_mask = BIT(17),
1052 .hw.init = &(struct clk_init_data)
1053 {
1054 .name = "gcc_blsp1_ahb_clk",
1055 .ops = &clk_branch2_ops,
1056 },
1057 },
1058 };
1059
1060 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1061 .halt_reg = 0x0648,
1062 .clkr = {
1063 .enable_reg = 0x0648,
1064 .enable_mask = BIT(0),
1065 .hw.init = &(struct clk_init_data)
1066 {
1067 .name = "gcc_blsp1_qup1_i2c_apps_clk",
1068 .parent_names = (const char *[]) {
1069 "blsp1_qup1_i2c_apps_clk_src",
1070 },
1071 .num_parents = 1,
1072 .flags = CLK_SET_RATE_PARENT,
1073 .ops = &clk_branch2_ops,
1074 },
1075 },
1076 };
1077
1078 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1079 .halt_reg = 0x0644,
1080 .clkr = {
1081 .enable_reg = 0x0644,
1082 .enable_mask = BIT(0),
1083 .hw.init = &(struct clk_init_data)
1084 {
1085 .name = "gcc_blsp1_qup1_spi_apps_clk",
1086 .parent_names = (const char *[]) {
1087 "blsp1_qup1_spi_apps_clk_src",
1088 },
1089 .num_parents = 1,
1090 .flags = CLK_SET_RATE_PARENT,
1091 .ops = &clk_branch2_ops,
1092 },
1093 },
1094 };
1095
1096 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1097 .halt_reg = 0x06c8,
1098 .clkr = {
1099 .enable_reg = 0x06c8,
1100 .enable_mask = BIT(0),
1101 .hw.init = &(struct clk_init_data)
1102 {
1103 .name = "gcc_blsp1_qup2_i2c_apps_clk",
1104 .parent_names = (const char *[]) {
1105 "blsp1_qup2_i2c_apps_clk_src",
1106 },
1107 .num_parents = 1,
1108 .flags = CLK_SET_RATE_PARENT,
1109 .ops = &clk_branch2_ops,
1110 },
1111 },
1112 };
1113
1114 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1115 .halt_reg = 0x06c4,
1116 .clkr = {
1117 .enable_reg = 0x06c4,
1118 .enable_mask = BIT(0),
1119 .hw.init = &(struct clk_init_data)
1120 {
1121 .name = "gcc_blsp1_qup2_spi_apps_clk",
1122 .parent_names = (const char *[]) {
1123 "blsp1_qup2_spi_apps_clk_src",
1124 },
1125 .num_parents = 1,
1126 .flags = CLK_SET_RATE_PARENT,
1127 .ops = &clk_branch2_ops,
1128 },
1129 },
1130 };
1131
1132 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1133 .halt_reg = 0x0748,
1134 .clkr = {
1135 .enable_reg = 0x0748,
1136 .enable_mask = BIT(0),
1137 .hw.init = &(struct clk_init_data)
1138 {
1139 .name = "gcc_blsp1_qup3_i2c_apps_clk",
1140 .parent_names = (const char *[]) {
1141 "blsp1_qup3_i2c_apps_clk_src",
1142 },
1143 .num_parents = 1,
1144 .flags = CLK_SET_RATE_PARENT,
1145 .ops = &clk_branch2_ops,
1146 },
1147 },
1148 };
1149
1150 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1151 .halt_reg = 0x0744,
1152 .clkr = {
1153 .enable_reg = 0x0744,
1154 .enable_mask = BIT(0),
1155 .hw.init = &(struct clk_init_data)
1156 {
1157 .name = "gcc_blsp1_qup3_spi_apps_clk",
1158 .parent_names = (const char *[]) {
1159 "blsp1_qup3_spi_apps_clk_src",
1160 },
1161 .num_parents = 1,
1162 .flags = CLK_SET_RATE_PARENT,
1163 .ops = &clk_branch2_ops,
1164 },
1165 },
1166 };
1167
1168 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
1169 .halt_reg = 0x07c8,
1170 .clkr = {
1171 .enable_reg = 0x07c8,
1172 .enable_mask = BIT(0),
1173 .hw.init = &(struct clk_init_data)
1174 {
1175 .name = "gcc_blsp1_qup4_i2c_apps_clk",
1176 .parent_names = (const char *[]) {
1177 "blsp1_qup4_i2c_apps_clk_src",
1178 },
1179 .num_parents = 1,
1180 .flags = CLK_SET_RATE_PARENT,
1181 .ops = &clk_branch2_ops,
1182 },
1183 },
1184 };
1185
1186 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
1187 .halt_reg = 0x07c4,
1188 .clkr = {
1189 .enable_reg = 0x07c4,
1190 .enable_mask = BIT(0),
1191 .hw.init = &(struct clk_init_data)
1192 {
1193 .name = "gcc_blsp1_qup4_spi_apps_clk",
1194 .parent_names = (const char *[]) {
1195 "blsp1_qup4_spi_apps_clk_src",
1196 },
1197 .num_parents = 1,
1198 .flags = CLK_SET_RATE_PARENT,
1199 .ops = &clk_branch2_ops,
1200 },
1201 },
1202 };
1203
1204 static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
1205 .halt_reg = 0x0848,
1206 .clkr = {
1207 .enable_reg = 0x0848,
1208 .enable_mask = BIT(0),
1209 .hw.init = &(struct clk_init_data)
1210 {
1211 .name = "gcc_blsp1_qup5_i2c_apps_clk",
1212 .parent_names = (const char *[]) {
1213 "blsp1_qup5_i2c_apps_clk_src",
1214 },
1215 .num_parents = 1,
1216 .flags = CLK_SET_RATE_PARENT,
1217 .ops = &clk_branch2_ops,
1218 },
1219 },
1220 };
1221
1222 static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
1223 .halt_reg = 0x0844,
1224 .clkr = {
1225 .enable_reg = 0x0844,
1226 .enable_mask = BIT(0),
1227 .hw.init = &(struct clk_init_data)
1228 {
1229 .name = "gcc_blsp1_qup5_spi_apps_clk",
1230 .parent_names = (const char *[]) {
1231 "blsp1_qup5_spi_apps_clk_src",
1232 },
1233 .num_parents = 1,
1234 .flags = CLK_SET_RATE_PARENT,
1235 .ops = &clk_branch2_ops,
1236 },
1237 },
1238 };
1239
1240 static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
1241 .halt_reg = 0x08c8,
1242 .clkr = {
1243 .enable_reg = 0x08c8,
1244 .enable_mask = BIT(0),
1245 .hw.init = &(struct clk_init_data)
1246 {
1247 .name = "gcc_blsp1_qup6_i2c_apps_clk",
1248 .parent_names = (const char *[]) {
1249 "blsp1_qup6_i2c_apps_clk_src",
1250 },
1251 .num_parents = 1,
1252 .flags = CLK_SET_RATE_PARENT,
1253 .ops = &clk_branch2_ops,
1254 },
1255 },
1256 };
1257
1258 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
1259 .halt_reg = 0x08c4,
1260 .clkr = {
1261 .enable_reg = 0x08c4,
1262 .enable_mask = BIT(0),
1263 .hw.init = &(struct clk_init_data)
1264 {
1265 .name = "gcc_blsp1_qup6_spi_apps_clk",
1266 .parent_names = (const char *[]) {
1267 "blsp1_qup6_spi_apps_clk_src",
1268 },
1269 .num_parents = 1,
1270 .flags = CLK_SET_RATE_PARENT,
1271 .ops = &clk_branch2_ops,
1272 },
1273 },
1274 };
1275
1276 static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1277 .halt_reg = 0x0684,
1278 .clkr = {
1279 .enable_reg = 0x0684,
1280 .enable_mask = BIT(0),
1281 .hw.init = &(struct clk_init_data)
1282 {
1283 .name = "gcc_blsp1_uart1_apps_clk",
1284 .parent_names = (const char *[]) {
1285 "blsp1_uart1_apps_clk_src",
1286 },
1287 .num_parents = 1,
1288 .flags = CLK_SET_RATE_PARENT,
1289 .ops = &clk_branch2_ops,
1290 },
1291 },
1292 };
1293
1294 static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1295 .halt_reg = 0x0704,
1296 .clkr = {
1297 .enable_reg = 0x0704,
1298 .enable_mask = BIT(0),
1299 .hw.init = &(struct clk_init_data)
1300 {
1301 .name = "gcc_blsp1_uart2_apps_clk",
1302 .parent_names = (const char *[]) {
1303 "blsp1_uart2_apps_clk_src",
1304 },
1305 .num_parents = 1,
1306 .flags = CLK_SET_RATE_PARENT,
1307 .ops = &clk_branch2_ops,
1308 },
1309 },
1310 };
1311
1312 static struct clk_branch gcc_blsp1_uart3_apps_clk = {
1313 .halt_reg = 0x0784,
1314 .clkr = {
1315 .enable_reg = 0x0784,
1316 .enable_mask = BIT(0),
1317 .hw.init = &(struct clk_init_data)
1318 {
1319 .name = "gcc_blsp1_uart3_apps_clk",
1320 .parent_names = (const char *[]) {
1321 "blsp1_uart3_apps_clk_src",
1322 },
1323 .num_parents = 1,
1324 .flags = CLK_SET_RATE_PARENT,
1325 .ops = &clk_branch2_ops,
1326 },
1327 },
1328 };
1329
1330 static struct clk_branch gcc_blsp1_uart4_apps_clk = {
1331 .halt_reg = 0x0804,
1332 .clkr = {
1333 .enable_reg = 0x0804,
1334 .enable_mask = BIT(0),
1335 .hw.init = &(struct clk_init_data)
1336 {
1337 .name = "gcc_blsp1_uart4_apps_clk",
1338 .parent_names = (const char *[]) {
1339 "blsp1_uart4_apps_clk_src",
1340 },
1341 .num_parents = 1,
1342 .flags = CLK_SET_RATE_PARENT,
1343 .ops = &clk_branch2_ops,
1344 },
1345 },
1346 };
1347
1348 static struct clk_branch gcc_blsp1_uart5_apps_clk = {
1349 .halt_reg = 0x0884,
1350 .clkr = {
1351 .enable_reg = 0x0884,
1352 .enable_mask = BIT(0),
1353 .hw.init = &(struct clk_init_data)
1354 {
1355 .name = "gcc_blsp1_uart5_apps_clk",
1356 .parent_names = (const char *[]) {
1357 "blsp1_uart5_apps_clk_src",
1358 },
1359 .num_parents = 1,
1360 .flags = CLK_SET_RATE_PARENT,
1361 .ops = &clk_branch2_ops,
1362 },
1363 },
1364 };
1365
1366 static struct clk_branch gcc_blsp1_uart6_apps_clk = {
1367 .halt_reg = 0x0904,
1368 .clkr = {
1369 .enable_reg = 0x0904,
1370 .enable_mask = BIT(0),
1371 .hw.init = &(struct clk_init_data)
1372 {
1373 .name = "gcc_blsp1_uart6_apps_clk",
1374 .parent_names = (const char *[]) {
1375 "blsp1_uart6_apps_clk_src",
1376 },
1377 .num_parents = 1,
1378 .flags = CLK_SET_RATE_PARENT,
1379 .ops = &clk_branch2_ops,
1380 },
1381 },
1382 };
1383
1384 static struct clk_branch gcc_blsp2_ahb_clk = {
1385 .halt_reg = 0x0944,
1386 .halt_check = BRANCH_HALT_VOTED,
1387 .clkr = {
1388 .enable_reg = 0x1484,
1389 .enable_mask = BIT(15),
1390 .hw.init = &(struct clk_init_data)
1391 {
1392 .name = "gcc_blsp2_ahb_clk",
1393 .ops = &clk_branch2_ops,
1394 },
1395 },
1396 };
1397
1398 static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
1399 .halt_reg = 0x0988,
1400 .clkr = {
1401 .enable_reg = 0x0988,
1402 .enable_mask = BIT(0),
1403 .hw.init = &(struct clk_init_data)
1404 {
1405 .name = "gcc_blsp2_qup1_i2c_apps_clk",
1406 .parent_names = (const char *[]) {
1407 "blsp2_qup1_i2c_apps_clk_src",
1408 },
1409 .num_parents = 1,
1410 .flags = CLK_SET_RATE_PARENT,
1411 .ops = &clk_branch2_ops,
1412 },
1413 },
1414 };
1415
1416 static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
1417 .halt_reg = 0x0984,
1418 .clkr = {
1419 .enable_reg = 0x0984,
1420 .enable_mask = BIT(0),
1421 .hw.init = &(struct clk_init_data)
1422 {
1423 .name = "gcc_blsp2_qup1_spi_apps_clk",
1424 .parent_names = (const char *[]) {
1425 "blsp2_qup1_spi_apps_clk_src",
1426 },
1427 .num_parents = 1,
1428 .flags = CLK_SET_RATE_PARENT,
1429 .ops = &clk_branch2_ops,
1430 },
1431 },
1432 };
1433
1434 static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
1435 .halt_reg = 0x0a08,
1436 .clkr = {
1437 .enable_reg = 0x0a08,
1438 .enable_mask = BIT(0),
1439 .hw.init = &(struct clk_init_data)
1440 {
1441 .name = "gcc_blsp2_qup2_i2c_apps_clk",
1442 .parent_names = (const char *[]) {
1443 "blsp2_qup2_i2c_apps_clk_src",
1444 },
1445 .num_parents = 1,
1446 .flags = CLK_SET_RATE_PARENT,
1447 .ops = &clk_branch2_ops,
1448 },
1449 },
1450 };
1451
1452 static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
1453 .halt_reg = 0x0a04,
1454 .clkr = {
1455 .enable_reg = 0x0a04,
1456 .enable_mask = BIT(0),
1457 .hw.init = &(struct clk_init_data)
1458 {
1459 .name = "gcc_blsp2_qup2_spi_apps_clk",
1460 .parent_names = (const char *[]) {
1461 "blsp2_qup2_spi_apps_clk_src",
1462 },
1463 .num_parents = 1,
1464 .flags = CLK_SET_RATE_PARENT,
1465 .ops = &clk_branch2_ops,
1466 },
1467 },
1468 };
1469
1470 static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
1471 .halt_reg = 0x0a88,
1472 .clkr = {
1473 .enable_reg = 0x0a88,
1474 .enable_mask = BIT(0),
1475 .hw.init = &(struct clk_init_data)
1476 {
1477 .name = "gcc_blsp2_qup3_i2c_apps_clk",
1478 .parent_names = (const char *[]) {
1479 "blsp2_qup3_i2c_apps_clk_src",
1480 },
1481 .num_parents = 1,
1482 .flags = CLK_SET_RATE_PARENT,
1483 .ops = &clk_branch2_ops,
1484 },
1485 },
1486 };
1487
1488 static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
1489 .halt_reg = 0x0a84,
1490 .clkr = {
1491 .enable_reg = 0x0a84,
1492 .enable_mask = BIT(0),
1493 .hw.init = &(struct clk_init_data)
1494 {
1495 .name = "gcc_blsp2_qup3_spi_apps_clk",
1496 .parent_names = (const char *[]) {
1497 "blsp2_qup3_spi_apps_clk_src",
1498 },
1499 .num_parents = 1,
1500 .flags = CLK_SET_RATE_PARENT,
1501 .ops = &clk_branch2_ops,
1502 },
1503 },
1504 };
1505
1506 static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
1507 .halt_reg = 0x0b08,
1508 .clkr = {
1509 .enable_reg = 0x0b08,
1510 .enable_mask = BIT(0),
1511 .hw.init = &(struct clk_init_data)
1512 {
1513 .name = "gcc_blsp2_qup4_i2c_apps_clk",
1514 .parent_names = (const char *[]) {
1515 "blsp2_qup4_i2c_apps_clk_src",
1516 },
1517 .num_parents = 1,
1518 .flags = CLK_SET_RATE_PARENT,
1519 .ops = &clk_branch2_ops,
1520 },
1521 },
1522 };
1523
1524 static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
1525 .halt_reg = 0x0b04,
1526 .clkr = {
1527 .enable_reg = 0x0b04,
1528 .enable_mask = BIT(0),
1529 .hw.init = &(struct clk_init_data)
1530 {
1531 .name = "gcc_blsp2_qup4_spi_apps_clk",
1532 .parent_names = (const char *[]) {
1533 "blsp2_qup4_spi_apps_clk_src",
1534 },
1535 .num_parents = 1,
1536 .flags = CLK_SET_RATE_PARENT,
1537 .ops = &clk_branch2_ops,
1538 },
1539 },
1540 };
1541
1542 static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {
1543 .halt_reg = 0x0b88,
1544 .clkr = {
1545 .enable_reg = 0x0b88,
1546 .enable_mask = BIT(0),
1547 .hw.init = &(struct clk_init_data)
1548 {
1549 .name = "gcc_blsp2_qup5_i2c_apps_clk",
1550 .parent_names = (const char *[]) {
1551 "blsp2_qup5_i2c_apps_clk_src",
1552 },
1553 .num_parents = 1,
1554 .flags = CLK_SET_RATE_PARENT,
1555 .ops = &clk_branch2_ops,
1556 },
1557 },
1558 };
1559
1560 static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {
1561 .halt_reg = 0x0b84,
1562 .clkr = {
1563 .enable_reg = 0x0b84,
1564 .enable_mask = BIT(0),
1565 .hw.init = &(struct clk_init_data)
1566 {
1567 .name = "gcc_blsp2_qup5_spi_apps_clk",
1568 .parent_names = (const char *[]) {
1569 "blsp2_qup5_spi_apps_clk_src",
1570 },
1571 .num_parents = 1,
1572 .flags = CLK_SET_RATE_PARENT,
1573 .ops = &clk_branch2_ops,
1574 },
1575 },
1576 };
1577
1578 static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {
1579 .halt_reg = 0x0c08,
1580 .clkr = {
1581 .enable_reg = 0x0c08,
1582 .enable_mask = BIT(0),
1583 .hw.init = &(struct clk_init_data)
1584 {
1585 .name = "gcc_blsp2_qup6_i2c_apps_clk",
1586 .parent_names = (const char *[]) {
1587 "blsp2_qup6_i2c_apps_clk_src",
1588 },
1589 .num_parents = 1,
1590 .flags = CLK_SET_RATE_PARENT,
1591 .ops = &clk_branch2_ops,
1592 },
1593 },
1594 };
1595
1596 static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {
1597 .halt_reg = 0x0c04,
1598 .clkr = {
1599 .enable_reg = 0x0c04,
1600 .enable_mask = BIT(0),
1601 .hw.init = &(struct clk_init_data)
1602 {
1603 .name = "gcc_blsp2_qup6_spi_apps_clk",
1604 .parent_names = (const char *[]) {
1605 "blsp2_qup6_spi_apps_clk_src",
1606 },
1607 .num_parents = 1,
1608 .flags = CLK_SET_RATE_PARENT,
1609 .ops = &clk_branch2_ops,
1610 },
1611 },
1612 };
1613
1614 static struct clk_branch gcc_blsp2_uart1_apps_clk = {
1615 .halt_reg = 0x09c4,
1616 .clkr = {
1617 .enable_reg = 0x09c4,
1618 .enable_mask = BIT(0),
1619 .hw.init = &(struct clk_init_data)
1620 {
1621 .name = "gcc_blsp2_uart1_apps_clk",
1622 .parent_names = (const char *[]) {
1623 "blsp2_uart1_apps_clk_src",
1624 },
1625 .num_parents = 1,
1626 .flags = CLK_SET_RATE_PARENT,
1627 .ops = &clk_branch2_ops,
1628 },
1629 },
1630 };
1631
1632 static struct clk_branch gcc_blsp2_uart2_apps_clk = {
1633 .halt_reg = 0x0a44,
1634 .clkr = {
1635 .enable_reg = 0x0a44,
1636 .enable_mask = BIT(0),
1637 .hw.init = &(struct clk_init_data)
1638 {
1639 .name = "gcc_blsp2_uart2_apps_clk",
1640 .parent_names = (const char *[]) {
1641 "blsp2_uart2_apps_clk_src",
1642 },
1643 .num_parents = 1,
1644 .flags = CLK_SET_RATE_PARENT,
1645 .ops = &clk_branch2_ops,
1646 },
1647 },
1648 };
1649
1650 static struct clk_branch gcc_blsp2_uart3_apps_clk = {
1651 .halt_reg = 0x0ac4,
1652 .clkr = {
1653 .enable_reg = 0x0ac4,
1654 .enable_mask = BIT(0),
1655 .hw.init = &(struct clk_init_data)
1656 {
1657 .name = "gcc_blsp2_uart3_apps_clk",
1658 .parent_names = (const char *[]) {
1659 "blsp2_uart3_apps_clk_src",
1660 },
1661 .num_parents = 1,
1662 .flags = CLK_SET_RATE_PARENT,
1663 .ops = &clk_branch2_ops,
1664 },
1665 },
1666 };
1667
1668 static struct clk_branch gcc_blsp2_uart4_apps_clk = {
1669 .halt_reg = 0x0b44,
1670 .clkr = {
1671 .enable_reg = 0x0b44,
1672 .enable_mask = BIT(0),
1673 .hw.init = &(struct clk_init_data)
1674 {
1675 .name = "gcc_blsp2_uart4_apps_clk",
1676 .parent_names = (const char *[]) {
1677 "blsp2_uart4_apps_clk_src",
1678 },
1679 .num_parents = 1,
1680 .flags = CLK_SET_RATE_PARENT,
1681 .ops = &clk_branch2_ops,
1682 },
1683 },
1684 };
1685
1686 static struct clk_branch gcc_blsp2_uart5_apps_clk = {
1687 .halt_reg = 0x0bc4,
1688 .clkr = {
1689 .enable_reg = 0x0bc4,
1690 .enable_mask = BIT(0),
1691 .hw.init = &(struct clk_init_data)
1692 {
1693 .name = "gcc_blsp2_uart5_apps_clk",
1694 .parent_names = (const char *[]) {
1695 "blsp2_uart5_apps_clk_src",
1696 },
1697 .num_parents = 1,
1698 .flags = CLK_SET_RATE_PARENT,
1699 .ops = &clk_branch2_ops,
1700 },
1701 },
1702 };
1703
1704 static struct clk_branch gcc_blsp2_uart6_apps_clk = {
1705 .halt_reg = 0x0c44,
1706 .clkr = {
1707 .enable_reg = 0x0c44,
1708 .enable_mask = BIT(0),
1709 .hw.init = &(struct clk_init_data)
1710 {
1711 .name = "gcc_blsp2_uart6_apps_clk",
1712 .parent_names = (const char *[]) {
1713 "blsp2_uart6_apps_clk_src",
1714 },
1715 .num_parents = 1,
1716 .flags = CLK_SET_RATE_PARENT,
1717 .ops = &clk_branch2_ops,
1718 },
1719 },
1720 };
1721
1722 static struct clk_branch gcc_gp1_clk = {
1723 .halt_reg = 0x1900,
1724 .clkr = {
1725 .enable_reg = 0x1900,
1726 .enable_mask = BIT(0),
1727 .hw.init = &(struct clk_init_data)
1728 {
1729 .name = "gcc_gp1_clk",
1730 .parent_names = (const char *[]) {
1731 "gp1_clk_src",
1732 },
1733 .num_parents = 1,
1734 .flags = CLK_SET_RATE_PARENT,
1735 .ops = &clk_branch2_ops,
1736 },
1737 },
1738 };
1739
1740 static struct clk_branch gcc_gp2_clk = {
1741 .halt_reg = 0x1940,
1742 .clkr = {
1743 .enable_reg = 0x1940,
1744 .enable_mask = BIT(0),
1745 .hw.init = &(struct clk_init_data)
1746 {
1747 .name = "gcc_gp2_clk",
1748 .parent_names = (const char *[]) {
1749 "gp2_clk_src",
1750 },
1751 .num_parents = 1,
1752 .flags = CLK_SET_RATE_PARENT,
1753 .ops = &clk_branch2_ops,
1754 },
1755 },
1756 };
1757
1758 static struct clk_branch gcc_gp3_clk = {
1759 .halt_reg = 0x1980,
1760 .clkr = {
1761 .enable_reg = 0x1980,
1762 .enable_mask = BIT(0),
1763 .hw.init = &(struct clk_init_data)
1764 {
1765 .name = "gcc_gp3_clk",
1766 .parent_names = (const char *[]) {
1767 "gp3_clk_src",
1768 },
1769 .num_parents = 1,
1770 .flags = CLK_SET_RATE_PARENT,
1771 .ops = &clk_branch2_ops,
1772 },
1773 },
1774 };
1775
1776 static struct clk_branch gcc_lpass_q6_axi_clk = {
1777 .halt_reg = 0x0280,
1778 .clkr = {
1779 .enable_reg = 0x0280,
1780 .enable_mask = BIT(0),
1781 .hw.init = &(struct clk_init_data)
1782 {
1783 .name = "gcc_lpass_q6_axi_clk",
1784 .ops = &clk_branch2_ops,
1785 },
1786 },
1787 };
1788
1789 static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
1790 .halt_reg = 0x0284,
1791 .clkr = {
1792 .enable_reg = 0x0284,
1793 .enable_mask = BIT(0),
1794 .hw.init = &(struct clk_init_data)
1795 {
1796 .name = "gcc_mss_q6_bimc_axi_clk",
1797 .ops = &clk_branch2_ops,
1798 },
1799 },
1800 };
1801
1802 static struct clk_branch gcc_pcie_0_aux_clk = {
1803 .halt_reg = 0x1ad4,
1804 .clkr = {
1805 .enable_reg = 0x1ad4,
1806 .enable_mask = BIT(0),
1807 .hw.init = &(struct clk_init_data)
1808 {
1809 .name = "gcc_pcie_0_aux_clk",
1810 .parent_names = (const char *[]) {
1811 "pcie_0_aux_clk_src",
1812 },
1813 .num_parents = 1,
1814 .flags = CLK_SET_RATE_PARENT,
1815 .ops = &clk_branch2_ops,
1816 },
1817 },
1818 };
1819
1820 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
1821 .halt_reg = 0x1ad0,
1822 .clkr = {
1823 .enable_reg = 0x1ad0,
1824 .enable_mask = BIT(0),
1825 .hw.init = &(struct clk_init_data)
1826 {
1827 .name = "gcc_pcie_0_cfg_ahb_clk",
1828 .ops = &clk_branch2_ops,
1829 },
1830 },
1831 };
1832
1833 static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
1834 .halt_reg = 0x1acc,
1835 .clkr = {
1836 .enable_reg = 0x1acc,
1837 .enable_mask = BIT(0),
1838 .hw.init = &(struct clk_init_data)
1839 {
1840 .name = "gcc_pcie_0_mstr_axi_clk",
1841 .ops = &clk_branch2_ops,
1842 },
1843 },
1844 };
1845
1846 static struct clk_branch gcc_pcie_0_pipe_clk = {
1847 .halt_reg = 0x1ad8,
1848 .halt_check = BRANCH_HALT_DELAY,
1849 .clkr = {
1850 .enable_reg = 0x1ad8,
1851 .enable_mask = BIT(0),
1852 .hw.init = &(struct clk_init_data)
1853 {
1854 .name = "gcc_pcie_0_pipe_clk",
1855 .parent_names = (const char *[]) {
1856 "pcie_0_pipe_clk_src",
1857 },
1858 .num_parents = 1,
1859 .flags = CLK_SET_RATE_PARENT,
1860 .ops = &clk_branch2_ops,
1861 },
1862 },
1863 };
1864
1865 static struct clk_branch gcc_pcie_0_slv_axi_clk = {
1866 .halt_reg = 0x1ac8,
1867 .halt_check = BRANCH_HALT_DELAY,
1868 .clkr = {
1869 .enable_reg = 0x1ac8,
1870 .enable_mask = BIT(0),
1871 .hw.init = &(struct clk_init_data)
1872 {
1873 .name = "gcc_pcie_0_slv_axi_clk",
1874 .ops = &clk_branch2_ops,
1875 },
1876 },
1877 };
1878
1879 static struct clk_branch gcc_pcie_1_aux_clk = {
1880 .halt_reg = 0x1b54,
1881 .clkr = {
1882 .enable_reg = 0x1b54,
1883 .enable_mask = BIT(0),
1884 .hw.init = &(struct clk_init_data)
1885 {
1886 .name = "gcc_pcie_1_aux_clk",
1887 .parent_names = (const char *[]) {
1888 "pcie_1_aux_clk_src",
1889 },
1890 .num_parents = 1,
1891 .flags = CLK_SET_RATE_PARENT,
1892 .ops = &clk_branch2_ops,
1893 },
1894 },
1895 };
1896
1897 static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
1898 .halt_reg = 0x1b54,
1899 .clkr = {
1900 .enable_reg = 0x1b54,
1901 .enable_mask = BIT(0),
1902 .hw.init = &(struct clk_init_data)
1903 {
1904 .name = "gcc_pcie_1_cfg_ahb_clk",
1905 .ops = &clk_branch2_ops,
1906 },
1907 },
1908 };
1909
1910 static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
1911 .halt_reg = 0x1b50,
1912 .clkr = {
1913 .enable_reg = 0x1b50,
1914 .enable_mask = BIT(0),
1915 .hw.init = &(struct clk_init_data)
1916 {
1917 .name = "gcc_pcie_1_mstr_axi_clk",
1918 .ops = &clk_branch2_ops,
1919 },
1920 },
1921 };
1922
1923 static struct clk_branch gcc_pcie_1_pipe_clk = {
1924 .halt_reg = 0x1b58,
1925 .halt_check = BRANCH_HALT_DELAY,
1926 .clkr = {
1927 .enable_reg = 0x1b58,
1928 .enable_mask = BIT(0),
1929 .hw.init = &(struct clk_init_data)
1930 {
1931 .name = "gcc_pcie_1_pipe_clk",
1932 .parent_names = (const char *[]) {
1933 "pcie_1_pipe_clk_src",
1934 },
1935 .num_parents = 1,
1936 .flags = CLK_SET_RATE_PARENT,
1937 .ops = &clk_branch2_ops,
1938 },
1939 },
1940 };
1941
1942 static struct clk_branch gcc_pcie_1_slv_axi_clk = {
1943 .halt_reg = 0x1b48,
1944 .clkr = {
1945 .enable_reg = 0x1b48,
1946 .enable_mask = BIT(0),
1947 .hw.init = &(struct clk_init_data)
1948 {
1949 .name = "gcc_pcie_1_slv_axi_clk",
1950 .ops = &clk_branch2_ops,
1951 },
1952 },
1953 };
1954
1955 static struct clk_branch gcc_pdm2_clk = {
1956 .halt_reg = 0x0ccc,
1957 .clkr = {
1958 .enable_reg = 0x0ccc,
1959 .enable_mask = BIT(0),
1960 .hw.init = &(struct clk_init_data)
1961 {
1962 .name = "gcc_pdm2_clk",
1963 .parent_names = (const char *[]) {
1964 "pdm2_clk_src",
1965 },
1966 .num_parents = 1,
1967 .flags = CLK_SET_RATE_PARENT,
1968 .ops = &clk_branch2_ops,
1969 },
1970 },
1971 };
1972
1973 static struct clk_branch gcc_pdm_ahb_clk = {
1974 .halt_reg = 0x0cc4,
1975 .clkr = {
1976 .enable_reg = 0x0cc4,
1977 .enable_mask = BIT(0),
1978 .hw.init = &(struct clk_init_data)
1979 {
1980 .name = "gcc_pdm_ahb_clk",
1981 .ops = &clk_branch2_ops,
1982 },
1983 },
1984 };
1985
1986 static struct clk_branch gcc_sdcc1_apps_clk = {
1987 .halt_reg = 0x04c4,
1988 .clkr = {
1989 .enable_reg = 0x04c4,
1990 .enable_mask = BIT(0),
1991 .hw.init = &(struct clk_init_data)
1992 {
1993 .name = "gcc_sdcc1_apps_clk",
1994 .parent_names = (const char *[]) {
1995 "sdcc1_apps_clk_src",
1996 },
1997 .num_parents = 1,
1998 .flags = CLK_SET_RATE_PARENT,
1999 .ops = &clk_branch2_ops,
2000 },
2001 },
2002 };
2003
2004 static struct clk_branch gcc_sdcc1_ahb_clk = {
2005 .halt_reg = 0x04c8,
2006 .clkr = {
2007 .enable_reg = 0x04c8,
2008 .enable_mask = BIT(0),
2009 .hw.init = &(struct clk_init_data)
2010 {
2011 .name = "gcc_sdcc1_ahb_clk",
2012 .parent_names = (const char *[]){
2013 "periph_noc_clk_src",
2014 },
2015 .num_parents = 1,
2016 .ops = &clk_branch2_ops,
2017 },
2018 },
2019 };
2020
2021 static struct clk_branch gcc_sdcc2_ahb_clk = {
2022 .halt_reg = 0x0508,
2023 .clkr = {
2024 .enable_reg = 0x0508,
2025 .enable_mask = BIT(0),
2026 .hw.init = &(struct clk_init_data)
2027 {
2028 .name = "gcc_sdcc2_ahb_clk",
2029 .parent_names = (const char *[]){
2030 "periph_noc_clk_src",
2031 },
2032 .num_parents = 1,
2033 .ops = &clk_branch2_ops,
2034 },
2035 },
2036 };
2037
2038 static struct clk_branch gcc_sdcc2_apps_clk = {
2039 .halt_reg = 0x0504,
2040 .clkr = {
2041 .enable_reg = 0x0504,
2042 .enable_mask = BIT(0),
2043 .hw.init = &(struct clk_init_data)
2044 {
2045 .name = "gcc_sdcc2_apps_clk",
2046 .parent_names = (const char *[]) {
2047 "sdcc2_apps_clk_src",
2048 },
2049 .num_parents = 1,
2050 .flags = CLK_SET_RATE_PARENT,
2051 .ops = &clk_branch2_ops,
2052 },
2053 },
2054 };
2055
2056 static struct clk_branch gcc_sdcc3_ahb_clk = {
2057 .halt_reg = 0x0548,
2058 .clkr = {
2059 .enable_reg = 0x0548,
2060 .enable_mask = BIT(0),
2061 .hw.init = &(struct clk_init_data)
2062 {
2063 .name = "gcc_sdcc3_ahb_clk",
2064 .parent_names = (const char *[]){
2065 "periph_noc_clk_src",
2066 },
2067 .num_parents = 1,
2068 .ops = &clk_branch2_ops,
2069 },
2070 },
2071 };
2072
2073 static struct clk_branch gcc_sdcc3_apps_clk = {
2074 .halt_reg = 0x0544,
2075 .clkr = {
2076 .enable_reg = 0x0544,
2077 .enable_mask = BIT(0),
2078 .hw.init = &(struct clk_init_data)
2079 {
2080 .name = "gcc_sdcc3_apps_clk",
2081 .parent_names = (const char *[]) {
2082 "sdcc3_apps_clk_src",
2083 },
2084 .num_parents = 1,
2085 .flags = CLK_SET_RATE_PARENT,
2086 .ops = &clk_branch2_ops,
2087 },
2088 },
2089 };
2090
2091 static struct clk_branch gcc_sdcc4_ahb_clk = {
2092 .halt_reg = 0x0588,
2093 .clkr = {
2094 .enable_reg = 0x0588,
2095 .enable_mask = BIT(0),
2096 .hw.init = &(struct clk_init_data)
2097 {
2098 .name = "gcc_sdcc4_ahb_clk",
2099 .parent_names = (const char *[]){
2100 "periph_noc_clk_src",
2101 },
2102 .num_parents = 1,
2103 .ops = &clk_branch2_ops,
2104 },
2105 },
2106 };
2107
2108 static struct clk_branch gcc_sdcc4_apps_clk = {
2109 .halt_reg = 0x0584,
2110 .clkr = {
2111 .enable_reg = 0x0584,
2112 .enable_mask = BIT(0),
2113 .hw.init = &(struct clk_init_data)
2114 {
2115 .name = "gcc_sdcc4_apps_clk",
2116 .parent_names = (const char *[]) {
2117 "sdcc4_apps_clk_src",
2118 },
2119 .num_parents = 1,
2120 .flags = CLK_SET_RATE_PARENT,
2121 .ops = &clk_branch2_ops,
2122 },
2123 },
2124 };
2125
2126 static struct clk_branch gcc_sys_noc_ufs_axi_clk = {
2127 .halt_reg = 0x1d7c,
2128 .clkr = {
2129 .enable_reg = 0x1d7c,
2130 .enable_mask = BIT(0),
2131 .hw.init = &(struct clk_init_data)
2132 {
2133 .name = "gcc_sys_noc_ufs_axi_clk",
2134 .parent_names = (const char *[]) {
2135 "ufs_axi_clk_src",
2136 },
2137 .num_parents = 1,
2138 .flags = CLK_SET_RATE_PARENT,
2139 .ops = &clk_branch2_ops,
2140 },
2141 },
2142 };
2143
2144 static struct clk_branch gcc_sys_noc_usb3_axi_clk = {
2145 .halt_reg = 0x03fc,
2146 .clkr = {
2147 .enable_reg = 0x03fc,
2148 .enable_mask = BIT(0),
2149 .hw.init = &(struct clk_init_data)
2150 {
2151 .name = "gcc_sys_noc_usb3_axi_clk",
2152 .parent_names = (const char *[]) {
2153 "usb30_master_clk_src",
2154 },
2155 .num_parents = 1,
2156 .flags = CLK_SET_RATE_PARENT,
2157 .ops = &clk_branch2_ops,
2158 },
2159 },
2160 };
2161
2162 static struct clk_branch gcc_tsif_ahb_clk = {
2163 .halt_reg = 0x0d84,
2164 .clkr = {
2165 .enable_reg = 0x0d84,
2166 .enable_mask = BIT(0),
2167 .hw.init = &(struct clk_init_data)
2168 {
2169 .name = "gcc_tsif_ahb_clk",
2170 .ops = &clk_branch2_ops,
2171 },
2172 },
2173 };
2174
2175 static struct clk_branch gcc_tsif_ref_clk = {
2176 .halt_reg = 0x0d88,
2177 .clkr = {
2178 .enable_reg = 0x0d88,
2179 .enable_mask = BIT(0),
2180 .hw.init = &(struct clk_init_data)
2181 {
2182 .name = "gcc_tsif_ref_clk",
2183 .parent_names = (const char *[]) {
2184 "tsif_ref_clk_src",
2185 },
2186 .num_parents = 1,
2187 .flags = CLK_SET_RATE_PARENT,
2188 .ops = &clk_branch2_ops,
2189 },
2190 },
2191 };
2192
2193 static struct clk_branch gcc_ufs_ahb_clk = {
2194 .halt_reg = 0x1d4c,
2195 .clkr = {
2196 .enable_reg = 0x1d4c,
2197 .enable_mask = BIT(0),
2198 .hw.init = &(struct clk_init_data)
2199 {
2200 .name = "gcc_ufs_ahb_clk",
2201 .ops = &clk_branch2_ops,
2202 },
2203 },
2204 };
2205
2206 static struct clk_branch gcc_ufs_axi_clk = {
2207 .halt_reg = 0x1d48,
2208 .clkr = {
2209 .enable_reg = 0x1d48,
2210 .enable_mask = BIT(0),
2211 .hw.init = &(struct clk_init_data)
2212 {
2213 .name = "gcc_ufs_axi_clk",
2214 .parent_names = (const char *[]) {
2215 "ufs_axi_clk_src",
2216 },
2217 .num_parents = 1,
2218 .flags = CLK_SET_RATE_PARENT,
2219 .ops = &clk_branch2_ops,
2220 },
2221 },
2222 };
2223
2224 static struct clk_branch gcc_ufs_rx_cfg_clk = {
2225 .halt_reg = 0x1d54,
2226 .clkr = {
2227 .enable_reg = 0x1d54,
2228 .enable_mask = BIT(0),
2229 .hw.init = &(struct clk_init_data)
2230 {
2231 .name = "gcc_ufs_rx_cfg_clk",
2232 .parent_names = (const char *[]) {
2233 "ufs_axi_clk_src",
2234 },
2235 .num_parents = 1,
2236 .flags = CLK_SET_RATE_PARENT,
2237 .ops = &clk_branch2_ops,
2238 },
2239 },
2240 };
2241
2242 static struct clk_branch gcc_ufs_rx_symbol_0_clk = {
2243 .halt_reg = 0x1d60,
2244 .halt_check = BRANCH_HALT_DELAY,
2245 .clkr = {
2246 .enable_reg = 0x1d60,
2247 .enable_mask = BIT(0),
2248 .hw.init = &(struct clk_init_data)
2249 {
2250 .name = "gcc_ufs_rx_symbol_0_clk",
2251 .ops = &clk_branch2_ops,
2252 },
2253 },
2254 };
2255
2256 static struct clk_branch gcc_ufs_rx_symbol_1_clk = {
2257 .halt_reg = 0x1d64,
2258 .halt_check = BRANCH_HALT_DELAY,
2259 .clkr = {
2260 .enable_reg = 0x1d64,
2261 .enable_mask = BIT(0),
2262 .hw.init = &(struct clk_init_data)
2263 {
2264 .name = "gcc_ufs_rx_symbol_1_clk",
2265 .ops = &clk_branch2_ops,
2266 },
2267 },
2268 };
2269
2270 static struct clk_branch gcc_ufs_tx_cfg_clk = {
2271 .halt_reg = 0x1d50,
2272 .clkr = {
2273 .enable_reg = 0x1d50,
2274 .enable_mask = BIT(0),
2275 .hw.init = &(struct clk_init_data)
2276 {
2277 .name = "gcc_ufs_tx_cfg_clk",
2278 .parent_names = (const char *[]) {
2279 "ufs_axi_clk_src",
2280 },
2281 .num_parents = 1,
2282 .flags = CLK_SET_RATE_PARENT,
2283 .ops = &clk_branch2_ops,
2284 },
2285 },
2286 };
2287
2288 static struct clk_branch gcc_ufs_tx_symbol_0_clk = {
2289 .halt_reg = 0x1d58,
2290 .halt_check = BRANCH_HALT_DELAY,
2291 .clkr = {
2292 .enable_reg = 0x1d58,
2293 .enable_mask = BIT(0),
2294 .hw.init = &(struct clk_init_data)
2295 {
2296 .name = "gcc_ufs_tx_symbol_0_clk",
2297 .ops = &clk_branch2_ops,
2298 },
2299 },
2300 };
2301
2302 static struct clk_branch gcc_ufs_tx_symbol_1_clk = {
2303 .halt_reg = 0x1d5c,
2304 .halt_check = BRANCH_HALT_DELAY,
2305 .clkr = {
2306 .enable_reg = 0x1d5c,
2307 .enable_mask = BIT(0),
2308 .hw.init = &(struct clk_init_data)
2309 {
2310 .name = "gcc_ufs_tx_symbol_1_clk",
2311 .ops = &clk_branch2_ops,
2312 },
2313 },
2314 };
2315
2316 static struct clk_branch gcc_usb2_hs_phy_sleep_clk = {
2317 .halt_reg = 0x04ac,
2318 .clkr = {
2319 .enable_reg = 0x04ac,
2320 .enable_mask = BIT(0),
2321 .hw.init = &(struct clk_init_data)
2322 {
2323 .name = "gcc_usb2_hs_phy_sleep_clk",
2324 .ops = &clk_branch2_ops,
2325 },
2326 },
2327 };
2328
2329 static struct clk_branch gcc_usb30_master_clk = {
2330 .halt_reg = 0x03c8,
2331 .clkr = {
2332 .enable_reg = 0x03c8,
2333 .enable_mask = BIT(0),
2334 .hw.init = &(struct clk_init_data)
2335 {
2336 .name = "gcc_usb30_master_clk",
2337 .parent_names = (const char *[]) {
2338 "usb30_master_clk_src",
2339 },
2340 .num_parents = 1,
2341 .flags = CLK_SET_RATE_PARENT,
2342 .ops = &clk_branch2_ops,
2343 },
2344 },
2345 };
2346
2347 static struct clk_branch gcc_usb30_mock_utmi_clk = {
2348 .halt_reg = 0x03d0,
2349 .clkr = {
2350 .enable_reg = 0x03d0,
2351 .enable_mask = BIT(0),
2352 .hw.init = &(struct clk_init_data)
2353 {
2354 .name = "gcc_usb30_mock_utmi_clk",
2355 .parent_names = (const char *[]) {
2356 "usb30_mock_utmi_clk_src",
2357 },
2358 .num_parents = 1,
2359 .flags = CLK_SET_RATE_PARENT,
2360 .ops = &clk_branch2_ops,
2361 },
2362 },
2363 };
2364
2365 static struct clk_branch gcc_usb30_sleep_clk = {
2366 .halt_reg = 0x03cc,
2367 .clkr = {
2368 .enable_reg = 0x03cc,
2369 .enable_mask = BIT(0),
2370 .hw.init = &(struct clk_init_data)
2371 {
2372 .name = "gcc_usb30_sleep_clk",
2373 .ops = &clk_branch2_ops,
2374 },
2375 },
2376 };
2377
2378 static struct clk_branch gcc_usb3_phy_aux_clk = {
2379 .halt_reg = 0x1408,
2380 .clkr = {
2381 .enable_reg = 0x1408,
2382 .enable_mask = BIT(0),
2383 .hw.init = &(struct clk_init_data)
2384 {
2385 .name = "gcc_usb3_phy_aux_clk",
2386 .parent_names = (const char *[]) {
2387 "usb3_phy_aux_clk_src",
2388 },
2389 .num_parents = 1,
2390 .flags = CLK_SET_RATE_PARENT,
2391 .ops = &clk_branch2_ops,
2392 },
2393 },
2394 };
2395
2396 static struct clk_branch gcc_usb_hs_ahb_clk = {
2397 .halt_reg = 0x0488,
2398 .clkr = {
2399 .enable_reg = 0x0488,
2400 .enable_mask = BIT(0),
2401 .hw.init = &(struct clk_init_data)
2402 {
2403 .name = "gcc_usb_hs_ahb_clk",
2404 .ops = &clk_branch2_ops,
2405 },
2406 },
2407 };
2408
2409 static struct clk_branch gcc_usb_hs_system_clk = {
2410 .halt_reg = 0x0484,
2411 .clkr = {
2412 .enable_reg = 0x0484,
2413 .enable_mask = BIT(0),
2414 .hw.init = &(struct clk_init_data)
2415 {
2416 .name = "gcc_usb_hs_system_clk",
2417 .parent_names = (const char *[]) {
2418 "usb_hs_system_clk_src",
2419 },
2420 .num_parents = 1,
2421 .flags = CLK_SET_RATE_PARENT,
2422 .ops = &clk_branch2_ops,
2423 },
2424 },
2425 };
2426
2427 static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
2428 .halt_reg = 0x1a84,
2429 .clkr = {
2430 .enable_reg = 0x1a84,
2431 .enable_mask = BIT(0),
2432 .hw.init = &(struct clk_init_data)
2433 {
2434 .name = "gcc_usb_phy_cfg_ahb2phy_clk",
2435 .ops = &clk_branch2_ops,
2436 },
2437 },
2438 };
2439
2440 static struct gdsc pcie_gdsc = {
2441 .gdscr = 0x1e18,
2442 .pd = {
2443 .name = "pcie",
2444 },
2445 .pwrsts = PWRSTS_OFF_ON,
2446 };
2447
2448 static struct gdsc pcie_0_gdsc = {
2449 .gdscr = 0x1ac4,
2450 .pd = {
2451 .name = "pcie_0",
2452 },
2453 .pwrsts = PWRSTS_OFF_ON,
2454 };
2455
2456 static struct gdsc pcie_1_gdsc = {
2457 .gdscr = 0x1b44,
2458 .pd = {
2459 .name = "pcie_1",
2460 },
2461 .pwrsts = PWRSTS_OFF_ON,
2462 };
2463
2464 static struct gdsc usb30_gdsc = {
2465 .gdscr = 0x3c4,
2466 .pd = {
2467 .name = "usb30",
2468 },
2469 .pwrsts = PWRSTS_OFF_ON,
2470 };
2471
2472 static struct gdsc ufs_gdsc = {
2473 .gdscr = 0x1d44,
2474 .pd = {
2475 .name = "ufs",
2476 },
2477 .pwrsts = PWRSTS_OFF_ON,
2478 };
2479
2480 static struct clk_regmap *gcc_msm8994_clocks[] = {
2481 [GPLL0_EARLY] = &gpll0_early.clkr,
2482 [GPLL0] = &gpll0.clkr,
2483 [GPLL4_EARLY] = &gpll4_early.clkr,
2484 [GPLL4] = &gpll4.clkr,
2485 [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr,
2486 [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
2487 [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
2488 [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
2489 [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
2490 [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
2491 [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
2492 [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
2493 [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
2494 [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
2495 [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
2496 [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
2497 [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
2498 [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
2499 [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
2500 [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
2501 [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
2502 [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
2503 [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
2504 [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
2505 [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
2506 [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
2507 [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
2508 [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
2509 [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
2510 [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
2511 [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
2512 [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
2513 [BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr,
2514 [BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr,
2515 [BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr,
2516 [BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr,
2517 [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
2518 [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
2519 [BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr,
2520 [BLSP2_UART4_APPS_CLK_SRC] = &blsp2_uart4_apps_clk_src.clkr,
2521 [BLSP2_UART5_APPS_CLK_SRC] = &blsp2_uart5_apps_clk_src.clkr,
2522 [BLSP2_UART6_APPS_CLK_SRC] = &blsp2_uart6_apps_clk_src.clkr,
2523 [GP1_CLK_SRC] = &gp1_clk_src.clkr,
2524 [GP2_CLK_SRC] = &gp2_clk_src.clkr,
2525 [GP3_CLK_SRC] = &gp3_clk_src.clkr,
2526 [PCIE_0_AUX_CLK_SRC] = &pcie_0_aux_clk_src.clkr,
2527 [PCIE_0_PIPE_CLK_SRC] = &pcie_0_pipe_clk_src.clkr,
2528 [PCIE_1_AUX_CLK_SRC] = &pcie_1_aux_clk_src.clkr,
2529 [PCIE_1_PIPE_CLK_SRC] = &pcie_1_pipe_clk_src.clkr,
2530 [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
2531 [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
2532 [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
2533 [SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr,
2534 [SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr,
2535 [TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr,
2536 [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
2537 [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,
2538 [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
2539 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
2540 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
2541 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
2542 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
2543 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
2544 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
2545 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
2546 [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
2547 [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
2548 [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
2549 [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
2550 [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
2551 [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
2552 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
2553 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
2554 [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
2555 [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
2556 [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
2557 [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
2558 [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
2559 [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
2560 [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
2561 [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
2562 [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
2563 [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
2564 [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
2565 [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
2566 [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
2567 [GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr,
2568 [GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr,
2569 [GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr,
2570 [GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr,
2571 [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
2572 [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
2573 [GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr,
2574 [GCC_BLSP2_UART4_APPS_CLK] = &gcc_blsp2_uart4_apps_clk.clkr,
2575 [GCC_BLSP2_UART5_APPS_CLK] = &gcc_blsp2_uart5_apps_clk.clkr,
2576 [GCC_BLSP2_UART6_APPS_CLK] = &gcc_blsp2_uart6_apps_clk.clkr,
2577 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
2578 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
2579 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
2580 [GCC_LPASS_Q6_AXI_CLK] = &gcc_lpass_q6_axi_clk.clkr,
2581 [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
2582 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
2583 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
2584 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
2585 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
2586 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
2587 [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
2588 [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
2589 [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
2590 [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
2591 [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
2592 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
2593 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
2594 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
2595 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
2596 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
2597 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
2598 [GCC_SDCC3_AHB_CLK] = &gcc_sdcc3_ahb_clk.clkr,
2599 [GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr,
2600 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
2601 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
2602 [GCC_SYS_NOC_UFS_AXI_CLK] = &gcc_sys_noc_ufs_axi_clk.clkr,
2603 [GCC_SYS_NOC_USB3_AXI_CLK] = &gcc_sys_noc_usb3_axi_clk.clkr,
2604 [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
2605 [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
2606 [GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr,
2607 [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr,
2608 [GCC_UFS_RX_CFG_CLK] = &gcc_ufs_rx_cfg_clk.clkr,
2609 [GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr,
2610 [GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr,
2611 [GCC_UFS_TX_CFG_CLK] = &gcc_ufs_tx_cfg_clk.clkr,
2612 [GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr,
2613 [GCC_UFS_TX_SYMBOL_1_CLK] = &gcc_ufs_tx_symbol_1_clk.clkr,
2614 [GCC_USB2_HS_PHY_SLEEP_CLK] = &gcc_usb2_hs_phy_sleep_clk.clkr,
2615 [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
2616 [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
2617 [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
2618 [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,
2619 [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr,
2620 [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
2621 [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
2622 };
2623
2624 static struct gdsc *gcc_msm8994_gdscs[] = {
2625 [PCIE_GDSC] = &pcie_gdsc,
2626 [PCIE_0_GDSC] = &pcie_0_gdsc,
2627 [PCIE_1_GDSC] = &pcie_1_gdsc,
2628 [USB30_GDSC] = &usb30_gdsc,
2629 [UFS_GDSC] = &ufs_gdsc,
2630 };
2631
2632 static const struct qcom_reset_map gcc_msm8994_resets[] = {
2633 [USB3_PHY_RESET] = { 0x1400 },
2634 [USB3PHY_PHY_RESET] = { 0x1404 },
2635 [PCIE_PHY_0_RESET] = { 0x1b18 },
2636 [PCIE_PHY_1_RESET] = { 0x1b98 },
2637 [QUSB2_PHY_RESET] = { 0x04b8 },
2638 };
2639
2640 static const struct regmap_config gcc_msm8994_regmap_config = {
2641 .reg_bits = 32,
2642 .reg_stride = 4,
2643 .val_bits = 32,
2644 .max_register = 0x2000,
2645 .fast_io = true,
2646 };
2647
2648 static const struct qcom_cc_desc gcc_msm8994_desc = {
2649 .config = &gcc_msm8994_regmap_config,
2650 .clks = gcc_msm8994_clocks,
2651 .num_clks = ARRAY_SIZE(gcc_msm8994_clocks),
2652 .resets = gcc_msm8994_resets,
2653 .num_resets = ARRAY_SIZE(gcc_msm8994_resets),
2654 .gdscs = gcc_msm8994_gdscs,
2655 .num_gdscs = ARRAY_SIZE(gcc_msm8994_gdscs),
2656 };
2657
2658 static const struct of_device_id gcc_msm8994_match_table[] = {
2659 { .compatible = "qcom,gcc-msm8994" },
2660 {}
2661 };
2662 MODULE_DEVICE_TABLE(of, gcc_msm8994_match_table);
2663
gcc_msm8994_probe(struct platform_device * pdev)2664 static int gcc_msm8994_probe(struct platform_device *pdev)
2665 {
2666 struct device *dev = &pdev->dev;
2667 struct clk *clk;
2668
2669 clk = devm_clk_register(dev, &xo.hw);
2670 if (IS_ERR(clk))
2671 return PTR_ERR(clk);
2672
2673 return qcom_cc_probe(pdev, &gcc_msm8994_desc);
2674 }
2675
2676 static struct platform_driver gcc_msm8994_driver = {
2677 .probe = gcc_msm8994_probe,
2678 .driver = {
2679 .name = "gcc-msm8994",
2680 .of_match_table = gcc_msm8994_match_table,
2681 },
2682 };
2683
gcc_msm8994_init(void)2684 static int __init gcc_msm8994_init(void)
2685 {
2686 return platform_driver_register(&gcc_msm8994_driver);
2687 }
2688 core_initcall(gcc_msm8994_init);
2689
gcc_msm8994_exit(void)2690 static void __exit gcc_msm8994_exit(void)
2691 {
2692 platform_driver_unregister(&gcc_msm8994_driver);
2693 }
2694 module_exit(gcc_msm8994_exit);
2695
2696 MODULE_DESCRIPTION("Qualcomm GCC MSM8994 Driver");
2697 MODULE_LICENSE("GPL v2");
2698 MODULE_ALIAS("platform:gcc-msm8994");
2699