1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2019, Jeffrey Hugo
4 */
5
6 #include <linux/kernel.h>
7 #include <linux/bitops.h>
8 #include <linux/err.h>
9 #include <linux/platform_device.h>
10 #include <linux/module.h>
11 #include <linux/of.h>
12 #include <linux/of_device.h>
13 #include <linux/clk-provider.h>
14 #include <linux/regmap.h>
15 #include <linux/reset-controller.h>
16
17 #include <dt-bindings/clock/qcom,gpucc-msm8998.h>
18
19 #include "common.h"
20 #include "clk-regmap.h"
21 #include "clk-regmap-divider.h"
22 #include "clk-alpha-pll.h"
23 #include "clk-rcg.h"
24 #include "clk-branch.h"
25 #include "reset.h"
26 #include "gdsc.h"
27
28 enum {
29 P_XO,
30 P_GPLL0,
31 P_GPUPLL0_OUT_EVEN,
32 };
33
34 /* Instead of going directly to the block, XO is routed through this branch */
35 static struct clk_branch gpucc_cxo_clk = {
36 .halt_reg = 0x1020,
37 .clkr = {
38 .enable_reg = 0x1020,
39 .enable_mask = BIT(0),
40 .hw.init = &(struct clk_init_data){
41 .name = "gpucc_cxo_clk",
42 .parent_data = &(const struct clk_parent_data){
43 .fw_name = "xo",
44 .name = "xo"
45 },
46 .num_parents = 1,
47 .ops = &clk_branch2_ops,
48 .flags = CLK_IS_CRITICAL,
49 },
50 },
51 };
52
53 static struct pll_vco fabia_vco[] = {
54 { 249600000, 2000000000, 0 },
55 { 125000000, 1000000000, 1 },
56 };
57
58 static const struct clk_div_table post_div_table_fabia_even[] = {
59 { 0x0, 1 },
60 { 0x1, 2 },
61 { 0x3, 4 },
62 { 0x7, 8 },
63 { }
64 };
65
66 static struct clk_alpha_pll gpupll0 = {
67 .offset = 0x0,
68 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
69 .vco_table = fabia_vco,
70 .num_vco = ARRAY_SIZE(fabia_vco),
71 .clkr.hw.init = &(struct clk_init_data){
72 .name = "gpupll0",
73 .parent_hws = (const struct clk_hw *[]){ &gpucc_cxo_clk.clkr.hw },
74 .num_parents = 1,
75 .ops = &clk_alpha_pll_fabia_ops,
76 },
77 };
78
79 static struct clk_alpha_pll_postdiv gpupll0_out_even = {
80 .offset = 0x0,
81 .post_div_shift = 8,
82 .post_div_table = post_div_table_fabia_even,
83 .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
84 .width = 4,
85 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
86 .clkr.hw.init = &(struct clk_init_data){
87 .name = "gpupll0_out_even",
88 .parent_hws = (const struct clk_hw *[]){ &gpupll0.clkr.hw },
89 .num_parents = 1,
90 .flags = CLK_SET_RATE_PARENT,
91 .ops = &clk_alpha_pll_postdiv_fabia_ops,
92 },
93 };
94
95 static const struct parent_map gpu_xo_gpll0_map[] = {
96 { P_XO, 0 },
97 { P_GPLL0, 5 },
98 };
99
100 static const struct clk_parent_data gpu_xo_gpll0[] = {
101 { .hw = &gpucc_cxo_clk.clkr.hw },
102 { .fw_name = "gpll0", .name = "gpll0" },
103 };
104
105 static const struct parent_map gpu_xo_gpupll0_map[] = {
106 { P_XO, 0 },
107 { P_GPUPLL0_OUT_EVEN, 1 },
108 };
109
110 static const struct clk_parent_data gpu_xo_gpupll0[] = {
111 { .hw = &gpucc_cxo_clk.clkr.hw },
112 { .hw = &gpupll0_out_even.clkr.hw },
113 };
114
115 static const struct freq_tbl ftbl_rbcpr_clk_src[] = {
116 F(19200000, P_XO, 1, 0, 0),
117 F(50000000, P_GPLL0, 12, 0, 0),
118 { }
119 };
120
121 static struct clk_rcg2 rbcpr_clk_src = {
122 .cmd_rcgr = 0x1030,
123 .hid_width = 5,
124 .parent_map = gpu_xo_gpll0_map,
125 .freq_tbl = ftbl_rbcpr_clk_src,
126 .clkr.hw.init = &(struct clk_init_data){
127 .name = "rbcpr_clk_src",
128 .parent_data = gpu_xo_gpll0,
129 .num_parents = 2,
130 .ops = &clk_rcg2_ops,
131 },
132 };
133
134 static const struct freq_tbl ftbl_gfx3d_clk_src[] = {
135 { .src = P_GPUPLL0_OUT_EVEN, .pre_div = 3 },
136 { }
137 };
138
139 static struct clk_rcg2 gfx3d_clk_src = {
140 .cmd_rcgr = 0x1070,
141 .hid_width = 5,
142 .parent_map = gpu_xo_gpupll0_map,
143 .freq_tbl = ftbl_gfx3d_clk_src,
144 .clkr.hw.init = &(struct clk_init_data){
145 .name = "gfx3d_clk_src",
146 .parent_data = gpu_xo_gpupll0,
147 .num_parents = 2,
148 .ops = &clk_rcg2_ops,
149 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
150 },
151 };
152
153 static const struct freq_tbl ftbl_rbbmtimer_clk_src[] = {
154 F(19200000, P_XO, 1, 0, 0),
155 { }
156 };
157
158 static struct clk_rcg2 rbbmtimer_clk_src = {
159 .cmd_rcgr = 0x10b0,
160 .hid_width = 5,
161 .parent_map = gpu_xo_gpll0_map,
162 .freq_tbl = ftbl_rbbmtimer_clk_src,
163 .clkr.hw.init = &(struct clk_init_data){
164 .name = "rbbmtimer_clk_src",
165 .parent_data = gpu_xo_gpll0,
166 .num_parents = 2,
167 .ops = &clk_rcg2_ops,
168 },
169 };
170
171 static const struct freq_tbl ftbl_gfx3d_isense_clk_src[] = {
172 F(19200000, P_XO, 1, 0, 0),
173 F(40000000, P_GPLL0, 15, 0, 0),
174 F(200000000, P_GPLL0, 3, 0, 0),
175 F(300000000, P_GPLL0, 2, 0, 0),
176 { }
177 };
178
179 static struct clk_rcg2 gfx3d_isense_clk_src = {
180 .cmd_rcgr = 0x1100,
181 .hid_width = 5,
182 .parent_map = gpu_xo_gpll0_map,
183 .freq_tbl = ftbl_gfx3d_isense_clk_src,
184 .clkr.hw.init = &(struct clk_init_data){
185 .name = "gfx3d_isense_clk_src",
186 .parent_data = gpu_xo_gpll0,
187 .num_parents = 2,
188 .ops = &clk_rcg2_ops,
189 },
190 };
191
192 static struct clk_branch rbcpr_clk = {
193 .halt_reg = 0x1054,
194 .clkr = {
195 .enable_reg = 0x1054,
196 .enable_mask = BIT(0),
197 .hw.init = &(struct clk_init_data){
198 .name = "rbcpr_clk",
199 .parent_hws = (const struct clk_hw *[]){ &rbcpr_clk_src.clkr.hw },
200 .num_parents = 1,
201 .ops = &clk_branch2_ops,
202 .flags = CLK_SET_RATE_PARENT,
203 },
204 },
205 };
206
207 static struct clk_branch gfx3d_clk = {
208 .halt_reg = 0x1098,
209 .clkr = {
210 .enable_reg = 0x1098,
211 .enable_mask = BIT(0),
212 .hw.init = &(struct clk_init_data){
213 .name = "gfx3d_clk",
214 .parent_hws = (const struct clk_hw *[]){ &gfx3d_clk_src.clkr.hw },
215 .num_parents = 1,
216 .ops = &clk_branch2_ops,
217 .flags = CLK_SET_RATE_PARENT,
218 },
219 },
220 };
221
222 static struct clk_branch rbbmtimer_clk = {
223 .halt_reg = 0x10d0,
224 .clkr = {
225 .enable_reg = 0x10d0,
226 .enable_mask = BIT(0),
227 .hw.init = &(struct clk_init_data){
228 .name = "rbbmtimer_clk",
229 .parent_hws = (const struct clk_hw *[]){ &rbbmtimer_clk_src.clkr.hw },
230 .num_parents = 1,
231 .ops = &clk_branch2_ops,
232 .flags = CLK_SET_RATE_PARENT,
233 },
234 },
235 };
236
237 static struct clk_branch gfx3d_isense_clk = {
238 .halt_reg = 0x1124,
239 .clkr = {
240 .enable_reg = 0x1124,
241 .enable_mask = BIT(0),
242 .hw.init = &(struct clk_init_data){
243 .name = "gfx3d_isense_clk",
244 .parent_hws = (const struct clk_hw *[]){ &gfx3d_isense_clk_src.clkr.hw },
245 .num_parents = 1,
246 .ops = &clk_branch2_ops,
247 },
248 },
249 };
250
251 static struct gdsc gpu_cx_gdsc = {
252 .gdscr = 0x1004,
253 .gds_hw_ctrl = 0x1008,
254 .pd = {
255 .name = "gpu_cx",
256 },
257 .pwrsts = PWRSTS_OFF_ON,
258 .flags = VOTABLE,
259 };
260
261 static struct gdsc gpu_gx_gdsc = {
262 .gdscr = 0x1094,
263 .clamp_io_ctrl = 0x130,
264 .resets = (unsigned int []){ GPU_GX_BCR },
265 .reset_count = 1,
266 .cxcs = (unsigned int []){ 0x1098 },
267 .cxc_count = 1,
268 .pd = {
269 .name = "gpu_gx",
270 },
271 .parent = &gpu_cx_gdsc.pd,
272 .pwrsts = PWRSTS_OFF_ON | PWRSTS_RET,
273 .flags = CLAMP_IO | SW_RESET | AON_RESET | NO_RET_PERIPH,
274 };
275
276 static struct clk_regmap *gpucc_msm8998_clocks[] = {
277 [GPUPLL0] = &gpupll0.clkr,
278 [GPUPLL0_OUT_EVEN] = &gpupll0_out_even.clkr,
279 [RBCPR_CLK_SRC] = &rbcpr_clk_src.clkr,
280 [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
281 [RBBMTIMER_CLK_SRC] = &rbbmtimer_clk_src.clkr,
282 [GFX3D_ISENSE_CLK_SRC] = &gfx3d_isense_clk_src.clkr,
283 [RBCPR_CLK] = &rbcpr_clk.clkr,
284 [GFX3D_CLK] = &gfx3d_clk.clkr,
285 [RBBMTIMER_CLK] = &rbbmtimer_clk.clkr,
286 [GFX3D_ISENSE_CLK] = &gfx3d_isense_clk.clkr,
287 [GPUCC_CXO_CLK] = &gpucc_cxo_clk.clkr,
288 };
289
290 static struct gdsc *gpucc_msm8998_gdscs[] = {
291 [GPU_CX_GDSC] = &gpu_cx_gdsc,
292 [GPU_GX_GDSC] = &gpu_gx_gdsc,
293 };
294
295 static const struct qcom_reset_map gpucc_msm8998_resets[] = {
296 [GPU_CX_BCR] = { 0x1000 },
297 [RBCPR_BCR] = { 0x1050 },
298 [GPU_GX_BCR] = { 0x1090 },
299 [GPU_ISENSE_BCR] = { 0x1120 },
300 };
301
302 static const struct regmap_config gpucc_msm8998_regmap_config = {
303 .reg_bits = 32,
304 .reg_stride = 4,
305 .val_bits = 32,
306 .max_register = 0x9000,
307 .fast_io = true,
308 };
309
310 static const struct qcom_cc_desc gpucc_msm8998_desc = {
311 .config = &gpucc_msm8998_regmap_config,
312 .clks = gpucc_msm8998_clocks,
313 .num_clks = ARRAY_SIZE(gpucc_msm8998_clocks),
314 .resets = gpucc_msm8998_resets,
315 .num_resets = ARRAY_SIZE(gpucc_msm8998_resets),
316 .gdscs = gpucc_msm8998_gdscs,
317 .num_gdscs = ARRAY_SIZE(gpucc_msm8998_gdscs),
318 };
319
320 static const struct of_device_id gpucc_msm8998_match_table[] = {
321 { .compatible = "qcom,msm8998-gpucc" },
322 { }
323 };
324 MODULE_DEVICE_TABLE(of, gpucc_msm8998_match_table);
325
gpucc_msm8998_probe(struct platform_device * pdev)326 static int gpucc_msm8998_probe(struct platform_device *pdev)
327 {
328 struct regmap *regmap;
329
330 regmap = qcom_cc_map(pdev, &gpucc_msm8998_desc);
331 if (IS_ERR(regmap))
332 return PTR_ERR(regmap);
333
334 /* force periph logic on to avoid perf counter corruption */
335 regmap_write_bits(regmap, gfx3d_clk.clkr.enable_reg, BIT(13), BIT(13));
336 /* tweak droop detector (GPUCC_GPU_DD_WRAP_CTRL) to reduce leakage */
337 regmap_write_bits(regmap, gfx3d_clk.clkr.enable_reg, BIT(0), BIT(0));
338
339 return qcom_cc_really_probe(pdev, &gpucc_msm8998_desc, regmap);
340 }
341
342 static struct platform_driver gpucc_msm8998_driver = {
343 .probe = gpucc_msm8998_probe,
344 .driver = {
345 .name = "gpucc-msm8998",
346 .of_match_table = gpucc_msm8998_match_table,
347 },
348 };
349 module_platform_driver(gpucc_msm8998_driver);
350
351 MODULE_DESCRIPTION("QCOM GPUCC MSM8998 Driver");
352 MODULE_LICENSE("GPL v2");
353