1 // SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only)
2 /* Copyright(c) 2020 Intel Corporation */
3 #include <adf_accel_devices.h>
4 #include <adf_common_drv.h>
5 #include <adf_pf2vf_msg.h>
6 #include <adf_gen4_hw_data.h>
7 #include "adf_4xxx_hw_data.h"
8 #include "icp_qat_hw.h"
9
10 struct adf_fw_config {
11 u32 ae_mask;
12 char *obj_name;
13 };
14
15 static struct adf_fw_config adf_4xxx_fw_config[] = {
16 {0xF0, ADF_4XXX_SYM_OBJ},
17 {0xF, ADF_4XXX_ASYM_OBJ},
18 {0x100, ADF_4XXX_ADMIN_OBJ},
19 };
20
21 /* Worker thread to service arbiter mappings */
22 static const u32 thrd_to_arb_map[ADF_4XXX_MAX_ACCELENGINES] = {
23 0x5555555, 0x5555555, 0x5555555, 0x5555555,
24 0xAAAAAAA, 0xAAAAAAA, 0xAAAAAAA, 0xAAAAAAA,
25 0x0
26 };
27
28 static struct adf_hw_device_class adf_4xxx_class = {
29 .name = ADF_4XXX_DEVICE_NAME,
30 .type = DEV_4XXX,
31 .instances = 0,
32 };
33
get_accel_mask(struct adf_hw_device_data * self)34 static u32 get_accel_mask(struct adf_hw_device_data *self)
35 {
36 return ADF_4XXX_ACCELERATORS_MASK;
37 }
38
get_ae_mask(struct adf_hw_device_data * self)39 static u32 get_ae_mask(struct adf_hw_device_data *self)
40 {
41 u32 me_disable = self->fuses;
42
43 return ~me_disable & ADF_4XXX_ACCELENGINES_MASK;
44 }
45
get_num_accels(struct adf_hw_device_data * self)46 static u32 get_num_accels(struct adf_hw_device_data *self)
47 {
48 return ADF_4XXX_MAX_ACCELERATORS;
49 }
50
get_num_aes(struct adf_hw_device_data * self)51 static u32 get_num_aes(struct adf_hw_device_data *self)
52 {
53 if (!self || !self->ae_mask)
54 return 0;
55
56 return hweight32(self->ae_mask);
57 }
58
get_misc_bar_id(struct adf_hw_device_data * self)59 static u32 get_misc_bar_id(struct adf_hw_device_data *self)
60 {
61 return ADF_4XXX_PMISC_BAR;
62 }
63
get_etr_bar_id(struct adf_hw_device_data * self)64 static u32 get_etr_bar_id(struct adf_hw_device_data *self)
65 {
66 return ADF_4XXX_ETR_BAR;
67 }
68
get_sram_bar_id(struct adf_hw_device_data * self)69 static u32 get_sram_bar_id(struct adf_hw_device_data *self)
70 {
71 return ADF_4XXX_SRAM_BAR;
72 }
73
74 /*
75 * The vector routing table is used to select the MSI-X entry to use for each
76 * interrupt source.
77 * The first ADF_4XXX_ETR_MAX_BANKS entries correspond to ring interrupts.
78 * The final entry corresponds to VF2PF or error interrupts.
79 * This vector table could be used to configure one MSI-X entry to be shared
80 * between multiple interrupt sources.
81 *
82 * The default routing is set to have a one to one correspondence between the
83 * interrupt source and the MSI-X entry used.
84 */
set_msix_default_rttable(struct adf_accel_dev * accel_dev)85 static void set_msix_default_rttable(struct adf_accel_dev *accel_dev)
86 {
87 void __iomem *csr;
88 int i;
89
90 csr = (&GET_BARS(accel_dev)[ADF_4XXX_PMISC_BAR])->virt_addr;
91 for (i = 0; i <= ADF_4XXX_ETR_MAX_BANKS; i++)
92 ADF_CSR_WR(csr, ADF_4XXX_MSIX_RTTABLE_OFFSET(i), i);
93 }
94
get_accel_cap(struct adf_accel_dev * accel_dev)95 static u32 get_accel_cap(struct adf_accel_dev *accel_dev)
96 {
97 struct pci_dev *pdev = accel_dev->accel_pci_dev.pci_dev;
98 u32 fusectl1;
99 u32 capabilities = ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC |
100 ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC |
101 ICP_ACCEL_CAPABILITIES_AUTHENTICATION |
102 ICP_ACCEL_CAPABILITIES_AES_V2;
103
104 /* Read accelerator capabilities mask */
105 pci_read_config_dword(pdev, ADF_4XXX_FUSECTL1_OFFSET, &fusectl1);
106
107 if (fusectl1 & ICP_ACCEL_4XXX_MASK_CIPHER_SLICE)
108 capabilities &= ~ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC;
109 if (fusectl1 & ICP_ACCEL_4XXX_MASK_AUTH_SLICE)
110 capabilities &= ~ICP_ACCEL_CAPABILITIES_AUTHENTICATION;
111 if (fusectl1 & ICP_ACCEL_4XXX_MASK_PKE_SLICE)
112 capabilities &= ~ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC;
113
114 return capabilities;
115 }
116
get_sku(struct adf_hw_device_data * self)117 static enum dev_sku_info get_sku(struct adf_hw_device_data *self)
118 {
119 return DEV_SKU_1;
120 }
121
adf_get_arbiter_mapping(void)122 static const u32 *adf_get_arbiter_mapping(void)
123 {
124 return thrd_to_arb_map;
125 }
126
get_arb_info(struct arb_info * arb_info)127 static void get_arb_info(struct arb_info *arb_info)
128 {
129 arb_info->arb_cfg = ADF_4XXX_ARB_CONFIG;
130 arb_info->arb_offset = ADF_4XXX_ARB_OFFSET;
131 arb_info->wt2sam_offset = ADF_4XXX_ARB_WRK_2_SER_MAP_OFFSET;
132 }
133
get_admin_info(struct admin_info * admin_csrs_info)134 static void get_admin_info(struct admin_info *admin_csrs_info)
135 {
136 admin_csrs_info->mailbox_offset = ADF_4XXX_MAILBOX_BASE_OFFSET;
137 admin_csrs_info->admin_msg_ur = ADF_4XXX_ADMINMSGUR_OFFSET;
138 admin_csrs_info->admin_msg_lr = ADF_4XXX_ADMINMSGLR_OFFSET;
139 }
140
adf_enable_error_correction(struct adf_accel_dev * accel_dev)141 static void adf_enable_error_correction(struct adf_accel_dev *accel_dev)
142 {
143 struct adf_bar *misc_bar = &GET_BARS(accel_dev)[ADF_4XXX_PMISC_BAR];
144 void __iomem *csr = misc_bar->virt_addr;
145
146 /* Enable all in errsou3 except VFLR notification on host */
147 ADF_CSR_WR(csr, ADF_4XXX_ERRMSK3, ADF_4XXX_VFLNOTIFY);
148 }
149
adf_enable_ints(struct adf_accel_dev * accel_dev)150 static void adf_enable_ints(struct adf_accel_dev *accel_dev)
151 {
152 void __iomem *addr;
153
154 addr = (&GET_BARS(accel_dev)[ADF_4XXX_PMISC_BAR])->virt_addr;
155
156 /* Enable bundle interrupts */
157 ADF_CSR_WR(addr, ADF_4XXX_SMIAPF_RP_X0_MASK_OFFSET, 0);
158 ADF_CSR_WR(addr, ADF_4XXX_SMIAPF_RP_X1_MASK_OFFSET, 0);
159
160 /* Enable misc interrupts */
161 ADF_CSR_WR(addr, ADF_4XXX_SMIAPF_MASK_OFFSET, 0);
162 }
163
adf_pf_enable_vf2pf_comms(struct adf_accel_dev * accel_dev)164 static int adf_pf_enable_vf2pf_comms(struct adf_accel_dev *accel_dev)
165 {
166 return 0;
167 }
168
uof_get_num_objs(void)169 static u32 uof_get_num_objs(void)
170 {
171 return ARRAY_SIZE(adf_4xxx_fw_config);
172 }
173
uof_get_name(u32 obj_num)174 static char *uof_get_name(u32 obj_num)
175 {
176 return adf_4xxx_fw_config[obj_num].obj_name;
177 }
178
uof_get_ae_mask(u32 obj_num)179 static u32 uof_get_ae_mask(u32 obj_num)
180 {
181 return adf_4xxx_fw_config[obj_num].ae_mask;
182 }
183
adf_init_hw_data_4xxx(struct adf_hw_device_data * hw_data)184 void adf_init_hw_data_4xxx(struct adf_hw_device_data *hw_data)
185 {
186 hw_data->dev_class = &adf_4xxx_class;
187 hw_data->instance_id = adf_4xxx_class.instances++;
188 hw_data->num_banks = ADF_4XXX_ETR_MAX_BANKS;
189 hw_data->num_rings_per_bank = ADF_4XXX_NUM_RINGS_PER_BANK;
190 hw_data->num_accel = ADF_4XXX_MAX_ACCELERATORS;
191 hw_data->num_engines = ADF_4XXX_MAX_ACCELENGINES;
192 hw_data->num_logical_accel = 1;
193 hw_data->tx_rx_gap = ADF_4XXX_RX_RINGS_OFFSET;
194 hw_data->tx_rings_mask = ADF_4XXX_TX_RINGS_MASK;
195 hw_data->alloc_irq = adf_isr_resource_alloc;
196 hw_data->free_irq = adf_isr_resource_free;
197 hw_data->enable_error_correction = adf_enable_error_correction;
198 hw_data->get_accel_mask = get_accel_mask;
199 hw_data->get_ae_mask = get_ae_mask;
200 hw_data->get_num_accels = get_num_accels;
201 hw_data->get_num_aes = get_num_aes;
202 hw_data->get_sram_bar_id = get_sram_bar_id;
203 hw_data->get_etr_bar_id = get_etr_bar_id;
204 hw_data->get_misc_bar_id = get_misc_bar_id;
205 hw_data->get_arb_info = get_arb_info;
206 hw_data->get_admin_info = get_admin_info;
207 hw_data->get_accel_cap = get_accel_cap;
208 hw_data->get_sku = get_sku;
209 hw_data->fw_name = ADF_4XXX_FW;
210 hw_data->fw_mmp_name = ADF_4XXX_MMP;
211 hw_data->init_admin_comms = adf_init_admin_comms;
212 hw_data->exit_admin_comms = adf_exit_admin_comms;
213 hw_data->disable_iov = adf_disable_sriov;
214 hw_data->send_admin_init = adf_send_admin_init;
215 hw_data->init_arb = adf_init_arb;
216 hw_data->exit_arb = adf_exit_arb;
217 hw_data->get_arb_mapping = adf_get_arbiter_mapping;
218 hw_data->enable_ints = adf_enable_ints;
219 hw_data->enable_vf2pf_comms = adf_pf_enable_vf2pf_comms;
220 hw_data->reset_device = adf_reset_flr;
221 hw_data->min_iov_compat_ver = ADF_PFVF_COMPATIBILITY_VERSION;
222 hw_data->admin_ae_mask = ADF_4XXX_ADMIN_AE_MASK;
223 hw_data->uof_get_num_objs = uof_get_num_objs;
224 hw_data->uof_get_name = uof_get_name;
225 hw_data->uof_get_ae_mask = uof_get_ae_mask;
226 hw_data->set_msix_rttable = set_msix_default_rttable;
227 hw_data->set_ssm_wdtimer = adf_gen4_set_ssm_wdtimer;
228
229 adf_gen4_init_hw_csr_ops(&hw_data->csr_ops);
230 }
231
adf_clean_hw_data_4xxx(struct adf_hw_device_data * hw_data)232 void adf_clean_hw_data_4xxx(struct adf_hw_device_data *hw_data)
233 {
234 hw_data->dev_class->instances--;
235 }
236