1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include <linux/delay.h>
27 #include <linux/slab.h>
28
29 #include "dm_services.h"
30 #include "basics/dc_common.h"
31 #include "dc.h"
32 #include "core_types.h"
33 #include "resource.h"
34 #include "ipp.h"
35 #include "timing_generator.h"
36
37 #define DC_LOGGER dc->ctx->logger
38
39 /*******************************************************************************
40 * Private functions
41 ******************************************************************************/
update_stream_signal(struct dc_stream_state * stream,struct dc_sink * sink)42 void update_stream_signal(struct dc_stream_state *stream, struct dc_sink *sink)
43 {
44 if (sink->sink_signal == SIGNAL_TYPE_NONE)
45 stream->signal = stream->link->connector_signal;
46 else
47 stream->signal = sink->sink_signal;
48
49 if (dc_is_dvi_signal(stream->signal)) {
50 if (stream->ctx->dc->caps.dual_link_dvi &&
51 (stream->timing.pix_clk_100hz / 10) > TMDS_MAX_PIXEL_CLOCK &&
52 sink->sink_signal != SIGNAL_TYPE_DVI_SINGLE_LINK)
53 stream->signal = SIGNAL_TYPE_DVI_DUAL_LINK;
54 else
55 stream->signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
56 }
57 }
58
dc_stream_construct(struct dc_stream_state * stream,struct dc_sink * dc_sink_data)59 static bool dc_stream_construct(struct dc_stream_state *stream,
60 struct dc_sink *dc_sink_data)
61 {
62 uint32_t i = 0;
63
64 stream->sink = dc_sink_data;
65 dc_sink_retain(dc_sink_data);
66
67 stream->ctx = dc_sink_data->ctx;
68 stream->link = dc_sink_data->link;
69 stream->sink_patches = dc_sink_data->edid_caps.panel_patch;
70 stream->converter_disable_audio = dc_sink_data->converter_disable_audio;
71 stream->qs_bit = dc_sink_data->edid_caps.qs_bit;
72 stream->qy_bit = dc_sink_data->edid_caps.qy_bit;
73
74 /* Copy audio modes */
75 /* TODO - Remove this translation */
76 for (i = 0; i < (dc_sink_data->edid_caps.audio_mode_count); i++)
77 {
78 stream->audio_info.modes[i].channel_count = dc_sink_data->edid_caps.audio_modes[i].channel_count;
79 stream->audio_info.modes[i].format_code = dc_sink_data->edid_caps.audio_modes[i].format_code;
80 stream->audio_info.modes[i].sample_rates.all = dc_sink_data->edid_caps.audio_modes[i].sample_rate;
81 stream->audio_info.modes[i].sample_size = dc_sink_data->edid_caps.audio_modes[i].sample_size;
82 }
83 stream->audio_info.mode_count = dc_sink_data->edid_caps.audio_mode_count;
84 stream->audio_info.audio_latency = dc_sink_data->edid_caps.audio_latency;
85 stream->audio_info.video_latency = dc_sink_data->edid_caps.video_latency;
86 memmove(
87 stream->audio_info.display_name,
88 dc_sink_data->edid_caps.display_name,
89 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
90 stream->audio_info.manufacture_id = dc_sink_data->edid_caps.manufacturer_id;
91 stream->audio_info.product_id = dc_sink_data->edid_caps.product_id;
92 stream->audio_info.flags.all = dc_sink_data->edid_caps.speaker_flags;
93
94 if (dc_sink_data->dc_container_id != NULL) {
95 struct dc_container_id *dc_container_id = dc_sink_data->dc_container_id;
96
97 stream->audio_info.port_id[0] = dc_container_id->portId[0];
98 stream->audio_info.port_id[1] = dc_container_id->portId[1];
99 } else {
100 /* TODO - WindowDM has implemented,
101 other DMs need Unhardcode port_id */
102 stream->audio_info.port_id[0] = 0x5558859e;
103 stream->audio_info.port_id[1] = 0xd989449;
104 }
105
106 /* EDID CAP translation for HDMI 2.0 */
107 stream->timing.flags.LTE_340MCSC_SCRAMBLE = dc_sink_data->edid_caps.lte_340mcsc_scramble;
108
109 memset(&stream->timing.dsc_cfg, 0, sizeof(stream->timing.dsc_cfg));
110 stream->timing.dsc_cfg.num_slices_h = 0;
111 stream->timing.dsc_cfg.num_slices_v = 0;
112 stream->timing.dsc_cfg.bits_per_pixel = 128;
113 stream->timing.dsc_cfg.block_pred_enable = 1;
114 stream->timing.dsc_cfg.linebuf_depth = 9;
115 stream->timing.dsc_cfg.version_minor = 2;
116 stream->timing.dsc_cfg.ycbcr422_simple = 0;
117
118 update_stream_signal(stream, dc_sink_data);
119
120 stream->out_transfer_func = dc_create_transfer_func();
121 if (stream->out_transfer_func == NULL) {
122 dc_sink_release(dc_sink_data);
123 return false;
124 }
125 stream->out_transfer_func->type = TF_TYPE_BYPASS;
126
127 stream->stream_id = stream->ctx->dc_stream_id_count;
128 stream->ctx->dc_stream_id_count++;
129
130 return true;
131 }
132
dc_stream_destruct(struct dc_stream_state * stream)133 static void dc_stream_destruct(struct dc_stream_state *stream)
134 {
135 dc_sink_release(stream->sink);
136 if (stream->out_transfer_func != NULL) {
137 dc_transfer_func_release(stream->out_transfer_func);
138 stream->out_transfer_func = NULL;
139 }
140 }
141
dc_stream_retain(struct dc_stream_state * stream)142 void dc_stream_retain(struct dc_stream_state *stream)
143 {
144 kref_get(&stream->refcount);
145 }
146
dc_stream_free(struct kref * kref)147 static void dc_stream_free(struct kref *kref)
148 {
149 struct dc_stream_state *stream = container_of(kref, struct dc_stream_state, refcount);
150
151 dc_stream_destruct(stream);
152 kfree(stream);
153 }
154
dc_stream_release(struct dc_stream_state * stream)155 void dc_stream_release(struct dc_stream_state *stream)
156 {
157 if (stream != NULL) {
158 kref_put(&stream->refcount, dc_stream_free);
159 }
160 }
161
dc_create_stream_for_sink(struct dc_sink * sink)162 struct dc_stream_state *dc_create_stream_for_sink(
163 struct dc_sink *sink)
164 {
165 struct dc_stream_state *stream;
166
167 if (sink == NULL)
168 return NULL;
169
170 stream = kzalloc(sizeof(struct dc_stream_state), GFP_KERNEL);
171 if (stream == NULL)
172 goto alloc_fail;
173
174 if (dc_stream_construct(stream, sink) == false)
175 goto construct_fail;
176
177 kref_init(&stream->refcount);
178
179 return stream;
180
181 construct_fail:
182 kfree(stream);
183
184 alloc_fail:
185 return NULL;
186 }
187
dc_copy_stream(const struct dc_stream_state * stream)188 struct dc_stream_state *dc_copy_stream(const struct dc_stream_state *stream)
189 {
190 struct dc_stream_state *new_stream;
191
192 new_stream = kmemdup(stream, sizeof(struct dc_stream_state), GFP_KERNEL);
193 if (!new_stream)
194 return NULL;
195
196 if (new_stream->sink)
197 dc_sink_retain(new_stream->sink);
198
199 if (new_stream->out_transfer_func)
200 dc_transfer_func_retain(new_stream->out_transfer_func);
201
202 new_stream->stream_id = new_stream->ctx->dc_stream_id_count;
203 new_stream->ctx->dc_stream_id_count++;
204
205 kref_init(&new_stream->refcount);
206
207 return new_stream;
208 }
209
210 /**
211 * dc_stream_get_status_from_state - Get stream status from given dc state
212 * @state: DC state to find the stream status in
213 * @stream: The stream to get the stream status for
214 *
215 * The given stream is expected to exist in the given dc state. Otherwise, NULL
216 * will be returned.
217 */
dc_stream_get_status_from_state(struct dc_state * state,struct dc_stream_state * stream)218 struct dc_stream_status *dc_stream_get_status_from_state(
219 struct dc_state *state,
220 struct dc_stream_state *stream)
221 {
222 uint8_t i;
223
224 for (i = 0; i < state->stream_count; i++) {
225 if (stream == state->streams[i])
226 return &state->stream_status[i];
227 }
228
229 return NULL;
230 }
231
232 /**
233 * dc_stream_get_status() - Get current stream status of the given stream state
234 * @stream: The stream to get the stream status for.
235 *
236 * The given stream is expected to exist in dc->current_state. Otherwise, NULL
237 * will be returned.
238 */
dc_stream_get_status(struct dc_stream_state * stream)239 struct dc_stream_status *dc_stream_get_status(
240 struct dc_stream_state *stream)
241 {
242 struct dc *dc = stream->ctx->dc;
243 return dc_stream_get_status_from_state(dc->current_state, stream);
244 }
245
246 #ifndef TRIM_FSFT
247 /*
248 * dc_optimize_timing_for_fsft() - dc to optimize timing
249 */
dc_optimize_timing_for_fsft(struct dc_stream_state * pStream,unsigned int max_input_rate_in_khz)250 bool dc_optimize_timing_for_fsft(
251 struct dc_stream_state *pStream,
252 unsigned int max_input_rate_in_khz)
253 {
254 struct dc *dc;
255
256 dc = pStream->ctx->dc;
257
258 return (dc->hwss.optimize_timing_for_fsft &&
259 dc->hwss.optimize_timing_for_fsft(dc, &pStream->timing, max_input_rate_in_khz));
260 }
261 #endif
262
263 /*
264 * dc_stream_set_cursor_attributes() - Update cursor attributes and set cursor surface address
265 */
dc_stream_set_cursor_attributes(struct dc_stream_state * stream,const struct dc_cursor_attributes * attributes)266 bool dc_stream_set_cursor_attributes(
267 struct dc_stream_state *stream,
268 const struct dc_cursor_attributes *attributes)
269 {
270 int i;
271 struct dc *dc;
272 struct resource_context *res_ctx;
273 struct pipe_ctx *pipe_to_program = NULL;
274 #if defined(CONFIG_DRM_AMD_DC_DCN)
275 bool reset_idle_optimizations = false;
276 #endif
277
278 if (NULL == stream) {
279 dm_error("DC: dc_stream is NULL!\n");
280 return false;
281 }
282 if (NULL == attributes) {
283 dm_error("DC: attributes is NULL!\n");
284 return false;
285 }
286
287 if (attributes->address.quad_part == 0) {
288 dm_output_to_console("DC: Cursor address is 0!\n");
289 return false;
290 }
291
292 dc = stream->ctx->dc;
293 res_ctx = &dc->current_state->res_ctx;
294 stream->cursor_attributes = *attributes;
295
296 #if defined(CONFIG_DRM_AMD_DC_DCN)
297 /* disable idle optimizations while updating cursor */
298 if (dc->idle_optimizations_allowed) {
299 dc_allow_idle_optimizations(dc, false);
300 reset_idle_optimizations = true;
301 }
302
303 #endif
304
305 for (i = 0; i < MAX_PIPES; i++) {
306 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
307
308 if (pipe_ctx->stream != stream)
309 continue;
310
311 if (!pipe_to_program) {
312 pipe_to_program = pipe_ctx;
313 dc->hwss.cursor_lock(dc, pipe_to_program, true);
314 }
315
316 dc->hwss.set_cursor_attribute(pipe_ctx);
317 if (dc->hwss.set_cursor_sdr_white_level)
318 dc->hwss.set_cursor_sdr_white_level(pipe_ctx);
319 }
320
321 if (pipe_to_program)
322 dc->hwss.cursor_lock(dc, pipe_to_program, false);
323
324 #if defined(CONFIG_DRM_AMD_DC_DCN)
325 /* re-enable idle optimizations if necessary */
326 if (reset_idle_optimizations)
327 dc_allow_idle_optimizations(dc, true);
328
329 #endif
330 return true;
331 }
332
dc_stream_set_cursor_position(struct dc_stream_state * stream,const struct dc_cursor_position * position)333 bool dc_stream_set_cursor_position(
334 struct dc_stream_state *stream,
335 const struct dc_cursor_position *position)
336 {
337 int i;
338 struct dc *dc;
339 struct resource_context *res_ctx;
340 struct pipe_ctx *pipe_to_program = NULL;
341 #if defined(CONFIG_DRM_AMD_DC_DCN)
342 bool reset_idle_optimizations = false;
343 #endif
344
345 if (NULL == stream) {
346 dm_error("DC: dc_stream is NULL!\n");
347 return false;
348 }
349
350 if (NULL == position) {
351 dm_error("DC: cursor position is NULL!\n");
352 return false;
353 }
354
355 dc = stream->ctx->dc;
356 res_ctx = &dc->current_state->res_ctx;
357 #if defined(CONFIG_DRM_AMD_DC_DCN)
358
359 /* disable idle optimizations if enabling cursor */
360 if (dc->idle_optimizations_allowed && !stream->cursor_position.enable && position->enable) {
361 dc_allow_idle_optimizations(dc, false);
362 reset_idle_optimizations = true;
363 }
364
365 #endif
366 stream->cursor_position = *position;
367
368 for (i = 0; i < MAX_PIPES; i++) {
369 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
370
371 if (pipe_ctx->stream != stream ||
372 (!pipe_ctx->plane_res.mi && !pipe_ctx->plane_res.hubp) ||
373 !pipe_ctx->plane_state ||
374 (!pipe_ctx->plane_res.xfm && !pipe_ctx->plane_res.dpp) ||
375 (!pipe_ctx->plane_res.ipp && !pipe_ctx->plane_res.dpp))
376 continue;
377
378 if (!pipe_to_program) {
379 pipe_to_program = pipe_ctx;
380 dc->hwss.cursor_lock(dc, pipe_to_program, true);
381 }
382
383 dc->hwss.set_cursor_position(pipe_ctx);
384 }
385
386 if (pipe_to_program)
387 dc->hwss.cursor_lock(dc, pipe_to_program, false);
388
389 #if defined(CONFIG_DRM_AMD_DC_DCN)
390 /* re-enable idle optimizations if necessary */
391 if (reset_idle_optimizations)
392 dc_allow_idle_optimizations(dc, true);
393
394 #endif
395 return true;
396 }
397
dc_stream_add_writeback(struct dc * dc,struct dc_stream_state * stream,struct dc_writeback_info * wb_info)398 bool dc_stream_add_writeback(struct dc *dc,
399 struct dc_stream_state *stream,
400 struct dc_writeback_info *wb_info)
401 {
402 bool isDrc = false;
403 int i = 0;
404 struct dwbc *dwb;
405
406 if (stream == NULL) {
407 dm_error("DC: dc_stream is NULL!\n");
408 return false;
409 }
410
411 if (wb_info == NULL) {
412 dm_error("DC: dc_writeback_info is NULL!\n");
413 return false;
414 }
415
416 if (wb_info->dwb_pipe_inst >= MAX_DWB_PIPES) {
417 dm_error("DC: writeback pipe is invalid!\n");
418 return false;
419 }
420
421 wb_info->dwb_params.out_transfer_func = stream->out_transfer_func;
422
423 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
424 dwb->dwb_is_drc = false;
425
426 /* recalculate and apply DML parameters */
427
428 for (i = 0; i < stream->num_wb_info; i++) {
429 /*dynamic update*/
430 if (stream->writeback_info[i].wb_enabled &&
431 stream->writeback_info[i].dwb_pipe_inst == wb_info->dwb_pipe_inst) {
432 stream->writeback_info[i] = *wb_info;
433 isDrc = true;
434 }
435 }
436
437 if (!isDrc) {
438 stream->writeback_info[stream->num_wb_info++] = *wb_info;
439 }
440
441 if (dc->hwss.enable_writeback) {
442 struct dc_stream_status *stream_status = dc_stream_get_status(stream);
443 struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
444 dwb->otg_inst = stream_status->primary_otg_inst;
445 }
446 if (IS_DIAG_DC(dc->ctx->dce_environment)) {
447 if (!dc->hwss.update_bandwidth(dc, dc->current_state)) {
448 dm_error("DC: update_bandwidth failed!\n");
449 return false;
450 }
451
452 /* enable writeback */
453 if (dc->hwss.enable_writeback) {
454 struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
455
456 if (dwb->funcs->is_enabled(dwb)) {
457 /* writeback pipe already enabled, only need to update */
458 dc->hwss.update_writeback(dc, wb_info, dc->current_state);
459 } else {
460 /* Enable writeback pipe from scratch*/
461 dc->hwss.enable_writeback(dc, wb_info, dc->current_state);
462 }
463 }
464 }
465 return true;
466 }
467
dc_stream_remove_writeback(struct dc * dc,struct dc_stream_state * stream,uint32_t dwb_pipe_inst)468 bool dc_stream_remove_writeback(struct dc *dc,
469 struct dc_stream_state *stream,
470 uint32_t dwb_pipe_inst)
471 {
472 int i = 0, j = 0;
473 if (stream == NULL) {
474 dm_error("DC: dc_stream is NULL!\n");
475 return false;
476 }
477
478 if (dwb_pipe_inst >= MAX_DWB_PIPES) {
479 dm_error("DC: writeback pipe is invalid!\n");
480 return false;
481 }
482
483 // stream->writeback_info[dwb_pipe_inst].wb_enabled = false;
484 for (i = 0; i < stream->num_wb_info; i++) {
485 /*dynamic update*/
486 if (stream->writeback_info[i].wb_enabled &&
487 stream->writeback_info[i].dwb_pipe_inst == dwb_pipe_inst) {
488 stream->writeback_info[i].wb_enabled = false;
489 }
490 }
491
492 /* remove writeback info for disabled writeback pipes from stream */
493 for (i = 0, j = 0; i < stream->num_wb_info; i++) {
494 if (stream->writeback_info[i].wb_enabled) {
495 if (i != j)
496 /* trim the array */
497 stream->writeback_info[j] = stream->writeback_info[i];
498 j++;
499 }
500 }
501 stream->num_wb_info = j;
502
503 if (IS_DIAG_DC(dc->ctx->dce_environment)) {
504 /* recalculate and apply DML parameters */
505 if (!dc->hwss.update_bandwidth(dc, dc->current_state)) {
506 dm_error("DC: update_bandwidth failed!\n");
507 return false;
508 }
509
510 /* disable writeback */
511 if (dc->hwss.disable_writeback)
512 dc->hwss.disable_writeback(dc, dwb_pipe_inst);
513 }
514 return true;
515 }
516
dc_stream_warmup_writeback(struct dc * dc,int num_dwb,struct dc_writeback_info * wb_info)517 bool dc_stream_warmup_writeback(struct dc *dc,
518 int num_dwb,
519 struct dc_writeback_info *wb_info)
520 {
521 if (dc->hwss.mmhubbub_warmup)
522 return dc->hwss.mmhubbub_warmup(dc, num_dwb, wb_info);
523 else
524 return false;
525 }
dc_stream_get_vblank_counter(const struct dc_stream_state * stream)526 uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream)
527 {
528 uint8_t i;
529 struct dc *dc = stream->ctx->dc;
530 struct resource_context *res_ctx =
531 &dc->current_state->res_ctx;
532
533 for (i = 0; i < MAX_PIPES; i++) {
534 struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg;
535
536 if (res_ctx->pipe_ctx[i].stream != stream)
537 continue;
538
539 return tg->funcs->get_frame_count(tg);
540 }
541
542 return 0;
543 }
544
dc_stream_send_dp_sdp(const struct dc_stream_state * stream,const uint8_t * custom_sdp_message,unsigned int sdp_message_size)545 bool dc_stream_send_dp_sdp(const struct dc_stream_state *stream,
546 const uint8_t *custom_sdp_message,
547 unsigned int sdp_message_size)
548 {
549 int i;
550 struct dc *dc;
551 struct resource_context *res_ctx;
552
553 if (stream == NULL) {
554 dm_error("DC: dc_stream is NULL!\n");
555 return false;
556 }
557
558 dc = stream->ctx->dc;
559 res_ctx = &dc->current_state->res_ctx;
560
561 for (i = 0; i < MAX_PIPES; i++) {
562 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
563
564 if (pipe_ctx->stream != stream)
565 continue;
566
567 if (dc->hwss.send_immediate_sdp_message != NULL)
568 dc->hwss.send_immediate_sdp_message(pipe_ctx,
569 custom_sdp_message,
570 sdp_message_size);
571 else
572 DC_LOG_WARNING("%s:send_immediate_sdp_message not implemented on this ASIC\n",
573 __func__);
574
575 }
576
577 return true;
578 }
579
dc_stream_get_scanoutpos(const struct dc_stream_state * stream,uint32_t * v_blank_start,uint32_t * v_blank_end,uint32_t * h_position,uint32_t * v_position)580 bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream,
581 uint32_t *v_blank_start,
582 uint32_t *v_blank_end,
583 uint32_t *h_position,
584 uint32_t *v_position)
585 {
586 uint8_t i;
587 bool ret = false;
588 struct dc *dc = stream->ctx->dc;
589 struct resource_context *res_ctx =
590 &dc->current_state->res_ctx;
591
592 for (i = 0; i < MAX_PIPES; i++) {
593 struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg;
594
595 if (res_ctx->pipe_ctx[i].stream != stream)
596 continue;
597
598 tg->funcs->get_scanoutpos(tg,
599 v_blank_start,
600 v_blank_end,
601 h_position,
602 v_position);
603
604 ret = true;
605 break;
606 }
607
608 return ret;
609 }
610
dc_stream_dmdata_status_done(struct dc * dc,struct dc_stream_state * stream)611 bool dc_stream_dmdata_status_done(struct dc *dc, struct dc_stream_state *stream)
612 {
613 struct pipe_ctx *pipe = NULL;
614 int i;
615
616 if (!dc->hwss.dmdata_status_done)
617 return false;
618
619 for (i = 0; i < MAX_PIPES; i++) {
620 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
621 if (pipe->stream == stream)
622 break;
623 }
624 /* Stream not found, by default we'll assume HUBP fetched dm data */
625 if (i == MAX_PIPES)
626 return true;
627
628 return dc->hwss.dmdata_status_done(pipe);
629 }
630
dc_stream_set_dynamic_metadata(struct dc * dc,struct dc_stream_state * stream,struct dc_dmdata_attributes * attr)631 bool dc_stream_set_dynamic_metadata(struct dc *dc,
632 struct dc_stream_state *stream,
633 struct dc_dmdata_attributes *attr)
634 {
635 struct pipe_ctx *pipe_ctx = NULL;
636 struct hubp *hubp;
637 int i;
638
639 /* Dynamic metadata is only supported on HDMI or DP */
640 if (!dc_is_hdmi_signal(stream->signal) && !dc_is_dp_signal(stream->signal))
641 return false;
642
643 /* Check hardware support */
644 if (!dc->hwss.program_dmdata_engine)
645 return false;
646
647 for (i = 0; i < MAX_PIPES; i++) {
648 pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
649 if (pipe_ctx->stream == stream)
650 break;
651 }
652
653 if (i == MAX_PIPES)
654 return false;
655
656 hubp = pipe_ctx->plane_res.hubp;
657 if (hubp == NULL)
658 return false;
659
660 pipe_ctx->stream->dmdata_address = attr->address;
661
662 dc->hwss.program_dmdata_engine(pipe_ctx);
663
664 if (hubp->funcs->dmdata_set_attributes != NULL &&
665 pipe_ctx->stream->dmdata_address.quad_part != 0) {
666 hubp->funcs->dmdata_set_attributes(hubp, attr);
667 }
668
669 return true;
670 }
671
dc_stream_add_dsc_to_resource(struct dc * dc,struct dc_state * state,struct dc_stream_state * stream)672 enum dc_status dc_stream_add_dsc_to_resource(struct dc *dc,
673 struct dc_state *state,
674 struct dc_stream_state *stream)
675 {
676 if (dc->res_pool->funcs->add_dsc_to_stream_resource) {
677 return dc->res_pool->funcs->add_dsc_to_stream_resource(dc, state, stream);
678 } else {
679 return DC_NO_DSC_RESOURCE;
680 }
681 }
682
dc_stream_log(const struct dc * dc,const struct dc_stream_state * stream)683 void dc_stream_log(const struct dc *dc, const struct dc_stream_state *stream)
684 {
685 DC_LOG_DC(
686 "core_stream 0x%p: src: %d, %d, %d, %d; dst: %d, %d, %d, %d, colorSpace:%d\n",
687 stream,
688 stream->src.x,
689 stream->src.y,
690 stream->src.width,
691 stream->src.height,
692 stream->dst.x,
693 stream->dst.y,
694 stream->dst.width,
695 stream->dst.height,
696 stream->output_color_space);
697 DC_LOG_DC(
698 "\tpix_clk_khz: %d, h_total: %d, v_total: %d, pixelencoder:%d, displaycolorDepth:%d\n",
699 stream->timing.pix_clk_100hz / 10,
700 stream->timing.h_total,
701 stream->timing.v_total,
702 stream->timing.pixel_encoding,
703 stream->timing.display_color_depth);
704 DC_LOG_DC(
705 "\tlink: %d\n",
706 stream->link->link_index);
707 }
708
709