1 /*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include "pp_debug.h"
24 #include <linux/types.h>
25 #include <linux/kernel.h>
26 #include <linux/gfp.h>
27 #include <linux/slab.h>
28 #include <linux/firmware.h>
29 #include "amd_shared.h"
30 #include "amd_powerplay.h"
31 #include "power_state.h"
32 #include "amdgpu.h"
33 #include "hwmgr.h"
34
35
36 static const struct amd_pm_funcs pp_dpm_funcs;
37
amd_powerplay_create(struct amdgpu_device * adev)38 static int amd_powerplay_create(struct amdgpu_device *adev)
39 {
40 struct pp_hwmgr *hwmgr;
41
42 if (adev == NULL)
43 return -EINVAL;
44
45 hwmgr = kzalloc(sizeof(struct pp_hwmgr), GFP_KERNEL);
46 if (hwmgr == NULL)
47 return -ENOMEM;
48
49 hwmgr->adev = adev;
50 hwmgr->not_vf = !amdgpu_sriov_vf(adev);
51 hwmgr->device = amdgpu_cgs_create_device(adev);
52 mutex_init(&hwmgr->smu_lock);
53 mutex_init(&hwmgr->msg_lock);
54 hwmgr->chip_family = adev->family;
55 hwmgr->chip_id = adev->asic_type;
56 hwmgr->feature_mask = adev->pm.pp_feature;
57 hwmgr->display_config = &adev->pm.pm_display_cfg;
58 adev->powerplay.pp_handle = hwmgr;
59 adev->powerplay.pp_funcs = &pp_dpm_funcs;
60 return 0;
61 }
62
63
amd_powerplay_destroy(struct amdgpu_device * adev)64 static void amd_powerplay_destroy(struct amdgpu_device *adev)
65 {
66 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
67
68 mutex_destroy(&hwmgr->msg_lock);
69
70 kfree(hwmgr->hardcode_pp_table);
71 hwmgr->hardcode_pp_table = NULL;
72
73 kfree(hwmgr);
74 hwmgr = NULL;
75 }
76
pp_early_init(void * handle)77 static int pp_early_init(void *handle)
78 {
79 int ret;
80 struct amdgpu_device *adev = handle;
81
82 ret = amd_powerplay_create(adev);
83
84 if (ret != 0)
85 return ret;
86
87 ret = hwmgr_early_init(adev->powerplay.pp_handle);
88 if (ret)
89 return -EINVAL;
90
91 return 0;
92 }
93
pp_sw_init(void * handle)94 static int pp_sw_init(void *handle)
95 {
96 struct amdgpu_device *adev = handle;
97 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
98 int ret = 0;
99
100 ret = hwmgr_sw_init(hwmgr);
101
102 pr_debug("powerplay sw init %s\n", ret ? "failed" : "successfully");
103
104 return ret;
105 }
106
pp_sw_fini(void * handle)107 static int pp_sw_fini(void *handle)
108 {
109 struct amdgpu_device *adev = handle;
110 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
111
112 hwmgr_sw_fini(hwmgr);
113
114 release_firmware(adev->pm.fw);
115 adev->pm.fw = NULL;
116
117 return 0;
118 }
119
pp_hw_init(void * handle)120 static int pp_hw_init(void *handle)
121 {
122 int ret = 0;
123 struct amdgpu_device *adev = handle;
124 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
125
126 ret = hwmgr_hw_init(hwmgr);
127
128 if (ret)
129 pr_err("powerplay hw init failed\n");
130
131 return ret;
132 }
133
pp_hw_fini(void * handle)134 static int pp_hw_fini(void *handle)
135 {
136 struct amdgpu_device *adev = handle;
137 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
138
139 hwmgr_hw_fini(hwmgr);
140
141 return 0;
142 }
143
pp_reserve_vram_for_smu(struct amdgpu_device * adev)144 static void pp_reserve_vram_for_smu(struct amdgpu_device *adev)
145 {
146 int r = -EINVAL;
147 void *cpu_ptr = NULL;
148 uint64_t gpu_addr;
149 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
150
151 if (amdgpu_bo_create_kernel(adev, adev->pm.smu_prv_buffer_size,
152 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
153 &adev->pm.smu_prv_buffer,
154 &gpu_addr,
155 &cpu_ptr)) {
156 DRM_ERROR("amdgpu: failed to create smu prv buffer\n");
157 return;
158 }
159
160 if (hwmgr->hwmgr_func->notify_cac_buffer_info)
161 r = hwmgr->hwmgr_func->notify_cac_buffer_info(hwmgr,
162 lower_32_bits((unsigned long)cpu_ptr),
163 upper_32_bits((unsigned long)cpu_ptr),
164 lower_32_bits(gpu_addr),
165 upper_32_bits(gpu_addr),
166 adev->pm.smu_prv_buffer_size);
167
168 if (r) {
169 amdgpu_bo_free_kernel(&adev->pm.smu_prv_buffer, NULL, NULL);
170 adev->pm.smu_prv_buffer = NULL;
171 DRM_ERROR("amdgpu: failed to notify SMU buffer address\n");
172 }
173 }
174
pp_late_init(void * handle)175 static int pp_late_init(void *handle)
176 {
177 struct amdgpu_device *adev = handle;
178 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
179
180 if (hwmgr && hwmgr->pm_en) {
181 mutex_lock(&hwmgr->smu_lock);
182 hwmgr_handle_task(hwmgr,
183 AMD_PP_TASK_COMPLETE_INIT, NULL);
184 mutex_unlock(&hwmgr->smu_lock);
185 }
186 if (adev->pm.smu_prv_buffer_size != 0)
187 pp_reserve_vram_for_smu(adev);
188
189 return 0;
190 }
191
pp_late_fini(void * handle)192 static void pp_late_fini(void *handle)
193 {
194 struct amdgpu_device *adev = handle;
195
196 if (adev->pm.smu_prv_buffer)
197 amdgpu_bo_free_kernel(&adev->pm.smu_prv_buffer, NULL, NULL);
198 amd_powerplay_destroy(adev);
199 }
200
201
pp_is_idle(void * handle)202 static bool pp_is_idle(void *handle)
203 {
204 return false;
205 }
206
pp_wait_for_idle(void * handle)207 static int pp_wait_for_idle(void *handle)
208 {
209 return 0;
210 }
211
pp_sw_reset(void * handle)212 static int pp_sw_reset(void *handle)
213 {
214 return 0;
215 }
216
pp_set_powergating_state(void * handle,enum amd_powergating_state state)217 static int pp_set_powergating_state(void *handle,
218 enum amd_powergating_state state)
219 {
220 return 0;
221 }
222
pp_suspend(void * handle)223 static int pp_suspend(void *handle)
224 {
225 struct amdgpu_device *adev = handle;
226 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
227
228 return hwmgr_suspend(hwmgr);
229 }
230
pp_resume(void * handle)231 static int pp_resume(void *handle)
232 {
233 struct amdgpu_device *adev = handle;
234 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
235
236 return hwmgr_resume(hwmgr);
237 }
238
pp_set_clockgating_state(void * handle,enum amd_clockgating_state state)239 static int pp_set_clockgating_state(void *handle,
240 enum amd_clockgating_state state)
241 {
242 return 0;
243 }
244
245 static const struct amd_ip_funcs pp_ip_funcs = {
246 .name = "powerplay",
247 .early_init = pp_early_init,
248 .late_init = pp_late_init,
249 .sw_init = pp_sw_init,
250 .sw_fini = pp_sw_fini,
251 .hw_init = pp_hw_init,
252 .hw_fini = pp_hw_fini,
253 .late_fini = pp_late_fini,
254 .suspend = pp_suspend,
255 .resume = pp_resume,
256 .is_idle = pp_is_idle,
257 .wait_for_idle = pp_wait_for_idle,
258 .soft_reset = pp_sw_reset,
259 .set_clockgating_state = pp_set_clockgating_state,
260 .set_powergating_state = pp_set_powergating_state,
261 };
262
263 const struct amdgpu_ip_block_version pp_smu_ip_block =
264 {
265 .type = AMD_IP_BLOCK_TYPE_SMC,
266 .major = 1,
267 .minor = 0,
268 .rev = 0,
269 .funcs = &pp_ip_funcs,
270 };
271
272 /* This interface only be supported On Vi,
273 * because only smu7/8 can help to load gfx/sdma fw,
274 * smu need to be enabled before load other ip's fw.
275 * so call start smu to load smu7 fw and other ip's fw
276 */
pp_dpm_load_fw(void * handle)277 static int pp_dpm_load_fw(void *handle)
278 {
279 struct pp_hwmgr *hwmgr = handle;
280
281 if (!hwmgr || !hwmgr->smumgr_funcs || !hwmgr->smumgr_funcs->start_smu)
282 return -EINVAL;
283
284 if (hwmgr->smumgr_funcs->start_smu(hwmgr)) {
285 pr_err("fw load failed\n");
286 return -EINVAL;
287 }
288
289 return 0;
290 }
291
pp_dpm_fw_loading_complete(void * handle)292 static int pp_dpm_fw_loading_complete(void *handle)
293 {
294 return 0;
295 }
296
pp_set_clockgating_by_smu(void * handle,uint32_t msg_id)297 static int pp_set_clockgating_by_smu(void *handle, uint32_t msg_id)
298 {
299 struct pp_hwmgr *hwmgr = handle;
300
301 if (!hwmgr || !hwmgr->pm_en)
302 return -EINVAL;
303
304 if (hwmgr->hwmgr_func->update_clock_gatings == NULL) {
305 pr_info_ratelimited("%s was not implemented.\n", __func__);
306 return 0;
307 }
308
309 return hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
310 }
311
pp_dpm_en_umd_pstate(struct pp_hwmgr * hwmgr,enum amd_dpm_forced_level * level)312 static void pp_dpm_en_umd_pstate(struct pp_hwmgr *hwmgr,
313 enum amd_dpm_forced_level *level)
314 {
315 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
316 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
317 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
318 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
319
320 if (!(hwmgr->dpm_level & profile_mode_mask)) {
321 /* enter umd pstate, save current level, disable gfx cg*/
322 if (*level & profile_mode_mask) {
323 hwmgr->saved_dpm_level = hwmgr->dpm_level;
324 hwmgr->en_umd_pstate = true;
325 amdgpu_device_ip_set_powergating_state(hwmgr->adev,
326 AMD_IP_BLOCK_TYPE_GFX,
327 AMD_PG_STATE_UNGATE);
328 amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
329 AMD_IP_BLOCK_TYPE_GFX,
330 AMD_CG_STATE_UNGATE);
331 }
332 } else {
333 /* exit umd pstate, restore level, enable gfx cg*/
334 if (!(*level & profile_mode_mask)) {
335 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
336 *level = hwmgr->saved_dpm_level;
337 hwmgr->en_umd_pstate = false;
338 amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
339 AMD_IP_BLOCK_TYPE_GFX,
340 AMD_CG_STATE_GATE);
341 amdgpu_device_ip_set_powergating_state(hwmgr->adev,
342 AMD_IP_BLOCK_TYPE_GFX,
343 AMD_PG_STATE_GATE);
344 }
345 }
346 }
347
pp_dpm_force_performance_level(void * handle,enum amd_dpm_forced_level level)348 static int pp_dpm_force_performance_level(void *handle,
349 enum amd_dpm_forced_level level)
350 {
351 struct pp_hwmgr *hwmgr = handle;
352
353 if (!hwmgr || !hwmgr->pm_en)
354 return -EINVAL;
355
356 if (level == hwmgr->dpm_level)
357 return 0;
358
359 mutex_lock(&hwmgr->smu_lock);
360 pp_dpm_en_umd_pstate(hwmgr, &level);
361 hwmgr->request_dpm_level = level;
362 hwmgr_handle_task(hwmgr, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
363 mutex_unlock(&hwmgr->smu_lock);
364
365 return 0;
366 }
367
pp_dpm_get_performance_level(void * handle)368 static enum amd_dpm_forced_level pp_dpm_get_performance_level(
369 void *handle)
370 {
371 struct pp_hwmgr *hwmgr = handle;
372 enum amd_dpm_forced_level level;
373
374 if (!hwmgr || !hwmgr->pm_en)
375 return -EINVAL;
376
377 mutex_lock(&hwmgr->smu_lock);
378 level = hwmgr->dpm_level;
379 mutex_unlock(&hwmgr->smu_lock);
380 return level;
381 }
382
pp_dpm_get_sclk(void * handle,bool low)383 static uint32_t pp_dpm_get_sclk(void *handle, bool low)
384 {
385 struct pp_hwmgr *hwmgr = handle;
386 uint32_t clk = 0;
387
388 if (!hwmgr || !hwmgr->pm_en)
389 return 0;
390
391 if (hwmgr->hwmgr_func->get_sclk == NULL) {
392 pr_info_ratelimited("%s was not implemented.\n", __func__);
393 return 0;
394 }
395 mutex_lock(&hwmgr->smu_lock);
396 clk = hwmgr->hwmgr_func->get_sclk(hwmgr, low);
397 mutex_unlock(&hwmgr->smu_lock);
398 return clk;
399 }
400
pp_dpm_get_mclk(void * handle,bool low)401 static uint32_t pp_dpm_get_mclk(void *handle, bool low)
402 {
403 struct pp_hwmgr *hwmgr = handle;
404 uint32_t clk = 0;
405
406 if (!hwmgr || !hwmgr->pm_en)
407 return 0;
408
409 if (hwmgr->hwmgr_func->get_mclk == NULL) {
410 pr_info_ratelimited("%s was not implemented.\n", __func__);
411 return 0;
412 }
413 mutex_lock(&hwmgr->smu_lock);
414 clk = hwmgr->hwmgr_func->get_mclk(hwmgr, low);
415 mutex_unlock(&hwmgr->smu_lock);
416 return clk;
417 }
418
pp_dpm_powergate_vce(void * handle,bool gate)419 static void pp_dpm_powergate_vce(void *handle, bool gate)
420 {
421 struct pp_hwmgr *hwmgr = handle;
422
423 if (!hwmgr || !hwmgr->pm_en)
424 return;
425
426 if (hwmgr->hwmgr_func->powergate_vce == NULL) {
427 pr_info_ratelimited("%s was not implemented.\n", __func__);
428 return;
429 }
430 mutex_lock(&hwmgr->smu_lock);
431 hwmgr->hwmgr_func->powergate_vce(hwmgr, gate);
432 mutex_unlock(&hwmgr->smu_lock);
433 }
434
pp_dpm_powergate_uvd(void * handle,bool gate)435 static void pp_dpm_powergate_uvd(void *handle, bool gate)
436 {
437 struct pp_hwmgr *hwmgr = handle;
438
439 if (!hwmgr || !hwmgr->pm_en)
440 return;
441
442 if (hwmgr->hwmgr_func->powergate_uvd == NULL) {
443 pr_info_ratelimited("%s was not implemented.\n", __func__);
444 return;
445 }
446 mutex_lock(&hwmgr->smu_lock);
447 hwmgr->hwmgr_func->powergate_uvd(hwmgr, gate);
448 mutex_unlock(&hwmgr->smu_lock);
449 }
450
pp_dpm_dispatch_tasks(void * handle,enum amd_pp_task task_id,enum amd_pm_state_type * user_state)451 static int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_task task_id,
452 enum amd_pm_state_type *user_state)
453 {
454 int ret = 0;
455 struct pp_hwmgr *hwmgr = handle;
456
457 if (!hwmgr || !hwmgr->pm_en)
458 return -EINVAL;
459
460 mutex_lock(&hwmgr->smu_lock);
461 ret = hwmgr_handle_task(hwmgr, task_id, user_state);
462 mutex_unlock(&hwmgr->smu_lock);
463
464 return ret;
465 }
466
pp_dpm_get_current_power_state(void * handle)467 static enum amd_pm_state_type pp_dpm_get_current_power_state(void *handle)
468 {
469 struct pp_hwmgr *hwmgr = handle;
470 struct pp_power_state *state;
471 enum amd_pm_state_type pm_type;
472
473 if (!hwmgr || !hwmgr->pm_en || !hwmgr->current_ps)
474 return -EINVAL;
475
476 mutex_lock(&hwmgr->smu_lock);
477
478 state = hwmgr->current_ps;
479
480 switch (state->classification.ui_label) {
481 case PP_StateUILabel_Battery:
482 pm_type = POWER_STATE_TYPE_BATTERY;
483 break;
484 case PP_StateUILabel_Balanced:
485 pm_type = POWER_STATE_TYPE_BALANCED;
486 break;
487 case PP_StateUILabel_Performance:
488 pm_type = POWER_STATE_TYPE_PERFORMANCE;
489 break;
490 default:
491 if (state->classification.flags & PP_StateClassificationFlag_Boot)
492 pm_type = POWER_STATE_TYPE_INTERNAL_BOOT;
493 else
494 pm_type = POWER_STATE_TYPE_DEFAULT;
495 break;
496 }
497 mutex_unlock(&hwmgr->smu_lock);
498
499 return pm_type;
500 }
501
pp_dpm_set_fan_control_mode(void * handle,uint32_t mode)502 static void pp_dpm_set_fan_control_mode(void *handle, uint32_t mode)
503 {
504 struct pp_hwmgr *hwmgr = handle;
505
506 if (!hwmgr || !hwmgr->pm_en)
507 return;
508
509 if (hwmgr->hwmgr_func->set_fan_control_mode == NULL) {
510 pr_info_ratelimited("%s was not implemented.\n", __func__);
511 return;
512 }
513 mutex_lock(&hwmgr->smu_lock);
514 hwmgr->hwmgr_func->set_fan_control_mode(hwmgr, mode);
515 mutex_unlock(&hwmgr->smu_lock);
516 }
517
pp_dpm_get_fan_control_mode(void * handle)518 static uint32_t pp_dpm_get_fan_control_mode(void *handle)
519 {
520 struct pp_hwmgr *hwmgr = handle;
521 uint32_t mode = 0;
522
523 if (!hwmgr || !hwmgr->pm_en)
524 return 0;
525
526 if (hwmgr->hwmgr_func->get_fan_control_mode == NULL) {
527 pr_info_ratelimited("%s was not implemented.\n", __func__);
528 return 0;
529 }
530 mutex_lock(&hwmgr->smu_lock);
531 mode = hwmgr->hwmgr_func->get_fan_control_mode(hwmgr);
532 mutex_unlock(&hwmgr->smu_lock);
533 return mode;
534 }
535
pp_dpm_set_fan_speed_percent(void * handle,uint32_t percent)536 static int pp_dpm_set_fan_speed_percent(void *handle, uint32_t percent)
537 {
538 struct pp_hwmgr *hwmgr = handle;
539 int ret = 0;
540
541 if (!hwmgr || !hwmgr->pm_en)
542 return -EINVAL;
543
544 if (hwmgr->hwmgr_func->set_fan_speed_percent == NULL) {
545 pr_info_ratelimited("%s was not implemented.\n", __func__);
546 return 0;
547 }
548 mutex_lock(&hwmgr->smu_lock);
549 ret = hwmgr->hwmgr_func->set_fan_speed_percent(hwmgr, percent);
550 mutex_unlock(&hwmgr->smu_lock);
551 return ret;
552 }
553
pp_dpm_get_fan_speed_percent(void * handle,uint32_t * speed)554 static int pp_dpm_get_fan_speed_percent(void *handle, uint32_t *speed)
555 {
556 struct pp_hwmgr *hwmgr = handle;
557 int ret = 0;
558
559 if (!hwmgr || !hwmgr->pm_en)
560 return -EINVAL;
561
562 if (hwmgr->hwmgr_func->get_fan_speed_percent == NULL) {
563 pr_info_ratelimited("%s was not implemented.\n", __func__);
564 return 0;
565 }
566
567 mutex_lock(&hwmgr->smu_lock);
568 ret = hwmgr->hwmgr_func->get_fan_speed_percent(hwmgr, speed);
569 mutex_unlock(&hwmgr->smu_lock);
570 return ret;
571 }
572
pp_dpm_get_fan_speed_rpm(void * handle,uint32_t * rpm)573 static int pp_dpm_get_fan_speed_rpm(void *handle, uint32_t *rpm)
574 {
575 struct pp_hwmgr *hwmgr = handle;
576 int ret = 0;
577
578 if (!hwmgr || !hwmgr->pm_en)
579 return -EINVAL;
580
581 if (hwmgr->hwmgr_func->get_fan_speed_rpm == NULL)
582 return -EINVAL;
583
584 mutex_lock(&hwmgr->smu_lock);
585 ret = hwmgr->hwmgr_func->get_fan_speed_rpm(hwmgr, rpm);
586 mutex_unlock(&hwmgr->smu_lock);
587 return ret;
588 }
589
pp_dpm_set_fan_speed_rpm(void * handle,uint32_t rpm)590 static int pp_dpm_set_fan_speed_rpm(void *handle, uint32_t rpm)
591 {
592 struct pp_hwmgr *hwmgr = handle;
593 int ret = 0;
594
595 if (!hwmgr || !hwmgr->pm_en)
596 return -EINVAL;
597
598 if (hwmgr->hwmgr_func->set_fan_speed_rpm == NULL) {
599 pr_info_ratelimited("%s was not implemented.\n", __func__);
600 return 0;
601 }
602 mutex_lock(&hwmgr->smu_lock);
603 ret = hwmgr->hwmgr_func->set_fan_speed_rpm(hwmgr, rpm);
604 mutex_unlock(&hwmgr->smu_lock);
605 return ret;
606 }
607
pp_dpm_get_pp_num_states(void * handle,struct pp_states_info * data)608 static int pp_dpm_get_pp_num_states(void *handle,
609 struct pp_states_info *data)
610 {
611 struct pp_hwmgr *hwmgr = handle;
612 int i;
613
614 memset(data, 0, sizeof(*data));
615
616 if (!hwmgr || !hwmgr->pm_en ||!hwmgr->ps)
617 return -EINVAL;
618
619 mutex_lock(&hwmgr->smu_lock);
620
621 data->nums = hwmgr->num_ps;
622
623 for (i = 0; i < hwmgr->num_ps; i++) {
624 struct pp_power_state *state = (struct pp_power_state *)
625 ((unsigned long)hwmgr->ps + i * hwmgr->ps_size);
626 switch (state->classification.ui_label) {
627 case PP_StateUILabel_Battery:
628 data->states[i] = POWER_STATE_TYPE_BATTERY;
629 break;
630 case PP_StateUILabel_Balanced:
631 data->states[i] = POWER_STATE_TYPE_BALANCED;
632 break;
633 case PP_StateUILabel_Performance:
634 data->states[i] = POWER_STATE_TYPE_PERFORMANCE;
635 break;
636 default:
637 if (state->classification.flags & PP_StateClassificationFlag_Boot)
638 data->states[i] = POWER_STATE_TYPE_INTERNAL_BOOT;
639 else
640 data->states[i] = POWER_STATE_TYPE_DEFAULT;
641 }
642 }
643 mutex_unlock(&hwmgr->smu_lock);
644 return 0;
645 }
646
pp_dpm_get_pp_table(void * handle,char ** table)647 static int pp_dpm_get_pp_table(void *handle, char **table)
648 {
649 struct pp_hwmgr *hwmgr = handle;
650 int size = 0;
651
652 if (!hwmgr || !hwmgr->pm_en ||!hwmgr->soft_pp_table)
653 return -EINVAL;
654
655 mutex_lock(&hwmgr->smu_lock);
656 *table = (char *)hwmgr->soft_pp_table;
657 size = hwmgr->soft_pp_table_size;
658 mutex_unlock(&hwmgr->smu_lock);
659 return size;
660 }
661
amd_powerplay_reset(void * handle)662 static int amd_powerplay_reset(void *handle)
663 {
664 struct pp_hwmgr *hwmgr = handle;
665 int ret;
666
667 ret = hwmgr_hw_fini(hwmgr);
668 if (ret)
669 return ret;
670
671 ret = hwmgr_hw_init(hwmgr);
672 if (ret)
673 return ret;
674
675 return hwmgr_handle_task(hwmgr, AMD_PP_TASK_COMPLETE_INIT, NULL);
676 }
677
pp_dpm_set_pp_table(void * handle,const char * buf,size_t size)678 static int pp_dpm_set_pp_table(void *handle, const char *buf, size_t size)
679 {
680 struct pp_hwmgr *hwmgr = handle;
681 int ret = -ENOMEM;
682
683 if (!hwmgr || !hwmgr->pm_en)
684 return -EINVAL;
685
686 mutex_lock(&hwmgr->smu_lock);
687 if (!hwmgr->hardcode_pp_table) {
688 hwmgr->hardcode_pp_table = kmemdup(hwmgr->soft_pp_table,
689 hwmgr->soft_pp_table_size,
690 GFP_KERNEL);
691 if (!hwmgr->hardcode_pp_table)
692 goto err;
693 }
694
695 memcpy(hwmgr->hardcode_pp_table, buf, size);
696
697 hwmgr->soft_pp_table = hwmgr->hardcode_pp_table;
698
699 ret = amd_powerplay_reset(handle);
700 if (ret)
701 goto err;
702
703 if (hwmgr->hwmgr_func->avfs_control) {
704 ret = hwmgr->hwmgr_func->avfs_control(hwmgr, false);
705 if (ret)
706 goto err;
707 }
708 mutex_unlock(&hwmgr->smu_lock);
709 return 0;
710 err:
711 mutex_unlock(&hwmgr->smu_lock);
712 return ret;
713 }
714
pp_dpm_force_clock_level(void * handle,enum pp_clock_type type,uint32_t mask)715 static int pp_dpm_force_clock_level(void *handle,
716 enum pp_clock_type type, uint32_t mask)
717 {
718 struct pp_hwmgr *hwmgr = handle;
719 int ret = 0;
720
721 if (!hwmgr || !hwmgr->pm_en)
722 return -EINVAL;
723
724 if (hwmgr->hwmgr_func->force_clock_level == NULL) {
725 pr_info_ratelimited("%s was not implemented.\n", __func__);
726 return 0;
727 }
728
729 if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
730 pr_debug("force clock level is for dpm manual mode only.\n");
731 return -EINVAL;
732 }
733
734 mutex_lock(&hwmgr->smu_lock);
735 ret = hwmgr->hwmgr_func->force_clock_level(hwmgr, type, mask);
736 mutex_unlock(&hwmgr->smu_lock);
737 return ret;
738 }
739
pp_dpm_print_clock_levels(void * handle,enum pp_clock_type type,char * buf)740 static int pp_dpm_print_clock_levels(void *handle,
741 enum pp_clock_type type, char *buf)
742 {
743 struct pp_hwmgr *hwmgr = handle;
744 int ret = 0;
745
746 if (!hwmgr || !hwmgr->pm_en)
747 return -EINVAL;
748
749 if (hwmgr->hwmgr_func->print_clock_levels == NULL) {
750 pr_info_ratelimited("%s was not implemented.\n", __func__);
751 return 0;
752 }
753 mutex_lock(&hwmgr->smu_lock);
754 ret = hwmgr->hwmgr_func->print_clock_levels(hwmgr, type, buf);
755 mutex_unlock(&hwmgr->smu_lock);
756 return ret;
757 }
758
pp_dpm_get_sclk_od(void * handle)759 static int pp_dpm_get_sclk_od(void *handle)
760 {
761 struct pp_hwmgr *hwmgr = handle;
762 int ret = 0;
763
764 if (!hwmgr || !hwmgr->pm_en)
765 return -EINVAL;
766
767 if (hwmgr->hwmgr_func->get_sclk_od == NULL) {
768 pr_info_ratelimited("%s was not implemented.\n", __func__);
769 return 0;
770 }
771 mutex_lock(&hwmgr->smu_lock);
772 ret = hwmgr->hwmgr_func->get_sclk_od(hwmgr);
773 mutex_unlock(&hwmgr->smu_lock);
774 return ret;
775 }
776
pp_dpm_set_sclk_od(void * handle,uint32_t value)777 static int pp_dpm_set_sclk_od(void *handle, uint32_t value)
778 {
779 struct pp_hwmgr *hwmgr = handle;
780 int ret = 0;
781
782 if (!hwmgr || !hwmgr->pm_en)
783 return -EINVAL;
784
785 if (hwmgr->hwmgr_func->set_sclk_od == NULL) {
786 pr_info_ratelimited("%s was not implemented.\n", __func__);
787 return 0;
788 }
789
790 mutex_lock(&hwmgr->smu_lock);
791 ret = hwmgr->hwmgr_func->set_sclk_od(hwmgr, value);
792 mutex_unlock(&hwmgr->smu_lock);
793 return ret;
794 }
795
pp_dpm_get_mclk_od(void * handle)796 static int pp_dpm_get_mclk_od(void *handle)
797 {
798 struct pp_hwmgr *hwmgr = handle;
799 int ret = 0;
800
801 if (!hwmgr || !hwmgr->pm_en)
802 return -EINVAL;
803
804 if (hwmgr->hwmgr_func->get_mclk_od == NULL) {
805 pr_info_ratelimited("%s was not implemented.\n", __func__);
806 return 0;
807 }
808 mutex_lock(&hwmgr->smu_lock);
809 ret = hwmgr->hwmgr_func->get_mclk_od(hwmgr);
810 mutex_unlock(&hwmgr->smu_lock);
811 return ret;
812 }
813
pp_dpm_set_mclk_od(void * handle,uint32_t value)814 static int pp_dpm_set_mclk_od(void *handle, uint32_t value)
815 {
816 struct pp_hwmgr *hwmgr = handle;
817 int ret = 0;
818
819 if (!hwmgr || !hwmgr->pm_en)
820 return -EINVAL;
821
822 if (hwmgr->hwmgr_func->set_mclk_od == NULL) {
823 pr_info_ratelimited("%s was not implemented.\n", __func__);
824 return 0;
825 }
826 mutex_lock(&hwmgr->smu_lock);
827 ret = hwmgr->hwmgr_func->set_mclk_od(hwmgr, value);
828 mutex_unlock(&hwmgr->smu_lock);
829 return ret;
830 }
831
pp_dpm_read_sensor(void * handle,int idx,void * value,int * size)832 static int pp_dpm_read_sensor(void *handle, int idx,
833 void *value, int *size)
834 {
835 struct pp_hwmgr *hwmgr = handle;
836 int ret = 0;
837
838 if (!hwmgr || !hwmgr->pm_en || !value)
839 return -EINVAL;
840
841 switch (idx) {
842 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK:
843 *((uint32_t *)value) = hwmgr->pstate_sclk;
844 return 0;
845 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK:
846 *((uint32_t *)value) = hwmgr->pstate_mclk;
847 return 0;
848 case AMDGPU_PP_SENSOR_MIN_FAN_RPM:
849 *((uint32_t *)value) = hwmgr->thermal_controller.fanInfo.ulMinRPM;
850 return 0;
851 case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
852 *((uint32_t *)value) = hwmgr->thermal_controller.fanInfo.ulMaxRPM;
853 return 0;
854 default:
855 mutex_lock(&hwmgr->smu_lock);
856 ret = hwmgr->hwmgr_func->read_sensor(hwmgr, idx, value, size);
857 mutex_unlock(&hwmgr->smu_lock);
858 return ret;
859 }
860 }
861
862 static struct amd_vce_state*
pp_dpm_get_vce_clock_state(void * handle,unsigned idx)863 pp_dpm_get_vce_clock_state(void *handle, unsigned idx)
864 {
865 struct pp_hwmgr *hwmgr = handle;
866
867 if (!hwmgr || !hwmgr->pm_en)
868 return NULL;
869
870 if (idx < hwmgr->num_vce_state_tables)
871 return &hwmgr->vce_states[idx];
872 return NULL;
873 }
874
pp_get_power_profile_mode(void * handle,char * buf)875 static int pp_get_power_profile_mode(void *handle, char *buf)
876 {
877 struct pp_hwmgr *hwmgr = handle;
878
879 if (!hwmgr || !hwmgr->pm_en || !buf)
880 return -EINVAL;
881
882 if (hwmgr->hwmgr_func->get_power_profile_mode == NULL) {
883 pr_info_ratelimited("%s was not implemented.\n", __func__);
884 return snprintf(buf, PAGE_SIZE, "\n");
885 }
886
887 return hwmgr->hwmgr_func->get_power_profile_mode(hwmgr, buf);
888 }
889
pp_set_power_profile_mode(void * handle,long * input,uint32_t size)890 static int pp_set_power_profile_mode(void *handle, long *input, uint32_t size)
891 {
892 struct pp_hwmgr *hwmgr = handle;
893 int ret = -EINVAL;
894
895 if (!hwmgr || !hwmgr->pm_en)
896 return ret;
897
898 if (hwmgr->hwmgr_func->set_power_profile_mode == NULL) {
899 pr_info_ratelimited("%s was not implemented.\n", __func__);
900 return ret;
901 }
902
903 if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
904 pr_debug("power profile setting is for manual dpm mode only.\n");
905 return ret;
906 }
907
908 mutex_lock(&hwmgr->smu_lock);
909 ret = hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, input, size);
910 mutex_unlock(&hwmgr->smu_lock);
911 return ret;
912 }
913
pp_set_fine_grain_clk_vol(void * handle,uint32_t type,long * input,uint32_t size)914 static int pp_set_fine_grain_clk_vol(void *handle, uint32_t type, long *input, uint32_t size)
915 {
916 struct pp_hwmgr *hwmgr = handle;
917
918 if (!hwmgr || !hwmgr->pm_en)
919 return -EINVAL;
920
921 if (hwmgr->hwmgr_func->set_fine_grain_clk_vol == NULL)
922 return 0;
923
924 return hwmgr->hwmgr_func->set_fine_grain_clk_vol(hwmgr, type, input, size);
925 }
926
pp_odn_edit_dpm_table(void * handle,uint32_t type,long * input,uint32_t size)927 static int pp_odn_edit_dpm_table(void *handle, uint32_t type, long *input, uint32_t size)
928 {
929 struct pp_hwmgr *hwmgr = handle;
930
931 if (!hwmgr || !hwmgr->pm_en)
932 return -EINVAL;
933
934 if (hwmgr->hwmgr_func->odn_edit_dpm_table == NULL) {
935 pr_info_ratelimited("%s was not implemented.\n", __func__);
936 return 0;
937 }
938
939 return hwmgr->hwmgr_func->odn_edit_dpm_table(hwmgr, type, input, size);
940 }
941
pp_dpm_set_mp1_state(void * handle,enum pp_mp1_state mp1_state)942 static int pp_dpm_set_mp1_state(void *handle, enum pp_mp1_state mp1_state)
943 {
944 struct pp_hwmgr *hwmgr = handle;
945
946 if (!hwmgr)
947 return -EINVAL;
948
949 if (!hwmgr->pm_en)
950 return 0;
951
952 if (hwmgr->hwmgr_func->set_mp1_state)
953 return hwmgr->hwmgr_func->set_mp1_state(hwmgr, mp1_state);
954
955 return 0;
956 }
957
pp_dpm_switch_power_profile(void * handle,enum PP_SMC_POWER_PROFILE type,bool en)958 static int pp_dpm_switch_power_profile(void *handle,
959 enum PP_SMC_POWER_PROFILE type, bool en)
960 {
961 struct pp_hwmgr *hwmgr = handle;
962 long workload;
963 uint32_t index;
964
965 if (!hwmgr || !hwmgr->pm_en)
966 return -EINVAL;
967
968 if (hwmgr->hwmgr_func->set_power_profile_mode == NULL) {
969 pr_info_ratelimited("%s was not implemented.\n", __func__);
970 return -EINVAL;
971 }
972
973 if (!(type < PP_SMC_POWER_PROFILE_CUSTOM))
974 return -EINVAL;
975
976 mutex_lock(&hwmgr->smu_lock);
977
978 if (!en) {
979 hwmgr->workload_mask &= ~(1 << hwmgr->workload_prority[type]);
980 index = fls(hwmgr->workload_mask);
981 index = index > 0 && index <= Workload_Policy_Max ? index - 1 : 0;
982 workload = hwmgr->workload_setting[index];
983 } else {
984 hwmgr->workload_mask |= (1 << hwmgr->workload_prority[type]);
985 index = fls(hwmgr->workload_mask);
986 index = index <= Workload_Policy_Max ? index - 1 : 0;
987 workload = hwmgr->workload_setting[index];
988 }
989
990 if (type == PP_SMC_POWER_PROFILE_COMPUTE &&
991 hwmgr->hwmgr_func->disable_power_features_for_compute_performance) {
992 if (hwmgr->hwmgr_func->disable_power_features_for_compute_performance(hwmgr, en)) {
993 mutex_unlock(&hwmgr->smu_lock);
994 return -EINVAL;
995 }
996 }
997
998 if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
999 hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, &workload, 0);
1000 mutex_unlock(&hwmgr->smu_lock);
1001
1002 return 0;
1003 }
1004
pp_set_power_limit(void * handle,uint32_t limit)1005 static int pp_set_power_limit(void *handle, uint32_t limit)
1006 {
1007 struct pp_hwmgr *hwmgr = handle;
1008 uint32_t max_power_limit;
1009
1010 if (!hwmgr || !hwmgr->pm_en)
1011 return -EINVAL;
1012
1013 if (hwmgr->hwmgr_func->set_power_limit == NULL) {
1014 pr_info_ratelimited("%s was not implemented.\n", __func__);
1015 return -EINVAL;
1016 }
1017
1018 if (limit == 0)
1019 limit = hwmgr->default_power_limit;
1020
1021 max_power_limit = hwmgr->default_power_limit;
1022 if (hwmgr->od_enabled) {
1023 max_power_limit *= (100 + hwmgr->platform_descriptor.TDPODLimit);
1024 max_power_limit /= 100;
1025 }
1026
1027 if (limit > max_power_limit)
1028 return -EINVAL;
1029
1030 mutex_lock(&hwmgr->smu_lock);
1031 hwmgr->hwmgr_func->set_power_limit(hwmgr, limit);
1032 hwmgr->power_limit = limit;
1033 mutex_unlock(&hwmgr->smu_lock);
1034 return 0;
1035 }
1036
pp_get_power_limit(void * handle,uint32_t * limit,uint32_t * max_limit,bool default_limit)1037 static int pp_get_power_limit(void *handle, uint32_t *limit,
1038 uint32_t *max_limit, bool default_limit)
1039 {
1040 struct pp_hwmgr *hwmgr = handle;
1041
1042 if (!hwmgr || !hwmgr->pm_en ||!limit)
1043 return -EINVAL;
1044
1045 mutex_lock(&hwmgr->smu_lock);
1046
1047 if (default_limit) {
1048 *limit = hwmgr->default_power_limit;
1049 if (max_limit) {
1050 *max_limit = *limit;
1051 if (hwmgr->od_enabled) {
1052 *max_limit *= (100 + hwmgr->platform_descriptor.TDPODLimit);
1053 *max_limit /= 100;
1054 }
1055 }
1056 }
1057 else
1058 *limit = hwmgr->power_limit;
1059
1060 mutex_unlock(&hwmgr->smu_lock);
1061
1062 return 0;
1063 }
1064
pp_display_configuration_change(void * handle,const struct amd_pp_display_configuration * display_config)1065 static int pp_display_configuration_change(void *handle,
1066 const struct amd_pp_display_configuration *display_config)
1067 {
1068 struct pp_hwmgr *hwmgr = handle;
1069
1070 if (!hwmgr || !hwmgr->pm_en)
1071 return -EINVAL;
1072
1073 mutex_lock(&hwmgr->smu_lock);
1074 phm_store_dal_configuration_data(hwmgr, display_config);
1075 mutex_unlock(&hwmgr->smu_lock);
1076 return 0;
1077 }
1078
pp_get_display_power_level(void * handle,struct amd_pp_simple_clock_info * output)1079 static int pp_get_display_power_level(void *handle,
1080 struct amd_pp_simple_clock_info *output)
1081 {
1082 struct pp_hwmgr *hwmgr = handle;
1083 int ret = 0;
1084
1085 if (!hwmgr || !hwmgr->pm_en ||!output)
1086 return -EINVAL;
1087
1088 mutex_lock(&hwmgr->smu_lock);
1089 ret = phm_get_dal_power_level(hwmgr, output);
1090 mutex_unlock(&hwmgr->smu_lock);
1091 return ret;
1092 }
1093
pp_get_current_clocks(void * handle,struct amd_pp_clock_info * clocks)1094 static int pp_get_current_clocks(void *handle,
1095 struct amd_pp_clock_info *clocks)
1096 {
1097 struct amd_pp_simple_clock_info simple_clocks = { 0 };
1098 struct pp_clock_info hw_clocks;
1099 struct pp_hwmgr *hwmgr = handle;
1100 int ret = 0;
1101
1102 if (!hwmgr || !hwmgr->pm_en)
1103 return -EINVAL;
1104
1105 mutex_lock(&hwmgr->smu_lock);
1106
1107 phm_get_dal_power_level(hwmgr, &simple_clocks);
1108
1109 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1110 PHM_PlatformCaps_PowerContainment))
1111 ret = phm_get_clock_info(hwmgr, &hwmgr->current_ps->hardware,
1112 &hw_clocks, PHM_PerformanceLevelDesignation_PowerContainment);
1113 else
1114 ret = phm_get_clock_info(hwmgr, &hwmgr->current_ps->hardware,
1115 &hw_clocks, PHM_PerformanceLevelDesignation_Activity);
1116
1117 if (ret) {
1118 pr_debug("Error in phm_get_clock_info \n");
1119 mutex_unlock(&hwmgr->smu_lock);
1120 return -EINVAL;
1121 }
1122
1123 clocks->min_engine_clock = hw_clocks.min_eng_clk;
1124 clocks->max_engine_clock = hw_clocks.max_eng_clk;
1125 clocks->min_memory_clock = hw_clocks.min_mem_clk;
1126 clocks->max_memory_clock = hw_clocks.max_mem_clk;
1127 clocks->min_bus_bandwidth = hw_clocks.min_bus_bandwidth;
1128 clocks->max_bus_bandwidth = hw_clocks.max_bus_bandwidth;
1129
1130 clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
1131 clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
1132
1133 if (simple_clocks.level == 0)
1134 clocks->max_clocks_state = PP_DAL_POWERLEVEL_7;
1135 else
1136 clocks->max_clocks_state = simple_clocks.level;
1137
1138 if (0 == phm_get_current_shallow_sleep_clocks(hwmgr, &hwmgr->current_ps->hardware, &hw_clocks)) {
1139 clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
1140 clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
1141 }
1142 mutex_unlock(&hwmgr->smu_lock);
1143 return 0;
1144 }
1145
pp_get_clock_by_type(void * handle,enum amd_pp_clock_type type,struct amd_pp_clocks * clocks)1146 static int pp_get_clock_by_type(void *handle, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks)
1147 {
1148 struct pp_hwmgr *hwmgr = handle;
1149 int ret = 0;
1150
1151 if (!hwmgr || !hwmgr->pm_en)
1152 return -EINVAL;
1153
1154 if (clocks == NULL)
1155 return -EINVAL;
1156
1157 mutex_lock(&hwmgr->smu_lock);
1158 ret = phm_get_clock_by_type(hwmgr, type, clocks);
1159 mutex_unlock(&hwmgr->smu_lock);
1160 return ret;
1161 }
1162
pp_get_clock_by_type_with_latency(void * handle,enum amd_pp_clock_type type,struct pp_clock_levels_with_latency * clocks)1163 static int pp_get_clock_by_type_with_latency(void *handle,
1164 enum amd_pp_clock_type type,
1165 struct pp_clock_levels_with_latency *clocks)
1166 {
1167 struct pp_hwmgr *hwmgr = handle;
1168 int ret = 0;
1169
1170 if (!hwmgr || !hwmgr->pm_en ||!clocks)
1171 return -EINVAL;
1172
1173 mutex_lock(&hwmgr->smu_lock);
1174 ret = phm_get_clock_by_type_with_latency(hwmgr, type, clocks);
1175 mutex_unlock(&hwmgr->smu_lock);
1176 return ret;
1177 }
1178
pp_get_clock_by_type_with_voltage(void * handle,enum amd_pp_clock_type type,struct pp_clock_levels_with_voltage * clocks)1179 static int pp_get_clock_by_type_with_voltage(void *handle,
1180 enum amd_pp_clock_type type,
1181 struct pp_clock_levels_with_voltage *clocks)
1182 {
1183 struct pp_hwmgr *hwmgr = handle;
1184 int ret = 0;
1185
1186 if (!hwmgr || !hwmgr->pm_en ||!clocks)
1187 return -EINVAL;
1188
1189 mutex_lock(&hwmgr->smu_lock);
1190
1191 ret = phm_get_clock_by_type_with_voltage(hwmgr, type, clocks);
1192
1193 mutex_unlock(&hwmgr->smu_lock);
1194 return ret;
1195 }
1196
pp_set_watermarks_for_clocks_ranges(void * handle,void * clock_ranges)1197 static int pp_set_watermarks_for_clocks_ranges(void *handle,
1198 void *clock_ranges)
1199 {
1200 struct pp_hwmgr *hwmgr = handle;
1201 int ret = 0;
1202
1203 if (!hwmgr || !hwmgr->pm_en || !clock_ranges)
1204 return -EINVAL;
1205
1206 mutex_lock(&hwmgr->smu_lock);
1207 ret = phm_set_watermarks_for_clocks_ranges(hwmgr,
1208 clock_ranges);
1209 mutex_unlock(&hwmgr->smu_lock);
1210
1211 return ret;
1212 }
1213
pp_display_clock_voltage_request(void * handle,struct pp_display_clock_request * clock)1214 static int pp_display_clock_voltage_request(void *handle,
1215 struct pp_display_clock_request *clock)
1216 {
1217 struct pp_hwmgr *hwmgr = handle;
1218 int ret = 0;
1219
1220 if (!hwmgr || !hwmgr->pm_en ||!clock)
1221 return -EINVAL;
1222
1223 mutex_lock(&hwmgr->smu_lock);
1224 ret = phm_display_clock_voltage_request(hwmgr, clock);
1225 mutex_unlock(&hwmgr->smu_lock);
1226
1227 return ret;
1228 }
1229
pp_get_display_mode_validation_clocks(void * handle,struct amd_pp_simple_clock_info * clocks)1230 static int pp_get_display_mode_validation_clocks(void *handle,
1231 struct amd_pp_simple_clock_info *clocks)
1232 {
1233 struct pp_hwmgr *hwmgr = handle;
1234 int ret = 0;
1235
1236 if (!hwmgr || !hwmgr->pm_en ||!clocks)
1237 return -EINVAL;
1238
1239 clocks->level = PP_DAL_POWERLEVEL_7;
1240
1241 mutex_lock(&hwmgr->smu_lock);
1242
1243 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DynamicPatchPowerState))
1244 ret = phm_get_max_high_clocks(hwmgr, clocks);
1245
1246 mutex_unlock(&hwmgr->smu_lock);
1247 return ret;
1248 }
1249
pp_dpm_powergate_mmhub(void * handle)1250 static int pp_dpm_powergate_mmhub(void *handle)
1251 {
1252 struct pp_hwmgr *hwmgr = handle;
1253
1254 if (!hwmgr || !hwmgr->pm_en)
1255 return -EINVAL;
1256
1257 if (hwmgr->hwmgr_func->powergate_mmhub == NULL) {
1258 pr_info_ratelimited("%s was not implemented.\n", __func__);
1259 return 0;
1260 }
1261
1262 return hwmgr->hwmgr_func->powergate_mmhub(hwmgr);
1263 }
1264
pp_dpm_powergate_gfx(void * handle,bool gate)1265 static int pp_dpm_powergate_gfx(void *handle, bool gate)
1266 {
1267 struct pp_hwmgr *hwmgr = handle;
1268
1269 if (!hwmgr || !hwmgr->pm_en)
1270 return 0;
1271
1272 if (hwmgr->hwmgr_func->powergate_gfx == NULL) {
1273 pr_info_ratelimited("%s was not implemented.\n", __func__);
1274 return 0;
1275 }
1276
1277 return hwmgr->hwmgr_func->powergate_gfx(hwmgr, gate);
1278 }
1279
pp_dpm_powergate_acp(void * handle,bool gate)1280 static void pp_dpm_powergate_acp(void *handle, bool gate)
1281 {
1282 struct pp_hwmgr *hwmgr = handle;
1283
1284 if (!hwmgr || !hwmgr->pm_en)
1285 return;
1286
1287 if (hwmgr->hwmgr_func->powergate_acp == NULL) {
1288 pr_info_ratelimited("%s was not implemented.\n", __func__);
1289 return;
1290 }
1291
1292 hwmgr->hwmgr_func->powergate_acp(hwmgr, gate);
1293 }
1294
pp_dpm_powergate_sdma(void * handle,bool gate)1295 static void pp_dpm_powergate_sdma(void *handle, bool gate)
1296 {
1297 struct pp_hwmgr *hwmgr = handle;
1298
1299 if (!hwmgr)
1300 return;
1301
1302 if (hwmgr->hwmgr_func->powergate_sdma == NULL) {
1303 pr_info_ratelimited("%s was not implemented.\n", __func__);
1304 return;
1305 }
1306
1307 hwmgr->hwmgr_func->powergate_sdma(hwmgr, gate);
1308 }
1309
pp_set_powergating_by_smu(void * handle,uint32_t block_type,bool gate)1310 static int pp_set_powergating_by_smu(void *handle,
1311 uint32_t block_type, bool gate)
1312 {
1313 int ret = 0;
1314
1315 switch (block_type) {
1316 case AMD_IP_BLOCK_TYPE_UVD:
1317 case AMD_IP_BLOCK_TYPE_VCN:
1318 pp_dpm_powergate_uvd(handle, gate);
1319 break;
1320 case AMD_IP_BLOCK_TYPE_VCE:
1321 pp_dpm_powergate_vce(handle, gate);
1322 break;
1323 case AMD_IP_BLOCK_TYPE_GMC:
1324 pp_dpm_powergate_mmhub(handle);
1325 break;
1326 case AMD_IP_BLOCK_TYPE_GFX:
1327 ret = pp_dpm_powergate_gfx(handle, gate);
1328 break;
1329 case AMD_IP_BLOCK_TYPE_ACP:
1330 pp_dpm_powergate_acp(handle, gate);
1331 break;
1332 case AMD_IP_BLOCK_TYPE_SDMA:
1333 pp_dpm_powergate_sdma(handle, gate);
1334 break;
1335 default:
1336 break;
1337 }
1338 return ret;
1339 }
1340
pp_notify_smu_enable_pwe(void * handle)1341 static int pp_notify_smu_enable_pwe(void *handle)
1342 {
1343 struct pp_hwmgr *hwmgr = handle;
1344
1345 if (!hwmgr || !hwmgr->pm_en)
1346 return -EINVAL;
1347
1348 if (hwmgr->hwmgr_func->smus_notify_pwe == NULL) {
1349 pr_info_ratelimited("%s was not implemented.\n", __func__);
1350 return -EINVAL;
1351 }
1352
1353 mutex_lock(&hwmgr->smu_lock);
1354 hwmgr->hwmgr_func->smus_notify_pwe(hwmgr);
1355 mutex_unlock(&hwmgr->smu_lock);
1356
1357 return 0;
1358 }
1359
pp_enable_mgpu_fan_boost(void * handle)1360 static int pp_enable_mgpu_fan_boost(void *handle)
1361 {
1362 struct pp_hwmgr *hwmgr = handle;
1363
1364 if (!hwmgr)
1365 return -EINVAL;
1366
1367 if (!hwmgr->pm_en ||
1368 hwmgr->hwmgr_func->enable_mgpu_fan_boost == NULL)
1369 return 0;
1370
1371 mutex_lock(&hwmgr->smu_lock);
1372 hwmgr->hwmgr_func->enable_mgpu_fan_boost(hwmgr);
1373 mutex_unlock(&hwmgr->smu_lock);
1374
1375 return 0;
1376 }
1377
pp_set_min_deep_sleep_dcefclk(void * handle,uint32_t clock)1378 static int pp_set_min_deep_sleep_dcefclk(void *handle, uint32_t clock)
1379 {
1380 struct pp_hwmgr *hwmgr = handle;
1381
1382 if (!hwmgr || !hwmgr->pm_en)
1383 return -EINVAL;
1384
1385 if (hwmgr->hwmgr_func->set_min_deep_sleep_dcefclk == NULL) {
1386 pr_debug("%s was not implemented.\n", __func__);
1387 return -EINVAL;
1388 }
1389
1390 mutex_lock(&hwmgr->smu_lock);
1391 hwmgr->hwmgr_func->set_min_deep_sleep_dcefclk(hwmgr, clock);
1392 mutex_unlock(&hwmgr->smu_lock);
1393
1394 return 0;
1395 }
1396
pp_set_hard_min_dcefclk_by_freq(void * handle,uint32_t clock)1397 static int pp_set_hard_min_dcefclk_by_freq(void *handle, uint32_t clock)
1398 {
1399 struct pp_hwmgr *hwmgr = handle;
1400
1401 if (!hwmgr || !hwmgr->pm_en)
1402 return -EINVAL;
1403
1404 if (hwmgr->hwmgr_func->set_hard_min_dcefclk_by_freq == NULL) {
1405 pr_debug("%s was not implemented.\n", __func__);
1406 return -EINVAL;
1407 }
1408
1409 mutex_lock(&hwmgr->smu_lock);
1410 hwmgr->hwmgr_func->set_hard_min_dcefclk_by_freq(hwmgr, clock);
1411 mutex_unlock(&hwmgr->smu_lock);
1412
1413 return 0;
1414 }
1415
pp_set_hard_min_fclk_by_freq(void * handle,uint32_t clock)1416 static int pp_set_hard_min_fclk_by_freq(void *handle, uint32_t clock)
1417 {
1418 struct pp_hwmgr *hwmgr = handle;
1419
1420 if (!hwmgr || !hwmgr->pm_en)
1421 return -EINVAL;
1422
1423 if (hwmgr->hwmgr_func->set_hard_min_fclk_by_freq == NULL) {
1424 pr_debug("%s was not implemented.\n", __func__);
1425 return -EINVAL;
1426 }
1427
1428 mutex_lock(&hwmgr->smu_lock);
1429 hwmgr->hwmgr_func->set_hard_min_fclk_by_freq(hwmgr, clock);
1430 mutex_unlock(&hwmgr->smu_lock);
1431
1432 return 0;
1433 }
1434
pp_set_active_display_count(void * handle,uint32_t count)1435 static int pp_set_active_display_count(void *handle, uint32_t count)
1436 {
1437 struct pp_hwmgr *hwmgr = handle;
1438 int ret = 0;
1439
1440 if (!hwmgr || !hwmgr->pm_en)
1441 return -EINVAL;
1442
1443 mutex_lock(&hwmgr->smu_lock);
1444 ret = phm_set_active_display_count(hwmgr, count);
1445 mutex_unlock(&hwmgr->smu_lock);
1446
1447 return ret;
1448 }
1449
pp_get_asic_baco_capability(void * handle,bool * cap)1450 static int pp_get_asic_baco_capability(void *handle, bool *cap)
1451 {
1452 struct pp_hwmgr *hwmgr = handle;
1453
1454 *cap = false;
1455 if (!hwmgr)
1456 return -EINVAL;
1457
1458 if (!(hwmgr->not_vf && amdgpu_dpm) ||
1459 !hwmgr->hwmgr_func->get_asic_baco_capability)
1460 return 0;
1461
1462 mutex_lock(&hwmgr->smu_lock);
1463 hwmgr->hwmgr_func->get_asic_baco_capability(hwmgr, cap);
1464 mutex_unlock(&hwmgr->smu_lock);
1465
1466 return 0;
1467 }
1468
pp_get_asic_baco_state(void * handle,int * state)1469 static int pp_get_asic_baco_state(void *handle, int *state)
1470 {
1471 struct pp_hwmgr *hwmgr = handle;
1472
1473 if (!hwmgr)
1474 return -EINVAL;
1475
1476 if (!hwmgr->pm_en || !hwmgr->hwmgr_func->get_asic_baco_state)
1477 return 0;
1478
1479 mutex_lock(&hwmgr->smu_lock);
1480 hwmgr->hwmgr_func->get_asic_baco_state(hwmgr, (enum BACO_STATE *)state);
1481 mutex_unlock(&hwmgr->smu_lock);
1482
1483 return 0;
1484 }
1485
pp_set_asic_baco_state(void * handle,int state)1486 static int pp_set_asic_baco_state(void *handle, int state)
1487 {
1488 struct pp_hwmgr *hwmgr = handle;
1489
1490 if (!hwmgr)
1491 return -EINVAL;
1492
1493 if (!(hwmgr->not_vf && amdgpu_dpm) ||
1494 !hwmgr->hwmgr_func->set_asic_baco_state)
1495 return 0;
1496
1497 mutex_lock(&hwmgr->smu_lock);
1498 hwmgr->hwmgr_func->set_asic_baco_state(hwmgr, (enum BACO_STATE)state);
1499 mutex_unlock(&hwmgr->smu_lock);
1500
1501 return 0;
1502 }
1503
pp_get_ppfeature_status(void * handle,char * buf)1504 static int pp_get_ppfeature_status(void *handle, char *buf)
1505 {
1506 struct pp_hwmgr *hwmgr = handle;
1507 int ret = 0;
1508
1509 if (!hwmgr || !hwmgr->pm_en || !buf)
1510 return -EINVAL;
1511
1512 if (hwmgr->hwmgr_func->get_ppfeature_status == NULL) {
1513 pr_info_ratelimited("%s was not implemented.\n", __func__);
1514 return -EINVAL;
1515 }
1516
1517 mutex_lock(&hwmgr->smu_lock);
1518 ret = hwmgr->hwmgr_func->get_ppfeature_status(hwmgr, buf);
1519 mutex_unlock(&hwmgr->smu_lock);
1520
1521 return ret;
1522 }
1523
pp_set_ppfeature_status(void * handle,uint64_t ppfeature_masks)1524 static int pp_set_ppfeature_status(void *handle, uint64_t ppfeature_masks)
1525 {
1526 struct pp_hwmgr *hwmgr = handle;
1527 int ret = 0;
1528
1529 if (!hwmgr || !hwmgr->pm_en)
1530 return -EINVAL;
1531
1532 if (hwmgr->hwmgr_func->set_ppfeature_status == NULL) {
1533 pr_info_ratelimited("%s was not implemented.\n", __func__);
1534 return -EINVAL;
1535 }
1536
1537 mutex_lock(&hwmgr->smu_lock);
1538 ret = hwmgr->hwmgr_func->set_ppfeature_status(hwmgr, ppfeature_masks);
1539 mutex_unlock(&hwmgr->smu_lock);
1540
1541 return ret;
1542 }
1543
pp_asic_reset_mode_2(void * handle)1544 static int pp_asic_reset_mode_2(void *handle)
1545 {
1546 struct pp_hwmgr *hwmgr = handle;
1547 int ret = 0;
1548
1549 if (!hwmgr || !hwmgr->pm_en)
1550 return -EINVAL;
1551
1552 if (hwmgr->hwmgr_func->asic_reset == NULL) {
1553 pr_info_ratelimited("%s was not implemented.\n", __func__);
1554 return -EINVAL;
1555 }
1556
1557 mutex_lock(&hwmgr->smu_lock);
1558 ret = hwmgr->hwmgr_func->asic_reset(hwmgr, SMU_ASIC_RESET_MODE_2);
1559 mutex_unlock(&hwmgr->smu_lock);
1560
1561 return ret;
1562 }
1563
pp_smu_i2c_bus_access(void * handle,bool acquire)1564 static int pp_smu_i2c_bus_access(void *handle, bool acquire)
1565 {
1566 struct pp_hwmgr *hwmgr = handle;
1567 int ret = 0;
1568
1569 if (!hwmgr || !hwmgr->pm_en)
1570 return -EINVAL;
1571
1572 if (hwmgr->hwmgr_func->smu_i2c_bus_access == NULL) {
1573 pr_info_ratelimited("%s was not implemented.\n", __func__);
1574 return -EINVAL;
1575 }
1576
1577 mutex_lock(&hwmgr->smu_lock);
1578 ret = hwmgr->hwmgr_func->smu_i2c_bus_access(hwmgr, acquire);
1579 mutex_unlock(&hwmgr->smu_lock);
1580
1581 return ret;
1582 }
1583
pp_set_df_cstate(void * handle,enum pp_df_cstate state)1584 static int pp_set_df_cstate(void *handle, enum pp_df_cstate state)
1585 {
1586 struct pp_hwmgr *hwmgr = handle;
1587
1588 if (!hwmgr)
1589 return -EINVAL;
1590
1591 if (!hwmgr->pm_en || !hwmgr->hwmgr_func->set_df_cstate)
1592 return 0;
1593
1594 mutex_lock(&hwmgr->smu_lock);
1595 hwmgr->hwmgr_func->set_df_cstate(hwmgr, state);
1596 mutex_unlock(&hwmgr->smu_lock);
1597
1598 return 0;
1599 }
1600
pp_set_xgmi_pstate(void * handle,uint32_t pstate)1601 static int pp_set_xgmi_pstate(void *handle, uint32_t pstate)
1602 {
1603 struct pp_hwmgr *hwmgr = handle;
1604
1605 if (!hwmgr)
1606 return -EINVAL;
1607
1608 if (!hwmgr->pm_en || !hwmgr->hwmgr_func->set_xgmi_pstate)
1609 return 0;
1610
1611 mutex_lock(&hwmgr->smu_lock);
1612 hwmgr->hwmgr_func->set_xgmi_pstate(hwmgr, pstate);
1613 mutex_unlock(&hwmgr->smu_lock);
1614
1615 return 0;
1616 }
1617
pp_get_gpu_metrics(void * handle,void ** table)1618 static ssize_t pp_get_gpu_metrics(void *handle, void **table)
1619 {
1620 struct pp_hwmgr *hwmgr = handle;
1621 ssize_t size;
1622
1623 if (!hwmgr)
1624 return -EINVAL;
1625
1626 if (!hwmgr->pm_en || !hwmgr->hwmgr_func->get_gpu_metrics)
1627 return -EOPNOTSUPP;
1628
1629 mutex_lock(&hwmgr->smu_lock);
1630 size = hwmgr->hwmgr_func->get_gpu_metrics(hwmgr, table);
1631 mutex_unlock(&hwmgr->smu_lock);
1632
1633 return size;
1634 }
1635
pp_gfx_state_change_set(void * handle,uint32_t state)1636 static int pp_gfx_state_change_set(void *handle, uint32_t state)
1637 {
1638 struct pp_hwmgr *hwmgr = handle;
1639
1640 if (!hwmgr || !hwmgr->pm_en)
1641 return -EINVAL;
1642
1643 if (hwmgr->hwmgr_func->gfx_state_change == NULL) {
1644 pr_info_ratelimited("%s was not implemented.\n", __func__);
1645 return -EINVAL;
1646 }
1647
1648 mutex_lock(&hwmgr->smu_lock);
1649 hwmgr->hwmgr_func->gfx_state_change(hwmgr, state);
1650 mutex_unlock(&hwmgr->smu_lock);
1651 return 0;
1652 }
1653
1654 static const struct amd_pm_funcs pp_dpm_funcs = {
1655 .load_firmware = pp_dpm_load_fw,
1656 .wait_for_fw_loading_complete = pp_dpm_fw_loading_complete,
1657 .force_performance_level = pp_dpm_force_performance_level,
1658 .get_performance_level = pp_dpm_get_performance_level,
1659 .get_current_power_state = pp_dpm_get_current_power_state,
1660 .dispatch_tasks = pp_dpm_dispatch_tasks,
1661 .set_fan_control_mode = pp_dpm_set_fan_control_mode,
1662 .get_fan_control_mode = pp_dpm_get_fan_control_mode,
1663 .set_fan_speed_percent = pp_dpm_set_fan_speed_percent,
1664 .get_fan_speed_percent = pp_dpm_get_fan_speed_percent,
1665 .get_fan_speed_rpm = pp_dpm_get_fan_speed_rpm,
1666 .set_fan_speed_rpm = pp_dpm_set_fan_speed_rpm,
1667 .get_pp_num_states = pp_dpm_get_pp_num_states,
1668 .get_pp_table = pp_dpm_get_pp_table,
1669 .set_pp_table = pp_dpm_set_pp_table,
1670 .force_clock_level = pp_dpm_force_clock_level,
1671 .print_clock_levels = pp_dpm_print_clock_levels,
1672 .get_sclk_od = pp_dpm_get_sclk_od,
1673 .set_sclk_od = pp_dpm_set_sclk_od,
1674 .get_mclk_od = pp_dpm_get_mclk_od,
1675 .set_mclk_od = pp_dpm_set_mclk_od,
1676 .read_sensor = pp_dpm_read_sensor,
1677 .get_vce_clock_state = pp_dpm_get_vce_clock_state,
1678 .switch_power_profile = pp_dpm_switch_power_profile,
1679 .set_clockgating_by_smu = pp_set_clockgating_by_smu,
1680 .set_powergating_by_smu = pp_set_powergating_by_smu,
1681 .get_power_profile_mode = pp_get_power_profile_mode,
1682 .set_power_profile_mode = pp_set_power_profile_mode,
1683 .set_fine_grain_clk_vol = pp_set_fine_grain_clk_vol,
1684 .odn_edit_dpm_table = pp_odn_edit_dpm_table,
1685 .set_mp1_state = pp_dpm_set_mp1_state,
1686 .set_power_limit = pp_set_power_limit,
1687 .get_power_limit = pp_get_power_limit,
1688 /* export to DC */
1689 .get_sclk = pp_dpm_get_sclk,
1690 .get_mclk = pp_dpm_get_mclk,
1691 .display_configuration_change = pp_display_configuration_change,
1692 .get_display_power_level = pp_get_display_power_level,
1693 .get_current_clocks = pp_get_current_clocks,
1694 .get_clock_by_type = pp_get_clock_by_type,
1695 .get_clock_by_type_with_latency = pp_get_clock_by_type_with_latency,
1696 .get_clock_by_type_with_voltage = pp_get_clock_by_type_with_voltage,
1697 .set_watermarks_for_clocks_ranges = pp_set_watermarks_for_clocks_ranges,
1698 .display_clock_voltage_request = pp_display_clock_voltage_request,
1699 .get_display_mode_validation_clocks = pp_get_display_mode_validation_clocks,
1700 .notify_smu_enable_pwe = pp_notify_smu_enable_pwe,
1701 .enable_mgpu_fan_boost = pp_enable_mgpu_fan_boost,
1702 .set_active_display_count = pp_set_active_display_count,
1703 .set_min_deep_sleep_dcefclk = pp_set_min_deep_sleep_dcefclk,
1704 .set_hard_min_dcefclk_by_freq = pp_set_hard_min_dcefclk_by_freq,
1705 .set_hard_min_fclk_by_freq = pp_set_hard_min_fclk_by_freq,
1706 .get_asic_baco_capability = pp_get_asic_baco_capability,
1707 .get_asic_baco_state = pp_get_asic_baco_state,
1708 .set_asic_baco_state = pp_set_asic_baco_state,
1709 .get_ppfeature_status = pp_get_ppfeature_status,
1710 .set_ppfeature_status = pp_set_ppfeature_status,
1711 .asic_reset_mode_2 = pp_asic_reset_mode_2,
1712 .smu_i2c_bus_access = pp_smu_i2c_bus_access,
1713 .set_df_cstate = pp_set_df_cstate,
1714 .set_xgmi_pstate = pp_set_xgmi_pstate,
1715 .get_gpu_metrics = pp_get_gpu_metrics,
1716 .gfx_state_change_set = pp_gfx_state_change_set,
1717 };
1718