1 /* SPDX-License-Identifier: GPL-2.0+ */
2 // Copyright (c) 2016-2017 Hisilicon Limited.
3
4 #ifndef __HCLGE_CMD_H
5 #define __HCLGE_CMD_H
6 #include <linux/types.h>
7 #include <linux/io.h>
8 #include <linux/etherdevice.h>
9 #include "hnae3.h"
10
11 #define HCLGE_CMDQ_TX_TIMEOUT 30000
12 #define HCLGE_DESC_DATA_LEN 6
13
14 struct hclge_dev;
15 struct hclge_desc {
16 __le16 opcode;
17
18 #define HCLGE_CMDQ_RX_INVLD_B 0
19 #define HCLGE_CMDQ_RX_OUTVLD_B 1
20
21 __le16 flag;
22 __le16 retval;
23 __le16 rsv;
24 __le32 data[HCLGE_DESC_DATA_LEN];
25 };
26
27 struct hclge_cmq_ring {
28 dma_addr_t desc_dma_addr;
29 struct hclge_desc *desc;
30 struct hclge_dev *dev;
31 u32 head;
32 u32 tail;
33
34 u16 buf_size;
35 u16 desc_num;
36 int next_to_use;
37 int next_to_clean;
38 u8 ring_type; /* cmq ring type */
39 spinlock_t lock; /* Command queue lock */
40 };
41
42 enum hclge_cmd_return_status {
43 HCLGE_CMD_EXEC_SUCCESS = 0,
44 HCLGE_CMD_NO_AUTH = 1,
45 HCLGE_CMD_NOT_SUPPORTED = 2,
46 HCLGE_CMD_QUEUE_FULL = 3,
47 HCLGE_CMD_NEXT_ERR = 4,
48 HCLGE_CMD_UNEXE_ERR = 5,
49 HCLGE_CMD_PARA_ERR = 6,
50 HCLGE_CMD_RESULT_ERR = 7,
51 HCLGE_CMD_TIMEOUT = 8,
52 HCLGE_CMD_HILINK_ERR = 9,
53 HCLGE_CMD_QUEUE_ILLEGAL = 10,
54 HCLGE_CMD_INVALID = 11,
55 };
56
57 enum hclge_cmd_status {
58 HCLGE_STATUS_SUCCESS = 0,
59 HCLGE_ERR_CSQ_FULL = -1,
60 HCLGE_ERR_CSQ_TIMEOUT = -2,
61 HCLGE_ERR_CSQ_ERROR = -3,
62 };
63
64 struct hclge_misc_vector {
65 u8 __iomem *addr;
66 int vector_irq;
67 char name[HNAE3_INT_NAME_LEN];
68 };
69
70 struct hclge_cmq {
71 struct hclge_cmq_ring csq;
72 struct hclge_cmq_ring crq;
73 u16 tx_timeout;
74 enum hclge_cmd_status last_status;
75 };
76
77 #define HCLGE_CMD_FLAG_IN BIT(0)
78 #define HCLGE_CMD_FLAG_OUT BIT(1)
79 #define HCLGE_CMD_FLAG_NEXT BIT(2)
80 #define HCLGE_CMD_FLAG_WR BIT(3)
81 #define HCLGE_CMD_FLAG_NO_INTR BIT(4)
82 #define HCLGE_CMD_FLAG_ERR_INTR BIT(5)
83
84 enum hclge_opcode_type {
85 /* Generic commands */
86 HCLGE_OPC_QUERY_FW_VER = 0x0001,
87 HCLGE_OPC_CFG_RST_TRIGGER = 0x0020,
88 HCLGE_OPC_GBL_RST_STATUS = 0x0021,
89 HCLGE_OPC_QUERY_FUNC_STATUS = 0x0022,
90 HCLGE_OPC_QUERY_PF_RSRC = 0x0023,
91 HCLGE_OPC_QUERY_VF_RSRC = 0x0024,
92 HCLGE_OPC_GET_CFG_PARAM = 0x0025,
93 HCLGE_OPC_PF_RST_DONE = 0x0026,
94 HCLGE_OPC_QUERY_VF_RST_RDY = 0x0027,
95
96 HCLGE_OPC_STATS_64_BIT = 0x0030,
97 HCLGE_OPC_STATS_32_BIT = 0x0031,
98 HCLGE_OPC_STATS_MAC = 0x0032,
99 HCLGE_OPC_QUERY_MAC_REG_NUM = 0x0033,
100 HCLGE_OPC_STATS_MAC_ALL = 0x0034,
101
102 HCLGE_OPC_QUERY_REG_NUM = 0x0040,
103 HCLGE_OPC_QUERY_32_BIT_REG = 0x0041,
104 HCLGE_OPC_QUERY_64_BIT_REG = 0x0042,
105 HCLGE_OPC_DFX_BD_NUM = 0x0043,
106 HCLGE_OPC_DFX_BIOS_COMMON_REG = 0x0044,
107 HCLGE_OPC_DFX_SSU_REG_0 = 0x0045,
108 HCLGE_OPC_DFX_SSU_REG_1 = 0x0046,
109 HCLGE_OPC_DFX_IGU_EGU_REG = 0x0047,
110 HCLGE_OPC_DFX_RPU_REG_0 = 0x0048,
111 HCLGE_OPC_DFX_RPU_REG_1 = 0x0049,
112 HCLGE_OPC_DFX_NCSI_REG = 0x004A,
113 HCLGE_OPC_DFX_RTC_REG = 0x004B,
114 HCLGE_OPC_DFX_PPP_REG = 0x004C,
115 HCLGE_OPC_DFX_RCB_REG = 0x004D,
116 HCLGE_OPC_DFX_TQP_REG = 0x004E,
117 HCLGE_OPC_DFX_SSU_REG_2 = 0x004F,
118
119 HCLGE_OPC_QUERY_DEV_SPECS = 0x0050,
120
121 /* MAC command */
122 HCLGE_OPC_CONFIG_MAC_MODE = 0x0301,
123 HCLGE_OPC_CONFIG_AN_MODE = 0x0304,
124 HCLGE_OPC_QUERY_LINK_STATUS = 0x0307,
125 HCLGE_OPC_CONFIG_MAX_FRM_SIZE = 0x0308,
126 HCLGE_OPC_CONFIG_SPEED_DUP = 0x0309,
127 HCLGE_OPC_QUERY_MAC_TNL_INT = 0x0310,
128 HCLGE_OPC_MAC_TNL_INT_EN = 0x0311,
129 HCLGE_OPC_CLEAR_MAC_TNL_INT = 0x0312,
130 HCLGE_OPC_COMMON_LOOPBACK = 0x0315,
131 HCLGE_OPC_CONFIG_FEC_MODE = 0x031A,
132
133 /* PFC/Pause commands */
134 HCLGE_OPC_CFG_MAC_PAUSE_EN = 0x0701,
135 HCLGE_OPC_CFG_PFC_PAUSE_EN = 0x0702,
136 HCLGE_OPC_CFG_MAC_PARA = 0x0703,
137 HCLGE_OPC_CFG_PFC_PARA = 0x0704,
138 HCLGE_OPC_QUERY_MAC_TX_PKT_CNT = 0x0705,
139 HCLGE_OPC_QUERY_MAC_RX_PKT_CNT = 0x0706,
140 HCLGE_OPC_QUERY_PFC_TX_PKT_CNT = 0x0707,
141 HCLGE_OPC_QUERY_PFC_RX_PKT_CNT = 0x0708,
142 HCLGE_OPC_PRI_TO_TC_MAPPING = 0x0709,
143 HCLGE_OPC_QOS_MAP = 0x070A,
144
145 /* ETS/scheduler commands */
146 HCLGE_OPC_TM_PG_TO_PRI_LINK = 0x0804,
147 HCLGE_OPC_TM_QS_TO_PRI_LINK = 0x0805,
148 HCLGE_OPC_TM_NQ_TO_QS_LINK = 0x0806,
149 HCLGE_OPC_TM_RQ_TO_QS_LINK = 0x0807,
150 HCLGE_OPC_TM_PORT_WEIGHT = 0x0808,
151 HCLGE_OPC_TM_PG_WEIGHT = 0x0809,
152 HCLGE_OPC_TM_QS_WEIGHT = 0x080A,
153 HCLGE_OPC_TM_PRI_WEIGHT = 0x080B,
154 HCLGE_OPC_TM_PRI_C_SHAPPING = 0x080C,
155 HCLGE_OPC_TM_PRI_P_SHAPPING = 0x080D,
156 HCLGE_OPC_TM_PG_C_SHAPPING = 0x080E,
157 HCLGE_OPC_TM_PG_P_SHAPPING = 0x080F,
158 HCLGE_OPC_TM_PORT_SHAPPING = 0x0810,
159 HCLGE_OPC_TM_PG_SCH_MODE_CFG = 0x0812,
160 HCLGE_OPC_TM_PRI_SCH_MODE_CFG = 0x0813,
161 HCLGE_OPC_TM_QS_SCH_MODE_CFG = 0x0814,
162 HCLGE_OPC_TM_BP_TO_QSET_MAPPING = 0x0815,
163 HCLGE_OPC_TM_NODES = 0x0816,
164 HCLGE_OPC_ETS_TC_WEIGHT = 0x0843,
165 HCLGE_OPC_QSET_DFX_STS = 0x0844,
166 HCLGE_OPC_PRI_DFX_STS = 0x0845,
167 HCLGE_OPC_PG_DFX_STS = 0x0846,
168 HCLGE_OPC_PORT_DFX_STS = 0x0847,
169 HCLGE_OPC_SCH_NQ_CNT = 0x0848,
170 HCLGE_OPC_SCH_RQ_CNT = 0x0849,
171 HCLGE_OPC_TM_INTERNAL_STS = 0x0850,
172 HCLGE_OPC_TM_INTERNAL_CNT = 0x0851,
173 HCLGE_OPC_TM_INTERNAL_STS_1 = 0x0852,
174
175 /* Packet buffer allocate commands */
176 HCLGE_OPC_TX_BUFF_ALLOC = 0x0901,
177 HCLGE_OPC_RX_PRIV_BUFF_ALLOC = 0x0902,
178 HCLGE_OPC_RX_PRIV_WL_ALLOC = 0x0903,
179 HCLGE_OPC_RX_COM_THRD_ALLOC = 0x0904,
180 HCLGE_OPC_RX_COM_WL_ALLOC = 0x0905,
181 HCLGE_OPC_RX_GBL_PKT_CNT = 0x0906,
182
183 /* TQP management command */
184 HCLGE_OPC_SET_TQP_MAP = 0x0A01,
185
186 /* TQP commands */
187 HCLGE_OPC_CFG_TX_QUEUE = 0x0B01,
188 HCLGE_OPC_QUERY_TX_POINTER = 0x0B02,
189 HCLGE_OPC_QUERY_TX_STATS = 0x0B03,
190 HCLGE_OPC_TQP_TX_QUEUE_TC = 0x0B04,
191 HCLGE_OPC_CFG_RX_QUEUE = 0x0B11,
192 HCLGE_OPC_QUERY_RX_POINTER = 0x0B12,
193 HCLGE_OPC_QUERY_RX_STATS = 0x0B13,
194 HCLGE_OPC_STASH_RX_QUEUE_LRO = 0x0B16,
195 HCLGE_OPC_CFG_RX_QUEUE_LRO = 0x0B17,
196 HCLGE_OPC_CFG_COM_TQP_QUEUE = 0x0B20,
197 HCLGE_OPC_RESET_TQP_QUEUE = 0x0B22,
198
199 /* PPU commands */
200 HCLGE_OPC_PPU_PF_OTHER_INT_DFX = 0x0B4A,
201
202 /* TSO command */
203 HCLGE_OPC_TSO_GENERIC_CONFIG = 0x0C01,
204 HCLGE_OPC_GRO_GENERIC_CONFIG = 0x0C10,
205
206 /* RSS commands */
207 HCLGE_OPC_RSS_GENERIC_CONFIG = 0x0D01,
208 HCLGE_OPC_RSS_INDIR_TABLE = 0x0D07,
209 HCLGE_OPC_RSS_TC_MODE = 0x0D08,
210 HCLGE_OPC_RSS_INPUT_TUPLE = 0x0D02,
211
212 /* Promisuous mode command */
213 HCLGE_OPC_CFG_PROMISC_MODE = 0x0E01,
214
215 /* Vlan offload commands */
216 HCLGE_OPC_VLAN_PORT_TX_CFG = 0x0F01,
217 HCLGE_OPC_VLAN_PORT_RX_CFG = 0x0F02,
218
219 /* Interrupts commands */
220 HCLGE_OPC_ADD_RING_TO_VECTOR = 0x1503,
221 HCLGE_OPC_DEL_RING_TO_VECTOR = 0x1504,
222
223 /* MAC commands */
224 HCLGE_OPC_MAC_VLAN_ADD = 0x1000,
225 HCLGE_OPC_MAC_VLAN_REMOVE = 0x1001,
226 HCLGE_OPC_MAC_VLAN_TYPE_ID = 0x1002,
227 HCLGE_OPC_MAC_VLAN_INSERT = 0x1003,
228 HCLGE_OPC_MAC_VLAN_ALLOCATE = 0x1004,
229 HCLGE_OPC_MAC_ETHTYPE_ADD = 0x1010,
230 HCLGE_OPC_MAC_ETHTYPE_REMOVE = 0x1011,
231
232 /* MAC VLAN commands */
233 HCLGE_OPC_MAC_VLAN_SWITCH_PARAM = 0x1033,
234
235 /* VLAN commands */
236 HCLGE_OPC_VLAN_FILTER_CTRL = 0x1100,
237 HCLGE_OPC_VLAN_FILTER_PF_CFG = 0x1101,
238 HCLGE_OPC_VLAN_FILTER_VF_CFG = 0x1102,
239
240 /* Flow Director commands */
241 HCLGE_OPC_FD_MODE_CTRL = 0x1200,
242 HCLGE_OPC_FD_GET_ALLOCATION = 0x1201,
243 HCLGE_OPC_FD_KEY_CONFIG = 0x1202,
244 HCLGE_OPC_FD_TCAM_OP = 0x1203,
245 HCLGE_OPC_FD_AD_OP = 0x1204,
246 HCLGE_OPC_FD_USER_DEF_OP = 0x1207,
247
248 /* MDIO command */
249 HCLGE_OPC_MDIO_CONFIG = 0x1900,
250
251 /* QCN commands */
252 HCLGE_OPC_QCN_MOD_CFG = 0x1A01,
253 HCLGE_OPC_QCN_GRP_TMPLT_CFG = 0x1A02,
254 HCLGE_OPC_QCN_SHAPPING_CFG = 0x1A03,
255 HCLGE_OPC_QCN_SHAPPING_BS_CFG = 0x1A04,
256 HCLGE_OPC_QCN_QSET_LINK_CFG = 0x1A05,
257 HCLGE_OPC_QCN_RP_STATUS_GET = 0x1A06,
258 HCLGE_OPC_QCN_AJUST_INIT = 0x1A07,
259 HCLGE_OPC_QCN_DFX_CNT_STATUS = 0x1A08,
260
261 /* Mailbox command */
262 HCLGEVF_OPC_MBX_PF_TO_VF = 0x2000,
263
264 /* Led command */
265 HCLGE_OPC_LED_STATUS_CFG = 0xB000,
266
267 /* NCL config command */
268 HCLGE_OPC_QUERY_NCL_CONFIG = 0x7011,
269
270 /* M7 stats command */
271 HCLGE_OPC_M7_STATS_BD = 0x7012,
272 HCLGE_OPC_M7_STATS_INFO = 0x7013,
273 HCLGE_OPC_M7_COMPAT_CFG = 0x701A,
274
275 /* SFP command */
276 HCLGE_OPC_GET_SFP_EEPROM = 0x7100,
277 HCLGE_OPC_GET_SFP_EXIST = 0x7101,
278 HCLGE_OPC_GET_SFP_INFO = 0x7104,
279
280 /* Error INT commands */
281 HCLGE_MAC_COMMON_INT_EN = 0x030E,
282 HCLGE_TM_SCH_ECC_INT_EN = 0x0829,
283 HCLGE_SSU_ECC_INT_CMD = 0x0989,
284 HCLGE_SSU_COMMON_INT_CMD = 0x098C,
285 HCLGE_PPU_MPF_ECC_INT_CMD = 0x0B40,
286 HCLGE_PPU_MPF_OTHER_INT_CMD = 0x0B41,
287 HCLGE_PPU_PF_OTHER_INT_CMD = 0x0B42,
288 HCLGE_COMMON_ECC_INT_CFG = 0x1505,
289 HCLGE_QUERY_RAS_INT_STS_BD_NUM = 0x1510,
290 HCLGE_QUERY_CLEAR_MPF_RAS_INT = 0x1511,
291 HCLGE_QUERY_CLEAR_PF_RAS_INT = 0x1512,
292 HCLGE_QUERY_MSIX_INT_STS_BD_NUM = 0x1513,
293 HCLGE_QUERY_CLEAR_ALL_MPF_MSIX_INT = 0x1514,
294 HCLGE_QUERY_CLEAR_ALL_PF_MSIX_INT = 0x1515,
295 HCLGE_CONFIG_ROCEE_RAS_INT_EN = 0x1580,
296 HCLGE_QUERY_CLEAR_ROCEE_RAS_INT = 0x1581,
297 HCLGE_ROCEE_PF_RAS_INT_CMD = 0x1584,
298 HCLGE_QUERY_ROCEE_ECC_RAS_INFO_CMD = 0x1585,
299 HCLGE_QUERY_ROCEE_AXI_RAS_INFO_CMD = 0x1586,
300 HCLGE_IGU_EGU_TNL_INT_EN = 0x1803,
301 HCLGE_IGU_COMMON_INT_EN = 0x1806,
302 HCLGE_TM_QCN_MEM_INT_CFG = 0x1A14,
303 HCLGE_PPP_CMD0_INT_CMD = 0x2100,
304 HCLGE_PPP_CMD1_INT_CMD = 0x2101,
305 HCLGE_MAC_ETHERTYPE_IDX_RD = 0x2105,
306 HCLGE_NCSI_INT_EN = 0x2401,
307
308 /* PHY command */
309 HCLGE_OPC_PHY_LINK_KSETTING = 0x7025,
310 HCLGE_OPC_PHY_REG = 0x7026,
311 };
312
313 #define HCLGE_TQP_REG_OFFSET 0x80000
314 #define HCLGE_TQP_REG_SIZE 0x200
315
316 #define HCLGE_TQP_MAX_SIZE_DEV_V2 1024
317 #define HCLGE_TQP_EXT_REG_OFFSET 0x100
318
319 #define HCLGE_RCB_INIT_QUERY_TIMEOUT 10
320 #define HCLGE_RCB_INIT_FLAG_EN_B 0
321 #define HCLGE_RCB_INIT_FLAG_FINI_B 8
322 struct hclge_config_rcb_init_cmd {
323 __le16 rcb_init_flag;
324 u8 rsv[22];
325 };
326
327 struct hclge_tqp_map_cmd {
328 __le16 tqp_id; /* Absolute tqp id for in this pf */
329 u8 tqp_vf; /* VF id */
330 #define HCLGE_TQP_MAP_TYPE_PF 0
331 #define HCLGE_TQP_MAP_TYPE_VF 1
332 #define HCLGE_TQP_MAP_TYPE_B 0
333 #define HCLGE_TQP_MAP_EN_B 1
334 u8 tqp_flag; /* Indicate it's pf or vf tqp */
335 __le16 tqp_vid; /* Virtual id in this pf/vf */
336 u8 rsv[18];
337 };
338
339 #define HCLGE_VECTOR_ELEMENTS_PER_CMD 10
340
341 enum hclge_int_type {
342 HCLGE_INT_TX,
343 HCLGE_INT_RX,
344 HCLGE_INT_EVENT,
345 };
346
347 struct hclge_ctrl_vector_chain_cmd {
348 #define HCLGE_VECTOR_ID_L_S 0
349 #define HCLGE_VECTOR_ID_L_M GENMASK(7, 0)
350 u8 int_vector_id_l;
351 u8 int_cause_num;
352 #define HCLGE_INT_TYPE_S 0
353 #define HCLGE_INT_TYPE_M GENMASK(1, 0)
354 #define HCLGE_TQP_ID_S 2
355 #define HCLGE_TQP_ID_M GENMASK(12, 2)
356 #define HCLGE_INT_GL_IDX_S 13
357 #define HCLGE_INT_GL_IDX_M GENMASK(14, 13)
358 __le16 tqp_type_and_id[HCLGE_VECTOR_ELEMENTS_PER_CMD];
359 u8 vfid;
360 #define HCLGE_VECTOR_ID_H_S 8
361 #define HCLGE_VECTOR_ID_H_M GENMASK(15, 8)
362 u8 int_vector_id_h;
363 };
364
365 #define HCLGE_MAX_TC_NUM 8
366 #define HCLGE_TC0_PRI_BUF_EN_B 15 /* Bit 15 indicate enable or not */
367 #define HCLGE_BUF_UNIT_S 7 /* Buf size is united by 128 bytes */
368 struct hclge_tx_buff_alloc_cmd {
369 __le16 tx_pkt_buff[HCLGE_MAX_TC_NUM];
370 u8 tx_buff_rsv[8];
371 };
372
373 struct hclge_rx_priv_buff_cmd {
374 __le16 buf_num[HCLGE_MAX_TC_NUM];
375 __le16 shared_buf;
376 u8 rsv[6];
377 };
378
379 enum HCLGE_CAP_BITS {
380 HCLGE_CAP_UDP_GSO_B,
381 HCLGE_CAP_QB_B,
382 HCLGE_CAP_FD_FORWARD_TC_B,
383 HCLGE_CAP_PTP_B,
384 HCLGE_CAP_INT_QL_B,
385 HCLGE_CAP_HW_TX_CSUM_B,
386 HCLGE_CAP_TX_PUSH_B,
387 HCLGE_CAP_PHY_IMP_B,
388 HCLGE_CAP_TQP_TXRX_INDEP_B,
389 HCLGE_CAP_HW_PAD_B,
390 HCLGE_CAP_STASH_B,
391 HCLGE_CAP_UDP_TUNNEL_CSUM_B,
392 HCLGE_CAP_FEC_B = 13,
393 HCLGE_CAP_PAUSE_B = 14,
394 };
395
396 enum HCLGE_API_CAP_BITS {
397 HCLGE_API_CAP_FLEX_RSS_TBL_B,
398 };
399
400 #define HCLGE_QUERY_CAP_LENGTH 3
401 struct hclge_query_version_cmd {
402 __le32 firmware;
403 __le32 hardware;
404 __le32 api_caps;
405 __le32 caps[HCLGE_QUERY_CAP_LENGTH]; /* capabilities of device */
406 };
407
408 #define HCLGE_RX_PRIV_EN_B 15
409 #define HCLGE_TC_NUM_ONE_DESC 4
410 struct hclge_priv_wl {
411 __le16 high;
412 __le16 low;
413 };
414
415 struct hclge_rx_priv_wl_buf {
416 struct hclge_priv_wl tc_wl[HCLGE_TC_NUM_ONE_DESC];
417 };
418
419 struct hclge_rx_com_thrd {
420 struct hclge_priv_wl com_thrd[HCLGE_TC_NUM_ONE_DESC];
421 };
422
423 struct hclge_rx_com_wl {
424 struct hclge_priv_wl com_wl;
425 };
426
427 struct hclge_waterline {
428 u32 low;
429 u32 high;
430 };
431
432 struct hclge_tc_thrd {
433 u32 low;
434 u32 high;
435 };
436
437 struct hclge_priv_buf {
438 struct hclge_waterline wl; /* Waterline for low and high*/
439 u32 buf_size; /* TC private buffer size */
440 u32 tx_buf_size;
441 u32 enable; /* Enable TC private buffer or not */
442 };
443
444 struct hclge_shared_buf {
445 struct hclge_waterline self;
446 struct hclge_tc_thrd tc_thrd[HCLGE_MAX_TC_NUM];
447 u32 buf_size;
448 };
449
450 struct hclge_pkt_buf_alloc {
451 struct hclge_priv_buf priv_buf[HCLGE_MAX_TC_NUM];
452 struct hclge_shared_buf s_buf;
453 };
454
455 #define HCLGE_RX_COM_WL_EN_B 15
456 struct hclge_rx_com_wl_buf_cmd {
457 __le16 high_wl;
458 __le16 low_wl;
459 u8 rsv[20];
460 };
461
462 #define HCLGE_RX_PKT_EN_B 15
463 struct hclge_rx_pkt_buf_cmd {
464 __le16 high_pkt;
465 __le16 low_pkt;
466 u8 rsv[20];
467 };
468
469 #define HCLGE_PF_STATE_DONE_B 0
470 #define HCLGE_PF_STATE_MAIN_B 1
471 #define HCLGE_PF_STATE_BOND_B 2
472 #define HCLGE_PF_STATE_MAC_N_B 6
473 #define HCLGE_PF_MAC_NUM_MASK 0x3
474 #define HCLGE_PF_STATE_MAIN BIT(HCLGE_PF_STATE_MAIN_B)
475 #define HCLGE_PF_STATE_DONE BIT(HCLGE_PF_STATE_DONE_B)
476 #define HCLGE_VF_RST_STATUS_CMD 4
477
478 struct hclge_func_status_cmd {
479 __le32 vf_rst_state[HCLGE_VF_RST_STATUS_CMD];
480 u8 pf_state;
481 u8 mac_id;
482 u8 rsv1;
483 u8 pf_cnt_in_mac;
484 u8 pf_num;
485 u8 vf_num;
486 u8 rsv[2];
487 };
488
489 struct hclge_pf_res_cmd {
490 __le16 tqp_num;
491 __le16 buf_size;
492 __le16 msixcap_localid_ba_nic;
493 __le16 msixcap_localid_number_nic;
494 __le16 pf_intr_vector_number_roce;
495 __le16 pf_own_fun_number;
496 __le16 tx_buf_size;
497 __le16 dv_buf_size;
498 __le16 ext_tqp_num;
499 u8 rsv[6];
500 };
501
502 #define HCLGE_CFG_OFFSET_S 0
503 #define HCLGE_CFG_OFFSET_M GENMASK(19, 0)
504 #define HCLGE_CFG_RD_LEN_S 24
505 #define HCLGE_CFG_RD_LEN_M GENMASK(27, 24)
506 #define HCLGE_CFG_RD_LEN_BYTES 16
507 #define HCLGE_CFG_RD_LEN_UNIT 4
508
509 #define HCLGE_CFG_TC_NUM_S 8
510 #define HCLGE_CFG_TC_NUM_M GENMASK(15, 8)
511 #define HCLGE_CFG_TQP_DESC_N_S 16
512 #define HCLGE_CFG_TQP_DESC_N_M GENMASK(31, 16)
513 #define HCLGE_CFG_PHY_ADDR_S 0
514 #define HCLGE_CFG_PHY_ADDR_M GENMASK(7, 0)
515 #define HCLGE_CFG_MEDIA_TP_S 8
516 #define HCLGE_CFG_MEDIA_TP_M GENMASK(15, 8)
517 #define HCLGE_CFG_RX_BUF_LEN_S 16
518 #define HCLGE_CFG_RX_BUF_LEN_M GENMASK(31, 16)
519 #define HCLGE_CFG_MAC_ADDR_H_S 0
520 #define HCLGE_CFG_MAC_ADDR_H_M GENMASK(15, 0)
521 #define HCLGE_CFG_DEFAULT_SPEED_S 16
522 #define HCLGE_CFG_DEFAULT_SPEED_M GENMASK(23, 16)
523 #define HCLGE_CFG_RSS_SIZE_S 24
524 #define HCLGE_CFG_RSS_SIZE_M GENMASK(31, 24)
525 #define HCLGE_CFG_SPEED_ABILITY_S 0
526 #define HCLGE_CFG_SPEED_ABILITY_M GENMASK(7, 0)
527 #define HCLGE_CFG_SPEED_ABILITY_EXT_S 10
528 #define HCLGE_CFG_SPEED_ABILITY_EXT_M GENMASK(15, 10)
529 #define HCLGE_CFG_UMV_TBL_SPACE_S 16
530 #define HCLGE_CFG_UMV_TBL_SPACE_M GENMASK(31, 16)
531 #define HCLGE_CFG_PF_RSS_SIZE_S 0
532 #define HCLGE_CFG_PF_RSS_SIZE_M GENMASK(3, 0)
533
534 #define HCLGE_CFG_CMD_CNT 4
535
536 struct hclge_cfg_param_cmd {
537 __le32 offset;
538 __le32 rsv;
539 __le32 param[HCLGE_CFG_CMD_CNT];
540 };
541
542 #define HCLGE_MAC_MODE 0x0
543 #define HCLGE_DESC_NUM 0x40
544
545 #define HCLGE_ALLOC_VALID_B 0
546 struct hclge_vf_num_cmd {
547 u8 alloc_valid;
548 u8 rsv[23];
549 };
550
551 #define HCLGE_RSS_DEFAULT_OUTPORT_B 4
552 #define HCLGE_RSS_HASH_KEY_OFFSET_B 4
553 #define HCLGE_RSS_HASH_KEY_NUM 16
554 struct hclge_rss_config_cmd {
555 u8 hash_config;
556 u8 rsv[7];
557 u8 hash_key[HCLGE_RSS_HASH_KEY_NUM];
558 };
559
560 struct hclge_rss_input_tuple_cmd {
561 u8 ipv4_tcp_en;
562 u8 ipv4_udp_en;
563 u8 ipv4_sctp_en;
564 u8 ipv4_fragment_en;
565 u8 ipv6_tcp_en;
566 u8 ipv6_udp_en;
567 u8 ipv6_sctp_en;
568 u8 ipv6_fragment_en;
569 u8 rsv[16];
570 };
571
572 #define HCLGE_RSS_CFG_TBL_SIZE 16
573 #define HCLGE_RSS_CFG_TBL_SIZE_H 4
574 #define HCLGE_RSS_CFG_TBL_BW_H 2U
575 #define HCLGE_RSS_CFG_TBL_BW_L 8U
576
577 struct hclge_rss_indirection_table_cmd {
578 __le16 start_table_index;
579 __le16 rss_set_bitmap;
580 u8 rss_qid_h[HCLGE_RSS_CFG_TBL_SIZE_H];
581 u8 rss_qid_l[HCLGE_RSS_CFG_TBL_SIZE];
582 };
583
584 #define HCLGE_RSS_TC_OFFSET_S 0
585 #define HCLGE_RSS_TC_OFFSET_M GENMASK(10, 0)
586 #define HCLGE_RSS_TC_SIZE_MSB_B 11
587 #define HCLGE_RSS_TC_SIZE_S 12
588 #define HCLGE_RSS_TC_SIZE_M GENMASK(14, 12)
589 #define HCLGE_RSS_TC_SIZE_MSB_OFFSET 3
590 #define HCLGE_RSS_TC_VALID_B 15
591 struct hclge_rss_tc_mode_cmd {
592 __le16 rss_tc_mode[HCLGE_MAX_TC_NUM];
593 u8 rsv[8];
594 };
595
596 #define HCLGE_LINK_STATUS_UP_B 0
597 #define HCLGE_LINK_STATUS_UP_M BIT(HCLGE_LINK_STATUS_UP_B)
598 struct hclge_link_status_cmd {
599 u8 status;
600 u8 rsv[23];
601 };
602
603 /* for DEVICE_VERSION_V1/2, reference to promisc cmd byte8 */
604 #define HCLGE_PROMISC_EN_UC 1
605 #define HCLGE_PROMISC_EN_MC 2
606 #define HCLGE_PROMISC_EN_BC 3
607 #define HCLGE_PROMISC_TX_EN 4
608 #define HCLGE_PROMISC_RX_EN 5
609
610 /* for DEVICE_VERSION_V3, reference to promisc cmd byte10 */
611 #define HCLGE_PROMISC_UC_RX_EN 2
612 #define HCLGE_PROMISC_MC_RX_EN 3
613 #define HCLGE_PROMISC_BC_RX_EN 4
614 #define HCLGE_PROMISC_UC_TX_EN 5
615 #define HCLGE_PROMISC_MC_TX_EN 6
616 #define HCLGE_PROMISC_BC_TX_EN 7
617
618 struct hclge_promisc_cfg_cmd {
619 u8 promisc;
620 u8 vf_id;
621 u8 extend_promisc;
622 u8 rsv0[21];
623 };
624
625 enum hclge_promisc_type {
626 HCLGE_UNICAST = 1,
627 HCLGE_MULTICAST = 2,
628 HCLGE_BROADCAST = 3,
629 };
630
631 #define HCLGE_MAC_TX_EN_B 6
632 #define HCLGE_MAC_RX_EN_B 7
633 #define HCLGE_MAC_PAD_TX_B 11
634 #define HCLGE_MAC_PAD_RX_B 12
635 #define HCLGE_MAC_1588_TX_B 13
636 #define HCLGE_MAC_1588_RX_B 14
637 #define HCLGE_MAC_APP_LP_B 15
638 #define HCLGE_MAC_LINE_LP_B 16
639 #define HCLGE_MAC_FCS_TX_B 17
640 #define HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B 18
641 #define HCLGE_MAC_RX_FCS_STRIP_B 19
642 #define HCLGE_MAC_RX_FCS_B 20
643 #define HCLGE_MAC_TX_UNDER_MIN_ERR_B 21
644 #define HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B 22
645
646 struct hclge_config_mac_mode_cmd {
647 __le32 txrx_pad_fcs_loop_en;
648 u8 rsv[20];
649 };
650
651 struct hclge_pf_rst_sync_cmd {
652 #define HCLGE_PF_RST_ALL_VF_RDY_B 0
653 u8 all_vf_ready;
654 u8 rsv[23];
655 };
656
657 #define HCLGE_CFG_SPEED_S 0
658 #define HCLGE_CFG_SPEED_M GENMASK(5, 0)
659
660 #define HCLGE_CFG_DUPLEX_B 7
661 #define HCLGE_CFG_DUPLEX_M BIT(HCLGE_CFG_DUPLEX_B)
662
663 struct hclge_config_mac_speed_dup_cmd {
664 u8 speed_dup;
665
666 #define HCLGE_CFG_MAC_SPEED_CHANGE_EN_B 0
667 u8 mac_change_fec_en;
668 u8 rsv[22];
669 };
670
671 #define HCLGE_TQP_ENABLE_B 0
672
673 #define HCLGE_MAC_CFG_AN_EN_B 0
674 #define HCLGE_MAC_CFG_AN_INT_EN_B 1
675 #define HCLGE_MAC_CFG_AN_INT_MSK_B 2
676 #define HCLGE_MAC_CFG_AN_INT_CLR_B 3
677 #define HCLGE_MAC_CFG_AN_RST_B 4
678
679 #define HCLGE_MAC_CFG_AN_EN BIT(HCLGE_MAC_CFG_AN_EN_B)
680
681 struct hclge_config_auto_neg_cmd {
682 __le32 cfg_an_cmd_flag;
683 u8 rsv[20];
684 };
685
686 struct hclge_sfp_info_cmd {
687 __le32 speed;
688 u8 query_type; /* 0: sfp speed, 1: active speed */
689 u8 active_fec;
690 u8 autoneg; /* autoneg state */
691 u8 autoneg_ability; /* whether support autoneg */
692 __le32 speed_ability; /* speed ability for current media */
693 __le32 module_type;
694 u8 rsv[8];
695 };
696
697 #define HCLGE_MAC_CFG_FEC_AUTO_EN_B 0
698 #define HCLGE_MAC_CFG_FEC_MODE_S 1
699 #define HCLGE_MAC_CFG_FEC_MODE_M GENMASK(3, 1)
700 #define HCLGE_MAC_CFG_FEC_SET_DEF_B 0
701 #define HCLGE_MAC_CFG_FEC_CLR_DEF_B 1
702
703 #define HCLGE_MAC_FEC_OFF 0
704 #define HCLGE_MAC_FEC_BASER 1
705 #define HCLGE_MAC_FEC_RS 2
706 struct hclge_config_fec_cmd {
707 u8 fec_mode;
708 u8 default_config;
709 u8 rsv[22];
710 };
711
712 #define HCLGE_MAC_UPLINK_PORT 0x100
713
714 struct hclge_config_max_frm_size_cmd {
715 __le16 max_frm_size;
716 u8 min_frm_size;
717 u8 rsv[21];
718 };
719
720 enum hclge_mac_vlan_tbl_opcode {
721 HCLGE_MAC_VLAN_ADD, /* Add new or modify mac_vlan */
722 HCLGE_MAC_VLAN_UPDATE, /* Modify other fields of this table */
723 HCLGE_MAC_VLAN_REMOVE, /* Remove a entry through mac_vlan key */
724 HCLGE_MAC_VLAN_LKUP, /* Lookup a entry through mac_vlan key */
725 };
726
727 enum hclge_mac_vlan_add_resp_code {
728 HCLGE_ADD_UC_OVERFLOW = 2, /* ADD failed for UC overflow */
729 HCLGE_ADD_MC_OVERFLOW, /* ADD failed for MC overflow */
730 };
731
732 #define HCLGE_MAC_VLAN_BIT0_EN_B 0
733 #define HCLGE_MAC_VLAN_BIT1_EN_B 1
734 #define HCLGE_MAC_EPORT_SW_EN_B 12
735 #define HCLGE_MAC_EPORT_TYPE_B 11
736 #define HCLGE_MAC_EPORT_VFID_S 3
737 #define HCLGE_MAC_EPORT_VFID_M GENMASK(10, 3)
738 #define HCLGE_MAC_EPORT_PFID_S 0
739 #define HCLGE_MAC_EPORT_PFID_M GENMASK(2, 0)
740 struct hclge_mac_vlan_tbl_entry_cmd {
741 u8 flags;
742 u8 resp_code;
743 __le16 vlan_tag;
744 __le32 mac_addr_hi32;
745 __le16 mac_addr_lo16;
746 __le16 rsv1;
747 u8 entry_type;
748 u8 mc_mac_en;
749 __le16 egress_port;
750 __le16 egress_queue;
751 u8 rsv2[6];
752 };
753
754 #define HCLGE_UMV_SPC_ALC_B 0
755 struct hclge_umv_spc_alc_cmd {
756 u8 allocate;
757 u8 rsv1[3];
758 __le32 space_size;
759 u8 rsv2[16];
760 };
761
762 #define HCLGE_MAC_MGR_MASK_VLAN_B BIT(0)
763 #define HCLGE_MAC_MGR_MASK_MAC_B BIT(1)
764 #define HCLGE_MAC_MGR_MASK_ETHERTYPE_B BIT(2)
765
766 struct hclge_mac_mgr_tbl_entry_cmd {
767 u8 flags;
768 u8 resp_code;
769 __le16 vlan_tag;
770 u8 mac_addr[ETH_ALEN];
771 __le16 rsv1;
772 __le16 ethter_type;
773 __le16 egress_port;
774 __le16 egress_queue;
775 u8 sw_port_id_aware;
776 u8 rsv2;
777 u8 i_port_bitmap;
778 u8 i_port_direction;
779 u8 rsv3[2];
780 };
781
782 struct hclge_vlan_filter_ctrl_cmd {
783 u8 vlan_type;
784 u8 vlan_fe;
785 u8 rsv1[2];
786 u8 vf_id;
787 u8 rsv2[19];
788 };
789
790 #define HCLGE_VLAN_ID_OFFSET_STEP 160
791 #define HCLGE_VLAN_BYTE_SIZE 8
792 #define HCLGE_VLAN_OFFSET_BITMAP \
793 (HCLGE_VLAN_ID_OFFSET_STEP / HCLGE_VLAN_BYTE_SIZE)
794
795 struct hclge_vlan_filter_pf_cfg_cmd {
796 u8 vlan_offset;
797 u8 vlan_cfg;
798 u8 rsv[2];
799 u8 vlan_offset_bitmap[HCLGE_VLAN_OFFSET_BITMAP];
800 };
801
802 #define HCLGE_MAX_VF_BYTES 16
803
804 struct hclge_vlan_filter_vf_cfg_cmd {
805 __le16 vlan_id;
806 u8 resp_code;
807 u8 rsv;
808 u8 vlan_cfg;
809 u8 rsv1[3];
810 u8 vf_bitmap[HCLGE_MAX_VF_BYTES];
811 };
812
813 #define HCLGE_SWITCH_ANTI_SPOOF_B 0U
814 #define HCLGE_SWITCH_ALW_LPBK_B 1U
815 #define HCLGE_SWITCH_ALW_LCL_LPBK_B 2U
816 #define HCLGE_SWITCH_ALW_DST_OVRD_B 3U
817 #define HCLGE_SWITCH_NO_MASK 0x0
818 #define HCLGE_SWITCH_ANTI_SPOOF_MASK 0xFE
819 #define HCLGE_SWITCH_ALW_LPBK_MASK 0xFD
820 #define HCLGE_SWITCH_ALW_LCL_LPBK_MASK 0xFB
821 #define HCLGE_SWITCH_LW_DST_OVRD_MASK 0xF7
822
823 struct hclge_mac_vlan_switch_cmd {
824 u8 roce_sel;
825 u8 rsv1[3];
826 __le32 func_id;
827 u8 switch_param;
828 u8 rsv2[3];
829 u8 param_mask;
830 u8 rsv3[11];
831 };
832
833 enum hclge_mac_vlan_cfg_sel {
834 HCLGE_MAC_VLAN_NIC_SEL = 0,
835 HCLGE_MAC_VLAN_ROCE_SEL,
836 };
837
838 #define HCLGE_ACCEPT_TAG1_B 0
839 #define HCLGE_ACCEPT_UNTAG1_B 1
840 #define HCLGE_PORT_INS_TAG1_EN_B 2
841 #define HCLGE_PORT_INS_TAG2_EN_B 3
842 #define HCLGE_CFG_NIC_ROCE_SEL_B 4
843 #define HCLGE_ACCEPT_TAG2_B 5
844 #define HCLGE_ACCEPT_UNTAG2_B 6
845 #define HCLGE_TAG_SHIFT_MODE_EN_B 7
846 #define HCLGE_VF_NUM_PER_BYTE 8
847
848 struct hclge_vport_vtag_tx_cfg_cmd {
849 u8 vport_vlan_cfg;
850 u8 vf_offset;
851 u8 rsv1[2];
852 __le16 def_vlan_tag1;
853 __le16 def_vlan_tag2;
854 u8 vf_bitmap[HCLGE_VF_NUM_PER_BYTE];
855 u8 rsv2[8];
856 };
857
858 #define HCLGE_REM_TAG1_EN_B 0
859 #define HCLGE_REM_TAG2_EN_B 1
860 #define HCLGE_SHOW_TAG1_EN_B 2
861 #define HCLGE_SHOW_TAG2_EN_B 3
862 #define HCLGE_DISCARD_TAG1_EN_B 5
863 #define HCLGE_DISCARD_TAG2_EN_B 6
864 struct hclge_vport_vtag_rx_cfg_cmd {
865 u8 vport_vlan_cfg;
866 u8 vf_offset;
867 u8 rsv1[6];
868 u8 vf_bitmap[HCLGE_VF_NUM_PER_BYTE];
869 u8 rsv2[8];
870 };
871
872 struct hclge_tx_vlan_type_cfg_cmd {
873 __le16 ot_vlan_type;
874 __le16 in_vlan_type;
875 u8 rsv[20];
876 };
877
878 struct hclge_rx_vlan_type_cfg_cmd {
879 __le16 ot_fst_vlan_type;
880 __le16 ot_sec_vlan_type;
881 __le16 in_fst_vlan_type;
882 __le16 in_sec_vlan_type;
883 u8 rsv[16];
884 };
885
886 struct hclge_cfg_com_tqp_queue_cmd {
887 __le16 tqp_id;
888 __le16 stream_id;
889 u8 enable;
890 u8 rsv[19];
891 };
892
893 struct hclge_cfg_tx_queue_pointer_cmd {
894 __le16 tqp_id;
895 __le16 tx_tail;
896 __le16 tx_head;
897 __le16 fbd_num;
898 __le16 ring_offset;
899 u8 rsv[14];
900 };
901
902 #pragma pack(1)
903 struct hclge_mac_ethertype_idx_rd_cmd {
904 u8 flags;
905 u8 resp_code;
906 __le16 vlan_tag;
907 u8 mac_addr[ETH_ALEN];
908 __le16 index;
909 __le16 ethter_type;
910 __le16 egress_port;
911 __le16 egress_queue;
912 __le16 rev0;
913 u8 i_port_bitmap;
914 u8 i_port_direction;
915 u8 rev1[2];
916 };
917
918 #pragma pack()
919
920 #define HCLGE_TSO_MSS_MIN_S 0
921 #define HCLGE_TSO_MSS_MIN_M GENMASK(13, 0)
922
923 #define HCLGE_TSO_MSS_MAX_S 16
924 #define HCLGE_TSO_MSS_MAX_M GENMASK(29, 16)
925
926 struct hclge_cfg_tso_status_cmd {
927 __le16 tso_mss_min;
928 __le16 tso_mss_max;
929 u8 rsv[20];
930 };
931
932 #define HCLGE_GRO_EN_B 0
933 struct hclge_cfg_gro_status_cmd {
934 u8 gro_en;
935 u8 rsv[23];
936 };
937
938 #define HCLGE_TSO_MSS_MIN 256
939 #define HCLGE_TSO_MSS_MAX 9668
940
941 #define HCLGE_TQP_RESET_B 0
942 struct hclge_reset_tqp_queue_cmd {
943 __le16 tqp_id;
944 u8 reset_req;
945 u8 ready_to_reset;
946 u8 rsv[20];
947 };
948
949 #define HCLGE_CFG_RESET_MAC_B 3
950 #define HCLGE_CFG_RESET_FUNC_B 7
951 #define HCLGE_CFG_RESET_RCB_B 1
952 struct hclge_reset_cmd {
953 u8 mac_func_reset;
954 u8 fun_reset_vfid;
955 u8 fun_reset_rcb;
956 u8 rsv;
957 __le16 fun_reset_rcb_vqid_start;
958 __le16 fun_reset_rcb_vqid_num;
959 u8 fun_reset_rcb_return_status;
960 u8 rsv1[15];
961 };
962
963 #define HCLGE_PF_RESET_DONE_BIT BIT(0)
964
965 struct hclge_pf_rst_done_cmd {
966 u8 pf_rst_done;
967 u8 rsv[23];
968 };
969
970 #define HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B BIT(0)
971 #define HCLGE_CMD_SERDES_PARALLEL_INNER_LOOP_B BIT(2)
972 #define HCLGE_CMD_GE_PHY_INNER_LOOP_B BIT(3)
973 #define HCLGE_CMD_COMMON_LB_DONE_B BIT(0)
974 #define HCLGE_CMD_COMMON_LB_SUCCESS_B BIT(1)
975 struct hclge_common_lb_cmd {
976 u8 mask;
977 u8 enable;
978 u8 result;
979 u8 rsv[21];
980 };
981
982 #define HCLGE_DEFAULT_TX_BUF 0x4000 /* 16k bytes */
983 #define HCLGE_TOTAL_PKT_BUF 0x108000 /* 1.03125M bytes */
984 #define HCLGE_DEFAULT_DV 0xA000 /* 40k byte */
985 #define HCLGE_DEFAULT_NON_DCB_DV 0x7800 /* 30K byte */
986 #define HCLGE_NON_DCB_ADDITIONAL_BUF 0x1400 /* 5120 byte */
987
988 #define HCLGE_TYPE_CRQ 0
989 #define HCLGE_TYPE_CSQ 1
990 #define HCLGE_NIC_CSQ_BASEADDR_L_REG 0x27000
991 #define HCLGE_NIC_CSQ_BASEADDR_H_REG 0x27004
992 #define HCLGE_NIC_CSQ_DEPTH_REG 0x27008
993 #define HCLGE_NIC_CSQ_TAIL_REG 0x27010
994 #define HCLGE_NIC_CSQ_HEAD_REG 0x27014
995 #define HCLGE_NIC_CRQ_BASEADDR_L_REG 0x27018
996 #define HCLGE_NIC_CRQ_BASEADDR_H_REG 0x2701c
997 #define HCLGE_NIC_CRQ_DEPTH_REG 0x27020
998 #define HCLGE_NIC_CRQ_TAIL_REG 0x27024
999 #define HCLGE_NIC_CRQ_HEAD_REG 0x27028
1000
1001 /* this bit indicates that the driver is ready for hardware reset */
1002 #define HCLGE_NIC_SW_RST_RDY_B 16
1003 #define HCLGE_NIC_SW_RST_RDY BIT(HCLGE_NIC_SW_RST_RDY_B)
1004
1005 #define HCLGE_NIC_CMQ_DESC_NUM 1024
1006 #define HCLGE_NIC_CMQ_DESC_NUM_S 3
1007
1008 #define HCLGE_LED_LOCATE_STATE_S 0
1009 #define HCLGE_LED_LOCATE_STATE_M GENMASK(1, 0)
1010
1011 struct hclge_set_led_state_cmd {
1012 u8 rsv1[3];
1013 u8 locate_led_config;
1014 u8 rsv2[20];
1015 };
1016
1017 struct hclge_get_fd_mode_cmd {
1018 u8 mode;
1019 u8 enable;
1020 u8 rsv[22];
1021 };
1022
1023 struct hclge_get_fd_allocation_cmd {
1024 __le32 stage1_entry_num;
1025 __le32 stage2_entry_num;
1026 __le16 stage1_counter_num;
1027 __le16 stage2_counter_num;
1028 u8 rsv[12];
1029 };
1030
1031 struct hclge_set_fd_key_config_cmd {
1032 u8 stage;
1033 u8 key_select;
1034 u8 inner_sipv6_word_en;
1035 u8 inner_dipv6_word_en;
1036 u8 outer_sipv6_word_en;
1037 u8 outer_dipv6_word_en;
1038 u8 rsv1[2];
1039 __le32 tuple_mask;
1040 __le32 meta_data_mask;
1041 u8 rsv2[8];
1042 };
1043
1044 #define HCLGE_FD_EPORT_SW_EN_B 0
1045 struct hclge_fd_tcam_config_1_cmd {
1046 u8 stage;
1047 u8 xy_sel;
1048 u8 port_info;
1049 u8 rsv1[1];
1050 __le32 index;
1051 u8 entry_vld;
1052 u8 rsv2[7];
1053 u8 tcam_data[8];
1054 };
1055
1056 struct hclge_fd_tcam_config_2_cmd {
1057 u8 tcam_data[24];
1058 };
1059
1060 struct hclge_fd_tcam_config_3_cmd {
1061 u8 tcam_data[20];
1062 u8 rsv[4];
1063 };
1064
1065 #define HCLGE_FD_AD_DROP_B 0
1066 #define HCLGE_FD_AD_DIRECT_QID_B 1
1067 #define HCLGE_FD_AD_QID_S 2
1068 #define HCLGE_FD_AD_QID_M GENMASK(11, 2)
1069 #define HCLGE_FD_AD_USE_COUNTER_B 12
1070 #define HCLGE_FD_AD_COUNTER_NUM_S 13
1071 #define HCLGE_FD_AD_COUNTER_NUM_M GENMASK(20, 13)
1072 #define HCLGE_FD_AD_NXT_STEP_B 20
1073 #define HCLGE_FD_AD_NXT_KEY_S 21
1074 #define HCLGE_FD_AD_NXT_KEY_M GENMASK(25, 21)
1075 #define HCLGE_FD_AD_WR_RULE_ID_B 0
1076 #define HCLGE_FD_AD_RULE_ID_S 1
1077 #define HCLGE_FD_AD_RULE_ID_M GENMASK(12, 1)
1078 #define HCLGE_FD_AD_TC_OVRD_B 16
1079 #define HCLGE_FD_AD_TC_SIZE_S 17
1080 #define HCLGE_FD_AD_TC_SIZE_M GENMASK(20, 17)
1081
1082 struct hclge_fd_ad_config_cmd {
1083 u8 stage;
1084 u8 rsv1[3];
1085 __le32 index;
1086 __le64 ad_data;
1087 u8 rsv2[8];
1088 };
1089
1090 #define HCLGE_FD_USER_DEF_OFT_S 0
1091 #define HCLGE_FD_USER_DEF_OFT_M GENMASK(14, 0)
1092 #define HCLGE_FD_USER_DEF_EN_B 15
1093 struct hclge_fd_user_def_cfg_cmd {
1094 __le16 ol2_cfg;
1095 __le16 l2_cfg;
1096 __le16 ol3_cfg;
1097 __le16 l3_cfg;
1098 __le16 ol4_cfg;
1099 __le16 l4_cfg;
1100 u8 rsv[12];
1101 };
1102
1103 struct hclge_get_m7_bd_cmd {
1104 __le32 bd_num;
1105 u8 rsv[20];
1106 };
1107
1108 struct hclge_query_ppu_pf_other_int_dfx_cmd {
1109 __le16 over_8bd_no_fe_qid;
1110 __le16 over_8bd_no_fe_vf_id;
1111 __le16 tso_mss_cmp_min_err_qid;
1112 __le16 tso_mss_cmp_min_err_vf_id;
1113 __le16 tso_mss_cmp_max_err_qid;
1114 __le16 tso_mss_cmp_max_err_vf_id;
1115 __le16 tx_rd_fbd_poison_qid;
1116 __le16 tx_rd_fbd_poison_vf_id;
1117 __le16 rx_rd_fbd_poison_qid;
1118 __le16 rx_rd_fbd_poison_vf_id;
1119 u8 rsv[4];
1120 };
1121
1122 #define HCLGE_LINK_EVENT_REPORT_EN_B 0
1123 #define HCLGE_NCSI_ERROR_REPORT_EN_B 1
1124 #define HCLGE_PHY_IMP_EN_B 2
1125 struct hclge_firmware_compat_cmd {
1126 __le32 compat;
1127 u8 rsv[20];
1128 };
1129
1130 #define HCLGE_SFP_INFO_CMD_NUM 6
1131 #define HCLGE_SFP_INFO_BD0_LEN 20
1132 #define HCLGE_SFP_INFO_BDX_LEN 24
1133 #define HCLGE_SFP_INFO_MAX_LEN \
1134 (HCLGE_SFP_INFO_BD0_LEN + \
1135 (HCLGE_SFP_INFO_CMD_NUM - 1) * HCLGE_SFP_INFO_BDX_LEN)
1136
1137 struct hclge_sfp_info_bd0_cmd {
1138 __le16 offset;
1139 __le16 read_len;
1140 u8 data[HCLGE_SFP_INFO_BD0_LEN];
1141 };
1142
1143 #define HCLGE_QUERY_DEV_SPECS_BD_NUM 4
1144
1145 struct hclge_dev_specs_0_cmd {
1146 __le32 rsv0;
1147 __le32 mac_entry_num;
1148 __le32 mng_entry_num;
1149 __le16 rss_ind_tbl_size;
1150 __le16 rss_key_size;
1151 __le16 int_ql_max;
1152 u8 max_non_tso_bd_num;
1153 u8 rsv1;
1154 __le32 max_tm_rate;
1155 };
1156
1157 #define HCLGE_DEF_MAX_INT_GL 0x1FE0U
1158
1159 struct hclge_dev_specs_1_cmd {
1160 __le16 max_frm_size;
1161 __le16 max_qset_num;
1162 __le16 max_int_gl;
1163 u8 rsv1[18];
1164 };
1165
1166 #define HCLGE_PHY_LINK_SETTING_BD_NUM 2
1167
1168 struct hclge_phy_link_ksetting_0_cmd {
1169 __le32 speed;
1170 u8 duplex;
1171 u8 autoneg;
1172 u8 eth_tp_mdix;
1173 u8 eth_tp_mdix_ctrl;
1174 u8 port;
1175 u8 transceiver;
1176 u8 phy_address;
1177 u8 rsv;
1178 __le32 supported;
1179 __le32 advertising;
1180 __le32 lp_advertising;
1181 };
1182
1183 struct hclge_phy_link_ksetting_1_cmd {
1184 u8 master_slave_cfg;
1185 u8 master_slave_state;
1186 u8 rsv[22];
1187 };
1188
1189 struct hclge_phy_reg_cmd {
1190 __le16 reg_addr;
1191 u8 rsv0[2];
1192 __le16 reg_val;
1193 u8 rsv1[18];
1194 };
1195
1196 int hclge_cmd_init(struct hclge_dev *hdev);
hclge_write_reg(void __iomem * base,u32 reg,u32 value)1197 static inline void hclge_write_reg(void __iomem *base, u32 reg, u32 value)
1198 {
1199 writel(value, base + reg);
1200 }
1201
1202 #define hclge_write_dev(a, reg, value) \
1203 hclge_write_reg((a)->io_base, reg, value)
1204 #define hclge_read_dev(a, reg) \
1205 hclge_read_reg((a)->io_base, reg)
1206
hclge_read_reg(u8 __iomem * base,u32 reg)1207 static inline u32 hclge_read_reg(u8 __iomem *base, u32 reg)
1208 {
1209 u8 __iomem *reg_addr = READ_ONCE(base);
1210
1211 return readl(reg_addr + reg);
1212 }
1213
1214 #define HCLGE_SEND_SYNC(flag) \
1215 ((flag) & HCLGE_CMD_FLAG_NO_INTR)
1216
1217 struct hclge_hw;
1218 int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num);
1219 void hclge_cmd_setup_basic_desc(struct hclge_desc *desc,
1220 enum hclge_opcode_type opcode, bool is_read);
1221 void hclge_cmd_reuse_desc(struct hclge_desc *desc, bool is_read);
1222
1223 enum hclge_cmd_status hclge_cmd_mdio_write(struct hclge_hw *hw,
1224 struct hclge_desc *desc);
1225 enum hclge_cmd_status hclge_cmd_mdio_read(struct hclge_hw *hw,
1226 struct hclge_desc *desc);
1227
1228 void hclge_cmd_uninit(struct hclge_dev *hdev);
1229 int hclge_cmd_queue_init(struct hclge_dev *hdev);
1230 #endif
1231