1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2018-2019 Realtek Corporation
3 */
4
5 #ifndef __RTK_MAIN_H_
6 #define __RTK_MAIN_H_
7
8 #include <net/mac80211.h>
9 #include <linux/vmalloc.h>
10 #include <linux/firmware.h>
11 #include <linux/average.h>
12 #include <linux/bitops.h>
13 #include <linux/bitfield.h>
14 #include <linux/iopoll.h>
15 #include <linux/interrupt.h>
16 #include <linux/workqueue.h>
17
18 #include "util.h"
19
20 #define RTW_NAPI_WEIGHT_NUM 64
21 #define RTW_MAX_MAC_ID_NUM 32
22 #define RTW_MAX_SEC_CAM_NUM 32
23 #define MAX_PG_CAM_BACKUP_NUM 8
24
25 #define RTW_MAX_PATTERN_NUM 12
26 #define RTW_MAX_PATTERN_MASK_SIZE 16
27 #define RTW_MAX_PATTERN_SIZE 128
28
29 #define RTW_WATCH_DOG_DELAY_TIME round_jiffies_relative(HZ * 2)
30
31 #define RFREG_MASK 0xfffff
32 #define INV_RF_DATA 0xffffffff
33 #define TX_PAGE_SIZE_SHIFT 7
34
35 #define RTW_CHANNEL_WIDTH_MAX 3
36 #define RTW_RF_PATH_MAX 4
37 #define HW_FEATURE_LEN 13
38
39 #define RTW_TP_SHIFT 18 /* bytes/2s --> Mbps */
40
41 extern bool rtw_bf_support;
42 extern bool rtw_disable_lps_deep_mode;
43 extern unsigned int rtw_debug_mask;
44 extern const struct ieee80211_ops rtw_ops;
45
46 #define RTW_MAX_CHANNEL_NUM_2G 14
47 #define RTW_MAX_CHANNEL_NUM_5G 49
48
49 struct rtw_dev;
50
51 enum rtw_hci_type {
52 RTW_HCI_TYPE_PCIE,
53 RTW_HCI_TYPE_USB,
54 RTW_HCI_TYPE_SDIO,
55
56 RTW_HCI_TYPE_UNDEFINE,
57 };
58
59 struct rtw_hci {
60 struct rtw_hci_ops *ops;
61 enum rtw_hci_type type;
62
63 u32 rpwm_addr;
64 u32 cpwm_addr;
65
66 u8 bulkout_num;
67 };
68
69 #define IS_CH_5G_BAND_1(channel) ((channel) >= 36 && (channel <= 48))
70 #define IS_CH_5G_BAND_2(channel) ((channel) >= 52 && (channel <= 64))
71 #define IS_CH_5G_BAND_3(channel) ((channel) >= 100 && (channel <= 144))
72 #define IS_CH_5G_BAND_4(channel) ((channel) >= 149 && (channel <= 177))
73
74 #define IS_CH_5G_BAND_MID(channel) \
75 (IS_CH_5G_BAND_2(channel) || IS_CH_5G_BAND_3(channel))
76
77 #define IS_CH_2G_BAND(channel) ((channel) <= 14)
78 #define IS_CH_5G_BAND(channel) \
79 (IS_CH_5G_BAND_1(channel) || IS_CH_5G_BAND_2(channel) || \
80 IS_CH_5G_BAND_3(channel) || IS_CH_5G_BAND_4(channel))
81
82 enum rtw_supported_band {
83 RTW_BAND_2G = 1 << 0,
84 RTW_BAND_5G = 1 << 1,
85 RTW_BAND_60G = 1 << 2,
86
87 RTW_BAND_MAX,
88 };
89
90 /* now, support upto 80M bw */
91 #define RTW_MAX_CHANNEL_WIDTH RTW_CHANNEL_WIDTH_80
92
93 enum rtw_bandwidth {
94 RTW_CHANNEL_WIDTH_20 = 0,
95 RTW_CHANNEL_WIDTH_40 = 1,
96 RTW_CHANNEL_WIDTH_80 = 2,
97 RTW_CHANNEL_WIDTH_160 = 3,
98 RTW_CHANNEL_WIDTH_80_80 = 4,
99 RTW_CHANNEL_WIDTH_5 = 5,
100 RTW_CHANNEL_WIDTH_10 = 6,
101 };
102
103 enum rtw_sc_offset {
104 RTW_SC_DONT_CARE = 0,
105 RTW_SC_20_UPPER = 1,
106 RTW_SC_20_LOWER = 2,
107 RTW_SC_20_UPMOST = 3,
108 RTW_SC_20_LOWEST = 4,
109 RTW_SC_40_UPPER = 9,
110 RTW_SC_40_LOWER = 10,
111 };
112
113 enum rtw_net_type {
114 RTW_NET_NO_LINK = 0,
115 RTW_NET_AD_HOC = 1,
116 RTW_NET_MGD_LINKED = 2,
117 RTW_NET_AP_MODE = 3,
118 };
119
120 enum rtw_rf_type {
121 RF_1T1R = 0,
122 RF_1T2R = 1,
123 RF_2T2R = 2,
124 RF_2T3R = 3,
125 RF_2T4R = 4,
126 RF_3T3R = 5,
127 RF_3T4R = 6,
128 RF_4T4R = 7,
129 RF_TYPE_MAX,
130 };
131
132 enum rtw_rf_path {
133 RF_PATH_A = 0,
134 RF_PATH_B = 1,
135 RF_PATH_C = 2,
136 RF_PATH_D = 3,
137 };
138
139 enum rtw_bb_path {
140 BB_PATH_A = BIT(0),
141 BB_PATH_B = BIT(1),
142 BB_PATH_C = BIT(2),
143 BB_PATH_D = BIT(3),
144
145 BB_PATH_AB = (BB_PATH_A | BB_PATH_B),
146 BB_PATH_AC = (BB_PATH_A | BB_PATH_C),
147 BB_PATH_AD = (BB_PATH_A | BB_PATH_D),
148 BB_PATH_BC = (BB_PATH_B | BB_PATH_C),
149 BB_PATH_BD = (BB_PATH_B | BB_PATH_D),
150 BB_PATH_CD = (BB_PATH_C | BB_PATH_D),
151
152 BB_PATH_ABC = (BB_PATH_A | BB_PATH_B | BB_PATH_C),
153 BB_PATH_ABD = (BB_PATH_A | BB_PATH_B | BB_PATH_D),
154 BB_PATH_ACD = (BB_PATH_A | BB_PATH_C | BB_PATH_D),
155 BB_PATH_BCD = (BB_PATH_B | BB_PATH_C | BB_PATH_D),
156
157 BB_PATH_ABCD = (BB_PATH_A | BB_PATH_B | BB_PATH_C | BB_PATH_D),
158 };
159
160 enum rtw_rate_section {
161 RTW_RATE_SECTION_CCK = 0,
162 RTW_RATE_SECTION_OFDM,
163 RTW_RATE_SECTION_HT_1S,
164 RTW_RATE_SECTION_HT_2S,
165 RTW_RATE_SECTION_VHT_1S,
166 RTW_RATE_SECTION_VHT_2S,
167
168 /* keep last */
169 RTW_RATE_SECTION_MAX,
170 };
171
172 enum rtw_wireless_set {
173 WIRELESS_CCK = 0x00000001,
174 WIRELESS_OFDM = 0x00000002,
175 WIRELESS_HT = 0x00000004,
176 WIRELESS_VHT = 0x00000008,
177 };
178
179 #define HT_STBC_EN BIT(0)
180 #define VHT_STBC_EN BIT(1)
181 #define HT_LDPC_EN BIT(0)
182 #define VHT_LDPC_EN BIT(1)
183
184 enum rtw_chip_type {
185 RTW_CHIP_TYPE_8822B,
186 RTW_CHIP_TYPE_8822C,
187 RTW_CHIP_TYPE_8723D,
188 RTW_CHIP_TYPE_8821C,
189 };
190
191 enum rtw_tx_queue_type {
192 /* the order of AC queues matters */
193 RTW_TX_QUEUE_BK = 0x0,
194 RTW_TX_QUEUE_BE = 0x1,
195 RTW_TX_QUEUE_VI = 0x2,
196 RTW_TX_QUEUE_VO = 0x3,
197
198 RTW_TX_QUEUE_BCN = 0x4,
199 RTW_TX_QUEUE_MGMT = 0x5,
200 RTW_TX_QUEUE_HI0 = 0x6,
201 RTW_TX_QUEUE_H2C = 0x7,
202 /* keep it last */
203 RTK_MAX_TX_QUEUE_NUM
204 };
205
206 enum rtw_rx_queue_type {
207 RTW_RX_QUEUE_MPDU = 0x0,
208 RTW_RX_QUEUE_C2H = 0x1,
209 /* keep it last */
210 RTK_MAX_RX_QUEUE_NUM
211 };
212
213 enum rtw_fw_type {
214 RTW_NORMAL_FW = 0x0,
215 RTW_WOWLAN_FW = 0x1,
216 };
217
218 enum rtw_rate_index {
219 RTW_RATEID_BGN_40M_2SS = 0,
220 RTW_RATEID_BGN_40M_1SS = 1,
221 RTW_RATEID_BGN_20M_2SS = 2,
222 RTW_RATEID_BGN_20M_1SS = 3,
223 RTW_RATEID_GN_N2SS = 4,
224 RTW_RATEID_GN_N1SS = 5,
225 RTW_RATEID_BG = 6,
226 RTW_RATEID_G = 7,
227 RTW_RATEID_B_20M = 8,
228 RTW_RATEID_ARFR0_AC_2SS = 9,
229 RTW_RATEID_ARFR1_AC_1SS = 10,
230 RTW_RATEID_ARFR2_AC_2G_1SS = 11,
231 RTW_RATEID_ARFR3_AC_2G_2SS = 12,
232 RTW_RATEID_ARFR4_AC_3SS = 13,
233 RTW_RATEID_ARFR5_N_3SS = 14,
234 RTW_RATEID_ARFR7_N_4SS = 15,
235 RTW_RATEID_ARFR6_AC_4SS = 16
236 };
237
238 enum rtw_trx_desc_rate {
239 DESC_RATE1M = 0x00,
240 DESC_RATE2M = 0x01,
241 DESC_RATE5_5M = 0x02,
242 DESC_RATE11M = 0x03,
243
244 DESC_RATE6M = 0x04,
245 DESC_RATE9M = 0x05,
246 DESC_RATE12M = 0x06,
247 DESC_RATE18M = 0x07,
248 DESC_RATE24M = 0x08,
249 DESC_RATE36M = 0x09,
250 DESC_RATE48M = 0x0a,
251 DESC_RATE54M = 0x0b,
252
253 DESC_RATEMCS0 = 0x0c,
254 DESC_RATEMCS1 = 0x0d,
255 DESC_RATEMCS2 = 0x0e,
256 DESC_RATEMCS3 = 0x0f,
257 DESC_RATEMCS4 = 0x10,
258 DESC_RATEMCS5 = 0x11,
259 DESC_RATEMCS6 = 0x12,
260 DESC_RATEMCS7 = 0x13,
261 DESC_RATEMCS8 = 0x14,
262 DESC_RATEMCS9 = 0x15,
263 DESC_RATEMCS10 = 0x16,
264 DESC_RATEMCS11 = 0x17,
265 DESC_RATEMCS12 = 0x18,
266 DESC_RATEMCS13 = 0x19,
267 DESC_RATEMCS14 = 0x1a,
268 DESC_RATEMCS15 = 0x1b,
269 DESC_RATEMCS16 = 0x1c,
270 DESC_RATEMCS17 = 0x1d,
271 DESC_RATEMCS18 = 0x1e,
272 DESC_RATEMCS19 = 0x1f,
273 DESC_RATEMCS20 = 0x20,
274 DESC_RATEMCS21 = 0x21,
275 DESC_RATEMCS22 = 0x22,
276 DESC_RATEMCS23 = 0x23,
277 DESC_RATEMCS24 = 0x24,
278 DESC_RATEMCS25 = 0x25,
279 DESC_RATEMCS26 = 0x26,
280 DESC_RATEMCS27 = 0x27,
281 DESC_RATEMCS28 = 0x28,
282 DESC_RATEMCS29 = 0x29,
283 DESC_RATEMCS30 = 0x2a,
284 DESC_RATEMCS31 = 0x2b,
285
286 DESC_RATEVHT1SS_MCS0 = 0x2c,
287 DESC_RATEVHT1SS_MCS1 = 0x2d,
288 DESC_RATEVHT1SS_MCS2 = 0x2e,
289 DESC_RATEVHT1SS_MCS3 = 0x2f,
290 DESC_RATEVHT1SS_MCS4 = 0x30,
291 DESC_RATEVHT1SS_MCS5 = 0x31,
292 DESC_RATEVHT1SS_MCS6 = 0x32,
293 DESC_RATEVHT1SS_MCS7 = 0x33,
294 DESC_RATEVHT1SS_MCS8 = 0x34,
295 DESC_RATEVHT1SS_MCS9 = 0x35,
296
297 DESC_RATEVHT2SS_MCS0 = 0x36,
298 DESC_RATEVHT2SS_MCS1 = 0x37,
299 DESC_RATEVHT2SS_MCS2 = 0x38,
300 DESC_RATEVHT2SS_MCS3 = 0x39,
301 DESC_RATEVHT2SS_MCS4 = 0x3a,
302 DESC_RATEVHT2SS_MCS5 = 0x3b,
303 DESC_RATEVHT2SS_MCS6 = 0x3c,
304 DESC_RATEVHT2SS_MCS7 = 0x3d,
305 DESC_RATEVHT2SS_MCS8 = 0x3e,
306 DESC_RATEVHT2SS_MCS9 = 0x3f,
307
308 DESC_RATEVHT3SS_MCS0 = 0x40,
309 DESC_RATEVHT3SS_MCS1 = 0x41,
310 DESC_RATEVHT3SS_MCS2 = 0x42,
311 DESC_RATEVHT3SS_MCS3 = 0x43,
312 DESC_RATEVHT3SS_MCS4 = 0x44,
313 DESC_RATEVHT3SS_MCS5 = 0x45,
314 DESC_RATEVHT3SS_MCS6 = 0x46,
315 DESC_RATEVHT3SS_MCS7 = 0x47,
316 DESC_RATEVHT3SS_MCS8 = 0x48,
317 DESC_RATEVHT3SS_MCS9 = 0x49,
318
319 DESC_RATEVHT4SS_MCS0 = 0x4a,
320 DESC_RATEVHT4SS_MCS1 = 0x4b,
321 DESC_RATEVHT4SS_MCS2 = 0x4c,
322 DESC_RATEVHT4SS_MCS3 = 0x4d,
323 DESC_RATEVHT4SS_MCS4 = 0x4e,
324 DESC_RATEVHT4SS_MCS5 = 0x4f,
325 DESC_RATEVHT4SS_MCS6 = 0x50,
326 DESC_RATEVHT4SS_MCS7 = 0x51,
327 DESC_RATEVHT4SS_MCS8 = 0x52,
328 DESC_RATEVHT4SS_MCS9 = 0x53,
329
330 DESC_RATE_MAX,
331 };
332
333 enum rtw_regulatory_domains {
334 RTW_REGD_FCC = 0,
335 RTW_REGD_MKK = 1,
336 RTW_REGD_ETSI = 2,
337 RTW_REGD_IC = 3,
338 RTW_REGD_KCC = 4,
339 RTW_REGD_ACMA = 5,
340 RTW_REGD_CHILE = 6,
341 RTW_REGD_UKRAINE = 7,
342 RTW_REGD_MEXICO = 8,
343 RTW_REGD_CN = 9,
344 RTW_REGD_WW,
345
346 RTW_REGD_MAX
347 };
348
349 enum rtw_txq_flags {
350 RTW_TXQ_AMPDU,
351 RTW_TXQ_BLOCK_BA,
352 };
353
354 enum rtw_flags {
355 RTW_FLAG_RUNNING,
356 RTW_FLAG_FW_RUNNING,
357 RTW_FLAG_SCANNING,
358 RTW_FLAG_INACTIVE_PS,
359 RTW_FLAG_LEISURE_PS,
360 RTW_FLAG_LEISURE_PS_DEEP,
361 RTW_FLAG_DIG_DISABLE,
362 RTW_FLAG_BUSY_TRAFFIC,
363 RTW_FLAG_WOWLAN,
364 RTW_FLAG_RESTARTING,
365
366 NUM_OF_RTW_FLAGS,
367 };
368
369 enum rtw_evm {
370 RTW_EVM_OFDM = 0,
371 RTW_EVM_1SS,
372 RTW_EVM_2SS_A,
373 RTW_EVM_2SS_B,
374 /* keep it last */
375 RTW_EVM_NUM
376 };
377
378 enum rtw_snr {
379 RTW_SNR_OFDM_A = 0,
380 RTW_SNR_OFDM_B,
381 RTW_SNR_OFDM_C,
382 RTW_SNR_OFDM_D,
383 RTW_SNR_1SS_A,
384 RTW_SNR_1SS_B,
385 RTW_SNR_1SS_C,
386 RTW_SNR_1SS_D,
387 RTW_SNR_2SS_A,
388 RTW_SNR_2SS_B,
389 RTW_SNR_2SS_C,
390 RTW_SNR_2SS_D,
391 /* keep it last */
392 RTW_SNR_NUM
393 };
394
395 enum rtw_wow_flags {
396 RTW_WOW_FLAG_EN_MAGIC_PKT,
397 RTW_WOW_FLAG_EN_REKEY_PKT,
398 RTW_WOW_FLAG_EN_DISCONNECT,
399
400 /* keep it last */
401 RTW_WOW_FLAG_MAX,
402 };
403
404 /* the power index is represented by differences, which cck-1s & ht40-1s are
405 * the base values, so for 1s's differences, there are only ht20 & ofdm
406 */
407 struct rtw_2g_1s_pwr_idx_diff {
408 #ifdef __LITTLE_ENDIAN
409 s8 ofdm:4;
410 s8 bw20:4;
411 #else
412 s8 bw20:4;
413 s8 ofdm:4;
414 #endif
415 } __packed;
416
417 struct rtw_2g_ns_pwr_idx_diff {
418 #ifdef __LITTLE_ENDIAN
419 s8 bw20:4;
420 s8 bw40:4;
421 s8 cck:4;
422 s8 ofdm:4;
423 #else
424 s8 ofdm:4;
425 s8 cck:4;
426 s8 bw40:4;
427 s8 bw20:4;
428 #endif
429 } __packed;
430
431 struct rtw_2g_txpwr_idx {
432 u8 cck_base[6];
433 u8 bw40_base[5];
434 struct rtw_2g_1s_pwr_idx_diff ht_1s_diff;
435 struct rtw_2g_ns_pwr_idx_diff ht_2s_diff;
436 struct rtw_2g_ns_pwr_idx_diff ht_3s_diff;
437 struct rtw_2g_ns_pwr_idx_diff ht_4s_diff;
438 };
439
440 struct rtw_5g_ht_1s_pwr_idx_diff {
441 #ifdef __LITTLE_ENDIAN
442 s8 ofdm:4;
443 s8 bw20:4;
444 #else
445 s8 bw20:4;
446 s8 ofdm:4;
447 #endif
448 } __packed;
449
450 struct rtw_5g_ht_ns_pwr_idx_diff {
451 #ifdef __LITTLE_ENDIAN
452 s8 bw20:4;
453 s8 bw40:4;
454 #else
455 s8 bw40:4;
456 s8 bw20:4;
457 #endif
458 } __packed;
459
460 struct rtw_5g_ofdm_ns_pwr_idx_diff {
461 #ifdef __LITTLE_ENDIAN
462 s8 ofdm_3s:4;
463 s8 ofdm_2s:4;
464 s8 ofdm_4s:4;
465 s8 res:4;
466 #else
467 s8 res:4;
468 s8 ofdm_4s:4;
469 s8 ofdm_2s:4;
470 s8 ofdm_3s:4;
471 #endif
472 } __packed;
473
474 struct rtw_5g_vht_ns_pwr_idx_diff {
475 #ifdef __LITTLE_ENDIAN
476 s8 bw160:4;
477 s8 bw80:4;
478 #else
479 s8 bw80:4;
480 s8 bw160:4;
481 #endif
482 } __packed;
483
484 struct rtw_5g_txpwr_idx {
485 u8 bw40_base[14];
486 struct rtw_5g_ht_1s_pwr_idx_diff ht_1s_diff;
487 struct rtw_5g_ht_ns_pwr_idx_diff ht_2s_diff;
488 struct rtw_5g_ht_ns_pwr_idx_diff ht_3s_diff;
489 struct rtw_5g_ht_ns_pwr_idx_diff ht_4s_diff;
490 struct rtw_5g_ofdm_ns_pwr_idx_diff ofdm_diff;
491 struct rtw_5g_vht_ns_pwr_idx_diff vht_1s_diff;
492 struct rtw_5g_vht_ns_pwr_idx_diff vht_2s_diff;
493 struct rtw_5g_vht_ns_pwr_idx_diff vht_3s_diff;
494 struct rtw_5g_vht_ns_pwr_idx_diff vht_4s_diff;
495 };
496
497 struct rtw_txpwr_idx {
498 struct rtw_2g_txpwr_idx pwr_idx_2g;
499 struct rtw_5g_txpwr_idx pwr_idx_5g;
500 };
501
502 struct rtw_timer_list {
503 struct timer_list timer;
504 void (*function)(void *data);
505 void *args;
506 };
507
508 struct rtw_channel_params {
509 u8 center_chan;
510 u8 bandwidth;
511 u8 primary_chan_idx;
512 /* center channel by different available bandwidth,
513 * val of (bw > current bandwidth) is invalid
514 */
515 u8 cch_by_bw[RTW_MAX_CHANNEL_WIDTH + 1];
516 };
517
518 struct rtw_hw_reg {
519 u32 addr;
520 u32 mask;
521 };
522
523 struct rtw_ltecoex_addr {
524 u32 ctrl;
525 u32 wdata;
526 u32 rdata;
527 };
528
529 struct rtw_reg_domain {
530 u32 addr;
531 u32 mask;
532 #define RTW_REG_DOMAIN_MAC32 0
533 #define RTW_REG_DOMAIN_MAC16 1
534 #define RTW_REG_DOMAIN_MAC8 2
535 #define RTW_REG_DOMAIN_RF_A 3
536 #define RTW_REG_DOMAIN_RF_B 4
537 #define RTW_REG_DOMAIN_NL 0xFF
538 u8 domain;
539 };
540
541 struct rtw_rf_sipi_addr {
542 u32 hssi_1;
543 u32 hssi_2;
544 u32 lssi_read;
545 u32 lssi_read_pi;
546 };
547
548 struct rtw_backup_info {
549 u8 len;
550 u32 reg;
551 u32 val;
552 };
553
554 enum rtw_vif_port_set {
555 PORT_SET_MAC_ADDR = BIT(0),
556 PORT_SET_BSSID = BIT(1),
557 PORT_SET_NET_TYPE = BIT(2),
558 PORT_SET_AID = BIT(3),
559 PORT_SET_BCN_CTRL = BIT(4),
560 };
561
562 struct rtw_vif_port {
563 struct rtw_hw_reg mac_addr;
564 struct rtw_hw_reg bssid;
565 struct rtw_hw_reg net_type;
566 struct rtw_hw_reg aid;
567 struct rtw_hw_reg bcn_ctrl;
568 };
569
570 struct rtw_tx_pkt_info {
571 u32 tx_pkt_size;
572 u8 offset;
573 u8 pkt_offset;
574 u8 mac_id;
575 u8 rate_id;
576 u8 rate;
577 u8 qsel;
578 u8 bw;
579 u8 sec_type;
580 u8 sn;
581 bool ampdu_en;
582 u8 ampdu_factor;
583 u8 ampdu_density;
584 u16 seq;
585 bool stbc;
586 bool ldpc;
587 bool dis_rate_fallback;
588 bool bmc;
589 bool use_rate;
590 bool ls;
591 bool fs;
592 bool short_gi;
593 bool report;
594 bool rts;
595 bool dis_qselseq;
596 bool en_hwseq;
597 u8 hw_ssn_sel;
598 bool nav_use_hdr;
599 bool bt_null;
600 };
601
602 struct rtw_rx_pkt_stat {
603 bool phy_status;
604 bool icv_err;
605 bool crc_err;
606 bool decrypted;
607 bool is_c2h;
608
609 s32 signal_power;
610 u16 pkt_len;
611 u8 bw;
612 u8 drv_info_sz;
613 u8 shift;
614 u8 rate;
615 u8 mac_id;
616 u8 cam_id;
617 u8 ppdu_cnt;
618 u32 tsf_low;
619 s8 rx_power[RTW_RF_PATH_MAX];
620 u8 rssi;
621 u8 rxsc;
622 s8 rx_snr[RTW_RF_PATH_MAX];
623 u8 rx_evm[RTW_RF_PATH_MAX];
624 s8 cfo_tail[RTW_RF_PATH_MAX];
625
626 struct rtw_sta_info *si;
627 struct ieee80211_vif *vif;
628 struct ieee80211_hdr *hdr;
629 };
630
631 DECLARE_EWMA(tp, 10, 2);
632
633 struct rtw_traffic_stats {
634 /* units in bytes */
635 u64 tx_unicast;
636 u64 rx_unicast;
637
638 /* count for packets */
639 u64 tx_cnt;
640 u64 rx_cnt;
641
642 /* units in Mbps */
643 u32 tx_throughput;
644 u32 rx_throughput;
645 struct ewma_tp tx_ewma_tp;
646 struct ewma_tp rx_ewma_tp;
647 };
648
649 enum rtw_lps_mode {
650 RTW_MODE_ACTIVE = 0,
651 RTW_MODE_LPS = 1,
652 RTW_MODE_WMM_PS = 2,
653 };
654
655 enum rtw_lps_deep_mode {
656 LPS_DEEP_MODE_NONE = 0,
657 LPS_DEEP_MODE_LCLK = 1,
658 LPS_DEEP_MODE_PG = 2,
659 };
660
661 enum rtw_pwr_state {
662 RTW_RF_OFF = 0x0,
663 RTW_RF_ON = 0x4,
664 RTW_ALL_ON = 0xc,
665 };
666
667 struct rtw_lps_conf {
668 enum rtw_lps_mode mode;
669 enum rtw_lps_deep_mode deep_mode;
670 enum rtw_lps_deep_mode wow_deep_mode;
671 enum rtw_pwr_state state;
672 u8 awake_interval;
673 u8 rlbm;
674 u8 smart_ps;
675 u8 port_id;
676 bool sec_cam_backup;
677 bool pattern_cam_backup;
678 };
679
680 enum rtw_hw_key_type {
681 RTW_CAM_NONE = 0,
682 RTW_CAM_WEP40 = 1,
683 RTW_CAM_TKIP = 2,
684 RTW_CAM_AES = 4,
685 RTW_CAM_WEP104 = 5,
686 };
687
688 struct rtw_cam_entry {
689 bool valid;
690 bool group;
691 u8 addr[ETH_ALEN];
692 u8 hw_key_type;
693 struct ieee80211_key_conf *key;
694 };
695
696 struct rtw_sec_desc {
697 /* search strategy */
698 bool default_key_search;
699
700 u32 total_cam_num;
701 struct rtw_cam_entry cam_table[RTW_MAX_SEC_CAM_NUM];
702 DECLARE_BITMAP(cam_map, RTW_MAX_SEC_CAM_NUM);
703 };
704
705 struct rtw_tx_report {
706 /* protect the tx report queue */
707 spinlock_t q_lock;
708 struct sk_buff_head queue;
709 atomic_t sn;
710 struct timer_list purge_timer;
711 };
712
713 struct rtw_ra_report {
714 struct rate_info txrate;
715 u32 bit_rate;
716 u8 desc_rate;
717 };
718
719 struct rtw_txq {
720 struct list_head list;
721
722 unsigned long flags;
723 unsigned long last_push;
724 };
725
726 #define RTW_BC_MC_MACID 1
727 DECLARE_EWMA(rssi, 10, 16);
728
729 struct rtw_sta_info {
730 struct ieee80211_sta *sta;
731 struct ieee80211_vif *vif;
732
733 struct ewma_rssi avg_rssi;
734 u8 rssi_level;
735
736 u8 mac_id;
737 u8 rate_id;
738 enum rtw_bandwidth bw_mode;
739 enum rtw_rf_type rf_type;
740 enum rtw_wireless_set wireless_set;
741 u8 stbc_en:2;
742 u8 ldpc_en:2;
743 bool sgi_enable;
744 bool vht_enable;
745 bool updated;
746 u8 init_ra_lv;
747 u64 ra_mask;
748
749 DECLARE_BITMAP(tid_ba, IEEE80211_NUM_TIDS);
750
751 struct rtw_ra_report ra_report;
752
753 bool use_cfg_mask;
754 struct cfg80211_bitrate_mask *mask;
755 };
756
757 enum rtw_bfee_role {
758 RTW_BFEE_NONE,
759 RTW_BFEE_SU,
760 RTW_BFEE_MU
761 };
762
763 struct rtw_bfee {
764 enum rtw_bfee_role role;
765
766 u16 p_aid;
767 u8 g_id;
768 u8 mac_addr[ETH_ALEN];
769 u8 sound_dim;
770
771 /* SU-MIMO */
772 u8 su_reg_index;
773
774 /* MU-MIMO */
775 u16 aid;
776 };
777
778 struct rtw_bf_info {
779 u8 bfer_mu_cnt;
780 u8 bfer_su_cnt;
781 DECLARE_BITMAP(bfer_su_reg_maping, 2);
782 u8 cur_csi_rpt_rate;
783 };
784
785 struct rtw_vif {
786 enum rtw_net_type net_type;
787 u16 aid;
788 u8 mac_addr[ETH_ALEN];
789 u8 bssid[ETH_ALEN];
790 u8 port;
791 u8 bcn_ctrl;
792 struct list_head rsvd_page_list;
793 struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS];
794 const struct rtw_vif_port *conf;
795
796 struct rtw_traffic_stats stats;
797
798 struct rtw_bfee bfee;
799 };
800
801 struct rtw_regulatory {
802 char alpha2[2];
803 u8 chplan;
804 u8 txpwr_regd;
805 };
806
807 struct rtw_chip_ops {
808 int (*mac_init)(struct rtw_dev *rtwdev);
809 void (*dump_fw_crash)(struct rtw_dev *rtwdev);
810 void (*shutdown)(struct rtw_dev *rtwdev);
811 int (*read_efuse)(struct rtw_dev *rtwdev, u8 *map);
812 void (*phy_set_param)(struct rtw_dev *rtwdev);
813 void (*set_channel)(struct rtw_dev *rtwdev, u8 channel,
814 u8 bandwidth, u8 primary_chan_idx);
815 void (*query_rx_desc)(struct rtw_dev *rtwdev, u8 *rx_desc,
816 struct rtw_rx_pkt_stat *pkt_stat,
817 struct ieee80211_rx_status *rx_status);
818 u32 (*read_rf)(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
819 u32 addr, u32 mask);
820 bool (*write_rf)(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
821 u32 addr, u32 mask, u32 data);
822 void (*set_tx_power_index)(struct rtw_dev *rtwdev);
823 int (*rsvd_page_dump)(struct rtw_dev *rtwdev, u8 *buf, u32 offset,
824 u32 size);
825 int (*set_antenna)(struct rtw_dev *rtwdev,
826 u32 antenna_tx,
827 u32 antenna_rx);
828 void (*cfg_ldo25)(struct rtw_dev *rtwdev, bool enable);
829 void (*efuse_grant)(struct rtw_dev *rtwdev, bool enable);
830 void (*false_alarm_statistics)(struct rtw_dev *rtwdev);
831 void (*phy_calibration)(struct rtw_dev *rtwdev);
832 void (*dpk_track)(struct rtw_dev *rtwdev);
833 void (*cck_pd_set)(struct rtw_dev *rtwdev, u8 level);
834 void (*pwr_track)(struct rtw_dev *rtwdev);
835 void (*config_bfee)(struct rtw_dev *rtwdev, struct rtw_vif *vif,
836 struct rtw_bfee *bfee, bool enable);
837 void (*set_gid_table)(struct rtw_dev *rtwdev,
838 struct ieee80211_vif *vif,
839 struct ieee80211_bss_conf *conf);
840 void (*cfg_csi_rate)(struct rtw_dev *rtwdev, u8 rssi, u8 cur_rate,
841 u8 fixrate_en, u8 *new_rate);
842 void (*cfo_init)(struct rtw_dev *rtwdev);
843 void (*cfo_track)(struct rtw_dev *rtwdev);
844
845 /* for coex */
846 void (*coex_set_init)(struct rtw_dev *rtwdev);
847 void (*coex_set_ant_switch)(struct rtw_dev *rtwdev,
848 u8 ctrl_type, u8 pos_type);
849 void (*coex_set_gnt_fix)(struct rtw_dev *rtwdev);
850 void (*coex_set_gnt_debug)(struct rtw_dev *rtwdev);
851 void (*coex_set_rfe_type)(struct rtw_dev *rtwdev);
852 void (*coex_set_wl_tx_power)(struct rtw_dev *rtwdev, u8 wl_pwr);
853 void (*coex_set_wl_rx_gain)(struct rtw_dev *rtwdev, bool low_gain);
854 };
855
856 #define RTW_PWR_POLLING_CNT 20000
857
858 #define RTW_PWR_CMD_READ 0x00
859 #define RTW_PWR_CMD_WRITE 0x01
860 #define RTW_PWR_CMD_POLLING 0x02
861 #define RTW_PWR_CMD_DELAY 0x03
862 #define RTW_PWR_CMD_END 0x04
863
864 /* define the base address of each block */
865 #define RTW_PWR_ADDR_MAC 0x00
866 #define RTW_PWR_ADDR_USB 0x01
867 #define RTW_PWR_ADDR_PCIE 0x02
868 #define RTW_PWR_ADDR_SDIO 0x03
869
870 #define RTW_PWR_INTF_SDIO_MSK BIT(0)
871 #define RTW_PWR_INTF_USB_MSK BIT(1)
872 #define RTW_PWR_INTF_PCI_MSK BIT(2)
873 #define RTW_PWR_INTF_ALL_MSK (BIT(0) | BIT(1) | BIT(2) | BIT(3))
874
875 #define RTW_PWR_CUT_TEST_MSK BIT(0)
876 #define RTW_PWR_CUT_A_MSK BIT(1)
877 #define RTW_PWR_CUT_B_MSK BIT(2)
878 #define RTW_PWR_CUT_C_MSK BIT(3)
879 #define RTW_PWR_CUT_D_MSK BIT(4)
880 #define RTW_PWR_CUT_E_MSK BIT(5)
881 #define RTW_PWR_CUT_F_MSK BIT(6)
882 #define RTW_PWR_CUT_G_MSK BIT(7)
883 #define RTW_PWR_CUT_ALL_MSK 0xFF
884
885 enum rtw_pwr_seq_cmd_delay_unit {
886 RTW_PWR_DELAY_US,
887 RTW_PWR_DELAY_MS,
888 };
889
890 struct rtw_pwr_seq_cmd {
891 u16 offset;
892 u8 cut_mask;
893 u8 intf_mask;
894 u8 base:4;
895 u8 cmd:4;
896 u8 mask;
897 u8 value;
898 };
899
900 enum rtw_chip_ver {
901 RTW_CHIP_VER_CUT_A = 0x00,
902 RTW_CHIP_VER_CUT_B = 0x01,
903 RTW_CHIP_VER_CUT_C = 0x02,
904 RTW_CHIP_VER_CUT_D = 0x03,
905 RTW_CHIP_VER_CUT_E = 0x04,
906 RTW_CHIP_VER_CUT_F = 0x05,
907 RTW_CHIP_VER_CUT_G = 0x06,
908 };
909
910 #define RTW_INTF_PHY_PLATFORM_ALL 0
911
912 enum rtw_intf_phy_cut {
913 RTW_INTF_PHY_CUT_A = BIT(0),
914 RTW_INTF_PHY_CUT_B = BIT(1),
915 RTW_INTF_PHY_CUT_C = BIT(2),
916 RTW_INTF_PHY_CUT_D = BIT(3),
917 RTW_INTF_PHY_CUT_E = BIT(4),
918 RTW_INTF_PHY_CUT_F = BIT(5),
919 RTW_INTF_PHY_CUT_G = BIT(6),
920 RTW_INTF_PHY_CUT_ALL = 0xFFFF,
921 };
922
923 enum rtw_ip_sel {
924 RTW_IP_SEL_PHY = 0,
925 RTW_IP_SEL_MAC = 1,
926 RTW_IP_SEL_DBI = 2,
927
928 RTW_IP_SEL_UNDEF = 0xFFFF
929 };
930
931 enum rtw_pq_map_id {
932 RTW_PQ_MAP_VO = 0x0,
933 RTW_PQ_MAP_VI = 0x1,
934 RTW_PQ_MAP_BE = 0x2,
935 RTW_PQ_MAP_BK = 0x3,
936 RTW_PQ_MAP_MG = 0x4,
937 RTW_PQ_MAP_HI = 0x5,
938 RTW_PQ_MAP_NUM = 0x6,
939
940 RTW_PQ_MAP_UNDEF,
941 };
942
943 enum rtw_dma_mapping {
944 RTW_DMA_MAPPING_EXTRA = 0,
945 RTW_DMA_MAPPING_LOW = 1,
946 RTW_DMA_MAPPING_NORMAL = 2,
947 RTW_DMA_MAPPING_HIGH = 3,
948
949 RTW_DMA_MAPPING_MAX,
950 RTW_DMA_MAPPING_UNDEF,
951 };
952
953 struct rtw_rqpn {
954 enum rtw_dma_mapping dma_map_vo;
955 enum rtw_dma_mapping dma_map_vi;
956 enum rtw_dma_mapping dma_map_be;
957 enum rtw_dma_mapping dma_map_bk;
958 enum rtw_dma_mapping dma_map_mg;
959 enum rtw_dma_mapping dma_map_hi;
960 };
961
962 struct rtw_prioq_addr {
963 u32 rsvd;
964 u32 avail;
965 };
966
967 struct rtw_prioq_addrs {
968 struct rtw_prioq_addr prio[RTW_DMA_MAPPING_MAX];
969 bool wsize;
970 };
971
972 struct rtw_page_table {
973 u16 hq_num;
974 u16 nq_num;
975 u16 lq_num;
976 u16 exq_num;
977 u16 gapq_num;
978 };
979
980 struct rtw_intf_phy_para {
981 u16 offset;
982 u16 value;
983 u16 ip_sel;
984 u16 cut_mask;
985 u16 platform;
986 };
987
988 struct rtw_wow_pattern {
989 u16 crc;
990 u8 type;
991 u8 valid;
992 u8 mask[RTW_MAX_PATTERN_MASK_SIZE];
993 };
994
995 struct rtw_pno_request {
996 bool inited;
997 u32 match_set_cnt;
998 struct cfg80211_match_set *match_sets;
999 u8 channel_cnt;
1000 struct ieee80211_channel *channels;
1001 struct cfg80211_sched_scan_plan scan_plan;
1002 };
1003
1004 struct rtw_wow_param {
1005 struct ieee80211_vif *wow_vif;
1006 DECLARE_BITMAP(flags, RTW_WOW_FLAG_MAX);
1007 u8 txpause;
1008 u8 pattern_cnt;
1009 struct rtw_wow_pattern patterns[RTW_MAX_PATTERN_NUM];
1010
1011 bool ips_enabled;
1012 struct rtw_pno_request pno_req;
1013 };
1014
1015 struct rtw_intf_phy_para_table {
1016 const struct rtw_intf_phy_para *usb2_para;
1017 const struct rtw_intf_phy_para *usb3_para;
1018 const struct rtw_intf_phy_para *gen1_para;
1019 const struct rtw_intf_phy_para *gen2_para;
1020 u8 n_usb2_para;
1021 u8 n_usb3_para;
1022 u8 n_gen1_para;
1023 u8 n_gen2_para;
1024 };
1025
1026 struct rtw_table {
1027 const void *data;
1028 const u32 size;
1029 void (*parse)(struct rtw_dev *rtwdev, const struct rtw_table *tbl);
1030 void (*do_cfg)(struct rtw_dev *rtwdev, const struct rtw_table *tbl,
1031 u32 addr, u32 data);
1032 enum rtw_rf_path rf_path;
1033 };
1034
rtw_load_table(struct rtw_dev * rtwdev,const struct rtw_table * tbl)1035 static inline void rtw_load_table(struct rtw_dev *rtwdev,
1036 const struct rtw_table *tbl)
1037 {
1038 (*tbl->parse)(rtwdev, tbl);
1039 }
1040
1041 enum rtw_rfe_fem {
1042 RTW_RFE_IFEM,
1043 RTW_RFE_EFEM,
1044 RTW_RFE_IFEM2G_EFEM5G,
1045 RTW_RFE_NUM,
1046 };
1047
1048 struct rtw_rfe_def {
1049 const struct rtw_table *phy_pg_tbl;
1050 const struct rtw_table *txpwr_lmt_tbl;
1051 const struct rtw_table *agc_btg_tbl;
1052 };
1053
1054 #define RTW_DEF_RFE(chip, bb_pg, pwrlmt) { \
1055 .phy_pg_tbl = &rtw ## chip ## _bb_pg_type ## bb_pg ## _tbl, \
1056 .txpwr_lmt_tbl = &rtw ## chip ## _txpwr_lmt_type ## pwrlmt ## _tbl, \
1057 }
1058
1059 #define RTW_DEF_RFE_EXT(chip, bb_pg, pwrlmt, btg) { \
1060 .phy_pg_tbl = &rtw ## chip ## _bb_pg_type ## bb_pg ## _tbl, \
1061 .txpwr_lmt_tbl = &rtw ## chip ## _txpwr_lmt_type ## pwrlmt ## _tbl, \
1062 .agc_btg_tbl = &rtw ## chip ## _agc_btg_type ## btg ## _tbl, \
1063 }
1064
1065 #define RTW_PWR_TRK_5G_1 0
1066 #define RTW_PWR_TRK_5G_2 1
1067 #define RTW_PWR_TRK_5G_3 2
1068 #define RTW_PWR_TRK_5G_NUM 3
1069
1070 #define RTW_PWR_TRK_TBL_SZ 30
1071
1072 /* This table stores the values of TX power that will be adjusted by power
1073 * tracking.
1074 *
1075 * For 5G bands, there are 3 different settings.
1076 * For 2G there are cck rate and ofdm rate with different settings.
1077 */
1078 struct rtw_pwr_track_tbl {
1079 const u8 *pwrtrk_5gb_n[RTW_PWR_TRK_5G_NUM];
1080 const u8 *pwrtrk_5gb_p[RTW_PWR_TRK_5G_NUM];
1081 const u8 *pwrtrk_5ga_n[RTW_PWR_TRK_5G_NUM];
1082 const u8 *pwrtrk_5ga_p[RTW_PWR_TRK_5G_NUM];
1083 const u8 *pwrtrk_2gb_n;
1084 const u8 *pwrtrk_2gb_p;
1085 const u8 *pwrtrk_2ga_n;
1086 const u8 *pwrtrk_2ga_p;
1087 const u8 *pwrtrk_2g_cckb_n;
1088 const u8 *pwrtrk_2g_cckb_p;
1089 const u8 *pwrtrk_2g_ccka_n;
1090 const u8 *pwrtrk_2g_ccka_p;
1091 const s8 *pwrtrk_xtal_n;
1092 const s8 *pwrtrk_xtal_p;
1093 };
1094
1095 enum rtw_wlan_cpu {
1096 RTW_WCPU_11AC,
1097 RTW_WCPU_11N,
1098 };
1099
1100 enum rtw_fw_fifo_sel {
1101 RTW_FW_FIFO_SEL_TX,
1102 RTW_FW_FIFO_SEL_RX,
1103 RTW_FW_FIFO_SEL_RSVD_PAGE,
1104 RTW_FW_FIFO_SEL_REPORT,
1105 RTW_FW_FIFO_SEL_LLT,
1106 RTW_FW_FIFO_SEL_RXBUF_FW,
1107
1108 RTW_FW_FIFO_MAX,
1109 };
1110
1111 /* hardware configuration for each IC */
1112 struct rtw_chip_info {
1113 struct rtw_chip_ops *ops;
1114 u8 id;
1115
1116 const char *fw_name;
1117 enum rtw_wlan_cpu wlan_cpu;
1118 u8 tx_pkt_desc_sz;
1119 u8 tx_buf_desc_sz;
1120 u8 rx_pkt_desc_sz;
1121 u8 rx_buf_desc_sz;
1122 u32 phy_efuse_size;
1123 u32 log_efuse_size;
1124 u32 ptct_efuse_size;
1125 u32 txff_size;
1126 u32 rxff_size;
1127 u32 fw_rxff_size;
1128 u8 band;
1129 u8 page_size;
1130 u8 csi_buf_pg_num;
1131 u8 dig_max;
1132 u8 dig_min;
1133 u8 txgi_factor;
1134 bool is_pwr_by_rate_dec;
1135 bool rx_ldpc;
1136 u8 max_power_index;
1137
1138 u16 fw_fifo_addr[RTW_FW_FIFO_MAX];
1139
1140 bool ht_supported;
1141 bool vht_supported;
1142 u8 lps_deep_mode_supported;
1143
1144 /* init values */
1145 u8 sys_func_en;
1146 const struct rtw_pwr_seq_cmd **pwr_on_seq;
1147 const struct rtw_pwr_seq_cmd **pwr_off_seq;
1148 const struct rtw_rqpn *rqpn_table;
1149 const struct rtw_prioq_addrs *prioq_addrs;
1150 const struct rtw_page_table *page_table;
1151 const struct rtw_intf_phy_para_table *intf_table;
1152
1153 const struct rtw_hw_reg *dig;
1154 const struct rtw_hw_reg *dig_cck;
1155 u32 rf_base_addr[2];
1156 u32 rf_sipi_addr[2];
1157 const struct rtw_rf_sipi_addr *rf_sipi_read_addr;
1158 u8 fix_rf_phy_num;
1159 const struct rtw_ltecoex_addr *ltecoex_addr;
1160
1161 const struct rtw_table *mac_tbl;
1162 const struct rtw_table *agc_tbl;
1163 const struct rtw_table *bb_tbl;
1164 const struct rtw_table *rf_tbl[RTW_RF_PATH_MAX];
1165 const struct rtw_table *rfk_init_tbl;
1166
1167 const struct rtw_rfe_def *rfe_defs;
1168 u32 rfe_defs_size;
1169
1170 bool en_dis_dpd;
1171 u16 dpd_ratemask;
1172 u8 iqk_threshold;
1173 u8 lck_threshold;
1174 const struct rtw_pwr_track_tbl *pwr_track_tbl;
1175
1176 u8 bfer_su_max_num;
1177 u8 bfer_mu_max_num;
1178
1179 const char *wow_fw_name;
1180 const struct wiphy_wowlan_support *wowlan_stub;
1181 const u8 max_sched_scan_ssids;
1182
1183 /* for 8821c set channel */
1184 u32 ch_param[3];
1185
1186 /* coex paras */
1187 u32 coex_para_ver;
1188 u8 bt_desired_ver;
1189 bool scbd_support;
1190 bool new_scbd10_def; /* true: fix 2M(8822c) */
1191 bool ble_hid_profile_support;
1192 u8 pstdma_type; /* 0: LPSoff, 1:LPSon */
1193 u8 bt_rssi_type;
1194 u8 ant_isolation;
1195 u8 rssi_tolerance;
1196 u8 table_sant_num;
1197 u8 table_nsant_num;
1198 u8 tdma_sant_num;
1199 u8 tdma_nsant_num;
1200 u8 bt_afh_span_bw20;
1201 u8 bt_afh_span_bw40;
1202 u8 afh_5g_num;
1203 u8 wl_rf_para_num;
1204 u8 coex_info_hw_regs_num;
1205 const u8 *bt_rssi_step;
1206 const u8 *wl_rssi_step;
1207 const struct coex_table_para *table_nsant;
1208 const struct coex_table_para *table_sant;
1209 const struct coex_tdma_para *tdma_sant;
1210 const struct coex_tdma_para *tdma_nsant;
1211 const struct coex_rf_para *wl_rf_para_tx;
1212 const struct coex_rf_para *wl_rf_para_rx;
1213 const struct coex_5g_afh_map *afh_5g;
1214 const struct rtw_hw_reg *btg_reg;
1215 const struct rtw_reg_domain *coex_info_hw_regs;
1216 u32 wl_fw_desired_ver;
1217 };
1218
1219 enum rtw_coex_bt_state_cnt {
1220 COEX_CNT_BT_RETRY,
1221 COEX_CNT_BT_REINIT,
1222 COEX_CNT_BT_REENABLE,
1223 COEX_CNT_BT_POPEVENT,
1224 COEX_CNT_BT_SETUPLINK,
1225 COEX_CNT_BT_IGNWLANACT,
1226 COEX_CNT_BT_INQ,
1227 COEX_CNT_BT_PAGE,
1228 COEX_CNT_BT_ROLESWITCH,
1229 COEX_CNT_BT_AFHUPDATE,
1230 COEX_CNT_BT_INFOUPDATE,
1231 COEX_CNT_BT_IQK,
1232 COEX_CNT_BT_IQKFAIL,
1233
1234 COEX_CNT_BT_MAX
1235 };
1236
1237 enum rtw_coex_wl_state_cnt {
1238 COEX_CNT_WL_SCANAP,
1239 COEX_CNT_WL_CONNPKT,
1240 COEX_CNT_WL_COEXRUN,
1241 COEX_CNT_WL_NOISY0,
1242 COEX_CNT_WL_NOISY1,
1243 COEX_CNT_WL_NOISY2,
1244 COEX_CNT_WL_5MS_NOEXTEND,
1245 COEX_CNT_WL_FW_NOTIFY,
1246
1247 COEX_CNT_WL_MAX
1248 };
1249
1250 struct rtw_coex_rfe {
1251 bool ant_switch_exist;
1252 bool ant_switch_diversity;
1253 bool ant_switch_with_bt;
1254 u8 rfe_module_type;
1255 u8 ant_switch_polarity;
1256
1257 /* true if WLG at BTG, else at WLAG */
1258 bool wlg_at_btg;
1259 };
1260
1261 #define COEX_WL_TDMA_PARA_LENGTH 5
1262
1263 struct rtw_coex_dm {
1264 bool cur_ps_tdma_on;
1265 bool cur_wl_rx_low_gain_en;
1266 bool ignore_wl_act;
1267
1268 u8 reason;
1269 u8 bt_rssi_state[4];
1270 u8 wl_rssi_state[4];
1271 u8 wl_ch_info[3];
1272 u8 cur_ps_tdma;
1273 u8 cur_table;
1274 u8 ps_tdma_para[5];
1275 u8 cur_bt_pwr_lvl;
1276 u8 cur_bt_lna_lvl;
1277 u8 cur_wl_pwr_lvl;
1278 u8 bt_status;
1279 u32 cur_ant_pos_type;
1280 u32 cur_switch_status;
1281 u32 setting_tdma;
1282 u8 fw_tdma_para[COEX_WL_TDMA_PARA_LENGTH];
1283 };
1284
1285 #define COEX_BTINFO_SRC_WL_FW 0x0
1286 #define COEX_BTINFO_SRC_BT_RSP 0x1
1287 #define COEX_BTINFO_SRC_BT_ACT 0x2
1288 #define COEX_BTINFO_SRC_BT_IQK 0x3
1289 #define COEX_BTINFO_SRC_BT_SCBD 0x4
1290 #define COEX_BTINFO_SRC_H2C60 0x5
1291 #define COEX_BTINFO_SRC_MAX 0x6
1292
1293 #define COEX_INFO_FTP BIT(7)
1294 #define COEX_INFO_A2DP BIT(6)
1295 #define COEX_INFO_HID BIT(5)
1296 #define COEX_INFO_SCO_BUSY BIT(4)
1297 #define COEX_INFO_ACL_BUSY BIT(3)
1298 #define COEX_INFO_INQ_PAGE BIT(2)
1299 #define COEX_INFO_SCO_ESCO BIT(1)
1300 #define COEX_INFO_CONNECTION BIT(0)
1301 #define COEX_BTINFO_LENGTH_MAX 10
1302 #define COEX_BTINFO_LENGTH 7
1303
1304 struct rtw_coex_stat {
1305 bool bt_disabled;
1306 bool bt_disabled_pre;
1307 bool bt_link_exist;
1308 bool bt_whck_test;
1309 bool bt_inq_page;
1310 bool bt_inq_remain;
1311 bool bt_inq;
1312 bool bt_page;
1313 bool bt_ble_voice;
1314 bool bt_ble_exist;
1315 bool bt_hfp_exist;
1316 bool bt_a2dp_exist;
1317 bool bt_hid_exist;
1318 bool bt_pan_exist; /* PAN or OPP */
1319 bool bt_opp_exist; /* OPP only */
1320 bool bt_acl_busy;
1321 bool bt_fix_2M;
1322 bool bt_setup_link;
1323 bool bt_multi_link;
1324 bool bt_multi_link_pre;
1325 bool bt_multi_link_remain;
1326 bool bt_a2dp_sink;
1327 bool bt_a2dp_active;
1328 bool bt_reenable;
1329 bool bt_ble_scan_en;
1330 bool bt_init_scan;
1331 bool bt_slave;
1332 bool bt_418_hid_exist;
1333 bool bt_ble_hid_exist;
1334 bool bt_mailbox_reply;
1335
1336 bool wl_under_lps;
1337 bool wl_under_ips;
1338 bool wl_hi_pri_task1;
1339 bool wl_hi_pri_task2;
1340 bool wl_force_lps_ctrl;
1341 bool wl_gl_busy;
1342 bool wl_linkscan_proc;
1343 bool wl_ps_state_fail;
1344 bool wl_tx_limit_en;
1345 bool wl_ampdu_limit_en;
1346 bool wl_connected;
1347 bool wl_slot_extend;
1348 bool wl_cck_lock;
1349 bool wl_cck_lock_pre;
1350 bool wl_cck_lock_ever;
1351 bool wl_connecting;
1352 bool wl_slot_toggle;
1353 bool wl_slot_toggle_change; /* if toggle to no-toggle */
1354
1355 u32 bt_supported_version;
1356 u32 bt_supported_feature;
1357 u32 hi_pri_tx;
1358 u32 hi_pri_rx;
1359 u32 lo_pri_tx;
1360 u32 lo_pri_rx;
1361 u32 patch_ver;
1362 u16 bt_reg_vendor_ae;
1363 u16 bt_reg_vendor_ac;
1364 s8 bt_rssi;
1365 u8 kt_ver;
1366 u8 gnt_workaround_state;
1367 u8 tdma_timer_base;
1368 u8 bt_profile_num;
1369 u8 bt_info_c2h[COEX_BTINFO_SRC_MAX][COEX_BTINFO_LENGTH_MAX];
1370 u8 bt_info_lb2;
1371 u8 bt_info_lb3;
1372 u8 bt_info_hb0;
1373 u8 bt_info_hb1;
1374 u8 bt_info_hb2;
1375 u8 bt_info_hb3;
1376 u8 bt_ble_scan_type;
1377 u8 bt_hid_pair_num;
1378 u8 bt_hid_slot;
1379 u8 bt_a2dp_bitpool;
1380 u8 bt_iqk_state;
1381
1382 u16 wl_beacon_interval;
1383 u8 wl_noisy_level;
1384 u8 wl_fw_dbg_info[10];
1385 u8 wl_fw_dbg_info_pre[10];
1386 u8 wl_rx_rate;
1387 u8 wl_tx_rate;
1388 u8 wl_rts_rx_rate;
1389 u8 wl_coex_mode;
1390 u8 wl_iot_peer;
1391 u8 ampdu_max_time;
1392 u8 wl_tput_dir;
1393
1394 u8 wl_toggle_para[6];
1395 u8 wl_toggle_interval;
1396
1397 u16 score_board;
1398 u16 retry_limit;
1399
1400 /* counters to record bt states */
1401 u32 cnt_bt[COEX_CNT_BT_MAX];
1402
1403 /* counters to record wifi states */
1404 u32 cnt_wl[COEX_CNT_WL_MAX];
1405
1406 /* counters to record bt c2h data */
1407 u32 cnt_bt_info_c2h[COEX_BTINFO_SRC_MAX];
1408
1409 u32 darfrc;
1410 u32 darfrch;
1411 };
1412
1413 struct rtw_coex {
1414 /* protects coex info request section */
1415 struct mutex mutex;
1416 struct sk_buff_head queue;
1417 wait_queue_head_t wait;
1418
1419 bool under_5g;
1420 bool stop_dm;
1421 bool freeze;
1422 bool freerun;
1423 bool wl_rf_off;
1424 bool manual_control;
1425
1426 struct rtw_coex_stat stat;
1427 struct rtw_coex_dm dm;
1428 struct rtw_coex_rfe rfe;
1429
1430 struct delayed_work bt_relink_work;
1431 struct delayed_work bt_reenable_work;
1432 struct delayed_work defreeze_work;
1433 struct delayed_work wl_remain_work;
1434 struct delayed_work bt_remain_work;
1435 struct delayed_work wl_connecting_work;
1436 struct delayed_work bt_multi_link_remain_work;
1437 struct delayed_work wl_ccklock_work;
1438
1439 };
1440
1441 #define DPK_RF_REG_NUM 7
1442 #define DPK_RF_PATH_NUM 2
1443 #define DPK_BB_REG_NUM 18
1444 #define DPK_CHANNEL_WIDTH_80 1
1445
1446 DECLARE_EWMA(thermal, 10, 4);
1447
1448 struct rtw_dpk_info {
1449 bool is_dpk_pwr_on;
1450 bool is_reload;
1451
1452 DECLARE_BITMAP(dpk_path_ok, DPK_RF_PATH_NUM);
1453
1454 u8 thermal_dpk[DPK_RF_PATH_NUM];
1455 struct ewma_thermal avg_thermal[DPK_RF_PATH_NUM];
1456
1457 u32 gnt_control;
1458 u32 gnt_value;
1459
1460 u8 result[RTW_RF_PATH_MAX];
1461 u8 dpk_txagc[RTW_RF_PATH_MAX];
1462 u32 coef[RTW_RF_PATH_MAX][20];
1463 u16 dpk_gs[RTW_RF_PATH_MAX];
1464 u8 thermal_dpk_delta[RTW_RF_PATH_MAX];
1465 u8 pre_pwsf[RTW_RF_PATH_MAX];
1466
1467 u8 dpk_band;
1468 u8 dpk_ch;
1469 u8 dpk_bw;
1470 };
1471
1472 struct rtw_phy_cck_pd_reg {
1473 u32 reg_pd;
1474 u32 mask_pd;
1475 u32 reg_cs;
1476 u32 mask_cs;
1477 };
1478
1479 #define DACK_MSBK_BACKUP_NUM 0xf
1480 #define DACK_DCK_BACKUP_NUM 0x2
1481
1482 struct rtw_swing_table {
1483 const u8 *p[RTW_RF_PATH_MAX];
1484 const u8 *n[RTW_RF_PATH_MAX];
1485 };
1486
1487 struct rtw_pkt_count {
1488 u16 num_bcn_pkt;
1489 u16 num_qry_pkt[DESC_RATE_MAX];
1490 };
1491
1492 DECLARE_EWMA(evm, 10, 4);
1493 DECLARE_EWMA(snr, 10, 4);
1494
1495 struct rtw_iqk_info {
1496 bool done;
1497 struct {
1498 u32 s1_x;
1499 u32 s1_y;
1500 u32 s0_x;
1501 u32 s0_y;
1502 } result;
1503 };
1504
1505 enum rtw_rf_band {
1506 RF_BAND_2G_CCK,
1507 RF_BAND_2G_OFDM,
1508 RF_BAND_5G_L,
1509 RF_BAND_5G_M,
1510 RF_BAND_5G_H,
1511 RF_BAND_MAX
1512 };
1513
1514 #define RF_GAIN_NUM 11
1515 #define RF_HW_OFFSET_NUM 10
1516
1517 struct rtw_gapk_info {
1518 u32 rf3f_bp[RF_BAND_MAX][RF_GAIN_NUM][RTW_RF_PATH_MAX];
1519 u32 rf3f_fs[RTW_RF_PATH_MAX][RF_GAIN_NUM];
1520 bool txgapk_bp_done;
1521 s8 offset[RF_GAIN_NUM][RTW_RF_PATH_MAX];
1522 s8 fianl_offset[RF_GAIN_NUM][RTW_RF_PATH_MAX];
1523 u8 read_txgain;
1524 u8 channel;
1525 };
1526
1527 struct rtw_cfo_track {
1528 bool is_adjust;
1529 u8 crystal_cap;
1530 s32 cfo_tail[RTW_RF_PATH_MAX];
1531 s32 cfo_cnt[RTW_RF_PATH_MAX];
1532 u32 packet_count;
1533 u32 packet_count_pre;
1534 };
1535
1536 #define RRSR_INIT_2G 0x15f
1537 #define RRSR_INIT_5G 0x150
1538
1539 enum rtw_dm_cap {
1540 RTW_DM_CAP_NA,
1541 RTW_DM_CAP_TXGAPK,
1542 RTW_DM_CAP_NUM
1543 };
1544
1545 struct rtw_dm_info {
1546 u32 cck_fa_cnt;
1547 u32 ofdm_fa_cnt;
1548 u32 total_fa_cnt;
1549 u32 cck_cca_cnt;
1550 u32 ofdm_cca_cnt;
1551 u32 total_cca_cnt;
1552
1553 u32 cck_ok_cnt;
1554 u32 cck_err_cnt;
1555 u32 ofdm_ok_cnt;
1556 u32 ofdm_err_cnt;
1557 u32 ht_ok_cnt;
1558 u32 ht_err_cnt;
1559 u32 vht_ok_cnt;
1560 u32 vht_err_cnt;
1561
1562 u8 min_rssi;
1563 u8 pre_min_rssi;
1564 u16 fa_history[4];
1565 u8 igi_history[4];
1566 u8 igi_bitmap;
1567 bool damping;
1568 u8 damping_cnt;
1569 u8 damping_rssi;
1570
1571 u8 cck_gi_u_bnd;
1572 u8 cck_gi_l_bnd;
1573
1574 u8 tx_rate;
1575 u32 rrsr_val_init;
1576 u32 rrsr_mask_min;
1577 u8 thermal_avg[RTW_RF_PATH_MAX];
1578 u8 thermal_meter_k;
1579 u8 thermal_meter_lck;
1580 s8 delta_power_index[RTW_RF_PATH_MAX];
1581 s8 delta_power_index_last[RTW_RF_PATH_MAX];
1582 u8 default_ofdm_index;
1583 bool pwr_trk_triggered;
1584 bool pwr_trk_init_trigger;
1585 struct ewma_thermal avg_thermal[RTW_RF_PATH_MAX];
1586 s8 txagc_remnant_cck;
1587 s8 txagc_remnant_ofdm;
1588
1589 /* backup dack results for each path and I/Q */
1590 u32 dack_adck[RTW_RF_PATH_MAX];
1591 u16 dack_msbk[RTW_RF_PATH_MAX][2][DACK_MSBK_BACKUP_NUM];
1592 u8 dack_dck[RTW_RF_PATH_MAX][2][DACK_DCK_BACKUP_NUM];
1593
1594 struct rtw_dpk_info dpk_info;
1595 struct rtw_cfo_track cfo_track;
1596
1597 /* [bandwidth 0:20M/1:40M][number of path] */
1598 u8 cck_pd_lv[2][RTW_RF_PATH_MAX];
1599 u32 cck_fa_avg;
1600 u8 cck_pd_default;
1601
1602 /* save the last rx phy status for debug */
1603 s8 rx_snr[RTW_RF_PATH_MAX];
1604 u8 rx_evm_dbm[RTW_RF_PATH_MAX];
1605 s16 cfo_tail[RTW_RF_PATH_MAX];
1606 u8 rssi[RTW_RF_PATH_MAX];
1607 u8 curr_rx_rate;
1608 struct rtw_pkt_count cur_pkt_count;
1609 struct rtw_pkt_count last_pkt_count;
1610 struct ewma_evm ewma_evm[RTW_EVM_NUM];
1611 struct ewma_snr ewma_snr[RTW_SNR_NUM];
1612
1613 u32 dm_flags; /* enum rtw_dm_cap */
1614 struct rtw_iqk_info iqk;
1615 struct rtw_gapk_info gapk;
1616 bool is_bt_iqk_timeout;
1617 };
1618
1619 struct rtw_efuse {
1620 u32 size;
1621 u32 physical_size;
1622 u32 logical_size;
1623 u32 protect_size;
1624
1625 u8 addr[ETH_ALEN];
1626 u8 channel_plan;
1627 u8 country_code[2];
1628 u8 rf_board_option;
1629 u8 rfe_option;
1630 u8 power_track_type;
1631 u8 thermal_meter[RTW_RF_PATH_MAX];
1632 u8 thermal_meter_k;
1633 u8 crystal_cap;
1634 u8 ant_div_cfg;
1635 u8 ant_div_type;
1636 u8 regd;
1637 u8 afe;
1638
1639 u8 lna_type_2g;
1640 u8 lna_type_5g;
1641 u8 glna_type;
1642 u8 alna_type;
1643 bool ext_lna_2g;
1644 bool ext_lna_5g;
1645 u8 pa_type_2g;
1646 u8 pa_type_5g;
1647 u8 gpa_type;
1648 u8 apa_type;
1649 bool ext_pa_2g;
1650 bool ext_pa_5g;
1651 u8 tx_bb_swing_setting_2g;
1652 u8 tx_bb_swing_setting_5g;
1653
1654 bool btcoex;
1655 /* bt share antenna with wifi */
1656 bool share_ant;
1657 u8 bt_setting;
1658
1659 struct {
1660 u8 hci;
1661 u8 bw;
1662 u8 ptcl;
1663 u8 nss;
1664 u8 ant_num;
1665 } hw_cap;
1666
1667 struct rtw_txpwr_idx txpwr_idx_table[4];
1668 };
1669
1670 struct rtw_phy_cond {
1671 #ifdef __LITTLE_ENDIAN
1672 u32 rfe:8;
1673 u32 intf:4;
1674 u32 pkg:4;
1675 u32 plat:4;
1676 u32 intf_rsvd:4;
1677 u32 cut:4;
1678 u32 branch:2;
1679 u32 neg:1;
1680 u32 pos:1;
1681 #else
1682 u32 pos:1;
1683 u32 neg:1;
1684 u32 branch:2;
1685 u32 cut:4;
1686 u32 intf_rsvd:4;
1687 u32 plat:4;
1688 u32 pkg:4;
1689 u32 intf:4;
1690 u32 rfe:8;
1691 #endif
1692 /* for intf:4 */
1693 #define INTF_PCIE BIT(0)
1694 #define INTF_USB BIT(1)
1695 #define INTF_SDIO BIT(2)
1696 /* for branch:2 */
1697 #define BRANCH_IF 0
1698 #define BRANCH_ELIF 1
1699 #define BRANCH_ELSE 2
1700 #define BRANCH_ENDIF 3
1701 };
1702
1703 struct rtw_fifo_conf {
1704 /* tx fifo information */
1705 u16 rsvd_boundary;
1706 u16 rsvd_pg_num;
1707 u16 rsvd_drv_pg_num;
1708 u16 txff_pg_num;
1709 u16 acq_pg_num;
1710 u16 rsvd_drv_addr;
1711 u16 rsvd_h2c_info_addr;
1712 u16 rsvd_h2c_sta_info_addr;
1713 u16 rsvd_h2cq_addr;
1714 u16 rsvd_cpu_instr_addr;
1715 u16 rsvd_fw_txbuf_addr;
1716 u16 rsvd_csibuf_addr;
1717 const struct rtw_rqpn *rqpn;
1718 };
1719
1720 #define FW_CD_TYPE 0xffff
1721 #define FW_CD_LEN 4
1722 #define FW_CD_VAL 0xaabbccdd
1723 struct rtw_fw_state {
1724 const struct firmware *firmware;
1725 struct rtw_dev *rtwdev;
1726 struct completion completion;
1727 u16 version;
1728 u8 sub_version;
1729 u8 sub_index;
1730 u16 h2c_version;
1731 u8 prev_dump_seq;
1732 u32 feature;
1733 };
1734
1735 struct rtw_hal {
1736 u32 rcr;
1737
1738 u32 chip_version;
1739 u8 cut_version;
1740 u8 mp_chip;
1741 u8 oem_id;
1742 struct rtw_phy_cond phy_cond;
1743
1744 u8 ps_mode;
1745 u8 current_channel;
1746 u8 current_band_width;
1747 u8 current_band_type;
1748
1749 /* center channel for different available bandwidth,
1750 * val of (bw > current_band_width) is invalid
1751 */
1752 u8 cch_by_bw[RTW_MAX_CHANNEL_WIDTH + 1];
1753
1754 u8 sec_ch_offset;
1755 u8 rf_type;
1756 u8 rf_path_num;
1757 u8 rf_phy_num;
1758 u32 antenna_tx;
1759 u32 antenna_rx;
1760 u8 bfee_sts_cap;
1761
1762 /* protect tx power section */
1763 struct mutex tx_power_mutex;
1764 s8 tx_pwr_by_rate_offset_2g[RTW_RF_PATH_MAX]
1765 [DESC_RATE_MAX];
1766 s8 tx_pwr_by_rate_offset_5g[RTW_RF_PATH_MAX]
1767 [DESC_RATE_MAX];
1768 s8 tx_pwr_by_rate_base_2g[RTW_RF_PATH_MAX]
1769 [RTW_RATE_SECTION_MAX];
1770 s8 tx_pwr_by_rate_base_5g[RTW_RF_PATH_MAX]
1771 [RTW_RATE_SECTION_MAX];
1772 s8 tx_pwr_limit_2g[RTW_REGD_MAX]
1773 [RTW_CHANNEL_WIDTH_MAX]
1774 [RTW_RATE_SECTION_MAX]
1775 [RTW_MAX_CHANNEL_NUM_2G];
1776 s8 tx_pwr_limit_5g[RTW_REGD_MAX]
1777 [RTW_CHANNEL_WIDTH_MAX]
1778 [RTW_RATE_SECTION_MAX]
1779 [RTW_MAX_CHANNEL_NUM_5G];
1780 s8 tx_pwr_tbl[RTW_RF_PATH_MAX]
1781 [DESC_RATE_MAX];
1782 };
1783
1784 struct rtw_dev {
1785 struct ieee80211_hw *hw;
1786 struct device *dev;
1787
1788 struct rtw_hci hci;
1789
1790 struct rtw_chip_info *chip;
1791 struct rtw_hal hal;
1792 struct rtw_fifo_conf fifo;
1793 struct rtw_fw_state fw;
1794 struct rtw_efuse efuse;
1795 struct rtw_sec_desc sec;
1796 struct rtw_traffic_stats stats;
1797 struct rtw_regulatory regd;
1798 struct rtw_bf_info bf_info;
1799
1800 struct rtw_dm_info dm_info;
1801 struct rtw_coex coex;
1802
1803 /* ensures exclusive access from mac80211 callbacks */
1804 struct mutex mutex;
1805
1806 /* read/write rf register */
1807 spinlock_t rf_lock;
1808
1809 /* watch dog every 2 sec */
1810 struct delayed_work watch_dog_work;
1811 u32 watch_dog_cnt;
1812
1813 struct list_head rsvd_page_list;
1814
1815 /* c2h cmd queue & handler work */
1816 struct sk_buff_head c2h_queue;
1817 struct work_struct c2h_work;
1818 struct work_struct fw_recovery_work;
1819
1820 /* used to protect txqs list */
1821 spinlock_t txq_lock;
1822 struct list_head txqs;
1823 struct workqueue_struct *tx_wq;
1824 struct work_struct tx_work;
1825 struct work_struct ba_work;
1826
1827 struct rtw_tx_report tx_report;
1828
1829 struct {
1830 /* incicate the mail box to use with fw */
1831 u8 last_box_num;
1832 /* protect to send h2c to fw */
1833 spinlock_t lock;
1834 u32 seq;
1835 } h2c;
1836
1837 /* lps power state & handler work */
1838 struct rtw_lps_conf lps_conf;
1839 bool ps_enabled;
1840 struct completion lps_leave_check;
1841
1842 struct dentry *debugfs;
1843
1844 u8 sta_cnt;
1845 u32 rts_threshold;
1846
1847 DECLARE_BITMAP(mac_id_map, RTW_MAX_MAC_ID_NUM);
1848 DECLARE_BITMAP(flags, NUM_OF_RTW_FLAGS);
1849
1850 u8 mp_mode;
1851
1852 struct rtw_fw_state wow_fw;
1853 struct rtw_wow_param wow;
1854
1855 bool need_rfk;
1856
1857 /* hci related data, must be last */
1858 u8 priv[] __aligned(sizeof(void *));
1859 };
1860
1861 #include "hci.h"
1862
rtw_is_assoc(struct rtw_dev * rtwdev)1863 static inline bool rtw_is_assoc(struct rtw_dev *rtwdev)
1864 {
1865 return !!rtwdev->sta_cnt;
1866 }
1867
rtwtxq_to_txq(struct rtw_txq * rtwtxq)1868 static inline struct ieee80211_txq *rtwtxq_to_txq(struct rtw_txq *rtwtxq)
1869 {
1870 void *p = rtwtxq;
1871
1872 return container_of(p, struct ieee80211_txq, drv_priv);
1873 }
1874
rtwvif_to_vif(struct rtw_vif * rtwvif)1875 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw_vif *rtwvif)
1876 {
1877 void *p = rtwvif;
1878
1879 return container_of(p, struct ieee80211_vif, drv_priv);
1880 }
1881
rtw_ssid_equal(struct cfg80211_ssid * a,struct cfg80211_ssid * b)1882 static inline bool rtw_ssid_equal(struct cfg80211_ssid *a,
1883 struct cfg80211_ssid *b)
1884 {
1885 if (!a || !b || a->ssid_len != b->ssid_len)
1886 return false;
1887
1888 if (memcmp(a->ssid, b->ssid, a->ssid_len))
1889 return false;
1890
1891 return true;
1892 }
1893
rtw_chip_efuse_grant_on(struct rtw_dev * rtwdev)1894 static inline void rtw_chip_efuse_grant_on(struct rtw_dev *rtwdev)
1895 {
1896 if (rtwdev->chip->ops->efuse_grant)
1897 rtwdev->chip->ops->efuse_grant(rtwdev, true);
1898 }
1899
rtw_chip_efuse_grant_off(struct rtw_dev * rtwdev)1900 static inline void rtw_chip_efuse_grant_off(struct rtw_dev *rtwdev)
1901 {
1902 if (rtwdev->chip->ops->efuse_grant)
1903 rtwdev->chip->ops->efuse_grant(rtwdev, false);
1904 }
1905
rtw_chip_wcpu_11n(struct rtw_dev * rtwdev)1906 static inline bool rtw_chip_wcpu_11n(struct rtw_dev *rtwdev)
1907 {
1908 return rtwdev->chip->wlan_cpu == RTW_WCPU_11N;
1909 }
1910
rtw_chip_wcpu_11ac(struct rtw_dev * rtwdev)1911 static inline bool rtw_chip_wcpu_11ac(struct rtw_dev *rtwdev)
1912 {
1913 return rtwdev->chip->wlan_cpu == RTW_WCPU_11AC;
1914 }
1915
rtw_chip_has_rx_ldpc(struct rtw_dev * rtwdev)1916 static inline bool rtw_chip_has_rx_ldpc(struct rtw_dev *rtwdev)
1917 {
1918 return rtwdev->chip->rx_ldpc;
1919 }
1920
rtw_release_macid(struct rtw_dev * rtwdev,u8 mac_id)1921 static inline void rtw_release_macid(struct rtw_dev *rtwdev, u8 mac_id)
1922 {
1923 clear_bit(mac_id, rtwdev->mac_id_map);
1924 }
1925
rtw_chip_dump_fw_crash(struct rtw_dev * rtwdev)1926 static inline void rtw_chip_dump_fw_crash(struct rtw_dev *rtwdev)
1927 {
1928 if (rtwdev->chip->ops->dump_fw_crash)
1929 rtwdev->chip->ops->dump_fw_crash(rtwdev);
1930 }
1931
1932 void rtw_get_channel_params(struct cfg80211_chan_def *chandef,
1933 struct rtw_channel_params *ch_param);
1934 bool check_hw_ready(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 target);
1935 bool ltecoex_read_reg(struct rtw_dev *rtwdev, u16 offset, u32 *val);
1936 bool ltecoex_reg_write(struct rtw_dev *rtwdev, u16 offset, u32 value);
1937 void rtw_restore_reg(struct rtw_dev *rtwdev,
1938 struct rtw_backup_info *bckp, u32 num);
1939 void rtw_desc_to_mcsrate(u16 rate, u8 *mcs, u8 *nss);
1940 void rtw_set_channel(struct rtw_dev *rtwdev);
1941 void rtw_chip_prepare_tx(struct rtw_dev *rtwdev);
1942 void rtw_vif_port_config(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif,
1943 u32 config);
1944 void rtw_tx_report_purge_timer(struct timer_list *t);
1945 void rtw_update_sta_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si);
1946 int rtw_core_start(struct rtw_dev *rtwdev);
1947 void rtw_core_stop(struct rtw_dev *rtwdev);
1948 int rtw_chip_info_setup(struct rtw_dev *rtwdev);
1949 int rtw_core_init(struct rtw_dev *rtwdev);
1950 void rtw_core_deinit(struct rtw_dev *rtwdev);
1951 int rtw_register_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw);
1952 void rtw_unregister_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw);
1953 u16 rtw_desc_to_bitrate(u8 desc_rate);
1954 void rtw_vif_assoc_changed(struct rtw_vif *rtwvif,
1955 struct ieee80211_bss_conf *conf);
1956 int rtw_sta_add(struct rtw_dev *rtwdev, struct ieee80211_sta *sta,
1957 struct ieee80211_vif *vif);
1958 void rtw_sta_remove(struct rtw_dev *rtwdev, struct ieee80211_sta *sta,
1959 bool fw_exist);
1960 void rtw_fw_recovery(struct rtw_dev *rtwdev);
1961 int rtw_dump_fw(struct rtw_dev *rtwdev, const u32 ocp_src, u32 size,
1962 const char *prefix_str);
1963 int rtw_dump_reg(struct rtw_dev *rtwdev, const u32 addr, const u32 size,
1964 const char *prefix_str);
1965
1966 #endif
1967