1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * DA9121 Single-channel dual-phase 10A buck converter 4 * DA9130 Single-channel dual-phase 10A buck converter (Automotive) 5 * DA9217 Single-channel dual-phase 6A buck converter 6 * DA9122 Dual-channel single-phase 5A buck converter 7 * DA9131 Dual-channel single-phase 5A buck converter (Automotive) 8 * DA9220 Dual-channel single-phase 3A buck converter 9 * DA9132 Dual-channel single-phase 3A buck converter (Automotive) 10 * 11 * Copyright (C) 2020 Dialog Semiconductor 12 * 13 * Authors: Steve Twiss, Dialog Semiconductor 14 * Adam Ward, Dialog Semiconductor 15 */ 16 17 #ifndef __DA9121_REGISTERS_H__ 18 #define __DA9121_REGISTERS_H__ 19 20 /* Values for: DA9121_REG_BUCK_BUCKx_4 registers, fields CHx_y_MODE 21 * DA9121_REG_BUCK_BUCKx_7 registers, fields CHx_RIPPLE_CANCEL 22 */ 23 #include <dt-bindings/regulator/dlg,da9121-regulator.h> 24 25 enum da9121_variant { 26 DA9121_TYPE_DA9121_DA9130, 27 DA9121_TYPE_DA9220_DA9132, 28 DA9121_TYPE_DA9122_DA9131, 29 DA9121_TYPE_DA9217 30 }; 31 32 enum da9121_subvariant { 33 DA9121_SUBTYPE_DA9121, 34 DA9121_SUBTYPE_DA9130, 35 DA9121_SUBTYPE_DA9220, 36 DA9121_SUBTYPE_DA9132, 37 DA9121_SUBTYPE_DA9122, 38 DA9121_SUBTYPE_DA9131, 39 DA9121_SUBTYPE_DA9217 40 }; 41 42 /* Minimum, maximum and default polling millisecond periods are provided 43 * here as an example. It is expected that any final implementation will 44 * include a modification of these settings to match the required 45 * application. 46 */ 47 #define DA9121_DEFAULT_POLLING_PERIOD_MS 3000 48 #define DA9121_MAX_POLLING_PERIOD_MS 10000 49 #define DA9121_MIN_POLLING_PERIOD_MS 1000 50 51 /* Registers */ 52 53 #define DA9121_REG_SYS_STATUS_0 0x01 54 #define DA9121_REG_SYS_STATUS_1 0x02 55 #define DA9121_REG_SYS_STATUS_2 0x03 56 #define DA9121_REG_SYS_EVENT_0 0x04 57 #define DA9121_REG_SYS_EVENT_1 0x05 58 #define DA9121_REG_SYS_EVENT_2 0x06 59 #define DA9121_REG_SYS_MASK_0 0x07 60 #define DA9121_REG_SYS_MASK_1 0x08 61 #define DA9121_REG_SYS_MASK_2 0x09 62 #define DA9121_REG_SYS_MASK_3 0x0A 63 #define DA9121_REG_SYS_CONFIG_0 0x0B 64 #define DA9121_REG_SYS_CONFIG_1 0x0C 65 #define DA9121_REG_SYS_CONFIG_2 0x0D 66 #define DA9121_REG_SYS_CONFIG_3 0x0E 67 #define DA9121_REG_SYS_GPIO0_0 0x10 68 #define DA9121_REG_SYS_GPIO0_1 0x11 69 #define DA9121_REG_SYS_GPIO1_0 0x12 70 #define DA9121_REG_SYS_GPIO1_1 0x13 71 #define DA9121_REG_SYS_GPIO2_0 0x14 72 #define DA9121_REG_SYS_GPIO2_1 0x15 73 #define DA9121_REG_BUCK_BUCK1_0 0x20 74 #define DA9121_REG_BUCK_BUCK1_1 0x21 75 #define DA9121_REG_BUCK_BUCK1_2 0x22 76 #define DA9121_REG_BUCK_BUCK1_3 0x23 77 #define DA9121_REG_BUCK_BUCK1_4 0x24 78 #define DA9121_REG_BUCK_BUCK1_5 0x25 79 #define DA9121_REG_BUCK_BUCK1_6 0x26 80 #define DA9121_REG_BUCK_BUCK1_7 0x27 81 #define DA9xxx_REG_BUCK_BUCK2_0 0x28 82 #define DA9xxx_REG_BUCK_BUCK2_1 0x29 83 #define DA9xxx_REG_BUCK_BUCK2_2 0x2A 84 #define DA9xxx_REG_BUCK_BUCK2_3 0x2B 85 #define DA9xxx_REG_BUCK_BUCK2_4 0x2C 86 #define DA9xxx_REG_BUCK_BUCK2_5 0x2D 87 #define DA9xxx_REG_BUCK_BUCK2_6 0x2E 88 #define DA9xxx_REG_BUCK_BUCK2_7 0x2F 89 #define DA9121_REG_OTP_DEVICE_ID 0x48 90 #define DA9121_REG_OTP_VARIANT_ID 0x49 91 #define DA9121_REG_OTP_CUSTOMER_ID 0x4A 92 #define DA9121_REG_OTP_CONFIG_ID 0x4B 93 94 /* Register bits */ 95 96 /* DA9121_REG_SYS_STATUS_0 */ 97 98 #define DA9xxx_MASK_SYS_STATUS_0_SG BIT(2) 99 #define DA9121_MASK_SYS_STATUS_0_TEMP_CRIT BIT(1) 100 #define DA9121_MASK_SYS_STATUS_0_TEMP_WARN BIT(0) 101 102 /* DA9121_REG_SYS_STATUS_1 */ 103 104 #define DA9xxx_MASK_SYS_STATUS_1_PG2 BIT(7) 105 #define DA9xxx_MASK_SYS_STATUS_1_OV2 BIT(6) 106 #define DA9xxx_MASK_SYS_STATUS_1_UV2 BIT(5) 107 #define DA9xxx_MASK_SYS_STATUS_1_OC2 BIT(4) 108 #define DA9121_MASK_SYS_STATUS_1_PG1 BIT(3) 109 #define DA9121_MASK_SYS_STATUS_1_OV1 BIT(2) 110 #define DA9121_MASK_SYS_STATUS_1_UV1 BIT(1) 111 #define DA9121_MASK_SYS_STATUS_1_OC1 BIT(0) 112 113 /* DA9121_REG_SYS_STATUS_2 */ 114 115 #define DA9121_MASK_SYS_STATUS_2_GPIO2 BIT(2) 116 #define DA9121_MASK_SYS_STATUS_2_GPIO1 BIT(1) 117 #define DA9121_MASK_SYS_STATUS_2_GPIO0 BIT(0) 118 119 /* DA9121_REG_SYS_EVENT_0 */ 120 121 #define DA9xxx_MASK_SYS_EVENT_0_E_SG BIT(2) 122 #define DA9121_MASK_SYS_EVENT_0_E_TEMP_CRIT BIT(1) 123 #define DA9121_MASK_SYS_EVENT_0_E_TEMP_WARN BIT(0) 124 125 /* DA9121_REG_SYS_EVENT_1 */ 126 127 #define DA9xxx_MASK_SYS_EVENT_1_E_PG2 BIT(7) 128 #define DA9xxx_MASK_SYS_EVENT_1_E_OV2 BIT(6) 129 #define DA9xxx_MASK_SYS_EVENT_1_E_UV2 BIT(5) 130 #define DA9xxx_MASK_SYS_EVENT_1_E_OC2 BIT(4) 131 #define DA9121_MASK_SYS_EVENT_1_E_PG1 BIT(3) 132 #define DA9121_MASK_SYS_EVENT_1_E_OV1 BIT(2) 133 #define DA9121_MASK_SYS_EVENT_1_E_UV1 BIT(1) 134 #define DA9121_MASK_SYS_EVENT_1_E_OC1 BIT(0) 135 136 /* DA9121_REG_SYS_EVENT_2 */ 137 138 #define DA9121_MASK_SYS_EVENT_2_E_GPIO2 BIT(2) 139 #define DA9121_MASK_SYS_EVENT_2_E_GPIO1 BIT(1) 140 #define DA9121_MASK_SYS_EVENT_2_E_GPIO0 BIT(0) 141 142 /* DA9121_REG_SYS_MASK_0 */ 143 144 #define DA9xxx_MASK_SYS_MASK_0_M_SG BIT(2) 145 #define DA9121_MASK_SYS_MASK_0_M_TEMP_CRIT BIT(1) 146 #define DA9121_MASK_SYS_MASK_0_M_TEMP_WARN BIT(0) 147 148 /* DA9121_REG_SYS_MASK_1 */ 149 150 #define DA9xxx_MASK_SYS_MASK_1_M_PG2 BIT(7) 151 #define DA9xxx_MASK_SYS_MASK_1_M_OV2 BIT(6) 152 #define DA9xxx_MASK_SYS_MASK_1_M_UV2 BIT(5) 153 #define DA9xxx_MASK_SYS_MASK_1_M_OC2 BIT(4) 154 #define DA9121_MASK_SYS_MASK_1_M_PG1 BIT(3) 155 #define DA9121_MASK_SYS_MASK_1_M_OV1 BIT(2) 156 #define DA9121_MASK_SYS_MASK_1_M_UV1 BIT(1) 157 #define DA9121_MASK_SYS_MASK_1_M_OC1 BIT(0) 158 159 /* DA9121_REG_SYS_MASK_2 */ 160 161 #define DA9121_MASK_SYS_MASK_2_M_GPIO2 BIT(2) 162 #define DA9121_MASK_SYS_MASK_2_M_GPIO1 BIT(1) 163 #define DA9121_MASK_SYS_MASK_2_M_GPIO0 BIT(0) 164 165 /* DA9122_REG_SYS_MASK_3 */ 166 167 #define DA9121_MASK_SYS_MASK_3_M_VR_HOT BIT(3) 168 #define DA9xxx_MASK_SYS_MASK_3_M_SG_STAT BIT(2) 169 #define DA9xxx_MASK_SYS_MASK_3_M_PG2_STAT BIT(1) 170 #define DA9121_MASK_SYS_MASK_3_M_PG1_STAT BIT(0) 171 172 /* DA9121_REG_SYS_CONFIG_0 */ 173 174 #define DA9121_MASK_SYS_CONFIG_0_CH1_DIS_DLY 0xF0 175 #define DA9121_MASK_SYS_CONFIG_0_CH1_EN_DLY 0x0F 176 177 /* DA9xxx_REG_SYS_CONFIG_1 */ 178 179 #define DA9xxx_MASK_SYS_CONFIG_1_CH2_DIS_DLY 0xF0 180 #define DA9xxx_MASK_SYS_CONFIG_1_CH2_EN_DLY 0x0F 181 182 /* DA9121_REG_SYS_CONFIG_2 */ 183 184 #define DA9121_MASK_SYS_CONFIG_2_OC_LATCHOFF 0x60 185 #define DA9121_MASK_SYS_CONFIG_2_OC_DVC_MASK BIT(4) 186 #define DA9121_MASK_SYS_CONFIG_2_PG_DVC_MASK 0x0C 187 188 /* DA9121_REG_SYS_CONFIG_3 */ 189 190 #define DA9121_MASK_SYS_CONFIG_3_OSC_TUNE 0X70 191 #define DA9121_MASK_SYS_CONFIG_3_I2C_TIMEOUT BIT(1) 192 193 /* DA9121_REG_SYS_GPIO0_0 */ 194 195 #define DA9121_MASK_SYS_GPIO0_0_GPIO0_MODE 0X1E 196 #define DA9121_MASK_SYS_GPIO0_0_GPIO0_OBUF BIT(0) 197 198 /* DA9121_REG_SYS_GPIO0_1 */ 199 200 #define DA9121_MASK_SYS_GPIO0_1_GPIO0_DEB_FALL BIT(7) 201 #define DA9121_MASK_SYS_GPIO0_1_GPIO0_DEB_RISE BIT(6) 202 #define DA9121_MASK_SYS_GPIO0_1_GPIO0_DEB 0x30 203 #define DA9121_MASK_SYS_GPIO0_1_GPIO0_PUPD BIT(3) 204 #define DA9121_MASK_SYS_GPIO0_1_GPIO0_POL BIT(2) 205 #define DA9121_MASK_SYS_GPIO0_1_GPIO0_TRIG 0x03 206 207 /* DA9121_REG_SYS_GPIO1_0 */ 208 209 #define DA9121_MASK_SYS_GPIO1_0_GPIO1_MODE 0x1E 210 #define DA9121_MASK_SYS_GPIO1_0_GPIO1_OBUF BIT(0) 211 212 /* DA9121_REG_SYS_GPIO1_1 */ 213 214 #define DA9121_MASK_SYS_GPIO1_1_GPIO1_DEB_FALL BIT(7) 215 #define DA9121_MASK_SYS_GPIO1_1_GPIO1_DEB_RISE BIT(6) 216 #define DA9121_MASK_SYS_GPIO1_1_GPIO1_DEB 0x30 217 #define DA9121_MASK_SYS_GPIO1_1_GPIO1_PUPD BIT(3) 218 #define DA9121_MASK_SYS_GPIO1_1_GPIO1_POL BIT(2) 219 #define DA9121_MASK_SYS_GPIO1_1_GPIO1_TRIG 0x03 220 221 /* DA9121_REG_SYS_GPIO2_0 */ 222 223 #define DA9121_MASK_SYS_GPIO2_0_GPIO2_MODE 0x1E 224 #define DA9121_MASK_SYS_GPIO2_0_GPIO2_OBUF BIT(0) 225 226 /* DA9121_REG_SYS_GPIO2_1 */ 227 228 #define DA9121_MASK_SYS_GPIO2_1_GPIO2_DEB_FALL BIT(7) 229 #define DA9121_MASK_SYS_GPIO2_1_GPIO2_DEB_RISE BIT(6) 230 #define DA9121_MASK_SYS_GPIO2_1_GPIO2_DEB 0x30 231 #define DA9121_MASK_SYS_GPIO2_1_GPIO2_PUPD BIT(3) 232 #define DA9121_MASK_SYS_GPIO2_1_GPIO2_POL BIT(2) 233 #define DA9121_MASK_SYS_GPIO2_1_GPIO2_TRIG 0x03 234 235 /* DA9121_REG_BUCK_BUCK1_0 / DA9xxx_REG_BUCK_BUCK2_0 */ 236 237 #define DA9121_MASK_BUCK_BUCKx_0_CHx_SR_DVC_DWN 0x70 238 #define DA9121_MASK_BUCK_BUCKx_0_CHx_SR_DVC_UP 0x0E 239 #define DA9121_MASK_BUCK_BUCKx_0_CHx_EN BIT(0) 240 241 /* DA9121_REG_BUCK_BUCK1_1 / DA9xxx_REG_BUCK_BUCK2_1 */ 242 243 #define DA9121_MASK_BUCK_BUCKx_1_CHx_SR_SHDN 0x70 244 #define DA9121_MASK_BUCK_BUCKx_1_CHx_SR_STARTUP 0x0E 245 #define DA9121_MASK_BUCK_BUCKx_1_CHx_PD_DIS BIT(0) 246 247 /* DA9121_REG_BUCK_BUCK1_2 / DA9xxx_REG_BUCK_BUCK2_2 */ 248 249 #define DA9121_MASK_BUCK_BUCKx_2_CHx_ILIM 0x0F 250 251 /* DA9121_REG_BUCK_BUCK1_3 / DA9xxx_REG_BUCK_BUCK2_3 */ 252 253 #define DA9121_MASK_BUCK_BUCKx_3_CHx_VMAX 0xFF 254 255 /* DA9121_REG_BUCK_BUCK1_4 / DA9xxx_REG_BUCK_BUCK2_4 */ 256 257 #define DA9121_MASK_BUCK_BUCKx_4_CHx_VSEL BIT(4) 258 #define DA9121_MASK_BUCK_BUCKx_4_CHx_B_MODE 0x0C 259 #define DA9121_MASK_BUCK_BUCKx_4_CHx_A_MODE 0x03 260 261 /* DA9121_REG_BUCK_BUCK1_5 / DA9xxx_REG_BUCK_BUCK2_5 */ 262 263 #define DA9121_MASK_BUCK_BUCKx_5_CHx_A_VOUT 0xFF 264 265 /* DA9121_REG_BUCK_BUCK1_6 / DA9xxx_REG_BUCK_BUCK2_6 */ 266 267 #define DA9121_MASK_BUCK_BUCKx_6_CHx_B_VOUT 0xFF 268 269 /* DA9121_REG_BUCK_BUCK1_7 / DA9xxx_REG_BUCK_BUCK2_7 */ 270 271 #define DA9xxx_MASK_BUCK_BUCKx_7_CHx_RIPPLE_CANCEL 0x03 272 273 274 /* DA9121_REG_OTP_DEVICE_ID */ 275 276 #define DA9121_MASK_OTP_DEVICE_ID_DEV_ID 0xFF 277 278 #define DA9121_DEVICE_ID 0x05 279 280 /* DA9121_REG_OTP_VARIANT_ID */ 281 282 #define DA9121_SHIFT_OTP_VARIANT_ID_MRC 4 283 #define DA9121_MASK_OTP_VARIANT_ID_MRC 0xF0 284 #define DA9121_SHIFT_OTP_VARIANT_ID_VRC 0 285 #define DA9121_MASK_OTP_VARIANT_ID_VRC 0x0F 286 287 #define DA9121_VARIANT_MRC_BASE 0x2 288 #define DA9121_VARIANT_VRC 0x1 289 #define DA9220_VARIANT_VRC 0x0 290 #define DA9122_VARIANT_VRC 0x2 291 #define DA9217_VARIANT_VRC 0x7 292 #define DA9130_VARIANT_VRC 0x0 293 #define DA9131_VARIANT_VRC 0x1 294 #define DA9132_VARIANT_VRC 0x2 295 296 /* DA9121_REG_OTP_CUSTOMER_ID */ 297 298 #define DA9121_MASK_OTP_CUSTOMER_ID_CUST_ID 0xFF 299 300 /* DA9121_REG_OTP_CONFIG_ID */ 301 302 #define DA9121_MASK_OTP_CONFIG_ID_CONFIG_REV 0xFF 303 304 #endif /* __DA9121_REGISTERS_H__ */ 305