1 // SPDX-License-Identifier: GPL-2.0
2 /******************************************************************************
3 *
4 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
5 *
6 ******************************************************************************/
7
8 #include "odm_precomp.h"
9 #include "phy.h"
10
dm_rx_hw_antena_div_init(struct odm_dm_struct * dm_odm)11 static void dm_rx_hw_antena_div_init(struct odm_dm_struct *dm_odm)
12 {
13 struct adapter *adapter = dm_odm->Adapter;
14 u32 value32;
15
16 if (*dm_odm->mp_mode == 1) {
17 dm_odm->AntDivType = CGCS_RX_SW_ANTDIV;
18 phy_set_bb_reg(adapter, ODM_REG_IGI_A_11N, BIT(7), 0);
19 phy_set_bb_reg(adapter, ODM_REG_LNA_SWITCH_11N, BIT(31), 1);
20 return;
21 }
22
23 /* MAC Setting */
24 value32 = phy_query_bb_reg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord);
25 phy_set_bb_reg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord,
26 value32 | (BIT(23) | BIT(25)));
27 /* Pin Settings */
28 phy_set_bb_reg(adapter, ODM_REG_PIN_CTRL_11N, BIT(9) | BIT(8), 0);
29 phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT(10), 0);
30 phy_set_bb_reg(adapter, ODM_REG_LNA_SWITCH_11N, BIT(22), 1);
31 phy_set_bb_reg(adapter, ODM_REG_LNA_SWITCH_11N, BIT(31), 1);
32 /* OFDM Settings */
33 phy_set_bb_reg(adapter, ODM_REG_ANTDIV_PARA1_11N, bMaskDWord,
34 0x000000a0);
35 /* CCK Settings */
36 phy_set_bb_reg(adapter, ODM_REG_BB_PWR_SAV4_11N, BIT(7), 1);
37 phy_set_bb_reg(adapter, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT(4), 1);
38 rtl88eu_dm_update_rx_idle_ant(dm_odm, MAIN_ANT);
39 phy_set_bb_reg(adapter, ODM_REG_ANT_MAPPING1_11N, 0xFFFF, 0x0201);
40 }
41
dm_trx_hw_antenna_div_init(struct odm_dm_struct * dm_odm)42 static void dm_trx_hw_antenna_div_init(struct odm_dm_struct *dm_odm)
43 {
44 struct adapter *adapter = dm_odm->Adapter;
45 u32 value32;
46
47 if (*dm_odm->mp_mode == 1) {
48 dm_odm->AntDivType = CGCS_RX_SW_ANTDIV;
49 phy_set_bb_reg(adapter, ODM_REG_IGI_A_11N, BIT(7), 0);
50 phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N,
51 BIT(5) | BIT(4) | BIT(3), 0);
52 return;
53 }
54
55 /* MAC Setting */
56 value32 = phy_query_bb_reg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord);
57 phy_set_bb_reg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord,
58 value32 | (BIT(23) | BIT(25)));
59 /* Pin Settings */
60 phy_set_bb_reg(adapter, ODM_REG_PIN_CTRL_11N, BIT(9) | BIT(8), 0);
61 phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT(10), 0);
62 phy_set_bb_reg(adapter, ODM_REG_LNA_SWITCH_11N, BIT(22), 0);
63 phy_set_bb_reg(adapter, ODM_REG_LNA_SWITCH_11N, BIT(31), 1);
64 /* OFDM Settings */
65 phy_set_bb_reg(adapter, ODM_REG_ANTDIV_PARA1_11N, bMaskDWord,
66 0x000000a0);
67 /* CCK Settings */
68 phy_set_bb_reg(adapter, ODM_REG_BB_PWR_SAV4_11N, BIT(7), 1);
69 phy_set_bb_reg(adapter, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT(4), 1);
70 /* Tx Settings */
71 phy_set_bb_reg(adapter, ODM_REG_TX_ANT_CTRL_11N, BIT(21), 0);
72 rtl88eu_dm_update_rx_idle_ant(dm_odm, MAIN_ANT);
73
74 /* antenna mapping table */
75 if (!dm_odm->bIsMPChip) { /* testchip */
76 phy_set_bb_reg(adapter, ODM_REG_RX_DEFAULT_A_11N,
77 BIT(10) | BIT(9) | BIT(8), 1);
78 phy_set_bb_reg(adapter, ODM_REG_RX_DEFAULT_A_11N,
79 BIT(13) | BIT(12) | BIT(11), 2);
80 } else { /* MPchip */
81 phy_set_bb_reg(adapter, ODM_REG_ANT_MAPPING1_11N, bMaskDWord,
82 0x0201);
83 }
84 }
85
dm_fast_training_init(struct odm_dm_struct * dm_odm)86 static void dm_fast_training_init(struct odm_dm_struct *dm_odm)
87 {
88 struct adapter *adapter = dm_odm->Adapter;
89 u32 value32, i;
90 struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable;
91
92 if (*dm_odm->mp_mode == 1)
93 return;
94
95 for (i = 0; i < 6; i++) {
96 dm_fat_tbl->Bssid[i] = 0;
97 dm_fat_tbl->antSumRSSI[i] = 0;
98 dm_fat_tbl->antRSSIcnt[i] = 0;
99 dm_fat_tbl->antAveRSSI[i] = 0;
100 }
101 dm_fat_tbl->TrainIdx = 0;
102 dm_fat_tbl->FAT_State = FAT_NORMAL_STATE;
103
104 /* MAC Setting */
105 value32 = phy_query_bb_reg(adapter, 0x4c, bMaskDWord);
106 phy_set_bb_reg(adapter, 0x4c, bMaskDWord,
107 value32 | (BIT(23) | BIT(25)));
108 value32 = phy_query_bb_reg(adapter, 0x7B4, bMaskDWord);
109 phy_set_bb_reg(adapter, 0x7b4, bMaskDWord,
110 value32 | (BIT(16) | BIT(17)));
111
112 /* Match MAC ADDR */
113 phy_set_bb_reg(adapter, 0x7b4, 0xFFFF, 0);
114 phy_set_bb_reg(adapter, 0x7b0, bMaskDWord, 0);
115
116 phy_set_bb_reg(adapter, 0x870, BIT(9) | BIT(8), 0);
117 phy_set_bb_reg(adapter, 0x864, BIT(10), 0);
118 phy_set_bb_reg(adapter, 0xb2c, BIT(22), 0);
119 phy_set_bb_reg(adapter, 0xb2c, BIT(31), 1);
120 phy_set_bb_reg(adapter, 0xca4, bMaskDWord, 0x000000a0);
121
122 /* antenna mapping table */
123 if (!dm_odm->bIsMPChip) { /* testchip */
124 phy_set_bb_reg(adapter, 0x858, BIT(10) | BIT(9) | BIT(8), 1);
125 phy_set_bb_reg(adapter, 0x858, BIT(13) | BIT(12) | BIT(11), 2);
126 } else { /* MPchip */
127 phy_set_bb_reg(adapter, 0x914, bMaskByte0, 1);
128 phy_set_bb_reg(adapter, 0x914, bMaskByte1, 2);
129 }
130
131 /* Default Ant Setting when no fast training */
132 phy_set_bb_reg(adapter, 0x80c, BIT(21), 1);
133 phy_set_bb_reg(adapter, 0x864, BIT(5) | BIT(4) | BIT(3), 0);
134 phy_set_bb_reg(adapter, 0x864, BIT(8) | BIT(7) | BIT(6), 1);
135
136 /* Enter Traing state */
137 phy_set_bb_reg(adapter, 0x864, BIT(2) | BIT(1) | BIT(0), 1);
138 phy_set_bb_reg(adapter, 0xc50, BIT(7), 1);
139 }
140
rtl88eu_dm_antenna_div_init(struct odm_dm_struct * dm_odm)141 void rtl88eu_dm_antenna_div_init(struct odm_dm_struct *dm_odm)
142 {
143 if (dm_odm->AntDivType == CGCS_RX_HW_ANTDIV)
144 dm_rx_hw_antena_div_init(dm_odm);
145 else if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV)
146 dm_trx_hw_antenna_div_init(dm_odm);
147 else if (dm_odm->AntDivType == CG_TRX_SMART_ANTDIV)
148 dm_fast_training_init(dm_odm);
149 }
150
rtl88eu_dm_update_rx_idle_ant(struct odm_dm_struct * dm_odm,u8 ant)151 void rtl88eu_dm_update_rx_idle_ant(struct odm_dm_struct *dm_odm, u8 ant)
152 {
153 struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable;
154 struct adapter *adapter = dm_odm->Adapter;
155 u32 default_ant, optional_ant;
156
157 if (dm_fat_tbl->RxIdleAnt == ant)
158 return;
159
160 if (ant == MAIN_ANT) {
161 default_ant = (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) ?
162 MAIN_ANT_CG_TRX : MAIN_ANT_CGCS_RX;
163 optional_ant = (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) ?
164 AUX_ANT_CG_TRX : AUX_ANT_CGCS_RX;
165 } else {
166 default_ant = (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) ?
167 AUX_ANT_CG_TRX : AUX_ANT_CGCS_RX;
168 optional_ant = (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) ?
169 MAIN_ANT_CG_TRX : MAIN_ANT_CGCS_RX;
170 }
171
172 if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) {
173 phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N,
174 BIT(5) | BIT(4) | BIT(3), default_ant);
175 phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N,
176 BIT(8) | BIT(7) | BIT(6), optional_ant);
177 phy_set_bb_reg(adapter, ODM_REG_ANTSEL_CTRL_11N,
178 BIT(14) | BIT(13) | BIT(12), default_ant);
179 phy_set_bb_reg(adapter, ODM_REG_RESP_TX_11N,
180 BIT(6) | BIT(7), default_ant);
181 } else if (dm_odm->AntDivType == CGCS_RX_HW_ANTDIV) {
182 phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N,
183 BIT(5) | BIT(4) | BIT(3), default_ant);
184 phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N,
185 BIT(8) | BIT(7) | BIT(6), optional_ant);
186 }
187
188 dm_fat_tbl->RxIdleAnt = ant;
189 }
190
update_tx_ant_88eu(struct odm_dm_struct * dm_odm,u8 ant,u32 mac_id)191 static void update_tx_ant_88eu(struct odm_dm_struct *dm_odm, u8 ant, u32 mac_id)
192 {
193 struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable;
194 u8 target_ant;
195
196 if (ant == MAIN_ANT)
197 target_ant = MAIN_ANT_CG_TRX;
198 else
199 target_ant = AUX_ANT_CG_TRX;
200 dm_fat_tbl->antsel_a[mac_id] = target_ant & BIT(0);
201 dm_fat_tbl->antsel_b[mac_id] = (target_ant & BIT(1)) >> 1;
202 dm_fat_tbl->antsel_c[mac_id] = (target_ant & BIT(2)) >> 2;
203 }
204
rtl88eu_dm_set_tx_ant_by_tx_info(struct odm_dm_struct * dm_odm,u8 * desc,u8 mac_id)205 void rtl88eu_dm_set_tx_ant_by_tx_info(struct odm_dm_struct *dm_odm,
206 u8 *desc, u8 mac_id)
207 {
208 struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable;
209
210 if ((dm_odm->AntDivType == CG_TRX_HW_ANTDIV) ||
211 (dm_odm->AntDivType == CG_TRX_SMART_ANTDIV)) {
212 SET_TX_DESC_ANTSEL_A_88E(desc, dm_fat_tbl->antsel_a[mac_id]);
213 SET_TX_DESC_ANTSEL_B_88E(desc, dm_fat_tbl->antsel_b[mac_id]);
214 SET_TX_DESC_ANTSEL_C_88E(desc, dm_fat_tbl->antsel_c[mac_id]);
215 }
216 }
217
rtl88eu_dm_ant_sel_statistics(struct odm_dm_struct * dm_odm,u8 antsel_tr_mux,u32 mac_id,u8 rx_pwdb_all)218 void rtl88eu_dm_ant_sel_statistics(struct odm_dm_struct *dm_odm,
219 u8 antsel_tr_mux, u32 mac_id, u8 rx_pwdb_all)
220 {
221 struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable;
222
223 if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) {
224 if (antsel_tr_mux == MAIN_ANT_CG_TRX) {
225 dm_fat_tbl->MainAnt_Sum[mac_id] += rx_pwdb_all;
226 dm_fat_tbl->MainAnt_Cnt[mac_id]++;
227 } else {
228 dm_fat_tbl->AuxAnt_Sum[mac_id] += rx_pwdb_all;
229 dm_fat_tbl->AuxAnt_Cnt[mac_id]++;
230 }
231 } else if (dm_odm->AntDivType == CGCS_RX_HW_ANTDIV) {
232 if (antsel_tr_mux == MAIN_ANT_CGCS_RX) {
233 dm_fat_tbl->MainAnt_Sum[mac_id] += rx_pwdb_all;
234 dm_fat_tbl->MainAnt_Cnt[mac_id]++;
235 } else {
236 dm_fat_tbl->AuxAnt_Sum[mac_id] += rx_pwdb_all;
237 dm_fat_tbl->AuxAnt_Cnt[mac_id]++;
238 }
239 }
240 }
241
rtl88eu_dm_hw_ant_div(struct odm_dm_struct * dm_odm)242 static void rtl88eu_dm_hw_ant_div(struct odm_dm_struct *dm_odm)
243 {
244 struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable;
245 struct rtw_dig *dig_table = &dm_odm->DM_DigTable;
246 struct sta_info *entry;
247 u32 i, min_rssi = 0xFF, ant_div_max_rssi = 0, max_rssi = 0;
248 u32 local_min_rssi, local_max_rssi;
249 u32 main_rssi, aux_rssi;
250 u8 RxIdleAnt = 0, target_ant = 7;
251
252 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
253 entry = dm_odm->pODM_StaInfo[i];
254 if (IS_STA_VALID(entry)) {
255 /* 2 Calculate RSSI per Antenna */
256 main_rssi = (dm_fat_tbl->MainAnt_Cnt[i] != 0) ?
257 (dm_fat_tbl->MainAnt_Sum[i] /
258 dm_fat_tbl->MainAnt_Cnt[i]) : 0;
259 aux_rssi = (dm_fat_tbl->AuxAnt_Cnt[i] != 0) ?
260 (dm_fat_tbl->AuxAnt_Sum[i] /
261 dm_fat_tbl->AuxAnt_Cnt[i]) : 0;
262 target_ant = (main_rssi >= aux_rssi) ? MAIN_ANT : AUX_ANT;
263 /* 2 Select max_rssi for DIG */
264 local_max_rssi = max(main_rssi, aux_rssi);
265 if ((local_max_rssi > ant_div_max_rssi) &&
266 (local_max_rssi < 40))
267 ant_div_max_rssi = local_max_rssi;
268 if (local_max_rssi > max_rssi)
269 max_rssi = local_max_rssi;
270
271 /* 2 Select RX Idle Antenna */
272 if ((dm_fat_tbl->RxIdleAnt == MAIN_ANT) &&
273 (main_rssi == 0))
274 main_rssi = aux_rssi;
275 else if ((dm_fat_tbl->RxIdleAnt == AUX_ANT) &&
276 (aux_rssi == 0))
277 aux_rssi = main_rssi;
278
279 local_min_rssi = min(main_rssi, aux_rssi);
280 if (local_min_rssi < min_rssi) {
281 min_rssi = local_min_rssi;
282 RxIdleAnt = target_ant;
283 }
284 /* 2 Select TRX Antenna */
285 if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV)
286 update_tx_ant_88eu(dm_odm, target_ant, i);
287 }
288 dm_fat_tbl->MainAnt_Sum[i] = 0;
289 dm_fat_tbl->AuxAnt_Sum[i] = 0;
290 dm_fat_tbl->MainAnt_Cnt[i] = 0;
291 dm_fat_tbl->AuxAnt_Cnt[i] = 0;
292 }
293
294 /* 2 Set RX Idle Antenna */
295 rtl88eu_dm_update_rx_idle_ant(dm_odm, RxIdleAnt);
296
297 dig_table->AntDiv_RSSI_max = ant_div_max_rssi;
298 dig_table->RSSI_max = max_rssi;
299 }
300
rtl88eu_dm_antenna_diversity(struct odm_dm_struct * dm_odm)301 void rtl88eu_dm_antenna_diversity(struct odm_dm_struct *dm_odm)
302 {
303 struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable;
304 struct adapter *adapter = dm_odm->Adapter;
305
306 if (!(dm_odm->SupportAbility & ODM_BB_ANT_DIV))
307 return;
308
309 if (!dm_odm->bLinked) {
310 ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
311 ("ODM_AntennaDiversity_88E(): No Link.\n"));
312 if (dm_fat_tbl->bBecomeLinked) {
313 ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
314 ("Need to Turn off HW AntDiv\n"));
315 phy_set_bb_reg(adapter, ODM_REG_IGI_A_11N, BIT(7), 0);
316 phy_set_bb_reg(adapter, ODM_REG_CCK_ANTDIV_PARA1_11N,
317 BIT(15), 0);
318 if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV)
319 phy_set_bb_reg(adapter, ODM_REG_TX_ANT_CTRL_11N,
320 BIT(21), 0);
321 dm_fat_tbl->bBecomeLinked = dm_odm->bLinked;
322 }
323 return;
324 }
325
326 if (!dm_fat_tbl->bBecomeLinked) {
327 ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
328 ("Need to Turn on HW AntDiv\n"));
329 phy_set_bb_reg(adapter, ODM_REG_IGI_A_11N, BIT(7), 1);
330 phy_set_bb_reg(adapter, ODM_REG_CCK_ANTDIV_PARA1_11N,
331 BIT(15), 1);
332 if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV)
333 phy_set_bb_reg(adapter, ODM_REG_TX_ANT_CTRL_11N,
334 BIT(21), 1);
335 dm_fat_tbl->bBecomeLinked = dm_odm->bLinked;
336 }
337
338 if ((dm_odm->AntDivType == CG_TRX_HW_ANTDIV) ||
339 (dm_odm->AntDivType == CGCS_RX_HW_ANTDIV))
340 rtl88eu_dm_hw_ant_div(dm_odm);
341 }
342