1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // Freescale ASRC ALSA SoC Digital Audio Interface (DAI) driver
4 //
5 // Copyright (C) 2014 Freescale Semiconductor, Inc.
6 //
7 // Author: Nicolin Chen <nicoleotsuka@gmail.com>
8
9 #include <linux/clk.h>
10 #include <linux/delay.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/module.h>
13 #include <linux/of_platform.h>
14 #include <linux/platform_data/dma-imx.h>
15 #include <linux/pm_runtime.h>
16 #include <sound/dmaengine_pcm.h>
17 #include <sound/pcm_params.h>
18
19 #include "fsl_asrc.h"
20
21 #define IDEAL_RATIO_DECIMAL_DEPTH 26
22
23 #define pair_err(fmt, ...) \
24 dev_err(&asrc->pdev->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__)
25
26 #define pair_dbg(fmt, ...) \
27 dev_dbg(&asrc->pdev->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__)
28
29 /* Corresponding to process_option */
30 static unsigned int supported_asrc_rate[] = {
31 5512, 8000, 11025, 12000, 16000, 22050, 24000, 32000, 44100, 48000,
32 64000, 88200, 96000, 128000, 176400, 192000,
33 };
34
35 static struct snd_pcm_hw_constraint_list fsl_asrc_rate_constraints = {
36 .count = ARRAY_SIZE(supported_asrc_rate),
37 .list = supported_asrc_rate,
38 };
39
40 /*
41 * The following tables map the relationship between asrc_inclk/asrc_outclk in
42 * fsl_asrc.h and the registers of ASRCSR
43 */
44 static unsigned char input_clk_map_imx35[ASRC_CLK_MAP_LEN] = {
45 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf,
46 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
47 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
48 };
49
50 static unsigned char output_clk_map_imx35[ASRC_CLK_MAP_LEN] = {
51 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf,
52 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
53 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
54 };
55
56 /* i.MX53 uses the same map for input and output */
57 static unsigned char input_clk_map_imx53[ASRC_CLK_MAP_LEN] = {
58 /* 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf */
59 0x0, 0x1, 0x2, 0x7, 0x4, 0x5, 0x6, 0x3, 0x8, 0x9, 0xa, 0xb, 0xc, 0xf, 0xe, 0xd,
60 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7,
61 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7,
62 };
63
64 static unsigned char output_clk_map_imx53[ASRC_CLK_MAP_LEN] = {
65 /* 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf */
66 0x8, 0x9, 0xa, 0x7, 0xc, 0x5, 0x6, 0xb, 0x0, 0x1, 0x2, 0x3, 0x4, 0xf, 0xe, 0xd,
67 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7,
68 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7,
69 };
70
71 /*
72 * i.MX8QM/i.MX8QXP uses the same map for input and output.
73 * clk_map_imx8qm[0] is for i.MX8QM asrc0
74 * clk_map_imx8qm[1] is for i.MX8QM asrc1
75 * clk_map_imx8qxp[0] is for i.MX8QXP asrc0
76 * clk_map_imx8qxp[1] is for i.MX8QXP asrc1
77 */
78 static unsigned char clk_map_imx8qm[2][ASRC_CLK_MAP_LEN] = {
79 {
80 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0x0,
81 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf,
82 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf,
83 },
84 {
85 0xf, 0xf, 0xf, 0xf, 0xf, 0x7, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0x0,
86 0x0, 0x1, 0x2, 0x3, 0xb, 0xc, 0xf, 0xf, 0xd, 0xe, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf,
87 0x4, 0x5, 0x6, 0xf, 0x8, 0x9, 0xa, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf,
88 },
89 };
90
91 static unsigned char clk_map_imx8qxp[2][ASRC_CLK_MAP_LEN] = {
92 {
93 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0x0,
94 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0xf, 0x7, 0x8, 0x9, 0xa, 0xb, 0xc, 0xf, 0xf,
95 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf,
96 },
97 {
98 0xf, 0xf, 0xf, 0xf, 0xf, 0x7, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0x0,
99 0x0, 0x1, 0x2, 0x3, 0x7, 0x8, 0xf, 0xf, 0x9, 0xa, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf,
100 0xf, 0xf, 0x6, 0xf, 0xf, 0xf, 0xa, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf,
101 },
102 };
103
104 /**
105 * fsl_asrc_sel_proc - Select the pre-processing and post-processing options
106 * @inrate: input sample rate
107 * @outrate: output sample rate
108 * @pre_proc: return value for pre-processing option
109 * @post_proc: return value for post-processing option
110 *
111 * Make sure to exclude following unsupported cases before
112 * calling this function:
113 * 1) inrate > 8.125 * outrate
114 * 2) inrate > 16.125 * outrate
115 *
116 */
fsl_asrc_sel_proc(int inrate,int outrate,int * pre_proc,int * post_proc)117 static void fsl_asrc_sel_proc(int inrate, int outrate,
118 int *pre_proc, int *post_proc)
119 {
120 bool post_proc_cond2;
121 bool post_proc_cond0;
122
123 /* select pre_proc between [0, 2] */
124 if (inrate * 8 > 33 * outrate)
125 *pre_proc = 2;
126 else if (inrate * 8 > 15 * outrate) {
127 if (inrate > 152000)
128 *pre_proc = 2;
129 else
130 *pre_proc = 1;
131 } else if (inrate < 76000)
132 *pre_proc = 0;
133 else if (inrate > 152000)
134 *pre_proc = 2;
135 else
136 *pre_proc = 1;
137
138 /* Condition for selection of post-processing */
139 post_proc_cond2 = (inrate * 15 > outrate * 16 && outrate < 56000) ||
140 (inrate > 56000 && outrate < 56000);
141 post_proc_cond0 = inrate * 23 < outrate * 8;
142
143 if (post_proc_cond2)
144 *post_proc = 2;
145 else if (post_proc_cond0)
146 *post_proc = 0;
147 else
148 *post_proc = 1;
149 }
150
151 /**
152 * fsl_asrc_request_pair - Request ASRC pair
153 * @channels: number of channels
154 * @pair: pointer to pair
155 *
156 * It assigns pair by the order of A->C->B because allocation of pair B,
157 * within range [ANCA, ANCA+ANCB-1], depends on the channels of pair A
158 * while pair A and pair C are comparatively independent.
159 */
fsl_asrc_request_pair(int channels,struct fsl_asrc_pair * pair)160 static int fsl_asrc_request_pair(int channels, struct fsl_asrc_pair *pair)
161 {
162 enum asrc_pair_index index = ASRC_INVALID_PAIR;
163 struct fsl_asrc *asrc = pair->asrc;
164 struct device *dev = &asrc->pdev->dev;
165 unsigned long lock_flags;
166 int i, ret = 0;
167
168 spin_lock_irqsave(&asrc->lock, lock_flags);
169
170 for (i = ASRC_PAIR_A; i < ASRC_PAIR_MAX_NUM; i++) {
171 if (asrc->pair[i] != NULL)
172 continue;
173
174 index = i;
175
176 if (i != ASRC_PAIR_B)
177 break;
178 }
179
180 if (index == ASRC_INVALID_PAIR) {
181 dev_err(dev, "all pairs are busy now\n");
182 ret = -EBUSY;
183 } else if (asrc->channel_avail < channels) {
184 dev_err(dev, "can't afford required channels: %d\n", channels);
185 ret = -EINVAL;
186 } else {
187 asrc->channel_avail -= channels;
188 asrc->pair[index] = pair;
189 pair->channels = channels;
190 pair->index = index;
191 }
192
193 spin_unlock_irqrestore(&asrc->lock, lock_flags);
194
195 return ret;
196 }
197
198 /**
199 * fsl_asrc_release_pair - Release ASRC pair
200 * @pair: pair to release
201 *
202 * It clears the resource from asrc and releases the occupied channels.
203 */
fsl_asrc_release_pair(struct fsl_asrc_pair * pair)204 static void fsl_asrc_release_pair(struct fsl_asrc_pair *pair)
205 {
206 struct fsl_asrc *asrc = pair->asrc;
207 enum asrc_pair_index index = pair->index;
208 unsigned long lock_flags;
209
210 /* Make sure the pair is disabled */
211 regmap_update_bits(asrc->regmap, REG_ASRCTR,
212 ASRCTR_ASRCEi_MASK(index), 0);
213
214 spin_lock_irqsave(&asrc->lock, lock_flags);
215
216 asrc->channel_avail += pair->channels;
217 asrc->pair[index] = NULL;
218 pair->error = 0;
219
220 spin_unlock_irqrestore(&asrc->lock, lock_flags);
221 }
222
223 /**
224 * fsl_asrc_set_watermarks- configure input and output thresholds
225 * @pair: pointer to pair
226 * @in: input threshold
227 * @out: output threshold
228 */
fsl_asrc_set_watermarks(struct fsl_asrc_pair * pair,u32 in,u32 out)229 static void fsl_asrc_set_watermarks(struct fsl_asrc_pair *pair, u32 in, u32 out)
230 {
231 struct fsl_asrc *asrc = pair->asrc;
232 enum asrc_pair_index index = pair->index;
233
234 regmap_update_bits(asrc->regmap, REG_ASRMCR(index),
235 ASRMCRi_EXTTHRSHi_MASK |
236 ASRMCRi_INFIFO_THRESHOLD_MASK |
237 ASRMCRi_OUTFIFO_THRESHOLD_MASK,
238 ASRMCRi_EXTTHRSHi |
239 ASRMCRi_INFIFO_THRESHOLD(in) |
240 ASRMCRi_OUTFIFO_THRESHOLD(out));
241 }
242
243 /**
244 * fsl_asrc_cal_asrck_divisor - Calculate the total divisor between asrck clock rate and sample rate
245 * @pair: pointer to pair
246 * @div: divider
247 *
248 * It follows the formula clk_rate = samplerate * (2 ^ prescaler) * divider
249 */
fsl_asrc_cal_asrck_divisor(struct fsl_asrc_pair * pair,u32 div)250 static u32 fsl_asrc_cal_asrck_divisor(struct fsl_asrc_pair *pair, u32 div)
251 {
252 u32 ps;
253
254 /* Calculate the divisors: prescaler [2^0, 2^7], divder [1, 8] */
255 for (ps = 0; div > 8; ps++)
256 div >>= 1;
257
258 return ((div - 1) << ASRCDRi_AxCPi_WIDTH) | ps;
259 }
260
261 /**
262 * fsl_asrc_set_ideal_ratio - Calculate and set the ratio for Ideal Ratio mode only
263 * @pair: pointer to pair
264 * @inrate: input rate
265 * @outrate: output rate
266 *
267 * The ratio is a 32-bit fixed point value with 26 fractional bits.
268 */
fsl_asrc_set_ideal_ratio(struct fsl_asrc_pair * pair,int inrate,int outrate)269 static int fsl_asrc_set_ideal_ratio(struct fsl_asrc_pair *pair,
270 int inrate, int outrate)
271 {
272 struct fsl_asrc *asrc = pair->asrc;
273 enum asrc_pair_index index = pair->index;
274 unsigned long ratio;
275 int i;
276
277 if (!outrate) {
278 pair_err("output rate should not be zero\n");
279 return -EINVAL;
280 }
281
282 /* Calculate the intergal part of the ratio */
283 ratio = (inrate / outrate) << IDEAL_RATIO_DECIMAL_DEPTH;
284
285 /* ... and then the 26 depth decimal part */
286 inrate %= outrate;
287
288 for (i = 1; i <= IDEAL_RATIO_DECIMAL_DEPTH; i++) {
289 inrate <<= 1;
290
291 if (inrate < outrate)
292 continue;
293
294 ratio |= 1 << (IDEAL_RATIO_DECIMAL_DEPTH - i);
295 inrate -= outrate;
296
297 if (!inrate)
298 break;
299 }
300
301 regmap_write(asrc->regmap, REG_ASRIDRL(index), ratio);
302 regmap_write(asrc->regmap, REG_ASRIDRH(index), ratio >> 24);
303
304 return 0;
305 }
306
307 /**
308 * fsl_asrc_config_pair - Configure the assigned ASRC pair
309 * @pair: pointer to pair
310 * @use_ideal_rate: boolean configuration
311 *
312 * It configures those ASRC registers according to a configuration instance
313 * of struct asrc_config which includes in/output sample rate, width, channel
314 * and clock settings.
315 *
316 * Note:
317 * The ideal ratio configuration can work with a flexible clock rate setting.
318 * Using IDEAL_RATIO_RATE gives a faster converting speed but overloads ASRC.
319 * For a regular audio playback, the clock rate should not be slower than an
320 * clock rate aligning with the output sample rate; For a use case requiring
321 * faster conversion, set use_ideal_rate to have the faster speed.
322 */
fsl_asrc_config_pair(struct fsl_asrc_pair * pair,bool use_ideal_rate)323 static int fsl_asrc_config_pair(struct fsl_asrc_pair *pair, bool use_ideal_rate)
324 {
325 struct fsl_asrc_pair_priv *pair_priv = pair->private;
326 struct asrc_config *config = pair_priv->config;
327 struct fsl_asrc *asrc = pair->asrc;
328 struct fsl_asrc_priv *asrc_priv = asrc->private;
329 enum asrc_pair_index index = pair->index;
330 enum asrc_word_width input_word_width;
331 enum asrc_word_width output_word_width;
332 u32 inrate, outrate, indiv, outdiv;
333 u32 clk_index[2], div[2], rem[2];
334 u64 clk_rate;
335 int in, out, channels;
336 int pre_proc, post_proc;
337 struct clk *clk;
338 bool ideal;
339
340 if (!config) {
341 pair_err("invalid pair config\n");
342 return -EINVAL;
343 }
344
345 /* Validate channels */
346 if (config->channel_num < 1 || config->channel_num > 10) {
347 pair_err("does not support %d channels\n", config->channel_num);
348 return -EINVAL;
349 }
350
351 switch (snd_pcm_format_width(config->input_format)) {
352 case 8:
353 input_word_width = ASRC_WIDTH_8_BIT;
354 break;
355 case 16:
356 input_word_width = ASRC_WIDTH_16_BIT;
357 break;
358 case 24:
359 input_word_width = ASRC_WIDTH_24_BIT;
360 break;
361 default:
362 pair_err("does not support this input format, %d\n",
363 config->input_format);
364 return -EINVAL;
365 }
366
367 switch (snd_pcm_format_width(config->output_format)) {
368 case 16:
369 output_word_width = ASRC_WIDTH_16_BIT;
370 break;
371 case 24:
372 output_word_width = ASRC_WIDTH_24_BIT;
373 break;
374 default:
375 pair_err("does not support this output format, %d\n",
376 config->output_format);
377 return -EINVAL;
378 }
379
380 inrate = config->input_sample_rate;
381 outrate = config->output_sample_rate;
382 ideal = config->inclk == INCLK_NONE;
383
384 /* Validate input and output sample rates */
385 for (in = 0; in < ARRAY_SIZE(supported_asrc_rate); in++)
386 if (inrate == supported_asrc_rate[in])
387 break;
388
389 if (in == ARRAY_SIZE(supported_asrc_rate)) {
390 pair_err("unsupported input sample rate: %dHz\n", inrate);
391 return -EINVAL;
392 }
393
394 for (out = 0; out < ARRAY_SIZE(supported_asrc_rate); out++)
395 if (outrate == supported_asrc_rate[out])
396 break;
397
398 if (out == ARRAY_SIZE(supported_asrc_rate)) {
399 pair_err("unsupported output sample rate: %dHz\n", outrate);
400 return -EINVAL;
401 }
402
403 if ((outrate >= 5512 && outrate <= 30000) &&
404 (outrate > 24 * inrate || inrate > 8 * outrate)) {
405 pair_err("exceed supported ratio range [1/24, 8] for \
406 inrate/outrate: %d/%d\n", inrate, outrate);
407 return -EINVAL;
408 }
409
410 /* Validate input and output clock sources */
411 clk_index[IN] = asrc_priv->clk_map[IN][config->inclk];
412 clk_index[OUT] = asrc_priv->clk_map[OUT][config->outclk];
413
414 /* We only have output clock for ideal ratio mode */
415 clk = asrc_priv->asrck_clk[clk_index[ideal ? OUT : IN]];
416
417 clk_rate = clk_get_rate(clk);
418 rem[IN] = do_div(clk_rate, inrate);
419 div[IN] = (u32)clk_rate;
420
421 /*
422 * The divider range is [1, 1024], defined by the hardware. For non-
423 * ideal ratio configuration, clock rate has to be strictly aligned
424 * with the sample rate. For ideal ratio configuration, clock rates
425 * only result in different converting speeds. So remainder does not
426 * matter, as long as we keep the divider within its valid range.
427 */
428 if (div[IN] == 0 || (!ideal && (div[IN] > 1024 || rem[IN] != 0))) {
429 pair_err("failed to support input sample rate %dHz by asrck_%x\n",
430 inrate, clk_index[ideal ? OUT : IN]);
431 return -EINVAL;
432 }
433
434 div[IN] = min_t(u32, 1024, div[IN]);
435
436 clk = asrc_priv->asrck_clk[clk_index[OUT]];
437 clk_rate = clk_get_rate(clk);
438 if (ideal && use_ideal_rate)
439 rem[OUT] = do_div(clk_rate, IDEAL_RATIO_RATE);
440 else
441 rem[OUT] = do_div(clk_rate, outrate);
442 div[OUT] = clk_rate;
443
444 /* Output divider has the same limitation as the input one */
445 if (div[OUT] == 0 || (!ideal && (div[OUT] > 1024 || rem[OUT] != 0))) {
446 pair_err("failed to support output sample rate %dHz by asrck_%x\n",
447 outrate, clk_index[OUT]);
448 return -EINVAL;
449 }
450
451 div[OUT] = min_t(u32, 1024, div[OUT]);
452
453 /* Set the channel number */
454 channels = config->channel_num;
455
456 if (asrc_priv->soc->channel_bits < 4)
457 channels /= 2;
458
459 /* Update channels for current pair */
460 regmap_update_bits(asrc->regmap, REG_ASRCNCR,
461 ASRCNCR_ANCi_MASK(index, asrc_priv->soc->channel_bits),
462 ASRCNCR_ANCi(index, channels, asrc_priv->soc->channel_bits));
463
464 /* Default setting: Automatic selection for processing mode */
465 regmap_update_bits(asrc->regmap, REG_ASRCTR,
466 ASRCTR_ATSi_MASK(index), ASRCTR_ATS(index));
467 regmap_update_bits(asrc->regmap, REG_ASRCTR,
468 ASRCTR_USRi_MASK(index), 0);
469
470 /* Set the input and output clock sources */
471 regmap_update_bits(asrc->regmap, REG_ASRCSR,
472 ASRCSR_AICSi_MASK(index) | ASRCSR_AOCSi_MASK(index),
473 ASRCSR_AICS(index, clk_index[IN]) |
474 ASRCSR_AOCS(index, clk_index[OUT]));
475
476 /* Calculate the input clock divisors */
477 indiv = fsl_asrc_cal_asrck_divisor(pair, div[IN]);
478 outdiv = fsl_asrc_cal_asrck_divisor(pair, div[OUT]);
479
480 /* Suppose indiv and outdiv includes prescaler, so add its MASK too */
481 regmap_update_bits(asrc->regmap, REG_ASRCDR(index),
482 ASRCDRi_AOCPi_MASK(index) | ASRCDRi_AICPi_MASK(index) |
483 ASRCDRi_AOCDi_MASK(index) | ASRCDRi_AICDi_MASK(index),
484 ASRCDRi_AOCP(index, outdiv) | ASRCDRi_AICP(index, indiv));
485
486 /* Implement word_width configurations */
487 regmap_update_bits(asrc->regmap, REG_ASRMCR1(index),
488 ASRMCR1i_OW16_MASK | ASRMCR1i_IWD_MASK,
489 ASRMCR1i_OW16(output_word_width) |
490 ASRMCR1i_IWD(input_word_width));
491
492 /* Enable BUFFER STALL */
493 regmap_update_bits(asrc->regmap, REG_ASRMCR(index),
494 ASRMCRi_BUFSTALLi_MASK, ASRMCRi_BUFSTALLi);
495
496 /* Set default thresholds for input and output FIFO */
497 fsl_asrc_set_watermarks(pair, ASRC_INPUTFIFO_THRESHOLD,
498 ASRC_INPUTFIFO_THRESHOLD);
499
500 /* Configure the following only for Ideal Ratio mode */
501 if (!ideal)
502 return 0;
503
504 /* Clear ASTSx bit to use Ideal Ratio mode */
505 regmap_update_bits(asrc->regmap, REG_ASRCTR,
506 ASRCTR_ATSi_MASK(index), 0);
507
508 /* Enable Ideal Ratio mode */
509 regmap_update_bits(asrc->regmap, REG_ASRCTR,
510 ASRCTR_IDRi_MASK(index) | ASRCTR_USRi_MASK(index),
511 ASRCTR_IDR(index) | ASRCTR_USR(index));
512
513 fsl_asrc_sel_proc(inrate, outrate, &pre_proc, &post_proc);
514
515 /* Apply configurations for pre- and post-processing */
516 regmap_update_bits(asrc->regmap, REG_ASRCFG,
517 ASRCFG_PREMODi_MASK(index) | ASRCFG_POSTMODi_MASK(index),
518 ASRCFG_PREMOD(index, pre_proc) |
519 ASRCFG_POSTMOD(index, post_proc));
520
521 return fsl_asrc_set_ideal_ratio(pair, inrate, outrate);
522 }
523
524 /**
525 * fsl_asrc_start_pair - Start the assigned ASRC pair
526 * @pair: pointer to pair
527 *
528 * It enables the assigned pair and makes it stopped at the stall level.
529 */
fsl_asrc_start_pair(struct fsl_asrc_pair * pair)530 static void fsl_asrc_start_pair(struct fsl_asrc_pair *pair)
531 {
532 struct fsl_asrc *asrc = pair->asrc;
533 enum asrc_pair_index index = pair->index;
534 int reg, retry = 10, i;
535
536 /* Enable the current pair */
537 regmap_update_bits(asrc->regmap, REG_ASRCTR,
538 ASRCTR_ASRCEi_MASK(index), ASRCTR_ASRCE(index));
539
540 /* Wait for status of initialization */
541 do {
542 udelay(5);
543 regmap_read(asrc->regmap, REG_ASRCFG, ®);
544 reg &= ASRCFG_INIRQi_MASK(index);
545 } while (!reg && --retry);
546
547 /* Make the input fifo to ASRC STALL level */
548 regmap_read(asrc->regmap, REG_ASRCNCR, ®);
549 for (i = 0; i < pair->channels * 4; i++)
550 regmap_write(asrc->regmap, REG_ASRDI(index), 0);
551
552 /* Enable overload interrupt */
553 regmap_write(asrc->regmap, REG_ASRIER, ASRIER_AOLIE);
554 }
555
556 /**
557 * fsl_asrc_stop_pair - Stop the assigned ASRC pair
558 * @pair: pointer to pair
559 */
fsl_asrc_stop_pair(struct fsl_asrc_pair * pair)560 static void fsl_asrc_stop_pair(struct fsl_asrc_pair *pair)
561 {
562 struct fsl_asrc *asrc = pair->asrc;
563 enum asrc_pair_index index = pair->index;
564
565 /* Stop the current pair */
566 regmap_update_bits(asrc->regmap, REG_ASRCTR,
567 ASRCTR_ASRCEi_MASK(index), 0);
568 }
569
570 /**
571 * fsl_asrc_get_dma_channel- Get DMA channel according to the pair and direction.
572 * @pair: pointer to pair
573 * @dir: DMA direction
574 */
fsl_asrc_get_dma_channel(struct fsl_asrc_pair * pair,bool dir)575 static struct dma_chan *fsl_asrc_get_dma_channel(struct fsl_asrc_pair *pair,
576 bool dir)
577 {
578 struct fsl_asrc *asrc = pair->asrc;
579 enum asrc_pair_index index = pair->index;
580 char name[4];
581
582 sprintf(name, "%cx%c", dir == IN ? 'r' : 't', index + 'a');
583
584 return dma_request_slave_channel(&asrc->pdev->dev, name);
585 }
586
fsl_asrc_dai_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)587 static int fsl_asrc_dai_startup(struct snd_pcm_substream *substream,
588 struct snd_soc_dai *dai)
589 {
590 struct fsl_asrc *asrc = snd_soc_dai_get_drvdata(dai);
591 struct fsl_asrc_priv *asrc_priv = asrc->private;
592
593 /* Odd channel number is not valid for older ASRC (channel_bits==3) */
594 if (asrc_priv->soc->channel_bits == 3)
595 snd_pcm_hw_constraint_step(substream->runtime, 0,
596 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
597
598
599 return snd_pcm_hw_constraint_list(substream->runtime, 0,
600 SNDRV_PCM_HW_PARAM_RATE, &fsl_asrc_rate_constraints);
601 }
602
603 /* Select proper clock source for internal ratio mode */
fsl_asrc_select_clk(struct fsl_asrc_priv * asrc_priv,struct fsl_asrc_pair * pair,int in_rate,int out_rate)604 static void fsl_asrc_select_clk(struct fsl_asrc_priv *asrc_priv,
605 struct fsl_asrc_pair *pair,
606 int in_rate,
607 int out_rate)
608 {
609 struct fsl_asrc_pair_priv *pair_priv = pair->private;
610 struct asrc_config *config = pair_priv->config;
611 int rate[2], select_clk[2]; /* Array size 2 means IN and OUT */
612 int clk_rate, clk_index;
613 int i, j;
614
615 rate[IN] = in_rate;
616 rate[OUT] = out_rate;
617
618 /* Select proper clock source for internal ratio mode */
619 for (j = 0; j < 2; j++) {
620 for (i = 0; i < ASRC_CLK_MAP_LEN; i++) {
621 clk_index = asrc_priv->clk_map[j][i];
622 clk_rate = clk_get_rate(asrc_priv->asrck_clk[clk_index]);
623 /* Only match a perfect clock source with no remainder */
624 if (clk_rate != 0 && (clk_rate / rate[j]) <= 1024 &&
625 (clk_rate % rate[j]) == 0)
626 break;
627 }
628
629 select_clk[j] = i;
630 }
631
632 /* Switch to ideal ratio mode if there is no proper clock source */
633 if (select_clk[IN] == ASRC_CLK_MAP_LEN || select_clk[OUT] == ASRC_CLK_MAP_LEN) {
634 select_clk[IN] = INCLK_NONE;
635 select_clk[OUT] = OUTCLK_ASRCK1_CLK;
636 }
637
638 config->inclk = select_clk[IN];
639 config->outclk = select_clk[OUT];
640 }
641
fsl_asrc_dai_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)642 static int fsl_asrc_dai_hw_params(struct snd_pcm_substream *substream,
643 struct snd_pcm_hw_params *params,
644 struct snd_soc_dai *dai)
645 {
646 struct fsl_asrc *asrc = snd_soc_dai_get_drvdata(dai);
647 struct fsl_asrc_priv *asrc_priv = asrc->private;
648 struct snd_pcm_runtime *runtime = substream->runtime;
649 struct fsl_asrc_pair *pair = runtime->private_data;
650 struct fsl_asrc_pair_priv *pair_priv = pair->private;
651 unsigned int channels = params_channels(params);
652 unsigned int rate = params_rate(params);
653 struct asrc_config config;
654 int ret;
655
656 ret = fsl_asrc_request_pair(channels, pair);
657 if (ret) {
658 dev_err(dai->dev, "fail to request asrc pair\n");
659 return ret;
660 }
661
662 pair_priv->config = &config;
663
664 config.pair = pair->index;
665 config.channel_num = channels;
666
667 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
668 config.input_format = params_format(params);
669 config.output_format = asrc->asrc_format;
670 config.input_sample_rate = rate;
671 config.output_sample_rate = asrc->asrc_rate;
672 } else {
673 config.input_format = asrc->asrc_format;
674 config.output_format = params_format(params);
675 config.input_sample_rate = asrc->asrc_rate;
676 config.output_sample_rate = rate;
677 }
678
679 fsl_asrc_select_clk(asrc_priv, pair,
680 config.input_sample_rate,
681 config.output_sample_rate);
682
683 ret = fsl_asrc_config_pair(pair, false);
684 if (ret) {
685 dev_err(dai->dev, "fail to config asrc pair\n");
686 return ret;
687 }
688
689 return 0;
690 }
691
fsl_asrc_dai_hw_free(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)692 static int fsl_asrc_dai_hw_free(struct snd_pcm_substream *substream,
693 struct snd_soc_dai *dai)
694 {
695 struct snd_pcm_runtime *runtime = substream->runtime;
696 struct fsl_asrc_pair *pair = runtime->private_data;
697
698 if (pair)
699 fsl_asrc_release_pair(pair);
700
701 return 0;
702 }
703
fsl_asrc_dai_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)704 static int fsl_asrc_dai_trigger(struct snd_pcm_substream *substream, int cmd,
705 struct snd_soc_dai *dai)
706 {
707 struct snd_pcm_runtime *runtime = substream->runtime;
708 struct fsl_asrc_pair *pair = runtime->private_data;
709
710 switch (cmd) {
711 case SNDRV_PCM_TRIGGER_START:
712 case SNDRV_PCM_TRIGGER_RESUME:
713 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
714 fsl_asrc_start_pair(pair);
715 break;
716 case SNDRV_PCM_TRIGGER_STOP:
717 case SNDRV_PCM_TRIGGER_SUSPEND:
718 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
719 fsl_asrc_stop_pair(pair);
720 break;
721 default:
722 return -EINVAL;
723 }
724
725 return 0;
726 }
727
728 static const struct snd_soc_dai_ops fsl_asrc_dai_ops = {
729 .startup = fsl_asrc_dai_startup,
730 .hw_params = fsl_asrc_dai_hw_params,
731 .hw_free = fsl_asrc_dai_hw_free,
732 .trigger = fsl_asrc_dai_trigger,
733 };
734
fsl_asrc_dai_probe(struct snd_soc_dai * dai)735 static int fsl_asrc_dai_probe(struct snd_soc_dai *dai)
736 {
737 struct fsl_asrc *asrc = snd_soc_dai_get_drvdata(dai);
738
739 snd_soc_dai_init_dma_data(dai, &asrc->dma_params_tx,
740 &asrc->dma_params_rx);
741
742 return 0;
743 }
744
745 #define FSL_ASRC_FORMATS (SNDRV_PCM_FMTBIT_S24_LE | \
746 SNDRV_PCM_FMTBIT_S16_LE | \
747 SNDRV_PCM_FMTBIT_S24_3LE)
748
749 static struct snd_soc_dai_driver fsl_asrc_dai = {
750 .probe = fsl_asrc_dai_probe,
751 .playback = {
752 .stream_name = "ASRC-Playback",
753 .channels_min = 1,
754 .channels_max = 10,
755 .rate_min = 5512,
756 .rate_max = 192000,
757 .rates = SNDRV_PCM_RATE_KNOT,
758 .formats = FSL_ASRC_FORMATS |
759 SNDRV_PCM_FMTBIT_S8,
760 },
761 .capture = {
762 .stream_name = "ASRC-Capture",
763 .channels_min = 1,
764 .channels_max = 10,
765 .rate_min = 5512,
766 .rate_max = 192000,
767 .rates = SNDRV_PCM_RATE_KNOT,
768 .formats = FSL_ASRC_FORMATS,
769 },
770 .ops = &fsl_asrc_dai_ops,
771 };
772
fsl_asrc_readable_reg(struct device * dev,unsigned int reg)773 static bool fsl_asrc_readable_reg(struct device *dev, unsigned int reg)
774 {
775 switch (reg) {
776 case REG_ASRCTR:
777 case REG_ASRIER:
778 case REG_ASRCNCR:
779 case REG_ASRCFG:
780 case REG_ASRCSR:
781 case REG_ASRCDR1:
782 case REG_ASRCDR2:
783 case REG_ASRSTR:
784 case REG_ASRPM1:
785 case REG_ASRPM2:
786 case REG_ASRPM3:
787 case REG_ASRPM4:
788 case REG_ASRPM5:
789 case REG_ASRTFR1:
790 case REG_ASRCCR:
791 case REG_ASRDOA:
792 case REG_ASRDOB:
793 case REG_ASRDOC:
794 case REG_ASRIDRHA:
795 case REG_ASRIDRLA:
796 case REG_ASRIDRHB:
797 case REG_ASRIDRLB:
798 case REG_ASRIDRHC:
799 case REG_ASRIDRLC:
800 case REG_ASR76K:
801 case REG_ASR56K:
802 case REG_ASRMCRA:
803 case REG_ASRFSTA:
804 case REG_ASRMCRB:
805 case REG_ASRFSTB:
806 case REG_ASRMCRC:
807 case REG_ASRFSTC:
808 case REG_ASRMCR1A:
809 case REG_ASRMCR1B:
810 case REG_ASRMCR1C:
811 return true;
812 default:
813 return false;
814 }
815 }
816
fsl_asrc_volatile_reg(struct device * dev,unsigned int reg)817 static bool fsl_asrc_volatile_reg(struct device *dev, unsigned int reg)
818 {
819 switch (reg) {
820 case REG_ASRSTR:
821 case REG_ASRDIA:
822 case REG_ASRDIB:
823 case REG_ASRDIC:
824 case REG_ASRDOA:
825 case REG_ASRDOB:
826 case REG_ASRDOC:
827 case REG_ASRFSTA:
828 case REG_ASRFSTB:
829 case REG_ASRFSTC:
830 case REG_ASRCFG:
831 return true;
832 default:
833 return false;
834 }
835 }
836
fsl_asrc_writeable_reg(struct device * dev,unsigned int reg)837 static bool fsl_asrc_writeable_reg(struct device *dev, unsigned int reg)
838 {
839 switch (reg) {
840 case REG_ASRCTR:
841 case REG_ASRIER:
842 case REG_ASRCNCR:
843 case REG_ASRCFG:
844 case REG_ASRCSR:
845 case REG_ASRCDR1:
846 case REG_ASRCDR2:
847 case REG_ASRSTR:
848 case REG_ASRPM1:
849 case REG_ASRPM2:
850 case REG_ASRPM3:
851 case REG_ASRPM4:
852 case REG_ASRPM5:
853 case REG_ASRTFR1:
854 case REG_ASRCCR:
855 case REG_ASRDIA:
856 case REG_ASRDIB:
857 case REG_ASRDIC:
858 case REG_ASRIDRHA:
859 case REG_ASRIDRLA:
860 case REG_ASRIDRHB:
861 case REG_ASRIDRLB:
862 case REG_ASRIDRHC:
863 case REG_ASRIDRLC:
864 case REG_ASR76K:
865 case REG_ASR56K:
866 case REG_ASRMCRA:
867 case REG_ASRMCRB:
868 case REG_ASRMCRC:
869 case REG_ASRMCR1A:
870 case REG_ASRMCR1B:
871 case REG_ASRMCR1C:
872 return true;
873 default:
874 return false;
875 }
876 }
877
878 static struct reg_default fsl_asrc_reg[] = {
879 { REG_ASRCTR, 0x0000 }, { REG_ASRIER, 0x0000 },
880 { REG_ASRCNCR, 0x0000 }, { REG_ASRCFG, 0x0000 },
881 { REG_ASRCSR, 0x0000 }, { REG_ASRCDR1, 0x0000 },
882 { REG_ASRCDR2, 0x0000 }, { REG_ASRSTR, 0x0000 },
883 { REG_ASRRA, 0x0000 }, { REG_ASRRB, 0x0000 },
884 { REG_ASRRC, 0x0000 }, { REG_ASRPM1, 0x0000 },
885 { REG_ASRPM2, 0x0000 }, { REG_ASRPM3, 0x0000 },
886 { REG_ASRPM4, 0x0000 }, { REG_ASRPM5, 0x0000 },
887 { REG_ASRTFR1, 0x0000 }, { REG_ASRCCR, 0x0000 },
888 { REG_ASRDIA, 0x0000 }, { REG_ASRDOA, 0x0000 },
889 { REG_ASRDIB, 0x0000 }, { REG_ASRDOB, 0x0000 },
890 { REG_ASRDIC, 0x0000 }, { REG_ASRDOC, 0x0000 },
891 { REG_ASRIDRHA, 0x0000 }, { REG_ASRIDRLA, 0x0000 },
892 { REG_ASRIDRHB, 0x0000 }, { REG_ASRIDRLB, 0x0000 },
893 { REG_ASRIDRHC, 0x0000 }, { REG_ASRIDRLC, 0x0000 },
894 { REG_ASR76K, 0x0A47 }, { REG_ASR56K, 0x0DF3 },
895 { REG_ASRMCRA, 0x0000 }, { REG_ASRFSTA, 0x0000 },
896 { REG_ASRMCRB, 0x0000 }, { REG_ASRFSTB, 0x0000 },
897 { REG_ASRMCRC, 0x0000 }, { REG_ASRFSTC, 0x0000 },
898 { REG_ASRMCR1A, 0x0000 }, { REG_ASRMCR1B, 0x0000 },
899 { REG_ASRMCR1C, 0x0000 },
900 };
901
902 static const struct regmap_config fsl_asrc_regmap_config = {
903 .reg_bits = 32,
904 .reg_stride = 4,
905 .val_bits = 32,
906
907 .max_register = REG_ASRMCR1C,
908 .reg_defaults = fsl_asrc_reg,
909 .num_reg_defaults = ARRAY_SIZE(fsl_asrc_reg),
910 .readable_reg = fsl_asrc_readable_reg,
911 .volatile_reg = fsl_asrc_volatile_reg,
912 .writeable_reg = fsl_asrc_writeable_reg,
913 .cache_type = REGCACHE_FLAT,
914 };
915
916 /**
917 * fsl_asrc_init - Initialize ASRC registers with a default configuration
918 * @asrc: ASRC context
919 */
fsl_asrc_init(struct fsl_asrc * asrc)920 static int fsl_asrc_init(struct fsl_asrc *asrc)
921 {
922 unsigned long ipg_rate;
923
924 /* Halt ASRC internal FP when input FIFO needs data for pair A, B, C */
925 regmap_write(asrc->regmap, REG_ASRCTR, ASRCTR_ASRCEN);
926
927 /* Disable interrupt by default */
928 regmap_write(asrc->regmap, REG_ASRIER, 0x0);
929
930 /* Apply recommended settings for parameters from Reference Manual */
931 regmap_write(asrc->regmap, REG_ASRPM1, 0x7fffff);
932 regmap_write(asrc->regmap, REG_ASRPM2, 0x255555);
933 regmap_write(asrc->regmap, REG_ASRPM3, 0xff7280);
934 regmap_write(asrc->regmap, REG_ASRPM4, 0xff7280);
935 regmap_write(asrc->regmap, REG_ASRPM5, 0xff7280);
936
937 /* Base address for task queue FIFO. Set to 0x7C */
938 regmap_update_bits(asrc->regmap, REG_ASRTFR1,
939 ASRTFR1_TF_BASE_MASK, ASRTFR1_TF_BASE(0xfc));
940
941 /*
942 * Set the period of the 76KHz and 56KHz sampling clocks based on
943 * the ASRC processing clock.
944 * On iMX6, ipg_clk = 133MHz, REG_ASR76K = 0x06D6, REG_ASR56K = 0x0947
945 */
946 ipg_rate = clk_get_rate(asrc->ipg_clk);
947 regmap_write(asrc->regmap, REG_ASR76K, ipg_rate / 76000);
948 return regmap_write(asrc->regmap, REG_ASR56K, ipg_rate / 56000);
949 }
950
951 /**
952 * fsl_asrc_isr- Interrupt handler for ASRC
953 * @irq: irq number
954 * @dev_id: ASRC context
955 */
fsl_asrc_isr(int irq,void * dev_id)956 static irqreturn_t fsl_asrc_isr(int irq, void *dev_id)
957 {
958 struct fsl_asrc *asrc = (struct fsl_asrc *)dev_id;
959 struct device *dev = &asrc->pdev->dev;
960 enum asrc_pair_index index;
961 u32 status;
962
963 regmap_read(asrc->regmap, REG_ASRSTR, &status);
964
965 /* Clean overload error */
966 regmap_write(asrc->regmap, REG_ASRSTR, ASRSTR_AOLE);
967
968 /*
969 * We here use dev_dbg() for all exceptions because ASRC itself does
970 * not care if FIFO overflowed or underrun while a warning in the
971 * interrupt would result a ridged conversion.
972 */
973 for (index = ASRC_PAIR_A; index < ASRC_PAIR_MAX_NUM; index++) {
974 if (!asrc->pair[index])
975 continue;
976
977 if (status & ASRSTR_ATQOL) {
978 asrc->pair[index]->error |= ASRC_TASK_Q_OVERLOAD;
979 dev_dbg(dev, "ASRC Task Queue FIFO overload\n");
980 }
981
982 if (status & ASRSTR_AOOL(index)) {
983 asrc->pair[index]->error |= ASRC_OUTPUT_TASK_OVERLOAD;
984 pair_dbg("Output Task Overload\n");
985 }
986
987 if (status & ASRSTR_AIOL(index)) {
988 asrc->pair[index]->error |= ASRC_INPUT_TASK_OVERLOAD;
989 pair_dbg("Input Task Overload\n");
990 }
991
992 if (status & ASRSTR_AODO(index)) {
993 asrc->pair[index]->error |= ASRC_OUTPUT_BUFFER_OVERFLOW;
994 pair_dbg("Output Data Buffer has overflowed\n");
995 }
996
997 if (status & ASRSTR_AIDU(index)) {
998 asrc->pair[index]->error |= ASRC_INPUT_BUFFER_UNDERRUN;
999 pair_dbg("Input Data Buffer has underflowed\n");
1000 }
1001 }
1002
1003 return IRQ_HANDLED;
1004 }
1005
fsl_asrc_get_fifo_addr(u8 dir,enum asrc_pair_index index)1006 static int fsl_asrc_get_fifo_addr(u8 dir, enum asrc_pair_index index)
1007 {
1008 return REG_ASRDx(dir, index);
1009 }
1010
1011 static int fsl_asrc_runtime_resume(struct device *dev);
1012 static int fsl_asrc_runtime_suspend(struct device *dev);
1013
fsl_asrc_probe(struct platform_device * pdev)1014 static int fsl_asrc_probe(struct platform_device *pdev)
1015 {
1016 struct device_node *np = pdev->dev.of_node;
1017 struct fsl_asrc_priv *asrc_priv;
1018 struct fsl_asrc *asrc;
1019 struct resource *res;
1020 void __iomem *regs;
1021 int irq, ret, i;
1022 u32 map_idx;
1023 char tmp[16];
1024 u32 width;
1025
1026 asrc = devm_kzalloc(&pdev->dev, sizeof(*asrc), GFP_KERNEL);
1027 if (!asrc)
1028 return -ENOMEM;
1029
1030 asrc_priv = devm_kzalloc(&pdev->dev, sizeof(*asrc_priv), GFP_KERNEL);
1031 if (!asrc_priv)
1032 return -ENOMEM;
1033
1034 asrc->pdev = pdev;
1035 asrc->private = asrc_priv;
1036
1037 /* Get the addresses and IRQ */
1038 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1039 regs = devm_ioremap_resource(&pdev->dev, res);
1040 if (IS_ERR(regs))
1041 return PTR_ERR(regs);
1042
1043 asrc->paddr = res->start;
1044
1045 asrc->regmap = devm_regmap_init_mmio(&pdev->dev, regs, &fsl_asrc_regmap_config);
1046 if (IS_ERR(asrc->regmap)) {
1047 dev_err(&pdev->dev, "failed to init regmap\n");
1048 return PTR_ERR(asrc->regmap);
1049 }
1050
1051 irq = platform_get_irq(pdev, 0);
1052 if (irq < 0)
1053 return irq;
1054
1055 ret = devm_request_irq(&pdev->dev, irq, fsl_asrc_isr, 0,
1056 dev_name(&pdev->dev), asrc);
1057 if (ret) {
1058 dev_err(&pdev->dev, "failed to claim irq %u: %d\n", irq, ret);
1059 return ret;
1060 }
1061
1062 asrc->mem_clk = devm_clk_get(&pdev->dev, "mem");
1063 if (IS_ERR(asrc->mem_clk)) {
1064 dev_err(&pdev->dev, "failed to get mem clock\n");
1065 return PTR_ERR(asrc->mem_clk);
1066 }
1067
1068 asrc->ipg_clk = devm_clk_get(&pdev->dev, "ipg");
1069 if (IS_ERR(asrc->ipg_clk)) {
1070 dev_err(&pdev->dev, "failed to get ipg clock\n");
1071 return PTR_ERR(asrc->ipg_clk);
1072 }
1073
1074 asrc->spba_clk = devm_clk_get(&pdev->dev, "spba");
1075 if (IS_ERR(asrc->spba_clk))
1076 dev_warn(&pdev->dev, "failed to get spba clock\n");
1077
1078 for (i = 0; i < ASRC_CLK_MAX_NUM; i++) {
1079 sprintf(tmp, "asrck_%x", i);
1080 asrc_priv->asrck_clk[i] = devm_clk_get(&pdev->dev, tmp);
1081 if (IS_ERR(asrc_priv->asrck_clk[i])) {
1082 dev_err(&pdev->dev, "failed to get %s clock\n", tmp);
1083 return PTR_ERR(asrc_priv->asrck_clk[i]);
1084 }
1085 }
1086
1087 asrc_priv->soc = of_device_get_match_data(&pdev->dev);
1088 asrc->use_edma = asrc_priv->soc->use_edma;
1089 asrc->get_dma_channel = fsl_asrc_get_dma_channel;
1090 asrc->request_pair = fsl_asrc_request_pair;
1091 asrc->release_pair = fsl_asrc_release_pair;
1092 asrc->get_fifo_addr = fsl_asrc_get_fifo_addr;
1093 asrc->pair_priv_size = sizeof(struct fsl_asrc_pair_priv);
1094
1095 if (of_device_is_compatible(np, "fsl,imx35-asrc")) {
1096 asrc_priv->clk_map[IN] = input_clk_map_imx35;
1097 asrc_priv->clk_map[OUT] = output_clk_map_imx35;
1098 } else if (of_device_is_compatible(np, "fsl,imx53-asrc")) {
1099 asrc_priv->clk_map[IN] = input_clk_map_imx53;
1100 asrc_priv->clk_map[OUT] = output_clk_map_imx53;
1101 } else if (of_device_is_compatible(np, "fsl,imx8qm-asrc") ||
1102 of_device_is_compatible(np, "fsl,imx8qxp-asrc")) {
1103 ret = of_property_read_u32(np, "fsl,asrc-clk-map", &map_idx);
1104 if (ret) {
1105 dev_err(&pdev->dev, "failed to get clk map index\n");
1106 return ret;
1107 }
1108
1109 if (map_idx > 1) {
1110 dev_err(&pdev->dev, "unsupported clk map index\n");
1111 return -EINVAL;
1112 }
1113 if (of_device_is_compatible(np, "fsl,imx8qm-asrc")) {
1114 asrc_priv->clk_map[IN] = clk_map_imx8qm[map_idx];
1115 asrc_priv->clk_map[OUT] = clk_map_imx8qm[map_idx];
1116 } else {
1117 asrc_priv->clk_map[IN] = clk_map_imx8qxp[map_idx];
1118 asrc_priv->clk_map[OUT] = clk_map_imx8qxp[map_idx];
1119 }
1120 }
1121
1122 asrc->channel_avail = 10;
1123
1124 ret = of_property_read_u32(np, "fsl,asrc-rate",
1125 &asrc->asrc_rate);
1126 if (ret) {
1127 dev_err(&pdev->dev, "failed to get output rate\n");
1128 return ret;
1129 }
1130
1131 ret = of_property_read_u32(np, "fsl,asrc-format", &asrc->asrc_format);
1132 if (ret) {
1133 ret = of_property_read_u32(np, "fsl,asrc-width", &width);
1134 if (ret) {
1135 dev_err(&pdev->dev, "failed to decide output format\n");
1136 return ret;
1137 }
1138
1139 switch (width) {
1140 case 16:
1141 asrc->asrc_format = SNDRV_PCM_FORMAT_S16_LE;
1142 break;
1143 case 24:
1144 asrc->asrc_format = SNDRV_PCM_FORMAT_S24_LE;
1145 break;
1146 default:
1147 dev_warn(&pdev->dev,
1148 "unsupported width, use default S24_LE\n");
1149 asrc->asrc_format = SNDRV_PCM_FORMAT_S24_LE;
1150 break;
1151 }
1152 }
1153
1154 if (!(FSL_ASRC_FORMATS & (1ULL << asrc->asrc_format))) {
1155 dev_warn(&pdev->dev, "unsupported width, use default S24_LE\n");
1156 asrc->asrc_format = SNDRV_PCM_FORMAT_S24_LE;
1157 }
1158
1159 platform_set_drvdata(pdev, asrc);
1160 spin_lock_init(&asrc->lock);
1161 pm_runtime_enable(&pdev->dev);
1162 if (!pm_runtime_enabled(&pdev->dev)) {
1163 ret = fsl_asrc_runtime_resume(&pdev->dev);
1164 if (ret)
1165 goto err_pm_disable;
1166 }
1167
1168 ret = pm_runtime_get_sync(&pdev->dev);
1169 if (ret < 0) {
1170 pm_runtime_put_noidle(&pdev->dev);
1171 goto err_pm_get_sync;
1172 }
1173
1174 ret = fsl_asrc_init(asrc);
1175 if (ret) {
1176 dev_err(&pdev->dev, "failed to init asrc %d\n", ret);
1177 goto err_pm_get_sync;
1178 }
1179
1180 ret = pm_runtime_put_sync(&pdev->dev);
1181 if (ret < 0)
1182 goto err_pm_get_sync;
1183
1184 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_asrc_component,
1185 &fsl_asrc_dai, 1);
1186 if (ret) {
1187 dev_err(&pdev->dev, "failed to register ASoC DAI\n");
1188 goto err_pm_get_sync;
1189 }
1190
1191 return 0;
1192
1193 err_pm_get_sync:
1194 if (!pm_runtime_status_suspended(&pdev->dev))
1195 fsl_asrc_runtime_suspend(&pdev->dev);
1196 err_pm_disable:
1197 pm_runtime_disable(&pdev->dev);
1198 return ret;
1199 }
1200
fsl_asrc_remove(struct platform_device * pdev)1201 static int fsl_asrc_remove(struct platform_device *pdev)
1202 {
1203 pm_runtime_disable(&pdev->dev);
1204 if (!pm_runtime_status_suspended(&pdev->dev))
1205 fsl_asrc_runtime_suspend(&pdev->dev);
1206
1207 return 0;
1208 }
1209
fsl_asrc_runtime_resume(struct device * dev)1210 static int fsl_asrc_runtime_resume(struct device *dev)
1211 {
1212 struct fsl_asrc *asrc = dev_get_drvdata(dev);
1213 struct fsl_asrc_priv *asrc_priv = asrc->private;
1214 int i, ret;
1215 u32 asrctr;
1216
1217 ret = clk_prepare_enable(asrc->mem_clk);
1218 if (ret)
1219 return ret;
1220 ret = clk_prepare_enable(asrc->ipg_clk);
1221 if (ret)
1222 goto disable_mem_clk;
1223 if (!IS_ERR(asrc->spba_clk)) {
1224 ret = clk_prepare_enable(asrc->spba_clk);
1225 if (ret)
1226 goto disable_ipg_clk;
1227 }
1228 for (i = 0; i < ASRC_CLK_MAX_NUM; i++) {
1229 ret = clk_prepare_enable(asrc_priv->asrck_clk[i]);
1230 if (ret)
1231 goto disable_asrck_clk;
1232 }
1233
1234 /* Stop all pairs provisionally */
1235 regmap_read(asrc->regmap, REG_ASRCTR, &asrctr);
1236 regmap_update_bits(asrc->regmap, REG_ASRCTR,
1237 ASRCTR_ASRCEi_ALL_MASK, 0);
1238
1239 /* Restore all registers */
1240 regcache_cache_only(asrc->regmap, false);
1241 regcache_mark_dirty(asrc->regmap);
1242 regcache_sync(asrc->regmap);
1243
1244 regmap_update_bits(asrc->regmap, REG_ASRCFG,
1245 ASRCFG_NDPRi_ALL_MASK | ASRCFG_POSTMODi_ALL_MASK |
1246 ASRCFG_PREMODi_ALL_MASK, asrc_priv->regcache_cfg);
1247
1248 /* Restart enabled pairs */
1249 regmap_update_bits(asrc->regmap, REG_ASRCTR,
1250 ASRCTR_ASRCEi_ALL_MASK, asrctr);
1251
1252 return 0;
1253
1254 disable_asrck_clk:
1255 for (i--; i >= 0; i--)
1256 clk_disable_unprepare(asrc_priv->asrck_clk[i]);
1257 if (!IS_ERR(asrc->spba_clk))
1258 clk_disable_unprepare(asrc->spba_clk);
1259 disable_ipg_clk:
1260 clk_disable_unprepare(asrc->ipg_clk);
1261 disable_mem_clk:
1262 clk_disable_unprepare(asrc->mem_clk);
1263 return ret;
1264 }
1265
fsl_asrc_runtime_suspend(struct device * dev)1266 static int fsl_asrc_runtime_suspend(struct device *dev)
1267 {
1268 struct fsl_asrc *asrc = dev_get_drvdata(dev);
1269 struct fsl_asrc_priv *asrc_priv = asrc->private;
1270 int i;
1271
1272 regmap_read(asrc->regmap, REG_ASRCFG,
1273 &asrc_priv->regcache_cfg);
1274
1275 regcache_cache_only(asrc->regmap, true);
1276
1277 for (i = 0; i < ASRC_CLK_MAX_NUM; i++)
1278 clk_disable_unprepare(asrc_priv->asrck_clk[i]);
1279 if (!IS_ERR(asrc->spba_clk))
1280 clk_disable_unprepare(asrc->spba_clk);
1281 clk_disable_unprepare(asrc->ipg_clk);
1282 clk_disable_unprepare(asrc->mem_clk);
1283
1284 return 0;
1285 }
1286
1287 static const struct dev_pm_ops fsl_asrc_pm = {
1288 SET_RUNTIME_PM_OPS(fsl_asrc_runtime_suspend, fsl_asrc_runtime_resume, NULL)
1289 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1290 pm_runtime_force_resume)
1291 };
1292
1293 static const struct fsl_asrc_soc_data fsl_asrc_imx35_data = {
1294 .use_edma = false,
1295 .channel_bits = 3,
1296 };
1297
1298 static const struct fsl_asrc_soc_data fsl_asrc_imx53_data = {
1299 .use_edma = false,
1300 .channel_bits = 4,
1301 };
1302
1303 static const struct fsl_asrc_soc_data fsl_asrc_imx8qm_data = {
1304 .use_edma = true,
1305 .channel_bits = 4,
1306 };
1307
1308 static const struct fsl_asrc_soc_data fsl_asrc_imx8qxp_data = {
1309 .use_edma = true,
1310 .channel_bits = 4,
1311 };
1312
1313 static const struct of_device_id fsl_asrc_ids[] = {
1314 { .compatible = "fsl,imx35-asrc", .data = &fsl_asrc_imx35_data },
1315 { .compatible = "fsl,imx53-asrc", .data = &fsl_asrc_imx53_data },
1316 { .compatible = "fsl,imx8qm-asrc", .data = &fsl_asrc_imx8qm_data },
1317 { .compatible = "fsl,imx8qxp-asrc", .data = &fsl_asrc_imx8qxp_data },
1318 {}
1319 };
1320 MODULE_DEVICE_TABLE(of, fsl_asrc_ids);
1321
1322 static struct platform_driver fsl_asrc_driver = {
1323 .probe = fsl_asrc_probe,
1324 .remove = fsl_asrc_remove,
1325 .driver = {
1326 .name = "fsl-asrc",
1327 .of_match_table = fsl_asrc_ids,
1328 .pm = &fsl_asrc_pm,
1329 },
1330 };
1331 module_platform_driver(fsl_asrc_driver);
1332
1333 MODULE_DESCRIPTION("Freescale ASRC ASoC driver");
1334 MODULE_AUTHOR("Nicolin Chen <nicoleotsuka@gmail.com>");
1335 MODULE_ALIAS("platform:fsl-asrc");
1336 MODULE_LICENSE("GPL v2");
1337