1 /*
2 * Copyright (c) 2010-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #ifndef ATH9K_HW_OPS_H
18 #define ATH9K_HW_OPS_H
19
20 FILE_LICENCE ( BSD2 );
21
22 #include "hw.h"
23
24 /* Hardware core and driver accessible callbacks */
25
ath9k_hw_configpcipowersave(struct ath_hw * ah,int restore,int power_off)26 static inline void ath9k_hw_configpcipowersave(struct ath_hw *ah,
27 int restore,
28 int power_off)
29 {
30 ath9k_hw_ops(ah)->config_pci_powersave(ah, restore, power_off);
31 }
32
ath9k_hw_rxena(struct ath_hw * ah)33 static inline void ath9k_hw_rxena(struct ath_hw *ah)
34 {
35 ath9k_hw_ops(ah)->rx_enable(ah);
36 }
37
ath9k_hw_set_desc_link(struct ath_hw * ah,void * ds,u32 link)38 static inline void ath9k_hw_set_desc_link(struct ath_hw *ah, void *ds,
39 u32 link)
40 {
41 ath9k_hw_ops(ah)->set_desc_link(ds, link);
42 }
43
ath9k_hw_get_desc_link(struct ath_hw * ah,void * ds,u32 ** link)44 static inline void ath9k_hw_get_desc_link(struct ath_hw *ah, void *ds,
45 u32 **link)
46 {
47 ath9k_hw_ops(ah)->get_desc_link(ds, link);
48 }
ath9k_hw_calibrate(struct ath_hw * ah,struct ath9k_channel * chan,u8 rxchainmask,int longcal)49 static inline int ath9k_hw_calibrate(struct ath_hw *ah,
50 struct ath9k_channel *chan,
51 u8 rxchainmask,
52 int longcal)
53 {
54 return ath9k_hw_ops(ah)->calibrate(ah, chan, rxchainmask, longcal);
55 }
56
ath9k_hw_getisr(struct ath_hw * ah,enum ath9k_int * masked)57 static inline int ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
58 {
59 return ath9k_hw_ops(ah)->get_isr(ah, masked);
60 }
61
ath9k_hw_filltxdesc(struct ath_hw * ah,void * ds,u32 seglen,int is_firstseg,int is_lastseg,const void * ds0,u32 buf_addr,unsigned int qcu)62 static inline void ath9k_hw_filltxdesc(struct ath_hw *ah, void *ds, u32 seglen,
63 int is_firstseg, int is_lastseg,
64 const void *ds0, u32 buf_addr,
65 unsigned int qcu)
66 {
67 ath9k_hw_ops(ah)->fill_txdesc(ah, ds, seglen, is_firstseg, is_lastseg,
68 ds0, buf_addr, qcu);
69 }
70
ath9k_hw_txprocdesc(struct ath_hw * ah,void * ds,struct ath_tx_status * ts)71 static inline int ath9k_hw_txprocdesc(struct ath_hw *ah, void *ds,
72 struct ath_tx_status *ts)
73 {
74 return ath9k_hw_ops(ah)->proc_txdesc(ah, ds, ts);
75 }
76
ath9k_hw_set11n_txdesc(struct ath_hw * ah,void * ds,u32 pktLen,enum ath9k_pkt_type type,u32 txPower,u32 keyIx,enum ath9k_key_type keyType,u32 flags)77 static inline void ath9k_hw_set11n_txdesc(struct ath_hw *ah, void *ds,
78 u32 pktLen, enum ath9k_pkt_type type,
79 u32 txPower, u32 keyIx,
80 enum ath9k_key_type keyType,
81 u32 flags)
82 {
83 ath9k_hw_ops(ah)->set11n_txdesc(ah, ds, pktLen, type, txPower, keyIx,
84 keyType, flags);
85 }
86
ath9k_hw_set11n_ratescenario(struct ath_hw * ah,void * ds,void * lastds,u32 durUpdateEn,u32 rtsctsRate,u32 rtsctsDuration,struct ath9k_11n_rate_series series[],u32 nseries,u32 flags)87 static inline void ath9k_hw_set11n_ratescenario(struct ath_hw *ah, void *ds,
88 void *lastds,
89 u32 durUpdateEn, u32 rtsctsRate,
90 u32 rtsctsDuration,
91 struct ath9k_11n_rate_series series[],
92 u32 nseries, u32 flags)
93 {
94 ath9k_hw_ops(ah)->set11n_ratescenario(ah, ds, lastds, durUpdateEn,
95 rtsctsRate, rtsctsDuration, series,
96 nseries, flags);
97 }
98
ath9k_hw_set11n_aggr_first(struct ath_hw * ah,void * ds,u32 aggrLen)99 static inline void ath9k_hw_set11n_aggr_first(struct ath_hw *ah, void *ds,
100 u32 aggrLen)
101 {
102 ath9k_hw_ops(ah)->set11n_aggr_first(ah, ds, aggrLen);
103 }
104
ath9k_hw_set11n_aggr_middle(struct ath_hw * ah,void * ds,u32 numDelims)105 static inline void ath9k_hw_set11n_aggr_middle(struct ath_hw *ah, void *ds,
106 u32 numDelims)
107 {
108 ath9k_hw_ops(ah)->set11n_aggr_middle(ah, ds, numDelims);
109 }
110
ath9k_hw_set11n_aggr_last(struct ath_hw * ah,void * ds)111 static inline void ath9k_hw_set11n_aggr_last(struct ath_hw *ah, void *ds)
112 {
113 ath9k_hw_ops(ah)->set11n_aggr_last(ah, ds);
114 }
115
ath9k_hw_clr11n_aggr(struct ath_hw * ah,void * ds)116 static inline void ath9k_hw_clr11n_aggr(struct ath_hw *ah, void *ds)
117 {
118 ath9k_hw_ops(ah)->clr11n_aggr(ah, ds);
119 }
120
ath9k_hw_set_clrdmask(struct ath_hw * ah,void * ds,int val)121 static inline void ath9k_hw_set_clrdmask(struct ath_hw *ah, void *ds, int val)
122 {
123 ath9k_hw_ops(ah)->set_clrdmask(ah, ds, val);
124 }
125
ath9k_hw_antdiv_comb_conf_get(struct ath_hw * ah,struct ath_hw_antcomb_conf * antconf)126 static inline void ath9k_hw_antdiv_comb_conf_get(struct ath_hw *ah,
127 struct ath_hw_antcomb_conf *antconf)
128 {
129 ath9k_hw_ops(ah)->antdiv_comb_conf_get(ah, antconf);
130 }
131
ath9k_hw_antdiv_comb_conf_set(struct ath_hw * ah,struct ath_hw_antcomb_conf * antconf)132 static inline void ath9k_hw_antdiv_comb_conf_set(struct ath_hw *ah,
133 struct ath_hw_antcomb_conf *antconf)
134 {
135 ath9k_hw_ops(ah)->antdiv_comb_conf_set(ah, antconf);
136 }
137
138 /* Private hardware call ops */
139
140 /* PHY ops */
141
ath9k_hw_rf_set_freq(struct ath_hw * ah,struct ath9k_channel * chan)142 static inline int ath9k_hw_rf_set_freq(struct ath_hw *ah,
143 struct ath9k_channel *chan)
144 {
145 return ath9k_hw_private_ops(ah)->rf_set_freq(ah, chan);
146 }
147
ath9k_hw_spur_mitigate_freq(struct ath_hw * ah,struct ath9k_channel * chan)148 static inline void ath9k_hw_spur_mitigate_freq(struct ath_hw *ah,
149 struct ath9k_channel *chan)
150 {
151 ath9k_hw_private_ops(ah)->spur_mitigate_freq(ah, chan);
152 }
153
ath9k_hw_rf_alloc_ext_banks(struct ath_hw * ah)154 static inline int ath9k_hw_rf_alloc_ext_banks(struct ath_hw *ah)
155 {
156 if (!ath9k_hw_private_ops(ah)->rf_alloc_ext_banks)
157 return 0;
158
159 return ath9k_hw_private_ops(ah)->rf_alloc_ext_banks(ah);
160 }
161
ath9k_hw_rf_free_ext_banks(struct ath_hw * ah)162 static inline void ath9k_hw_rf_free_ext_banks(struct ath_hw *ah)
163 {
164 if (!ath9k_hw_private_ops(ah)->rf_free_ext_banks)
165 return;
166
167 ath9k_hw_private_ops(ah)->rf_free_ext_banks(ah);
168 }
169
ath9k_hw_set_rf_regs(struct ath_hw * ah,struct ath9k_channel * chan,u16 modesIndex)170 static inline int ath9k_hw_set_rf_regs(struct ath_hw *ah,
171 struct ath9k_channel *chan,
172 u16 modesIndex)
173 {
174 if (!ath9k_hw_private_ops(ah)->set_rf_regs)
175 return 1;
176
177 return ath9k_hw_private_ops(ah)->set_rf_regs(ah, chan, modesIndex);
178 }
179
ath9k_hw_init_bb(struct ath_hw * ah,struct ath9k_channel * chan)180 static inline void ath9k_hw_init_bb(struct ath_hw *ah,
181 struct ath9k_channel *chan)
182 {
183 return ath9k_hw_private_ops(ah)->init_bb(ah, chan);
184 }
185
ath9k_hw_set_channel_regs(struct ath_hw * ah,struct ath9k_channel * chan)186 static inline void ath9k_hw_set_channel_regs(struct ath_hw *ah,
187 struct ath9k_channel *chan)
188 {
189 return ath9k_hw_private_ops(ah)->set_channel_regs(ah, chan);
190 }
191
ath9k_hw_process_ini(struct ath_hw * ah,struct ath9k_channel * chan)192 static inline int ath9k_hw_process_ini(struct ath_hw *ah,
193 struct ath9k_channel *chan)
194 {
195 return ath9k_hw_private_ops(ah)->process_ini(ah, chan);
196 }
197
ath9k_olc_init(struct ath_hw * ah)198 static inline void ath9k_olc_init(struct ath_hw *ah)
199 {
200 if (!ath9k_hw_private_ops(ah)->olc_init)
201 return;
202
203 return ath9k_hw_private_ops(ah)->olc_init(ah);
204 }
205
ath9k_hw_set_rfmode(struct ath_hw * ah,struct ath9k_channel * chan)206 static inline void ath9k_hw_set_rfmode(struct ath_hw *ah,
207 struct ath9k_channel *chan)
208 {
209 return ath9k_hw_private_ops(ah)->set_rfmode(ah, chan);
210 }
211
ath9k_hw_mark_phy_inactive(struct ath_hw * ah)212 static inline void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
213 {
214 return ath9k_hw_private_ops(ah)->mark_phy_inactive(ah);
215 }
216
ath9k_hw_set_delta_slope(struct ath_hw * ah,struct ath9k_channel * chan)217 static inline void ath9k_hw_set_delta_slope(struct ath_hw *ah,
218 struct ath9k_channel *chan)
219 {
220 return ath9k_hw_private_ops(ah)->set_delta_slope(ah, chan);
221 }
222
ath9k_hw_rfbus_req(struct ath_hw * ah)223 static inline int ath9k_hw_rfbus_req(struct ath_hw *ah)
224 {
225 return ath9k_hw_private_ops(ah)->rfbus_req(ah);
226 }
227
ath9k_hw_rfbus_done(struct ath_hw * ah)228 static inline void ath9k_hw_rfbus_done(struct ath_hw *ah)
229 {
230 return ath9k_hw_private_ops(ah)->rfbus_done(ah);
231 }
232
ath9k_hw_restore_chainmask(struct ath_hw * ah)233 static inline void ath9k_hw_restore_chainmask(struct ath_hw *ah)
234 {
235 if (!ath9k_hw_private_ops(ah)->restore_chainmask)
236 return;
237
238 return ath9k_hw_private_ops(ah)->restore_chainmask(ah);
239 }
240
ath9k_hw_set_diversity(struct ath_hw * ah,int value)241 static inline void ath9k_hw_set_diversity(struct ath_hw *ah, int value)
242 {
243 return ath9k_hw_private_ops(ah)->set_diversity(ah, value);
244 }
245
ath9k_hw_ani_control(struct ath_hw * ah,enum ath9k_ani_cmd cmd,int param)246 static inline int ath9k_hw_ani_control(struct ath_hw *ah,
247 enum ath9k_ani_cmd cmd, int param)
248 {
249 return ath9k_hw_private_ops(ah)->ani_control(ah, cmd, param);
250 }
251
ath9k_hw_do_getnf(struct ath_hw * ah,int16_t nfarray[NUM_NF_READINGS])252 static inline void ath9k_hw_do_getnf(struct ath_hw *ah,
253 int16_t nfarray[NUM_NF_READINGS])
254 {
255 ath9k_hw_private_ops(ah)->do_getnf(ah, nfarray);
256 }
257
ath9k_hw_init_cal(struct ath_hw * ah,struct ath9k_channel * chan)258 static inline int ath9k_hw_init_cal(struct ath_hw *ah,
259 struct ath9k_channel *chan)
260 {
261 return ath9k_hw_private_ops(ah)->init_cal(ah, chan);
262 }
263
ath9k_hw_setup_calibration(struct ath_hw * ah,struct ath9k_cal_list * currCal)264 static inline void ath9k_hw_setup_calibration(struct ath_hw *ah,
265 struct ath9k_cal_list *currCal)
266 {
267 ath9k_hw_private_ops(ah)->setup_calibration(ah, currCal);
268 }
269
270 #endif /* ATH9K_HW_OPS_H */
271