1 /*
2 ** PPC IR assembler (SSA IR -> machine code).
3 ** Copyright (C) 2005-2014 Mike Pall. See Copyright Notice in luajit.h
4 */
5
6 /* -- Register allocator extensions --------------------------------------- */
7
8 /* Allocate a register with a hint. */
ra_hintalloc(ASMState * as,IRRef ref,Reg hint,RegSet allow)9 static Reg ra_hintalloc(ASMState *as, IRRef ref, Reg hint, RegSet allow)
10 {
11 Reg r = IR(ref)->r;
12 if (ra_noreg(r)) {
13 if (!ra_hashint(r) && !iscrossref(as, ref))
14 ra_sethint(IR(ref)->r, hint); /* Propagate register hint. */
15 r = ra_allocref(as, ref, allow);
16 }
17 ra_noweak(as, r);
18 return r;
19 }
20
21 /* Allocate two source registers for three-operand instructions. */
ra_alloc2(ASMState * as,IRIns * ir,RegSet allow)22 static Reg ra_alloc2(ASMState *as, IRIns *ir, RegSet allow)
23 {
24 IRIns *irl = IR(ir->op1), *irr = IR(ir->op2);
25 Reg left = irl->r, right = irr->r;
26 if (ra_hasreg(left)) {
27 ra_noweak(as, left);
28 if (ra_noreg(right))
29 right = ra_allocref(as, ir->op2, rset_exclude(allow, left));
30 else
31 ra_noweak(as, right);
32 } else if (ra_hasreg(right)) {
33 ra_noweak(as, right);
34 left = ra_allocref(as, ir->op1, rset_exclude(allow, right));
35 } else if (ra_hashint(right)) {
36 right = ra_allocref(as, ir->op2, allow);
37 left = ra_alloc1(as, ir->op1, rset_exclude(allow, right));
38 } else {
39 left = ra_allocref(as, ir->op1, allow);
40 right = ra_alloc1(as, ir->op2, rset_exclude(allow, left));
41 }
42 return left | (right << 8);
43 }
44
45 /* -- Guard handling ------------------------------------------------------ */
46
47 /* Setup exit stubs after the end of each trace. */
asm_exitstub_setup(ASMState * as,ExitNo nexits)48 static void asm_exitstub_setup(ASMState *as, ExitNo nexits)
49 {
50 ExitNo i;
51 MCode *mxp = as->mctop;
52 /* 1: mflr r0; bl ->vm_exit_handler; li r0, traceno; bl <1; bl <1; ... */
53 for (i = nexits-1; (int32_t)i >= 0; i--)
54 *--mxp = PPCI_BL|(((-3-i)&0x00ffffffu)<<2);
55 *--mxp = PPCI_LI|PPCF_T(RID_TMP)|as->T->traceno; /* Read by exit handler. */
56 mxp--;
57 *mxp = PPCI_BL|((((MCode *)(void *)lj_vm_exit_handler-mxp)&0x00ffffffu)<<2);
58 *--mxp = PPCI_MFLR|PPCF_T(RID_TMP);
59 as->mctop = mxp;
60 }
61
asm_exitstub_addr(ASMState * as,ExitNo exitno)62 static MCode *asm_exitstub_addr(ASMState *as, ExitNo exitno)
63 {
64 /* Keep this in-sync with exitstub_trace_addr(). */
65 return as->mctop + exitno + 3;
66 }
67
68 /* Emit conditional branch to exit for guard. */
asm_guardcc(ASMState * as,PPCCC cc)69 static void asm_guardcc(ASMState *as, PPCCC cc)
70 {
71 MCode *target = asm_exitstub_addr(as, as->snapno);
72 MCode *p = as->mcp;
73 if (LJ_UNLIKELY(p == as->invmcp)) {
74 as->loopinv = 1;
75 *p = PPCI_B | (((target-p) & 0x00ffffffu) << 2);
76 emit_condbranch(as, PPCI_BC, cc^4, p);
77 return;
78 }
79 emit_condbranch(as, PPCI_BC, cc, target);
80 }
81
82 /* -- Operand fusion ------------------------------------------------------ */
83
84 /* Limit linear search to this distance. Avoids O(n^2) behavior. */
85 #define CONFLICT_SEARCH_LIM 31
86
87 /* Check if there's no conflicting instruction between curins and ref. */
noconflict(ASMState * as,IRRef ref,IROp conflict)88 static int noconflict(ASMState *as, IRRef ref, IROp conflict)
89 {
90 IRIns *ir = as->ir;
91 IRRef i = as->curins;
92 if (i > ref + CONFLICT_SEARCH_LIM)
93 return 0; /* Give up, ref is too far away. */
94 while (--i > ref)
95 if (ir[i].o == conflict)
96 return 0; /* Conflict found. */
97 return 1; /* Ok, no conflict. */
98 }
99
100 /* Fuse the array base of colocated arrays. */
asm_fuseabase(ASMState * as,IRRef ref)101 static int32_t asm_fuseabase(ASMState *as, IRRef ref)
102 {
103 IRIns *ir = IR(ref);
104 if (ir->o == IR_TNEW && ir->op1 <= LJ_MAX_COLOSIZE &&
105 !neverfuse(as) && noconflict(as, ref, IR_NEWREF))
106 return (int32_t)sizeof(GCtab);
107 return 0;
108 }
109
110 /* Indicates load/store indexed is ok. */
111 #define AHUREF_LSX ((int32_t)0x80000000)
112
113 /* Fuse array/hash/upvalue reference into register+offset operand. */
asm_fuseahuref(ASMState * as,IRRef ref,int32_t * ofsp,RegSet allow)114 static Reg asm_fuseahuref(ASMState *as, IRRef ref, int32_t *ofsp, RegSet allow)
115 {
116 IRIns *ir = IR(ref);
117 if (ra_noreg(ir->r)) {
118 if (ir->o == IR_AREF) {
119 if (mayfuse(as, ref)) {
120 if (irref_isk(ir->op2)) {
121 IRRef tab = IR(ir->op1)->op1;
122 int32_t ofs = asm_fuseabase(as, tab);
123 IRRef refa = ofs ? tab : ir->op1;
124 ofs += 8*IR(ir->op2)->i;
125 if (checki16(ofs)) {
126 *ofsp = ofs;
127 return ra_alloc1(as, refa, allow);
128 }
129 }
130 if (*ofsp == AHUREF_LSX) {
131 Reg base = ra_alloc1(as, ir->op1, allow);
132 Reg idx = ra_alloc1(as, ir->op2, rset_exclude(RSET_GPR, base));
133 return base | (idx << 8);
134 }
135 }
136 } else if (ir->o == IR_HREFK) {
137 if (mayfuse(as, ref)) {
138 int32_t ofs = (int32_t)(IR(ir->op2)->op2 * sizeof(Node));
139 if (checki16(ofs)) {
140 *ofsp = ofs;
141 return ra_alloc1(as, ir->op1, allow);
142 }
143 }
144 } else if (ir->o == IR_UREFC) {
145 if (irref_isk(ir->op1)) {
146 GCfunc *fn = ir_kfunc(IR(ir->op1));
147 int32_t ofs = i32ptr(&gcref(fn->l.uvptr[(ir->op2 >> 8)])->uv.tv);
148 int32_t jgl = (intptr_t)J2G(as->J);
149 if ((uint32_t)(ofs-jgl) < 65536) {
150 *ofsp = ofs-jgl-32768;
151 return RID_JGL;
152 } else {
153 *ofsp = (int16_t)ofs;
154 return ra_allock(as, ofs-(int16_t)ofs, allow);
155 }
156 }
157 }
158 }
159 *ofsp = 0;
160 return ra_alloc1(as, ref, allow);
161 }
162
163 /* Fuse XLOAD/XSTORE reference into load/store operand. */
asm_fusexref(ASMState * as,PPCIns pi,Reg rt,IRRef ref,RegSet allow,int32_t ofs)164 static void asm_fusexref(ASMState *as, PPCIns pi, Reg rt, IRRef ref,
165 RegSet allow, int32_t ofs)
166 {
167 IRIns *ir = IR(ref);
168 Reg base;
169 if (ra_noreg(ir->r) && canfuse(as, ir)) {
170 if (ir->o == IR_ADD) {
171 int32_t ofs2;
172 if (irref_isk(ir->op2) && (ofs2 = ofs + IR(ir->op2)->i, checki16(ofs2))) {
173 ofs = ofs2;
174 ref = ir->op1;
175 } else if (ofs == 0) {
176 Reg right, left = ra_alloc2(as, ir, allow);
177 right = (left >> 8); left &= 255;
178 emit_fab(as, PPCI_LWZX | ((pi >> 20) & 0x780), rt, left, right);
179 return;
180 }
181 } else if (ir->o == IR_STRREF) {
182 lua_assert(ofs == 0);
183 ofs = (int32_t)sizeof(GCstr);
184 if (irref_isk(ir->op2)) {
185 ofs += IR(ir->op2)->i;
186 ref = ir->op1;
187 } else if (irref_isk(ir->op1)) {
188 ofs += IR(ir->op1)->i;
189 ref = ir->op2;
190 } else {
191 /* NYI: Fuse ADD with constant. */
192 Reg tmp, right, left = ra_alloc2(as, ir, allow);
193 right = (left >> 8); left &= 255;
194 tmp = ra_scratch(as, rset_exclude(rset_exclude(allow, left), right));
195 emit_fai(as, pi, rt, tmp, ofs);
196 emit_tab(as, PPCI_ADD, tmp, left, right);
197 return;
198 }
199 if (!checki16(ofs)) {
200 Reg left = ra_alloc1(as, ref, allow);
201 Reg right = ra_allock(as, ofs, rset_exclude(allow, left));
202 emit_fab(as, PPCI_LWZX | ((pi >> 20) & 0x780), rt, left, right);
203 return;
204 }
205 }
206 }
207 base = ra_alloc1(as, ref, allow);
208 emit_fai(as, pi, rt, base, ofs);
209 }
210
211 /* Fuse XLOAD/XSTORE reference into indexed-only load/store operand. */
asm_fusexrefx(ASMState * as,PPCIns pi,Reg rt,IRRef ref,RegSet allow)212 static void asm_fusexrefx(ASMState *as, PPCIns pi, Reg rt, IRRef ref,
213 RegSet allow)
214 {
215 IRIns *ira = IR(ref);
216 Reg right, left;
217 if (canfuse(as, ira) && ira->o == IR_ADD && ra_noreg(ira->r)) {
218 left = ra_alloc2(as, ira, allow);
219 right = (left >> 8); left &= 255;
220 } else {
221 right = ra_alloc1(as, ref, allow);
222 left = RID_R0;
223 }
224 emit_tab(as, pi, rt, left, right);
225 }
226
227 /* Fuse to multiply-add/sub instruction. */
asm_fusemadd(ASMState * as,IRIns * ir,PPCIns pi,PPCIns pir)228 static int asm_fusemadd(ASMState *as, IRIns *ir, PPCIns pi, PPCIns pir)
229 {
230 IRRef lref = ir->op1, rref = ir->op2;
231 IRIns *irm;
232 if (lref != rref &&
233 ((mayfuse(as, lref) && (irm = IR(lref), irm->o == IR_MUL) &&
234 ra_noreg(irm->r)) ||
235 (mayfuse(as, rref) && (irm = IR(rref), irm->o == IR_MUL) &&
236 (rref = lref, pi = pir, ra_noreg(irm->r))))) {
237 Reg dest = ra_dest(as, ir, RSET_FPR);
238 Reg add = ra_alloc1(as, rref, RSET_FPR);
239 Reg right, left = ra_alloc2(as, irm, rset_exclude(RSET_FPR, add));
240 right = (left >> 8); left &= 255;
241 emit_facb(as, pi, dest, left, right, add);
242 return 1;
243 }
244 return 0;
245 }
246
247 /* -- Calls --------------------------------------------------------------- */
248
249 /* Generate a call to a C function. */
asm_gencall(ASMState * as,const CCallInfo * ci,IRRef * args)250 static void asm_gencall(ASMState *as, const CCallInfo *ci, IRRef *args)
251 {
252 uint32_t n, nargs = CCI_NARGS(ci);
253 int32_t ofs = 8;
254 Reg gpr = REGARG_FIRSTGPR, fpr = REGARG_FIRSTFPR;
255 if ((void *)ci->func)
256 emit_call(as, (void *)ci->func);
257 for (n = 0; n < nargs; n++) { /* Setup args. */
258 IRRef ref = args[n];
259 if (ref) {
260 IRIns *ir = IR(ref);
261 if (irt_isfp(ir->t)) {
262 if (fpr <= REGARG_LASTFPR) {
263 lua_assert(rset_test(as->freeset, fpr)); /* Already evicted. */
264 ra_leftov(as, fpr, ref);
265 fpr++;
266 } else {
267 Reg r = ra_alloc1(as, ref, RSET_FPR);
268 if (irt_isnum(ir->t)) ofs = (ofs + 4) & ~4;
269 emit_spstore(as, ir, r, ofs);
270 ofs += irt_isnum(ir->t) ? 8 : 4;
271 }
272 } else {
273 if (gpr <= REGARG_LASTGPR) {
274 lua_assert(rset_test(as->freeset, gpr)); /* Already evicted. */
275 ra_leftov(as, gpr, ref);
276 gpr++;
277 } else {
278 Reg r = ra_alloc1(as, ref, RSET_GPR);
279 emit_spstore(as, ir, r, ofs);
280 ofs += 4;
281 }
282 }
283 } else {
284 if (gpr <= REGARG_LASTGPR)
285 gpr++;
286 else
287 ofs += 4;
288 }
289 checkmclim(as);
290 }
291 if ((ci->flags & CCI_VARARG)) /* Vararg calls need to know about FPR use. */
292 emit_tab(as, fpr == REGARG_FIRSTFPR ? PPCI_CRXOR : PPCI_CREQV, 6, 6, 6);
293 }
294
295 /* Setup result reg/sp for call. Evict scratch regs. */
asm_setupresult(ASMState * as,IRIns * ir,const CCallInfo * ci)296 static void asm_setupresult(ASMState *as, IRIns *ir, const CCallInfo *ci)
297 {
298 RegSet drop = RSET_SCRATCH;
299 int hiop = ((ir+1)->o == IR_HIOP);
300 if ((ci->flags & CCI_NOFPRCLOBBER))
301 drop &= ~RSET_FPR;
302 if (ra_hasreg(ir->r))
303 rset_clear(drop, ir->r); /* Dest reg handled below. */
304 if (hiop && ra_hasreg((ir+1)->r))
305 rset_clear(drop, (ir+1)->r); /* Dest reg handled below. */
306 ra_evictset(as, drop); /* Evictions must be performed first. */
307 if (ra_used(ir)) {
308 lua_assert(!irt_ispri(ir->t));
309 if (irt_isfp(ir->t)) {
310 if ((ci->flags & CCI_CASTU64)) {
311 /* Use spill slot or temp slots. */
312 int32_t ofs = ir->s ? sps_scale(ir->s) : SPOFS_TMP;
313 Reg dest = ir->r;
314 if (ra_hasreg(dest)) {
315 ra_free(as, dest);
316 ra_modified(as, dest);
317 emit_fai(as, PPCI_LFD, dest, RID_SP, ofs);
318 }
319 emit_tai(as, PPCI_STW, RID_RETHI, RID_SP, ofs);
320 emit_tai(as, PPCI_STW, RID_RETLO, RID_SP, ofs+4);
321 } else {
322 ra_destreg(as, ir, RID_FPRET);
323 }
324 } else if (hiop) {
325 ra_destpair(as, ir);
326 } else {
327 ra_destreg(as, ir, RID_RET);
328 }
329 }
330 }
331
asm_call(ASMState * as,IRIns * ir)332 static void asm_call(ASMState *as, IRIns *ir)
333 {
334 IRRef args[CCI_NARGS_MAX];
335 const CCallInfo *ci = &lj_ir_callinfo[ir->op2];
336 asm_collectargs(as, ir, ci, args);
337 asm_setupresult(as, ir, ci);
338 asm_gencall(as, ci, args);
339 }
340
asm_callx(ASMState * as,IRIns * ir)341 static void asm_callx(ASMState *as, IRIns *ir)
342 {
343 IRRef args[CCI_NARGS_MAX*2];
344 CCallInfo ci;
345 IRRef func;
346 IRIns *irf;
347 ci.flags = asm_callx_flags(as, ir);
348 asm_collectargs(as, ir, &ci, args);
349 asm_setupresult(as, ir, &ci);
350 func = ir->op2; irf = IR(func);
351 if (irf->o == IR_CARG) { func = irf->op1; irf = IR(func); }
352 if (irref_isk(func)) { /* Call to constant address. */
353 ci.func = (ASMFunction)(void *)(irf->i);
354 } else { /* Need a non-argument register for indirect calls. */
355 RegSet allow = RSET_GPR & ~RSET_RANGE(RID_R0, REGARG_LASTGPR+1);
356 Reg freg = ra_alloc1(as, func, allow);
357 *--as->mcp = PPCI_BCTRL;
358 *--as->mcp = PPCI_MTCTR | PPCF_T(freg);
359 ci.func = (ASMFunction)(void *)0;
360 }
361 asm_gencall(as, &ci, args);
362 }
363
asm_callid(ASMState * as,IRIns * ir,IRCallID id)364 static void asm_callid(ASMState *as, IRIns *ir, IRCallID id)
365 {
366 const CCallInfo *ci = &lj_ir_callinfo[id];
367 IRRef args[2];
368 args[0] = ir->op1;
369 args[1] = ir->op2;
370 asm_setupresult(as, ir, ci);
371 asm_gencall(as, ci, args);
372 }
373
374 /* -- Returns ------------------------------------------------------------- */
375
376 /* Return to lower frame. Guard that it goes to the right spot. */
asm_retf(ASMState * as,IRIns * ir)377 static void asm_retf(ASMState *as, IRIns *ir)
378 {
379 Reg base = ra_alloc1(as, REF_BASE, RSET_GPR);
380 void *pc = ir_kptr(IR(ir->op2));
381 int32_t delta = 1+bc_a(*((const BCIns *)pc - 1));
382 as->topslot -= (BCReg)delta;
383 if ((int32_t)as->topslot < 0) as->topslot = 0;
384 irt_setmark(IR(REF_BASE)->t); /* Children must not coalesce with BASE reg. */
385 emit_setgl(as, base, jit_base);
386 emit_addptr(as, base, -8*delta);
387 asm_guardcc(as, CC_NE);
388 emit_ab(as, PPCI_CMPW, RID_TMP,
389 ra_allock(as, i32ptr(pc), rset_exclude(RSET_GPR, base)));
390 emit_tai(as, PPCI_LWZ, RID_TMP, base, -8);
391 }
392
393 /* -- Type conversions ---------------------------------------------------- */
394
asm_tointg(ASMState * as,IRIns * ir,Reg left)395 static void asm_tointg(ASMState *as, IRIns *ir, Reg left)
396 {
397 RegSet allow = RSET_FPR;
398 Reg tmp = ra_scratch(as, rset_clear(allow, left));
399 Reg fbias = ra_scratch(as, rset_clear(allow, tmp));
400 Reg dest = ra_dest(as, ir, RSET_GPR);
401 Reg hibias = ra_allock(as, 0x43300000, rset_exclude(RSET_GPR, dest));
402 asm_guardcc(as, CC_NE);
403 emit_fab(as, PPCI_FCMPU, 0, tmp, left);
404 emit_fab(as, PPCI_FSUB, tmp, tmp, fbias);
405 emit_fai(as, PPCI_LFD, tmp, RID_SP, SPOFS_TMP);
406 emit_tai(as, PPCI_STW, RID_TMP, RID_SP, SPOFS_TMPLO);
407 emit_tai(as, PPCI_STW, hibias, RID_SP, SPOFS_TMPHI);
408 emit_asi(as, PPCI_XORIS, RID_TMP, dest, 0x8000);
409 emit_tai(as, PPCI_LWZ, dest, RID_SP, SPOFS_TMPLO);
410 emit_lsptr(as, PPCI_LFS, (fbias & 31),
411 (void *)lj_ir_k64_find(as->J, U64x(59800004,59800000)),
412 RSET_GPR);
413 emit_fai(as, PPCI_STFD, tmp, RID_SP, SPOFS_TMP);
414 emit_fb(as, PPCI_FCTIWZ, tmp, left);
415 }
416
asm_tobit(ASMState * as,IRIns * ir)417 static void asm_tobit(ASMState *as, IRIns *ir)
418 {
419 RegSet allow = RSET_FPR;
420 Reg dest = ra_dest(as, ir, RSET_GPR);
421 Reg left = ra_alloc1(as, ir->op1, allow);
422 Reg right = ra_alloc1(as, ir->op2, rset_clear(allow, left));
423 Reg tmp = ra_scratch(as, rset_clear(allow, right));
424 emit_tai(as, PPCI_LWZ, dest, RID_SP, SPOFS_TMPLO);
425 emit_fai(as, PPCI_STFD, tmp, RID_SP, SPOFS_TMP);
426 emit_fab(as, PPCI_FADD, tmp, left, right);
427 }
428
asm_conv(ASMState * as,IRIns * ir)429 static void asm_conv(ASMState *as, IRIns *ir)
430 {
431 IRType st = (IRType)(ir->op2 & IRCONV_SRCMASK);
432 int stfp = (st == IRT_NUM || st == IRT_FLOAT);
433 IRRef lref = ir->op1;
434 lua_assert(irt_type(ir->t) != st);
435 lua_assert(!(irt_isint64(ir->t) ||
436 (st == IRT_I64 || st == IRT_U64))); /* Handled by SPLIT. */
437 if (irt_isfp(ir->t)) {
438 Reg dest = ra_dest(as, ir, RSET_FPR);
439 if (stfp) { /* FP to FP conversion. */
440 if (st == IRT_NUM) /* double -> float conversion. */
441 emit_fb(as, PPCI_FRSP, dest, ra_alloc1(as, lref, RSET_FPR));
442 else /* float -> double conversion is a no-op on PPC. */
443 ra_leftov(as, dest, lref); /* Do nothing, but may need to move regs. */
444 } else { /* Integer to FP conversion. */
445 /* IRT_INT: Flip hibit, bias with 2^52, subtract 2^52+2^31. */
446 /* IRT_U32: Bias with 2^52, subtract 2^52. */
447 RegSet allow = RSET_GPR;
448 Reg left = ra_alloc1(as, lref, allow);
449 Reg hibias = ra_allock(as, 0x43300000, rset_clear(allow, left));
450 Reg fbias = ra_scratch(as, rset_exclude(RSET_FPR, dest));
451 const float *kbias;
452 if (irt_isfloat(ir->t)) emit_fb(as, PPCI_FRSP, dest, dest);
453 emit_fab(as, PPCI_FSUB, dest, dest, fbias);
454 emit_fai(as, PPCI_LFD, dest, RID_SP, SPOFS_TMP);
455 kbias = (const float *)lj_ir_k64_find(as->J, U64x(59800004,59800000));
456 if (st == IRT_U32) kbias++;
457 emit_lsptr(as, PPCI_LFS, (fbias & 31), (void *)kbias,
458 rset_clear(allow, hibias));
459 emit_tai(as, PPCI_STW, st == IRT_U32 ? left : RID_TMP,
460 RID_SP, SPOFS_TMPLO);
461 emit_tai(as, PPCI_STW, hibias, RID_SP, SPOFS_TMPHI);
462 if (st != IRT_U32) emit_asi(as, PPCI_XORIS, RID_TMP, left, 0x8000);
463 }
464 } else if (stfp) { /* FP to integer conversion. */
465 if (irt_isguard(ir->t)) {
466 /* Checked conversions are only supported from number to int. */
467 lua_assert(irt_isint(ir->t) && st == IRT_NUM);
468 asm_tointg(as, ir, ra_alloc1(as, lref, RSET_FPR));
469 } else {
470 Reg dest = ra_dest(as, ir, RSET_GPR);
471 Reg left = ra_alloc1(as, lref, RSET_FPR);
472 Reg tmp = ra_scratch(as, rset_exclude(RSET_FPR, left));
473 if (irt_isu32(ir->t)) {
474 /* Convert both x and x-2^31 to int and merge results. */
475 Reg tmpi = ra_scratch(as, rset_exclude(RSET_GPR, dest));
476 emit_asb(as, PPCI_OR, dest, dest, tmpi); /* Select with mask idiom. */
477 emit_asb(as, PPCI_AND, tmpi, tmpi, RID_TMP);
478 emit_asb(as, PPCI_ANDC, dest, dest, RID_TMP);
479 emit_tai(as, PPCI_LWZ, tmpi, RID_SP, SPOFS_TMPLO); /* tmp = (int)(x) */
480 emit_tai(as, PPCI_ADDIS, dest, dest, 0x8000); /* dest += 2^31 */
481 emit_asb(as, PPCI_SRAWI, RID_TMP, dest, 31); /* mask = -(dest < 0) */
482 emit_fai(as, PPCI_STFD, tmp, RID_SP, SPOFS_TMP);
483 emit_tai(as, PPCI_LWZ, dest,
484 RID_SP, SPOFS_TMPLO); /* dest = (int)(x-2^31) */
485 emit_fb(as, PPCI_FCTIWZ, tmp, left);
486 emit_fai(as, PPCI_STFD, tmp, RID_SP, SPOFS_TMP);
487 emit_fb(as, PPCI_FCTIWZ, tmp, tmp);
488 emit_fab(as, PPCI_FSUB, tmp, left, tmp);
489 emit_lsptr(as, PPCI_LFS, (tmp & 31),
490 (void *)lj_ir_k64_find(as->J, U64x(4f000000,00000000)),
491 RSET_GPR);
492 } else {
493 emit_tai(as, PPCI_LWZ, dest, RID_SP, SPOFS_TMPLO);
494 emit_fai(as, PPCI_STFD, tmp, RID_SP, SPOFS_TMP);
495 emit_fb(as, PPCI_FCTIWZ, tmp, left);
496 }
497 }
498 } else {
499 Reg dest = ra_dest(as, ir, RSET_GPR);
500 if (st >= IRT_I8 && st <= IRT_U16) { /* Extend to 32 bit integer. */
501 Reg left = ra_alloc1(as, ir->op1, RSET_GPR);
502 lua_assert(irt_isint(ir->t) || irt_isu32(ir->t));
503 if ((ir->op2 & IRCONV_SEXT))
504 emit_as(as, st == IRT_I8 ? PPCI_EXTSB : PPCI_EXTSH, dest, left);
505 else
506 emit_rot(as, PPCI_RLWINM, dest, left, 0, st == IRT_U8 ? 24 : 16, 31);
507 } else { /* 32/64 bit integer conversions. */
508 /* Only need to handle 32/32 bit no-op (cast) on 32 bit archs. */
509 ra_leftov(as, dest, lref); /* Do nothing, but may need to move regs. */
510 }
511 }
512 }
513
514 #if LJ_HASFFI
asm_conv64(ASMState * as,IRIns * ir)515 static void asm_conv64(ASMState *as, IRIns *ir)
516 {
517 IRType st = (IRType)((ir-1)->op2 & IRCONV_SRCMASK);
518 IRType dt = (((ir-1)->op2 & IRCONV_DSTMASK) >> IRCONV_DSH);
519 IRCallID id;
520 const CCallInfo *ci;
521 IRRef args[2];
522 args[0] = ir->op1;
523 args[1] = (ir-1)->op1;
524 if (st == IRT_NUM || st == IRT_FLOAT) {
525 id = IRCALL_fp64_d2l + ((st == IRT_FLOAT) ? 2 : 0) + (dt - IRT_I64);
526 ir--;
527 } else {
528 id = IRCALL_fp64_l2d + ((dt == IRT_FLOAT) ? 2 : 0) + (st - IRT_I64);
529 }
530 ci = &lj_ir_callinfo[id];
531 asm_setupresult(as, ir, ci);
532 asm_gencall(as, ci, args);
533 }
534 #endif
535
asm_strto(ASMState * as,IRIns * ir)536 static void asm_strto(ASMState *as, IRIns *ir)
537 {
538 const CCallInfo *ci = &lj_ir_callinfo[IRCALL_lj_strscan_num];
539 IRRef args[2];
540 int32_t ofs;
541 RegSet drop = RSET_SCRATCH;
542 if (ra_hasreg(ir->r)) rset_set(drop, ir->r); /* Spill dest reg (if any). */
543 ra_evictset(as, drop);
544 asm_guardcc(as, CC_EQ);
545 emit_ai(as, PPCI_CMPWI, RID_RET, 0); /* Test return status. */
546 args[0] = ir->op1; /* GCstr *str */
547 args[1] = ASMREF_TMP1; /* TValue *n */
548 asm_gencall(as, ci, args);
549 /* Store the result to the spill slot or temp slots. */
550 ofs = ir->s ? sps_scale(ir->s) : SPOFS_TMP;
551 emit_tai(as, PPCI_ADDI, ra_releasetmp(as, ASMREF_TMP1), RID_SP, ofs);
552 }
553
554 /* Get pointer to TValue. */
asm_tvptr(ASMState * as,Reg dest,IRRef ref)555 static void asm_tvptr(ASMState *as, Reg dest, IRRef ref)
556 {
557 IRIns *ir = IR(ref);
558 if (irt_isnum(ir->t)) {
559 if (irref_isk(ref)) /* Use the number constant itself as a TValue. */
560 ra_allockreg(as, i32ptr(ir_knum(ir)), dest);
561 else /* Otherwise force a spill and use the spill slot. */
562 emit_tai(as, PPCI_ADDI, dest, RID_SP, ra_spill(as, ir));
563 } else {
564 /* Otherwise use g->tmptv to hold the TValue. */
565 RegSet allow = rset_exclude(RSET_GPR, dest);
566 Reg type;
567 emit_tai(as, PPCI_ADDI, dest, RID_JGL, offsetof(global_State, tmptv)-32768);
568 if (!irt_ispri(ir->t)) {
569 Reg src = ra_alloc1(as, ref, allow);
570 emit_setgl(as, src, tmptv.gcr);
571 }
572 type = ra_allock(as, irt_toitype(ir->t), allow);
573 emit_setgl(as, type, tmptv.it);
574 }
575 }
576
asm_tostr(ASMState * as,IRIns * ir)577 static void asm_tostr(ASMState *as, IRIns *ir)
578 {
579 IRRef args[2];
580 args[0] = ASMREF_L;
581 as->gcsteps++;
582 if (irt_isnum(IR(ir->op1)->t) || (ir+1)->o == IR_HIOP) {
583 const CCallInfo *ci = &lj_ir_callinfo[IRCALL_lj_str_fromnum];
584 args[1] = ASMREF_TMP1; /* const lua_Number * */
585 asm_setupresult(as, ir, ci); /* GCstr * */
586 asm_gencall(as, ci, args);
587 asm_tvptr(as, ra_releasetmp(as, ASMREF_TMP1), ir->op1);
588 } else {
589 const CCallInfo *ci = &lj_ir_callinfo[IRCALL_lj_str_fromint];
590 args[1] = ir->op1; /* int32_t k */
591 asm_setupresult(as, ir, ci); /* GCstr * */
592 asm_gencall(as, ci, args);
593 }
594 }
595
596 /* -- Memory references --------------------------------------------------- */
597
asm_aref(ASMState * as,IRIns * ir)598 static void asm_aref(ASMState *as, IRIns *ir)
599 {
600 Reg dest = ra_dest(as, ir, RSET_GPR);
601 Reg idx, base;
602 if (irref_isk(ir->op2)) {
603 IRRef tab = IR(ir->op1)->op1;
604 int32_t ofs = asm_fuseabase(as, tab);
605 IRRef refa = ofs ? tab : ir->op1;
606 ofs += 8*IR(ir->op2)->i;
607 if (checki16(ofs)) {
608 base = ra_alloc1(as, refa, RSET_GPR);
609 emit_tai(as, PPCI_ADDI, dest, base, ofs);
610 return;
611 }
612 }
613 base = ra_alloc1(as, ir->op1, RSET_GPR);
614 idx = ra_alloc1(as, ir->op2, rset_exclude(RSET_GPR, base));
615 emit_tab(as, PPCI_ADD, dest, RID_TMP, base);
616 emit_slwi(as, RID_TMP, idx, 3);
617 }
618
619 /* Inlined hash lookup. Specialized for key type and for const keys.
620 ** The equivalent C code is:
621 ** Node *n = hashkey(t, key);
622 ** do {
623 ** if (lj_obj_equal(&n->key, key)) return &n->val;
624 ** } while ((n = nextnode(n)));
625 ** return niltv(L);
626 */
asm_href(ASMState * as,IRIns * ir,IROp merge)627 static void asm_href(ASMState *as, IRIns *ir, IROp merge)
628 {
629 RegSet allow = RSET_GPR;
630 int destused = ra_used(ir);
631 Reg dest = ra_dest(as, ir, allow);
632 Reg tab = ra_alloc1(as, ir->op1, rset_clear(allow, dest));
633 Reg key = RID_NONE, tmp1 = RID_TMP, tmp2;
634 Reg tisnum = RID_NONE, tmpnum = RID_NONE;
635 IRRef refkey = ir->op2;
636 IRIns *irkey = IR(refkey);
637 IRType1 kt = irkey->t;
638 uint32_t khash;
639 MCLabel l_end, l_loop, l_next;
640
641 rset_clear(allow, tab);
642 if (irt_isnum(kt)) {
643 key = ra_alloc1(as, refkey, RSET_FPR);
644 tmpnum = ra_scratch(as, rset_exclude(RSET_FPR, key));
645 tisnum = ra_allock(as, (int32_t)LJ_TISNUM, allow);
646 rset_clear(allow, tisnum);
647 } else if (!irt_ispri(kt)) {
648 key = ra_alloc1(as, refkey, allow);
649 rset_clear(allow, key);
650 }
651 tmp2 = ra_scratch(as, allow);
652 rset_clear(allow, tmp2);
653
654 /* Key not found in chain: jump to exit (if merged) or load niltv. */
655 l_end = emit_label(as);
656 as->invmcp = NULL;
657 if (merge == IR_NE)
658 asm_guardcc(as, CC_EQ);
659 else if (destused)
660 emit_loada(as, dest, niltvg(J2G(as->J)));
661
662 /* Follow hash chain until the end. */
663 l_loop = --as->mcp;
664 emit_ai(as, PPCI_CMPWI, dest, 0);
665 emit_tai(as, PPCI_LWZ, dest, dest, (int32_t)offsetof(Node, next));
666 l_next = emit_label(as);
667
668 /* Type and value comparison. */
669 if (merge == IR_EQ)
670 asm_guardcc(as, CC_EQ);
671 else
672 emit_condbranch(as, PPCI_BC|PPCF_Y, CC_EQ, l_end);
673 if (irt_isnum(kt)) {
674 emit_fab(as, PPCI_FCMPU, 0, tmpnum, key);
675 emit_condbranch(as, PPCI_BC, CC_GE, l_next);
676 emit_ab(as, PPCI_CMPLW, tmp1, tisnum);
677 emit_fai(as, PPCI_LFD, tmpnum, dest, (int32_t)offsetof(Node, key.n));
678 } else {
679 if (!irt_ispri(kt)) {
680 emit_ab(as, PPCI_CMPW, tmp2, key);
681 emit_condbranch(as, PPCI_BC, CC_NE, l_next);
682 }
683 emit_ai(as, PPCI_CMPWI, tmp1, irt_toitype(irkey->t));
684 if (!irt_ispri(kt))
685 emit_tai(as, PPCI_LWZ, tmp2, dest, (int32_t)offsetof(Node, key.gcr));
686 }
687 emit_tai(as, PPCI_LWZ, tmp1, dest, (int32_t)offsetof(Node, key.it));
688 *l_loop = PPCI_BC | PPCF_Y | PPCF_CC(CC_NE) |
689 (((char *)as->mcp-(char *)l_loop) & 0xffffu);
690
691 /* Load main position relative to tab->node into dest. */
692 khash = irref_isk(refkey) ? ir_khash(irkey) : 1;
693 if (khash == 0) {
694 emit_tai(as, PPCI_LWZ, dest, tab, (int32_t)offsetof(GCtab, node));
695 } else {
696 Reg tmphash = tmp1;
697 if (irref_isk(refkey))
698 tmphash = ra_allock(as, khash, allow);
699 emit_tab(as, PPCI_ADD, dest, dest, tmp1);
700 emit_tai(as, PPCI_MULLI, tmp1, tmp1, sizeof(Node));
701 emit_asb(as, PPCI_AND, tmp1, tmp2, tmphash);
702 emit_tai(as, PPCI_LWZ, dest, tab, (int32_t)offsetof(GCtab, node));
703 emit_tai(as, PPCI_LWZ, tmp2, tab, (int32_t)offsetof(GCtab, hmask));
704 if (irref_isk(refkey)) {
705 /* Nothing to do. */
706 } else if (irt_isstr(kt)) {
707 emit_tai(as, PPCI_LWZ, tmp1, key, (int32_t)offsetof(GCstr, hash));
708 } else { /* Must match with hash*() in lj_tab.c. */
709 emit_tab(as, PPCI_SUBF, tmp1, tmp2, tmp1);
710 emit_rotlwi(as, tmp2, tmp2, HASH_ROT3);
711 emit_asb(as, PPCI_XOR, tmp1, tmp1, tmp2);
712 emit_rotlwi(as, tmp1, tmp1, (HASH_ROT2+HASH_ROT1)&31);
713 emit_tab(as, PPCI_SUBF, tmp2, dest, tmp2);
714 if (irt_isnum(kt)) {
715 int32_t ofs = ra_spill(as, irkey);
716 emit_asb(as, PPCI_XOR, tmp2, tmp2, tmp1);
717 emit_rotlwi(as, dest, tmp1, HASH_ROT1);
718 emit_tab(as, PPCI_ADD, tmp1, tmp1, tmp1);
719 emit_tai(as, PPCI_LWZ, tmp2, RID_SP, ofs+4);
720 emit_tai(as, PPCI_LWZ, tmp1, RID_SP, ofs);
721 } else {
722 emit_asb(as, PPCI_XOR, tmp2, key, tmp1);
723 emit_rotlwi(as, dest, tmp1, HASH_ROT1);
724 emit_tai(as, PPCI_ADDI, tmp1, tmp2, HASH_BIAS);
725 emit_tai(as, PPCI_ADDIS, tmp2, key, (HASH_BIAS + 32768)>>16);
726 }
727 }
728 }
729 }
730
asm_hrefk(ASMState * as,IRIns * ir)731 static void asm_hrefk(ASMState *as, IRIns *ir)
732 {
733 IRIns *kslot = IR(ir->op2);
734 IRIns *irkey = IR(kslot->op1);
735 int32_t ofs = (int32_t)(kslot->op2 * sizeof(Node));
736 int32_t kofs = ofs + (int32_t)offsetof(Node, key);
737 Reg dest = (ra_used(ir)||ofs > 32736) ? ra_dest(as, ir, RSET_GPR) : RID_NONE;
738 Reg node = ra_alloc1(as, ir->op1, RSET_GPR);
739 Reg key = RID_NONE, type = RID_TMP, idx = node;
740 RegSet allow = rset_exclude(RSET_GPR, node);
741 lua_assert(ofs % sizeof(Node) == 0);
742 if (ofs > 32736) {
743 idx = dest;
744 rset_clear(allow, dest);
745 kofs = (int32_t)offsetof(Node, key);
746 } else if (ra_hasreg(dest)) {
747 emit_tai(as, PPCI_ADDI, dest, node, ofs);
748 }
749 asm_guardcc(as, CC_NE);
750 if (!irt_ispri(irkey->t)) {
751 key = ra_scratch(as, allow);
752 rset_clear(allow, key);
753 }
754 rset_clear(allow, type);
755 if (irt_isnum(irkey->t)) {
756 emit_cmpi(as, key, (int32_t)ir_knum(irkey)->u32.lo);
757 asm_guardcc(as, CC_NE);
758 emit_cmpi(as, type, (int32_t)ir_knum(irkey)->u32.hi);
759 } else {
760 if (ra_hasreg(key)) {
761 emit_cmpi(as, key, irkey->i); /* May use RID_TMP, i.e. type. */
762 asm_guardcc(as, CC_NE);
763 }
764 emit_ai(as, PPCI_CMPWI, type, irt_toitype(irkey->t));
765 }
766 if (ra_hasreg(key)) emit_tai(as, PPCI_LWZ, key, idx, kofs+4);
767 emit_tai(as, PPCI_LWZ, type, idx, kofs);
768 if (ofs > 32736) {
769 emit_tai(as, PPCI_ADDIS, dest, dest, (ofs + 32768) >> 16);
770 emit_tai(as, PPCI_ADDI, dest, node, ofs);
771 }
772 }
773
asm_newref(ASMState * as,IRIns * ir)774 static void asm_newref(ASMState *as, IRIns *ir)
775 {
776 const CCallInfo *ci = &lj_ir_callinfo[IRCALL_lj_tab_newkey];
777 IRRef args[3];
778 if (ir->r == RID_SINK)
779 return;
780 args[0] = ASMREF_L; /* lua_State *L */
781 args[1] = ir->op1; /* GCtab *t */
782 args[2] = ASMREF_TMP1; /* cTValue *key */
783 asm_setupresult(as, ir, ci); /* TValue * */
784 asm_gencall(as, ci, args);
785 asm_tvptr(as, ra_releasetmp(as, ASMREF_TMP1), ir->op2);
786 }
787
asm_uref(ASMState * as,IRIns * ir)788 static void asm_uref(ASMState *as, IRIns *ir)
789 {
790 /* NYI: Check that UREFO is still open and not aliasing a slot. */
791 Reg dest = ra_dest(as, ir, RSET_GPR);
792 if (irref_isk(ir->op1)) {
793 GCfunc *fn = ir_kfunc(IR(ir->op1));
794 MRef *v = &gcref(fn->l.uvptr[(ir->op2 >> 8)])->uv.v;
795 emit_lsptr(as, PPCI_LWZ, dest, v, RSET_GPR);
796 } else {
797 Reg uv = ra_scratch(as, RSET_GPR);
798 Reg func = ra_alloc1(as, ir->op1, RSET_GPR);
799 if (ir->o == IR_UREFC) {
800 asm_guardcc(as, CC_NE);
801 emit_ai(as, PPCI_CMPWI, RID_TMP, 1);
802 emit_tai(as, PPCI_ADDI, dest, uv, (int32_t)offsetof(GCupval, tv));
803 emit_tai(as, PPCI_LBZ, RID_TMP, uv, (int32_t)offsetof(GCupval, closed));
804 } else {
805 emit_tai(as, PPCI_LWZ, dest, uv, (int32_t)offsetof(GCupval, v));
806 }
807 emit_tai(as, PPCI_LWZ, uv, func,
808 (int32_t)offsetof(GCfuncL, uvptr) + 4*(int32_t)(ir->op2 >> 8));
809 }
810 }
811
asm_fref(ASMState * as,IRIns * ir)812 static void asm_fref(ASMState *as, IRIns *ir)
813 {
814 UNUSED(as); UNUSED(ir);
815 lua_assert(!ra_used(ir));
816 }
817
asm_strref(ASMState * as,IRIns * ir)818 static void asm_strref(ASMState *as, IRIns *ir)
819 {
820 Reg dest = ra_dest(as, ir, RSET_GPR);
821 IRRef ref = ir->op2, refk = ir->op1;
822 int32_t ofs = (int32_t)sizeof(GCstr);
823 Reg r;
824 if (irref_isk(ref)) {
825 IRRef tmp = refk; refk = ref; ref = tmp;
826 } else if (!irref_isk(refk)) {
827 Reg right, left = ra_alloc1(as, ir->op1, RSET_GPR);
828 IRIns *irr = IR(ir->op2);
829 if (ra_hasreg(irr->r)) {
830 ra_noweak(as, irr->r);
831 right = irr->r;
832 } else if (mayfuse(as, irr->op2) &&
833 irr->o == IR_ADD && irref_isk(irr->op2) &&
834 checki16(ofs + IR(irr->op2)->i)) {
835 ofs += IR(irr->op2)->i;
836 right = ra_alloc1(as, irr->op1, rset_exclude(RSET_GPR, left));
837 } else {
838 right = ra_allocref(as, ir->op2, rset_exclude(RSET_GPR, left));
839 }
840 emit_tai(as, PPCI_ADDI, dest, dest, ofs);
841 emit_tab(as, PPCI_ADD, dest, left, right);
842 return;
843 }
844 r = ra_alloc1(as, ref, RSET_GPR);
845 ofs += IR(refk)->i;
846 if (checki16(ofs))
847 emit_tai(as, PPCI_ADDI, dest, r, ofs);
848 else
849 emit_tab(as, PPCI_ADD, dest, r,
850 ra_allock(as, ofs, rset_exclude(RSET_GPR, r)));
851 }
852
853 /* -- Loads and stores ---------------------------------------------------- */
854
asm_fxloadins(IRIns * ir)855 static PPCIns asm_fxloadins(IRIns *ir)
856 {
857 switch (irt_type(ir->t)) {
858 case IRT_I8: return PPCI_LBZ; /* Needs sign-extension. */
859 case IRT_U8: return PPCI_LBZ;
860 case IRT_I16: return PPCI_LHA;
861 case IRT_U16: return PPCI_LHZ;
862 case IRT_NUM: return PPCI_LFD;
863 case IRT_FLOAT: return PPCI_LFS;
864 default: return PPCI_LWZ;
865 }
866 }
867
asm_fxstoreins(IRIns * ir)868 static PPCIns asm_fxstoreins(IRIns *ir)
869 {
870 switch (irt_type(ir->t)) {
871 case IRT_I8: case IRT_U8: return PPCI_STB;
872 case IRT_I16: case IRT_U16: return PPCI_STH;
873 case IRT_NUM: return PPCI_STFD;
874 case IRT_FLOAT: return PPCI_STFS;
875 default: return PPCI_STW;
876 }
877 }
878
asm_fload(ASMState * as,IRIns * ir)879 static void asm_fload(ASMState *as, IRIns *ir)
880 {
881 Reg dest = ra_dest(as, ir, RSET_GPR);
882 Reg idx = ra_alloc1(as, ir->op1, RSET_GPR);
883 PPCIns pi = asm_fxloadins(ir);
884 int32_t ofs;
885 if (ir->op2 == IRFL_TAB_ARRAY) {
886 ofs = asm_fuseabase(as, ir->op1);
887 if (ofs) { /* Turn the t->array load into an add for colocated arrays. */
888 emit_tai(as, PPCI_ADDI, dest, idx, ofs);
889 return;
890 }
891 }
892 ofs = field_ofs[ir->op2];
893 lua_assert(!irt_isi8(ir->t));
894 emit_tai(as, pi, dest, idx, ofs);
895 }
896
asm_fstore(ASMState * as,IRIns * ir)897 static void asm_fstore(ASMState *as, IRIns *ir)
898 {
899 if (ir->r != RID_SINK) {
900 Reg src = ra_alloc1(as, ir->op2, RSET_GPR);
901 IRIns *irf = IR(ir->op1);
902 Reg idx = ra_alloc1(as, irf->op1, rset_exclude(RSET_GPR, src));
903 int32_t ofs = field_ofs[irf->op2];
904 PPCIns pi = asm_fxstoreins(ir);
905 emit_tai(as, pi, src, idx, ofs);
906 }
907 }
908
asm_xload(ASMState * as,IRIns * ir)909 static void asm_xload(ASMState *as, IRIns *ir)
910 {
911 Reg dest = ra_dest(as, ir, irt_isfp(ir->t) ? RSET_FPR : RSET_GPR);
912 lua_assert(!(ir->op2 & IRXLOAD_UNALIGNED));
913 if (irt_isi8(ir->t))
914 emit_as(as, PPCI_EXTSB, dest, dest);
915 asm_fusexref(as, asm_fxloadins(ir), dest, ir->op1, RSET_GPR, 0);
916 }
917
asm_xstore(ASMState * as,IRIns * ir,int32_t ofs)918 static void asm_xstore(ASMState *as, IRIns *ir, int32_t ofs)
919 {
920 IRIns *irb;
921 if (ir->r == RID_SINK)
922 return;
923 if (ofs == 0 && mayfuse(as, ir->op2) && (irb = IR(ir->op2))->o == IR_BSWAP &&
924 ra_noreg(irb->r) && (irt_isint(ir->t) || irt_isu32(ir->t))) {
925 /* Fuse BSWAP with XSTORE to stwbrx. */
926 Reg src = ra_alloc1(as, irb->op1, RSET_GPR);
927 asm_fusexrefx(as, PPCI_STWBRX, src, ir->op1, rset_exclude(RSET_GPR, src));
928 } else {
929 Reg src = ra_alloc1(as, ir->op2, irt_isfp(ir->t) ? RSET_FPR : RSET_GPR);
930 asm_fusexref(as, asm_fxstoreins(ir), src, ir->op1,
931 rset_exclude(RSET_GPR, src), ofs);
932 }
933 }
934
asm_ahuvload(ASMState * as,IRIns * ir)935 static void asm_ahuvload(ASMState *as, IRIns *ir)
936 {
937 IRType1 t = ir->t;
938 Reg dest = RID_NONE, type = RID_TMP, tmp = RID_TMP, idx;
939 RegSet allow = RSET_GPR;
940 int32_t ofs = AHUREF_LSX;
941 if (ra_used(ir)) {
942 lua_assert(irt_isnum(t) || irt_isint(t) || irt_isaddr(t));
943 if (!irt_isnum(t)) ofs = 0;
944 dest = ra_dest(as, ir, irt_isnum(t) ? RSET_FPR : RSET_GPR);
945 rset_clear(allow, dest);
946 }
947 idx = asm_fuseahuref(as, ir->op1, &ofs, allow);
948 if (irt_isnum(t)) {
949 Reg tisnum = ra_allock(as, (int32_t)LJ_TISNUM, rset_exclude(allow, idx));
950 asm_guardcc(as, CC_GE);
951 emit_ab(as, PPCI_CMPLW, type, tisnum);
952 if (ra_hasreg(dest)) {
953 if (ofs == AHUREF_LSX) {
954 tmp = ra_scratch(as, rset_exclude(rset_exclude(RSET_GPR,
955 (idx&255)), (idx>>8)));
956 emit_fab(as, PPCI_LFDX, dest, (idx&255), tmp);
957 } else {
958 emit_fai(as, PPCI_LFD, dest, idx, ofs);
959 }
960 }
961 } else {
962 asm_guardcc(as, CC_NE);
963 emit_ai(as, PPCI_CMPWI, type, irt_toitype(t));
964 if (ra_hasreg(dest)) emit_tai(as, PPCI_LWZ, dest, idx, ofs+4);
965 }
966 if (ofs == AHUREF_LSX) {
967 emit_tab(as, PPCI_LWZX, type, (idx&255), tmp);
968 emit_slwi(as, tmp, (idx>>8), 3);
969 } else {
970 emit_tai(as, PPCI_LWZ, type, idx, ofs);
971 }
972 }
973
asm_ahustore(ASMState * as,IRIns * ir)974 static void asm_ahustore(ASMState *as, IRIns *ir)
975 {
976 RegSet allow = RSET_GPR;
977 Reg idx, src = RID_NONE, type = RID_NONE;
978 int32_t ofs = AHUREF_LSX;
979 if (ir->r == RID_SINK)
980 return;
981 if (irt_isnum(ir->t)) {
982 src = ra_alloc1(as, ir->op2, RSET_FPR);
983 } else {
984 if (!irt_ispri(ir->t)) {
985 src = ra_alloc1(as, ir->op2, allow);
986 rset_clear(allow, src);
987 ofs = 0;
988 }
989 type = ra_allock(as, (int32_t)irt_toitype(ir->t), allow);
990 rset_clear(allow, type);
991 }
992 idx = asm_fuseahuref(as, ir->op1, &ofs, allow);
993 if (irt_isnum(ir->t)) {
994 if (ofs == AHUREF_LSX) {
995 emit_fab(as, PPCI_STFDX, src, (idx&255), RID_TMP);
996 emit_slwi(as, RID_TMP, (idx>>8), 3);
997 } else {
998 emit_fai(as, PPCI_STFD, src, idx, ofs);
999 }
1000 } else {
1001 if (ra_hasreg(src))
1002 emit_tai(as, PPCI_STW, src, idx, ofs+4);
1003 if (ofs == AHUREF_LSX) {
1004 emit_tab(as, PPCI_STWX, type, (idx&255), RID_TMP);
1005 emit_slwi(as, RID_TMP, (idx>>8), 3);
1006 } else {
1007 emit_tai(as, PPCI_STW, type, idx, ofs);
1008 }
1009 }
1010 }
1011
asm_sload(ASMState * as,IRIns * ir)1012 static void asm_sload(ASMState *as, IRIns *ir)
1013 {
1014 int32_t ofs = 8*((int32_t)ir->op1-1) + ((ir->op2 & IRSLOAD_FRAME) ? 0 : 4);
1015 IRType1 t = ir->t;
1016 Reg dest = RID_NONE, type = RID_NONE, base;
1017 RegSet allow = RSET_GPR;
1018 lua_assert(!(ir->op2 & IRSLOAD_PARENT)); /* Handled by asm_head_side(). */
1019 lua_assert(irt_isguard(t) || !(ir->op2 & IRSLOAD_TYPECHECK));
1020 lua_assert(LJ_DUALNUM ||
1021 !irt_isint(t) || (ir->op2 & (IRSLOAD_CONVERT|IRSLOAD_FRAME)));
1022 if ((ir->op2 & IRSLOAD_CONVERT) && irt_isguard(t) && irt_isint(t)) {
1023 dest = ra_scratch(as, RSET_FPR);
1024 asm_tointg(as, ir, dest);
1025 t.irt = IRT_NUM; /* Continue with a regular number type check. */
1026 } else if (ra_used(ir)) {
1027 lua_assert(irt_isnum(t) || irt_isint(t) || irt_isaddr(t));
1028 dest = ra_dest(as, ir, irt_isnum(t) ? RSET_FPR : RSET_GPR);
1029 rset_clear(allow, dest);
1030 base = ra_alloc1(as, REF_BASE, allow);
1031 rset_clear(allow, base);
1032 if ((ir->op2 & IRSLOAD_CONVERT)) {
1033 if (irt_isint(t)) {
1034 emit_tai(as, PPCI_LWZ, dest, RID_SP, SPOFS_TMPLO);
1035 dest = ra_scratch(as, RSET_FPR);
1036 emit_fai(as, PPCI_STFD, dest, RID_SP, SPOFS_TMP);
1037 emit_fb(as, PPCI_FCTIWZ, dest, dest);
1038 t.irt = IRT_NUM; /* Check for original type. */
1039 } else {
1040 Reg tmp = ra_scratch(as, allow);
1041 Reg hibias = ra_allock(as, 0x43300000, rset_clear(allow, tmp));
1042 Reg fbias = ra_scratch(as, rset_exclude(RSET_FPR, dest));
1043 emit_fab(as, PPCI_FSUB, dest, dest, fbias);
1044 emit_fai(as, PPCI_LFD, dest, RID_SP, SPOFS_TMP);
1045 emit_lsptr(as, PPCI_LFS, (fbias & 31),
1046 (void *)lj_ir_k64_find(as->J, U64x(59800004,59800000)),
1047 rset_clear(allow, hibias));
1048 emit_tai(as, PPCI_STW, tmp, RID_SP, SPOFS_TMPLO);
1049 emit_tai(as, PPCI_STW, hibias, RID_SP, SPOFS_TMPHI);
1050 emit_asi(as, PPCI_XORIS, tmp, tmp, 0x8000);
1051 dest = tmp;
1052 t.irt = IRT_INT; /* Check for original type. */
1053 }
1054 }
1055 goto dotypecheck;
1056 }
1057 base = ra_alloc1(as, REF_BASE, allow);
1058 rset_clear(allow, base);
1059 dotypecheck:
1060 if (irt_isnum(t)) {
1061 if ((ir->op2 & IRSLOAD_TYPECHECK)) {
1062 Reg tisnum = ra_allock(as, (int32_t)LJ_TISNUM, allow);
1063 asm_guardcc(as, CC_GE);
1064 emit_ab(as, PPCI_CMPLW, RID_TMP, tisnum);
1065 type = RID_TMP;
1066 }
1067 if (ra_hasreg(dest)) emit_fai(as, PPCI_LFD, dest, base, ofs-4);
1068 } else {
1069 if ((ir->op2 & IRSLOAD_TYPECHECK)) {
1070 asm_guardcc(as, CC_NE);
1071 emit_ai(as, PPCI_CMPWI, RID_TMP, irt_toitype(t));
1072 type = RID_TMP;
1073 }
1074 if (ra_hasreg(dest)) emit_tai(as, PPCI_LWZ, dest, base, ofs);
1075 }
1076 if (ra_hasreg(type)) emit_tai(as, PPCI_LWZ, type, base, ofs-4);
1077 }
1078
1079 /* -- Allocations --------------------------------------------------------- */
1080
1081 #if LJ_HASFFI
asm_cnew(ASMState * as,IRIns * ir)1082 static void asm_cnew(ASMState *as, IRIns *ir)
1083 {
1084 CTState *cts = ctype_ctsG(J2G(as->J));
1085 CTypeID ctypeid = (CTypeID)IR(ir->op1)->i;
1086 CTSize sz = (ir->o == IR_CNEWI || ir->op2 == REF_NIL) ?
1087 lj_ctype_size(cts, ctypeid) : (CTSize)IR(ir->op2)->i;
1088 const CCallInfo *ci = &lj_ir_callinfo[IRCALL_lj_mem_newgco];
1089 IRRef args[2];
1090 RegSet allow = (RSET_GPR & ~RSET_SCRATCH);
1091 RegSet drop = RSET_SCRATCH;
1092 lua_assert(sz != CTSIZE_INVALID);
1093
1094 args[0] = ASMREF_L; /* lua_State *L */
1095 args[1] = ASMREF_TMP1; /* MSize size */
1096 as->gcsteps++;
1097
1098 if (ra_hasreg(ir->r))
1099 rset_clear(drop, ir->r); /* Dest reg handled below. */
1100 ra_evictset(as, drop);
1101 if (ra_used(ir))
1102 ra_destreg(as, ir, RID_RET); /* GCcdata * */
1103
1104 /* Initialize immutable cdata object. */
1105 if (ir->o == IR_CNEWI) {
1106 int32_t ofs = sizeof(GCcdata);
1107 lua_assert(sz == 4 || sz == 8);
1108 if (sz == 8) {
1109 ofs += 4;
1110 lua_assert((ir+1)->o == IR_HIOP);
1111 }
1112 for (;;) {
1113 Reg r = ra_alloc1(as, ir->op2, allow);
1114 emit_tai(as, PPCI_STW, r, RID_RET, ofs);
1115 rset_clear(allow, r);
1116 if (ofs == sizeof(GCcdata)) break;
1117 ofs -= 4; ir++;
1118 }
1119 }
1120 /* Initialize gct and ctypeid. lj_mem_newgco() already sets marked. */
1121 emit_tai(as, PPCI_STB, RID_RET+1, RID_RET, offsetof(GCcdata, gct));
1122 emit_tai(as, PPCI_STH, RID_TMP, RID_RET, offsetof(GCcdata, ctypeid));
1123 emit_ti(as, PPCI_LI, RID_RET+1, ~LJ_TCDATA);
1124 emit_ti(as, PPCI_LI, RID_TMP, ctypeid); /* Lower 16 bit used. Sign-ext ok. */
1125 asm_gencall(as, ci, args);
1126 ra_allockreg(as, (int32_t)(sz+sizeof(GCcdata)),
1127 ra_releasetmp(as, ASMREF_TMP1));
1128 }
1129 #else
1130 #define asm_cnew(as, ir) ((void)0)
1131 #endif
1132
1133 /* -- Write barriers ------------------------------------------------------ */
1134
asm_tbar(ASMState * as,IRIns * ir)1135 static void asm_tbar(ASMState *as, IRIns *ir)
1136 {
1137 Reg tab = ra_alloc1(as, ir->op1, RSET_GPR);
1138 Reg mark = ra_scratch(as, rset_exclude(RSET_GPR, tab));
1139 Reg link = RID_TMP;
1140 MCLabel l_end = emit_label(as);
1141 emit_tai(as, PPCI_STW, link, tab, (int32_t)offsetof(GCtab, gclist));
1142 emit_tai(as, PPCI_STB, mark, tab, (int32_t)offsetof(GCtab, marked));
1143 emit_setgl(as, tab, gc.grayagain);
1144 lua_assert(LJ_GC_BLACK == 0x04);
1145 emit_rot(as, PPCI_RLWINM, mark, mark, 0, 30, 28); /* Clear black bit. */
1146 emit_getgl(as, link, gc.grayagain);
1147 emit_condbranch(as, PPCI_BC|PPCF_Y, CC_EQ, l_end);
1148 emit_asi(as, PPCI_ANDIDOT, RID_TMP, mark, LJ_GC_BLACK);
1149 emit_tai(as, PPCI_LBZ, mark, tab, (int32_t)offsetof(GCtab, marked));
1150 }
1151
asm_obar(ASMState * as,IRIns * ir)1152 static void asm_obar(ASMState *as, IRIns *ir)
1153 {
1154 const CCallInfo *ci = &lj_ir_callinfo[IRCALL_lj_gc_barrieruv];
1155 IRRef args[2];
1156 MCLabel l_end;
1157 Reg obj, val, tmp;
1158 /* No need for other object barriers (yet). */
1159 lua_assert(IR(ir->op1)->o == IR_UREFC);
1160 ra_evictset(as, RSET_SCRATCH);
1161 l_end = emit_label(as);
1162 args[0] = ASMREF_TMP1; /* global_State *g */
1163 args[1] = ir->op1; /* TValue *tv */
1164 asm_gencall(as, ci, args);
1165 emit_tai(as, PPCI_ADDI, ra_releasetmp(as, ASMREF_TMP1), RID_JGL, -32768);
1166 obj = IR(ir->op1)->r;
1167 tmp = ra_scratch(as, rset_exclude(RSET_GPR, obj));
1168 emit_condbranch(as, PPCI_BC|PPCF_Y, CC_EQ, l_end);
1169 emit_asi(as, PPCI_ANDIDOT, tmp, tmp, LJ_GC_BLACK);
1170 emit_condbranch(as, PPCI_BC, CC_EQ, l_end);
1171 emit_asi(as, PPCI_ANDIDOT, RID_TMP, RID_TMP, LJ_GC_WHITES);
1172 val = ra_alloc1(as, ir->op2, rset_exclude(RSET_GPR, obj));
1173 emit_tai(as, PPCI_LBZ, tmp, obj,
1174 (int32_t)offsetof(GCupval, marked)-(int32_t)offsetof(GCupval, tv));
1175 emit_tai(as, PPCI_LBZ, RID_TMP, val, (int32_t)offsetof(GChead, marked));
1176 }
1177
1178 /* -- Arithmetic and logic operations ------------------------------------- */
1179
asm_fparith(ASMState * as,IRIns * ir,PPCIns pi)1180 static void asm_fparith(ASMState *as, IRIns *ir, PPCIns pi)
1181 {
1182 Reg dest = ra_dest(as, ir, RSET_FPR);
1183 Reg right, left = ra_alloc2(as, ir, RSET_FPR);
1184 right = (left >> 8); left &= 255;
1185 if (pi == PPCI_FMUL)
1186 emit_fac(as, pi, dest, left, right);
1187 else
1188 emit_fab(as, pi, dest, left, right);
1189 }
1190
asm_fpunary(ASMState * as,IRIns * ir,PPCIns pi)1191 static void asm_fpunary(ASMState *as, IRIns *ir, PPCIns pi)
1192 {
1193 Reg dest = ra_dest(as, ir, RSET_FPR);
1194 Reg left = ra_hintalloc(as, ir->op1, dest, RSET_FPR);
1195 emit_fb(as, pi, dest, left);
1196 }
1197
asm_fpjoin_pow(ASMState * as,IRIns * ir)1198 static int asm_fpjoin_pow(ASMState *as, IRIns *ir)
1199 {
1200 IRIns *irp = IR(ir->op1);
1201 if (irp == ir-1 && irp->o == IR_MUL && !ra_used(irp)) {
1202 IRIns *irpp = IR(irp->op1);
1203 if (irpp == ir-2 && irpp->o == IR_FPMATH &&
1204 irpp->op2 == IRFPM_LOG2 && !ra_used(irpp)) {
1205 const CCallInfo *ci = &lj_ir_callinfo[IRCALL_pow];
1206 IRRef args[2];
1207 args[0] = irpp->op1;
1208 args[1] = irp->op2;
1209 asm_setupresult(as, ir, ci);
1210 asm_gencall(as, ci, args);
1211 return 1;
1212 }
1213 }
1214 return 0;
1215 }
1216
asm_add(ASMState * as,IRIns * ir)1217 static void asm_add(ASMState *as, IRIns *ir)
1218 {
1219 if (irt_isnum(ir->t)) {
1220 if (!asm_fusemadd(as, ir, PPCI_FMADD, PPCI_FMADD))
1221 asm_fparith(as, ir, PPCI_FADD);
1222 } else {
1223 Reg dest = ra_dest(as, ir, RSET_GPR);
1224 Reg right, left = ra_hintalloc(as, ir->op1, dest, RSET_GPR);
1225 PPCIns pi;
1226 if (irref_isk(ir->op2)) {
1227 int32_t k = IR(ir->op2)->i;
1228 if (checki16(k)) {
1229 pi = PPCI_ADDI;
1230 /* May fail due to spills/restores above, but simplifies the logic. */
1231 if (as->flagmcp == as->mcp) {
1232 as->flagmcp = NULL;
1233 as->mcp++;
1234 pi = PPCI_ADDICDOT;
1235 }
1236 emit_tai(as, pi, dest, left, k);
1237 return;
1238 } else if ((k & 0xffff) == 0) {
1239 emit_tai(as, PPCI_ADDIS, dest, left, (k >> 16));
1240 return;
1241 } else if (!as->sectref) {
1242 emit_tai(as, PPCI_ADDIS, dest, dest, (k + 32768) >> 16);
1243 emit_tai(as, PPCI_ADDI, dest, left, k);
1244 return;
1245 }
1246 }
1247 pi = PPCI_ADD;
1248 /* May fail due to spills/restores above, but simplifies the logic. */
1249 if (as->flagmcp == as->mcp) {
1250 as->flagmcp = NULL;
1251 as->mcp++;
1252 pi |= PPCF_DOT;
1253 }
1254 right = ra_alloc1(as, ir->op2, rset_exclude(RSET_GPR, left));
1255 emit_tab(as, pi, dest, left, right);
1256 }
1257 }
1258
asm_sub(ASMState * as,IRIns * ir)1259 static void asm_sub(ASMState *as, IRIns *ir)
1260 {
1261 if (irt_isnum(ir->t)) {
1262 if (!asm_fusemadd(as, ir, PPCI_FMSUB, PPCI_FNMSUB))
1263 asm_fparith(as, ir, PPCI_FSUB);
1264 } else {
1265 PPCIns pi = PPCI_SUBF;
1266 Reg dest = ra_dest(as, ir, RSET_GPR);
1267 Reg left, right;
1268 if (irref_isk(ir->op1)) {
1269 int32_t k = IR(ir->op1)->i;
1270 if (checki16(k)) {
1271 right = ra_alloc1(as, ir->op2, RSET_GPR);
1272 emit_tai(as, PPCI_SUBFIC, dest, right, k);
1273 return;
1274 }
1275 }
1276 /* May fail due to spills/restores above, but simplifies the logic. */
1277 if (as->flagmcp == as->mcp) {
1278 as->flagmcp = NULL;
1279 as->mcp++;
1280 pi |= PPCF_DOT;
1281 }
1282 left = ra_hintalloc(as, ir->op1, dest, RSET_GPR);
1283 right = ra_alloc1(as, ir->op2, rset_exclude(RSET_GPR, left));
1284 emit_tab(as, pi, dest, right, left); /* Subtract right _from_ left. */
1285 }
1286 }
1287
asm_mul(ASMState * as,IRIns * ir)1288 static void asm_mul(ASMState *as, IRIns *ir)
1289 {
1290 if (irt_isnum(ir->t)) {
1291 asm_fparith(as, ir, PPCI_FMUL);
1292 } else {
1293 PPCIns pi = PPCI_MULLW;
1294 Reg dest = ra_dest(as, ir, RSET_GPR);
1295 Reg right, left = ra_hintalloc(as, ir->op1, dest, RSET_GPR);
1296 if (irref_isk(ir->op2)) {
1297 int32_t k = IR(ir->op2)->i;
1298 if (checki16(k)) {
1299 emit_tai(as, PPCI_MULLI, dest, left, k);
1300 return;
1301 }
1302 }
1303 /* May fail due to spills/restores above, but simplifies the logic. */
1304 if (as->flagmcp == as->mcp) {
1305 as->flagmcp = NULL;
1306 as->mcp++;
1307 pi |= PPCF_DOT;
1308 }
1309 right = ra_alloc1(as, ir->op2, rset_exclude(RSET_GPR, left));
1310 emit_tab(as, pi, dest, left, right);
1311 }
1312 }
1313
asm_neg(ASMState * as,IRIns * ir)1314 static void asm_neg(ASMState *as, IRIns *ir)
1315 {
1316 if (irt_isnum(ir->t)) {
1317 asm_fpunary(as, ir, PPCI_FNEG);
1318 } else {
1319 Reg dest, left;
1320 PPCIns pi = PPCI_NEG;
1321 if (as->flagmcp == as->mcp) {
1322 as->flagmcp = NULL;
1323 as->mcp++;
1324 pi |= PPCF_DOT;
1325 }
1326 dest = ra_dest(as, ir, RSET_GPR);
1327 left = ra_hintalloc(as, ir->op1, dest, RSET_GPR);
1328 emit_tab(as, pi, dest, left, 0);
1329 }
1330 }
1331
asm_arithov(ASMState * as,IRIns * ir,PPCIns pi)1332 static void asm_arithov(ASMState *as, IRIns *ir, PPCIns pi)
1333 {
1334 Reg dest, left, right;
1335 if (as->flagmcp == as->mcp) {
1336 as->flagmcp = NULL;
1337 as->mcp++;
1338 }
1339 asm_guardcc(as, CC_SO);
1340 dest = ra_dest(as, ir, RSET_GPR);
1341 left = ra_alloc2(as, ir, RSET_GPR);
1342 right = (left >> 8); left &= 255;
1343 if (pi == PPCI_SUBFO) { Reg tmp = left; left = right; right = tmp; }
1344 emit_tab(as, pi|PPCF_DOT, dest, left, right);
1345 }
1346
1347 #if LJ_HASFFI
asm_add64(ASMState * as,IRIns * ir)1348 static void asm_add64(ASMState *as, IRIns *ir)
1349 {
1350 Reg dest = ra_dest(as, ir, RSET_GPR);
1351 Reg right, left = ra_alloc1(as, ir->op1, RSET_GPR);
1352 PPCIns pi = PPCI_ADDE;
1353 if (irref_isk(ir->op2)) {
1354 int32_t k = IR(ir->op2)->i;
1355 if (k == 0)
1356 pi = PPCI_ADDZE;
1357 else if (k == -1)
1358 pi = PPCI_ADDME;
1359 else
1360 goto needright;
1361 right = 0;
1362 } else {
1363 needright:
1364 right = ra_alloc1(as, ir->op2, rset_exclude(RSET_GPR, left));
1365 }
1366 emit_tab(as, pi, dest, left, right);
1367 ir--;
1368 dest = ra_dest(as, ir, RSET_GPR);
1369 left = ra_alloc1(as, ir->op1, RSET_GPR);
1370 if (irref_isk(ir->op2)) {
1371 int32_t k = IR(ir->op2)->i;
1372 if (checki16(k)) {
1373 emit_tai(as, PPCI_ADDIC, dest, left, k);
1374 return;
1375 }
1376 }
1377 right = ra_alloc1(as, ir->op2, rset_exclude(RSET_GPR, left));
1378 emit_tab(as, PPCI_ADDC, dest, left, right);
1379 }
1380
asm_sub64(ASMState * as,IRIns * ir)1381 static void asm_sub64(ASMState *as, IRIns *ir)
1382 {
1383 Reg dest = ra_dest(as, ir, RSET_GPR);
1384 Reg left, right = ra_alloc1(as, ir->op2, RSET_GPR);
1385 PPCIns pi = PPCI_SUBFE;
1386 if (irref_isk(ir->op1)) {
1387 int32_t k = IR(ir->op1)->i;
1388 if (k == 0)
1389 pi = PPCI_SUBFZE;
1390 else if (k == -1)
1391 pi = PPCI_SUBFME;
1392 else
1393 goto needleft;
1394 left = 0;
1395 } else {
1396 needleft:
1397 left = ra_alloc1(as, ir->op1, rset_exclude(RSET_GPR, right));
1398 }
1399 emit_tab(as, pi, dest, right, left); /* Subtract right _from_ left. */
1400 ir--;
1401 dest = ra_dest(as, ir, RSET_GPR);
1402 right = ra_alloc1(as, ir->op2, RSET_GPR);
1403 if (irref_isk(ir->op1)) {
1404 int32_t k = IR(ir->op1)->i;
1405 if (checki16(k)) {
1406 emit_tai(as, PPCI_SUBFIC, dest, right, k);
1407 return;
1408 }
1409 }
1410 left = ra_alloc1(as, ir->op1, rset_exclude(RSET_GPR, right));
1411 emit_tab(as, PPCI_SUBFC, dest, right, left);
1412 }
1413
asm_neg64(ASMState * as,IRIns * ir)1414 static void asm_neg64(ASMState *as, IRIns *ir)
1415 {
1416 Reg dest = ra_dest(as, ir, RSET_GPR);
1417 Reg left = ra_alloc1(as, ir->op1, RSET_GPR);
1418 emit_tab(as, PPCI_SUBFZE, dest, left, 0);
1419 ir--;
1420 dest = ra_dest(as, ir, RSET_GPR);
1421 left = ra_alloc1(as, ir->op1, RSET_GPR);
1422 emit_tai(as, PPCI_SUBFIC, dest, left, 0);
1423 }
1424 #endif
1425
asm_bitnot(ASMState * as,IRIns * ir)1426 static void asm_bitnot(ASMState *as, IRIns *ir)
1427 {
1428 Reg dest, left, right;
1429 PPCIns pi = PPCI_NOR;
1430 if (as->flagmcp == as->mcp) {
1431 as->flagmcp = NULL;
1432 as->mcp++;
1433 pi |= PPCF_DOT;
1434 }
1435 dest = ra_dest(as, ir, RSET_GPR);
1436 if (mayfuse(as, ir->op1)) {
1437 IRIns *irl = IR(ir->op1);
1438 if (irl->o == IR_BAND)
1439 pi ^= (PPCI_NOR ^ PPCI_NAND);
1440 else if (irl->o == IR_BXOR)
1441 pi ^= (PPCI_NOR ^ PPCI_EQV);
1442 else if (irl->o != IR_BOR)
1443 goto nofuse;
1444 left = ra_hintalloc(as, irl->op1, dest, RSET_GPR);
1445 right = ra_alloc1(as, irl->op2, rset_exclude(RSET_GPR, left));
1446 } else {
1447 nofuse:
1448 left = right = ra_hintalloc(as, ir->op1, dest, RSET_GPR);
1449 }
1450 emit_asb(as, pi, dest, left, right);
1451 }
1452
asm_bitswap(ASMState * as,IRIns * ir)1453 static void asm_bitswap(ASMState *as, IRIns *ir)
1454 {
1455 Reg dest = ra_dest(as, ir, RSET_GPR);
1456 IRIns *irx;
1457 if (mayfuse(as, ir->op1) && (irx = IR(ir->op1))->o == IR_XLOAD &&
1458 ra_noreg(irx->r) && (irt_isint(irx->t) || irt_isu32(irx->t))) {
1459 /* Fuse BSWAP with XLOAD to lwbrx. */
1460 asm_fusexrefx(as, PPCI_LWBRX, dest, irx->op1, RSET_GPR);
1461 } else {
1462 Reg left = ra_alloc1(as, ir->op1, RSET_GPR);
1463 Reg tmp = dest;
1464 if (tmp == left) {
1465 tmp = RID_TMP;
1466 emit_mr(as, dest, RID_TMP);
1467 }
1468 emit_rot(as, PPCI_RLWIMI, tmp, left, 24, 16, 23);
1469 emit_rot(as, PPCI_RLWIMI, tmp, left, 24, 0, 7);
1470 emit_rotlwi(as, tmp, left, 8);
1471 }
1472 }
1473
asm_bitop(ASMState * as,IRIns * ir,PPCIns pi,PPCIns pik)1474 static void asm_bitop(ASMState *as, IRIns *ir, PPCIns pi, PPCIns pik)
1475 {
1476 Reg dest = ra_dest(as, ir, RSET_GPR);
1477 Reg right, left = ra_hintalloc(as, ir->op1, dest, RSET_GPR);
1478 if (irref_isk(ir->op2)) {
1479 int32_t k = IR(ir->op2)->i;
1480 Reg tmp = left;
1481 if ((checku16(k) || (k & 0xffff) == 0) || (tmp = dest, !as->sectref)) {
1482 if (!checku16(k)) {
1483 emit_asi(as, pik ^ (PPCI_ORI ^ PPCI_ORIS), dest, tmp, (k >> 16));
1484 if ((k & 0xffff) == 0) return;
1485 }
1486 emit_asi(as, pik, dest, left, k);
1487 return;
1488 }
1489 }
1490 /* May fail due to spills/restores above, but simplifies the logic. */
1491 if (as->flagmcp == as->mcp) {
1492 as->flagmcp = NULL;
1493 as->mcp++;
1494 pi |= PPCF_DOT;
1495 }
1496 right = ra_alloc1(as, ir->op2, rset_exclude(RSET_GPR, left));
1497 emit_asb(as, pi, dest, left, right);
1498 }
1499
1500 /* Fuse BAND with contiguous bitmask and a shift to rlwinm. */
asm_fuseandsh(ASMState * as,PPCIns pi,int32_t mask,IRRef ref)1501 static void asm_fuseandsh(ASMState *as, PPCIns pi, int32_t mask, IRRef ref)
1502 {
1503 IRIns *ir;
1504 Reg left;
1505 if (mayfuse(as, ref) && (ir = IR(ref), ra_noreg(ir->r)) &&
1506 irref_isk(ir->op2) && ir->o >= IR_BSHL && ir->o <= IR_BROR) {
1507 int32_t sh = (IR(ir->op2)->i & 31);
1508 switch (ir->o) {
1509 case IR_BSHL:
1510 if ((mask & ((1u<<sh)-1))) goto nofuse;
1511 break;
1512 case IR_BSHR:
1513 if ((mask & ~((~0u)>>sh))) goto nofuse;
1514 sh = ((32-sh)&31);
1515 break;
1516 case IR_BROL:
1517 break;
1518 default:
1519 goto nofuse;
1520 }
1521 left = ra_alloc1(as, ir->op1, RSET_GPR);
1522 *--as->mcp = pi | PPCF_T(left) | PPCF_B(sh);
1523 return;
1524 }
1525 nofuse:
1526 left = ra_alloc1(as, ref, RSET_GPR);
1527 *--as->mcp = pi | PPCF_T(left);
1528 }
1529
asm_bitand(ASMState * as,IRIns * ir)1530 static void asm_bitand(ASMState *as, IRIns *ir)
1531 {
1532 Reg dest, left, right;
1533 IRRef lref = ir->op1;
1534 PPCIns dot = 0;
1535 IRRef op2;
1536 if (as->flagmcp == as->mcp) {
1537 as->flagmcp = NULL;
1538 as->mcp++;
1539 dot = PPCF_DOT;
1540 }
1541 dest = ra_dest(as, ir, RSET_GPR);
1542 if (irref_isk(ir->op2)) {
1543 int32_t k = IR(ir->op2)->i;
1544 if (k) {
1545 /* First check for a contiguous bitmask as used by rlwinm. */
1546 uint32_t s1 = lj_ffs((uint32_t)k);
1547 uint32_t k1 = ((uint32_t)k >> s1);
1548 if ((k1 & (k1+1)) == 0) {
1549 asm_fuseandsh(as, PPCI_RLWINM|dot | PPCF_A(dest) |
1550 PPCF_MB(31-lj_fls((uint32_t)k)) | PPCF_ME(31-s1),
1551 k, lref);
1552 return;
1553 }
1554 if (~(uint32_t)k) {
1555 uint32_t s2 = lj_ffs(~(uint32_t)k);
1556 uint32_t k2 = (~(uint32_t)k >> s2);
1557 if ((k2 & (k2+1)) == 0) {
1558 asm_fuseandsh(as, PPCI_RLWINM|dot | PPCF_A(dest) |
1559 PPCF_MB(32-s2) | PPCF_ME(30-lj_fls(~(uint32_t)k)),
1560 k, lref);
1561 return;
1562 }
1563 }
1564 }
1565 if (checku16(k)) {
1566 left = ra_alloc1(as, lref, RSET_GPR);
1567 emit_asi(as, PPCI_ANDIDOT, dest, left, k);
1568 return;
1569 } else if ((k & 0xffff) == 0) {
1570 left = ra_alloc1(as, lref, RSET_GPR);
1571 emit_asi(as, PPCI_ANDISDOT, dest, left, (k >> 16));
1572 return;
1573 }
1574 }
1575 op2 = ir->op2;
1576 if (mayfuse(as, op2) && IR(op2)->o == IR_BNOT && ra_noreg(IR(op2)->r)) {
1577 dot ^= (PPCI_AND ^ PPCI_ANDC);
1578 op2 = IR(op2)->op1;
1579 }
1580 left = ra_hintalloc(as, lref, dest, RSET_GPR);
1581 right = ra_alloc1(as, op2, rset_exclude(RSET_GPR, left));
1582 emit_asb(as, PPCI_AND ^ dot, dest, left, right);
1583 }
1584
asm_bitshift(ASMState * as,IRIns * ir,PPCIns pi,PPCIns pik)1585 static void asm_bitshift(ASMState *as, IRIns *ir, PPCIns pi, PPCIns pik)
1586 {
1587 Reg dest, left;
1588 Reg dot = 0;
1589 if (as->flagmcp == as->mcp) {
1590 as->flagmcp = NULL;
1591 as->mcp++;
1592 dot = PPCF_DOT;
1593 }
1594 dest = ra_dest(as, ir, RSET_GPR);
1595 left = ra_alloc1(as, ir->op1, RSET_GPR);
1596 if (irref_isk(ir->op2)) { /* Constant shifts. */
1597 int32_t shift = (IR(ir->op2)->i & 31);
1598 if (pik == 0) /* SLWI */
1599 emit_rot(as, PPCI_RLWINM|dot, dest, left, shift, 0, 31-shift);
1600 else if (pik == 1) /* SRWI */
1601 emit_rot(as, PPCI_RLWINM|dot, dest, left, (32-shift)&31, shift, 31);
1602 else
1603 emit_asb(as, pik|dot, dest, left, shift);
1604 } else {
1605 Reg right = ra_alloc1(as, ir->op2, rset_exclude(RSET_GPR, left));
1606 emit_asb(as, pi|dot, dest, left, right);
1607 }
1608 }
1609
asm_min_max(ASMState * as,IRIns * ir,int ismax)1610 static void asm_min_max(ASMState *as, IRIns *ir, int ismax)
1611 {
1612 if (irt_isnum(ir->t)) {
1613 Reg dest = ra_dest(as, ir, RSET_FPR);
1614 Reg tmp = dest;
1615 Reg right, left = ra_alloc2(as, ir, RSET_FPR);
1616 right = (left >> 8); left &= 255;
1617 if (tmp == left || tmp == right)
1618 tmp = ra_scratch(as, rset_exclude(rset_exclude(rset_exclude(RSET_FPR,
1619 dest), left), right));
1620 emit_facb(as, PPCI_FSEL, dest, tmp,
1621 ismax ? left : right, ismax ? right : left);
1622 emit_fab(as, PPCI_FSUB, tmp, left, right);
1623 } else {
1624 Reg dest = ra_dest(as, ir, RSET_GPR);
1625 Reg tmp1 = RID_TMP, tmp2 = dest;
1626 Reg right, left = ra_alloc2(as, ir, RSET_GPR);
1627 right = (left >> 8); left &= 255;
1628 if (tmp2 == left || tmp2 == right)
1629 tmp2 = ra_scratch(as, rset_exclude(rset_exclude(rset_exclude(RSET_GPR,
1630 dest), left), right));
1631 emit_tab(as, PPCI_ADD, dest, tmp2, right);
1632 emit_asb(as, ismax ? PPCI_ANDC : PPCI_AND, tmp2, tmp2, tmp1);
1633 emit_tab(as, PPCI_SUBFE, tmp1, tmp1, tmp1);
1634 emit_tab(as, PPCI_SUBFC, tmp2, tmp2, tmp1);
1635 emit_asi(as, PPCI_XORIS, tmp2, right, 0x8000);
1636 emit_asi(as, PPCI_XORIS, tmp1, left, 0x8000);
1637 }
1638 }
1639
1640 /* -- Comparisons --------------------------------------------------------- */
1641
1642 #define CC_UNSIGNED 0x08 /* Unsigned integer comparison. */
1643 #define CC_TWO 0x80 /* Check two flags for FP comparison. */
1644
1645 /* Map of comparisons to flags. ORDER IR. */
1646 static const uint8_t asm_compmap[IR_ABC+1] = {
1647 /* op int cc FP cc */
1648 /* LT */ CC_GE + (CC_GE<<4),
1649 /* GE */ CC_LT + (CC_LE<<4) + CC_TWO,
1650 /* LE */ CC_GT + (CC_GE<<4) + CC_TWO,
1651 /* GT */ CC_LE + (CC_LE<<4),
1652 /* ULT */ CC_GE + CC_UNSIGNED + (CC_GT<<4) + CC_TWO,
1653 /* UGE */ CC_LT + CC_UNSIGNED + (CC_LT<<4),
1654 /* ULE */ CC_GT + CC_UNSIGNED + (CC_GT<<4),
1655 /* UGT */ CC_LE + CC_UNSIGNED + (CC_LT<<4) + CC_TWO,
1656 /* EQ */ CC_NE + (CC_NE<<4),
1657 /* NE */ CC_EQ + (CC_EQ<<4),
1658 /* ABC */ CC_LE + CC_UNSIGNED + (CC_LT<<4) + CC_TWO /* Same as UGT. */
1659 };
1660
asm_intcomp_(ASMState * as,IRRef lref,IRRef rref,Reg cr,PPCCC cc)1661 static void asm_intcomp_(ASMState *as, IRRef lref, IRRef rref, Reg cr, PPCCC cc)
1662 {
1663 Reg right, left = ra_alloc1(as, lref, RSET_GPR);
1664 if (irref_isk(rref)) {
1665 int32_t k = IR(rref)->i;
1666 if ((cc & CC_UNSIGNED) == 0) { /* Signed comparison with constant. */
1667 if (checki16(k)) {
1668 emit_tai(as, PPCI_CMPWI, cr, left, k);
1669 /* Signed comparison with zero and referencing previous ins? */
1670 if (k == 0 && lref == as->curins-1)
1671 as->flagmcp = as->mcp; /* Allow elimination of the compare. */
1672 return;
1673 } else if ((cc & 3) == (CC_EQ & 3)) { /* Use CMPLWI for EQ or NE. */
1674 if (checku16(k)) {
1675 emit_tai(as, PPCI_CMPLWI, cr, left, k);
1676 return;
1677 } else if (!as->sectref && ra_noreg(IR(rref)->r)) {
1678 emit_tai(as, PPCI_CMPLWI, cr, RID_TMP, k);
1679 emit_asi(as, PPCI_XORIS, RID_TMP, left, (k >> 16));
1680 return;
1681 }
1682 }
1683 } else { /* Unsigned comparison with constant. */
1684 if (checku16(k)) {
1685 emit_tai(as, PPCI_CMPLWI, cr, left, k);
1686 return;
1687 }
1688 }
1689 }
1690 right = ra_alloc1(as, rref, rset_exclude(RSET_GPR, left));
1691 emit_tab(as, (cc & CC_UNSIGNED) ? PPCI_CMPLW : PPCI_CMPW, cr, left, right);
1692 }
1693
asm_comp(ASMState * as,IRIns * ir)1694 static void asm_comp(ASMState *as, IRIns *ir)
1695 {
1696 PPCCC cc = asm_compmap[ir->o];
1697 if (irt_isnum(ir->t)) {
1698 Reg right, left = ra_alloc2(as, ir, RSET_FPR);
1699 right = (left >> 8); left &= 255;
1700 asm_guardcc(as, (cc >> 4));
1701 if ((cc & CC_TWO))
1702 emit_tab(as, PPCI_CROR, ((cc>>4)&3), ((cc>>4)&3), (CC_EQ&3));
1703 emit_fab(as, PPCI_FCMPU, 0, left, right);
1704 } else {
1705 IRRef lref = ir->op1, rref = ir->op2;
1706 if (irref_isk(lref) && !irref_isk(rref)) {
1707 /* Swap constants to the right (only for ABC). */
1708 IRRef tmp = lref; lref = rref; rref = tmp;
1709 if ((cc & 2) == 0) cc ^= 1; /* LT <-> GT, LE <-> GE */
1710 }
1711 asm_guardcc(as, cc);
1712 asm_intcomp_(as, lref, rref, 0, cc);
1713 }
1714 }
1715
1716 #if LJ_HASFFI
1717 /* 64 bit integer comparisons. */
asm_comp64(ASMState * as,IRIns * ir)1718 static void asm_comp64(ASMState *as, IRIns *ir)
1719 {
1720 PPCCC cc = asm_compmap[(ir-1)->o];
1721 if ((cc&3) == (CC_EQ&3)) {
1722 asm_guardcc(as, cc);
1723 emit_tab(as, (cc&4) ? PPCI_CRAND : PPCI_CROR,
1724 (CC_EQ&3), (CC_EQ&3), 4+(CC_EQ&3));
1725 } else {
1726 asm_guardcc(as, CC_EQ);
1727 emit_tab(as, PPCI_CROR, (CC_EQ&3), (CC_EQ&3), ((cc^~(cc>>2))&1));
1728 emit_tab(as, (cc&4) ? PPCI_CRAND : PPCI_CRANDC,
1729 (CC_EQ&3), (CC_EQ&3), 4+(cc&3));
1730 }
1731 /* Loword comparison sets cr1 and is unsigned, except for equality. */
1732 asm_intcomp_(as, (ir-1)->op1, (ir-1)->op2, 4,
1733 cc | ((cc&3) == (CC_EQ&3) ? 0 : CC_UNSIGNED));
1734 /* Hiword comparison sets cr0. */
1735 asm_intcomp_(as, ir->op1, ir->op2, 0, cc);
1736 as->flagmcp = NULL; /* Doesn't work here. */
1737 }
1738 #endif
1739
1740 /* -- Support for 64 bit ops in 32 bit mode ------------------------------- */
1741
1742 /* Hiword op of a split 64 bit op. Previous op must be the loword op. */
asm_hiop(ASMState * as,IRIns * ir)1743 static void asm_hiop(ASMState *as, IRIns *ir)
1744 {
1745 #if LJ_HASFFI
1746 /* HIOP is marked as a store because it needs its own DCE logic. */
1747 int uselo = ra_used(ir-1), usehi = ra_used(ir); /* Loword/hiword used? */
1748 if (LJ_UNLIKELY(!(as->flags & JIT_F_OPT_DCE))) uselo = usehi = 1;
1749 if ((ir-1)->o == IR_CONV) { /* Conversions to/from 64 bit. */
1750 as->curins--; /* Always skip the CONV. */
1751 if (usehi || uselo)
1752 asm_conv64(as, ir);
1753 return;
1754 } else if ((ir-1)->o <= IR_NE) { /* 64 bit integer comparisons. ORDER IR. */
1755 as->curins--; /* Always skip the loword comparison. */
1756 asm_comp64(as, ir);
1757 return;
1758 } else if ((ir-1)->o == IR_XSTORE) {
1759 as->curins--; /* Handle both stores here. */
1760 if ((ir-1)->r != RID_SINK) {
1761 asm_xstore(as, ir, 0);
1762 asm_xstore(as, ir-1, 4);
1763 }
1764 return;
1765 }
1766 if (!usehi) return; /* Skip unused hiword op for all remaining ops. */
1767 switch ((ir-1)->o) {
1768 case IR_ADD: as->curins--; asm_add64(as, ir); break;
1769 case IR_SUB: as->curins--; asm_sub64(as, ir); break;
1770 case IR_NEG: as->curins--; asm_neg64(as, ir); break;
1771 case IR_CALLN:
1772 case IR_CALLXS:
1773 if (!uselo)
1774 ra_allocref(as, ir->op1, RID2RSET(RID_RETLO)); /* Mark lo op as used. */
1775 break;
1776 case IR_CNEWI:
1777 /* Nothing to do here. Handled by lo op itself. */
1778 break;
1779 default: lua_assert(0); break;
1780 }
1781 #else
1782 UNUSED(as); UNUSED(ir); lua_assert(0); /* Unused without FFI. */
1783 #endif
1784 }
1785
1786 /* -- Stack handling ------------------------------------------------------ */
1787
1788 /* Check Lua stack size for overflow. Use exit handler as fallback. */
asm_stack_check(ASMState * as,BCReg topslot,IRIns * irp,RegSet allow,ExitNo exitno)1789 static void asm_stack_check(ASMState *as, BCReg topslot,
1790 IRIns *irp, RegSet allow, ExitNo exitno)
1791 {
1792 /* Try to get an unused temp. register, otherwise spill/restore RID_RET*. */
1793 Reg tmp, pbase = irp ? (ra_hasreg(irp->r) ? irp->r : RID_TMP) : RID_BASE;
1794 rset_clear(allow, pbase);
1795 tmp = allow ? rset_pickbot(allow) :
1796 (pbase == RID_RETHI ? RID_RETLO : RID_RETHI);
1797 emit_condbranch(as, PPCI_BC, CC_LT, asm_exitstub_addr(as, exitno));
1798 if (allow == RSET_EMPTY) /* Restore temp. register. */
1799 emit_tai(as, PPCI_LWZ, tmp, RID_SP, SPOFS_TMPW);
1800 else
1801 ra_modified(as, tmp);
1802 emit_ai(as, PPCI_CMPLWI, RID_TMP, (int32_t)(8*topslot));
1803 emit_tab(as, PPCI_SUBF, RID_TMP, pbase, tmp);
1804 emit_tai(as, PPCI_LWZ, tmp, tmp, offsetof(lua_State, maxstack));
1805 if (pbase == RID_TMP)
1806 emit_getgl(as, RID_TMP, jit_base);
1807 emit_getgl(as, tmp, jit_L);
1808 if (allow == RSET_EMPTY) /* Spill temp. register. */
1809 emit_tai(as, PPCI_STW, tmp, RID_SP, SPOFS_TMPW);
1810 }
1811
1812 /* Restore Lua stack from on-trace state. */
asm_stack_restore(ASMState * as,SnapShot * snap)1813 static void asm_stack_restore(ASMState *as, SnapShot *snap)
1814 {
1815 SnapEntry *map = &as->T->snapmap[snap->mapofs];
1816 SnapEntry *flinks = &as->T->snapmap[snap_nextofs(as->T, snap)-1];
1817 MSize n, nent = snap->nent;
1818 /* Store the value of all modified slots to the Lua stack. */
1819 for (n = 0; n < nent; n++) {
1820 SnapEntry sn = map[n];
1821 BCReg s = snap_slot(sn);
1822 int32_t ofs = 8*((int32_t)s-1);
1823 IRRef ref = snap_ref(sn);
1824 IRIns *ir = IR(ref);
1825 if ((sn & SNAP_NORESTORE))
1826 continue;
1827 if (irt_isnum(ir->t)) {
1828 Reg src = ra_alloc1(as, ref, RSET_FPR);
1829 emit_fai(as, PPCI_STFD, src, RID_BASE, ofs);
1830 } else {
1831 Reg type;
1832 RegSet allow = rset_exclude(RSET_GPR, RID_BASE);
1833 lua_assert(irt_ispri(ir->t) || irt_isaddr(ir->t) || irt_isinteger(ir->t));
1834 if (!irt_ispri(ir->t)) {
1835 Reg src = ra_alloc1(as, ref, allow);
1836 rset_clear(allow, src);
1837 emit_tai(as, PPCI_STW, src, RID_BASE, ofs+4);
1838 }
1839 if ((sn & (SNAP_CONT|SNAP_FRAME))) {
1840 if (s == 0) continue; /* Do not overwrite link to previous frame. */
1841 type = ra_allock(as, (int32_t)(*flinks--), allow);
1842 } else {
1843 type = ra_allock(as, (int32_t)irt_toitype(ir->t), allow);
1844 }
1845 emit_tai(as, PPCI_STW, type, RID_BASE, ofs);
1846 }
1847 checkmclim(as);
1848 }
1849 lua_assert(map + nent == flinks);
1850 }
1851
1852 /* -- GC handling --------------------------------------------------------- */
1853
1854 /* Check GC threshold and do one or more GC steps. */
asm_gc_check(ASMState * as)1855 static void asm_gc_check(ASMState *as)
1856 {
1857 const CCallInfo *ci = &lj_ir_callinfo[IRCALL_lj_gc_step_jit];
1858 IRRef args[2];
1859 MCLabel l_end;
1860 Reg tmp;
1861 ra_evictset(as, RSET_SCRATCH);
1862 l_end = emit_label(as);
1863 /* Exit trace if in GCSatomic or GCSfinalize. Avoids syncing GC objects. */
1864 asm_guardcc(as, CC_NE); /* Assumes asm_snap_prep() already done. */
1865 emit_ai(as, PPCI_CMPWI, RID_RET, 0);
1866 args[0] = ASMREF_TMP1; /* global_State *g */
1867 args[1] = ASMREF_TMP2; /* MSize steps */
1868 asm_gencall(as, ci, args);
1869 emit_tai(as, PPCI_ADDI, ra_releasetmp(as, ASMREF_TMP1), RID_JGL, -32768);
1870 tmp = ra_releasetmp(as, ASMREF_TMP2);
1871 emit_loadi(as, tmp, as->gcsteps);
1872 /* Jump around GC step if GC total < GC threshold. */
1873 emit_condbranch(as, PPCI_BC|PPCF_Y, CC_LT, l_end);
1874 emit_ab(as, PPCI_CMPLW, RID_TMP, tmp);
1875 emit_getgl(as, tmp, gc.threshold);
1876 emit_getgl(as, RID_TMP, gc.total);
1877 as->gcsteps = 0;
1878 checkmclim(as);
1879 }
1880
1881 /* -- Loop handling ------------------------------------------------------- */
1882
1883 /* Fixup the loop branch. */
asm_loop_fixup(ASMState * as)1884 static void asm_loop_fixup(ASMState *as)
1885 {
1886 MCode *p = as->mctop;
1887 MCode *target = as->mcp;
1888 if (as->loopinv) { /* Inverted loop branch? */
1889 /* asm_guardcc already inverted the cond branch and patched the final b. */
1890 p[-2] = (p[-2] & (0xffff0000u & ~PPCF_Y)) | (((target-p+2) & 0x3fffu) << 2);
1891 } else {
1892 p[-1] = PPCI_B|(((target-p+1)&0x00ffffffu)<<2);
1893 }
1894 }
1895
1896 /* -- Head of trace ------------------------------------------------------- */
1897
1898 /* Coalesce BASE register for a root trace. */
asm_head_root_base(ASMState * as)1899 static void asm_head_root_base(ASMState *as)
1900 {
1901 IRIns *ir = IR(REF_BASE);
1902 Reg r = ir->r;
1903 if (ra_hasreg(r)) {
1904 ra_free(as, r);
1905 if (rset_test(as->modset, r) || irt_ismarked(ir->t))
1906 ir->r = RID_INIT; /* No inheritance for modified BASE register. */
1907 if (r != RID_BASE)
1908 emit_mr(as, r, RID_BASE);
1909 }
1910 }
1911
1912 /* Coalesce BASE register for a side trace. */
asm_head_side_base(ASMState * as,IRIns * irp,RegSet allow)1913 static RegSet asm_head_side_base(ASMState *as, IRIns *irp, RegSet allow)
1914 {
1915 IRIns *ir = IR(REF_BASE);
1916 Reg r = ir->r;
1917 if (ra_hasreg(r)) {
1918 ra_free(as, r);
1919 if (rset_test(as->modset, r) || irt_ismarked(ir->t))
1920 ir->r = RID_INIT; /* No inheritance for modified BASE register. */
1921 if (irp->r == r) {
1922 rset_clear(allow, r); /* Mark same BASE register as coalesced. */
1923 } else if (ra_hasreg(irp->r) && rset_test(as->freeset, irp->r)) {
1924 rset_clear(allow, irp->r);
1925 emit_mr(as, r, irp->r); /* Move from coalesced parent reg. */
1926 } else {
1927 emit_getgl(as, r, jit_base); /* Otherwise reload BASE. */
1928 }
1929 }
1930 return allow;
1931 }
1932
1933 /* -- Tail of trace ------------------------------------------------------- */
1934
1935 /* Fixup the tail code. */
asm_tail_fixup(ASMState * as,TraceNo lnk)1936 static void asm_tail_fixup(ASMState *as, TraceNo lnk)
1937 {
1938 MCode *p = as->mctop;
1939 MCode *target;
1940 int32_t spadj = as->T->spadjust;
1941 if (spadj == 0) {
1942 *--p = PPCI_NOP;
1943 *--p = PPCI_NOP;
1944 as->mctop = p;
1945 } else {
1946 /* Patch stack adjustment. */
1947 lua_assert(checki16(CFRAME_SIZE+spadj));
1948 p[-3] = PPCI_ADDI | PPCF_T(RID_TMP) | PPCF_A(RID_SP) | (CFRAME_SIZE+spadj);
1949 p[-2] = PPCI_STWU | PPCF_T(RID_TMP) | PPCF_A(RID_SP) | spadj;
1950 }
1951 /* Patch exit branch. */
1952 target = lnk ? traceref(as->J, lnk)->mcode : (MCode *)lj_vm_exit_interp;
1953 p[-1] = PPCI_B|(((target-p+1)&0x00ffffffu)<<2);
1954 }
1955
1956 /* Prepare tail of code. */
asm_tail_prep(ASMState * as)1957 static void asm_tail_prep(ASMState *as)
1958 {
1959 MCode *p = as->mctop - 1; /* Leave room for exit branch. */
1960 if (as->loopref) {
1961 as->invmcp = as->mcp = p;
1962 } else {
1963 as->mcp = p-2; /* Leave room for stack pointer adjustment. */
1964 as->invmcp = NULL;
1965 }
1966 }
1967
1968 /* -- Instruction dispatch ------------------------------------------------ */
1969
1970 /* Assemble a single instruction. */
asm_ir(ASMState * as,IRIns * ir)1971 static void asm_ir(ASMState *as, IRIns *ir)
1972 {
1973 switch ((IROp)ir->o) {
1974 /* Miscellaneous ops. */
1975 case IR_LOOP: asm_loop(as); break;
1976 case IR_NOP: case IR_XBAR: lua_assert(!ra_used(ir)); break;
1977 case IR_USE:
1978 ra_alloc1(as, ir->op1, irt_isfp(ir->t) ? RSET_FPR : RSET_GPR); break;
1979 case IR_PHI: asm_phi(as, ir); break;
1980 case IR_HIOP: asm_hiop(as, ir); break;
1981 case IR_GCSTEP: asm_gcstep(as, ir); break;
1982
1983 /* Guarded assertions. */
1984 case IR_EQ: case IR_NE:
1985 if ((ir-1)->o == IR_HREF && ir->op1 == as->curins-1) {
1986 as->curins--;
1987 asm_href(as, ir-1, (IROp)ir->o);
1988 break;
1989 }
1990 /* fallthrough */
1991 case IR_LT: case IR_GE: case IR_LE: case IR_GT:
1992 case IR_ULT: case IR_UGE: case IR_ULE: case IR_UGT:
1993 case IR_ABC:
1994 asm_comp(as, ir);
1995 break;
1996
1997 case IR_RETF: asm_retf(as, ir); break;
1998
1999 /* Bit ops. */
2000 case IR_BNOT: asm_bitnot(as, ir); break;
2001 case IR_BSWAP: asm_bitswap(as, ir); break;
2002
2003 case IR_BAND: asm_bitand(as, ir); break;
2004 case IR_BOR: asm_bitop(as, ir, PPCI_OR, PPCI_ORI); break;
2005 case IR_BXOR: asm_bitop(as, ir, PPCI_XOR, PPCI_XORI); break;
2006
2007 case IR_BSHL: asm_bitshift(as, ir, PPCI_SLW, 0); break;
2008 case IR_BSHR: asm_bitshift(as, ir, PPCI_SRW, 1); break;
2009 case IR_BSAR: asm_bitshift(as, ir, PPCI_SRAW, PPCI_SRAWI); break;
2010 case IR_BROL: asm_bitshift(as, ir, PPCI_RLWNM|PPCF_MB(0)|PPCF_ME(31),
2011 PPCI_RLWINM|PPCF_MB(0)|PPCF_ME(31)); break;
2012 case IR_BROR: lua_assert(0); break;
2013
2014 /* Arithmetic ops. */
2015 case IR_ADD: asm_add(as, ir); break;
2016 case IR_SUB: asm_sub(as, ir); break;
2017 case IR_MUL: asm_mul(as, ir); break;
2018 case IR_DIV: asm_fparith(as, ir, PPCI_FDIV); break;
2019 case IR_MOD: asm_callid(as, ir, IRCALL_lj_vm_modi); break;
2020 case IR_POW: asm_callid(as, ir, IRCALL_lj_vm_powi); break;
2021 case IR_NEG: asm_neg(as, ir); break;
2022
2023 case IR_ABS: asm_fpunary(as, ir, PPCI_FABS); break;
2024 case IR_ATAN2: asm_callid(as, ir, IRCALL_atan2); break;
2025 case IR_LDEXP: asm_callid(as, ir, IRCALL_ldexp); break;
2026 case IR_MIN: asm_min_max(as, ir, 0); break;
2027 case IR_MAX: asm_min_max(as, ir, 1); break;
2028 case IR_FPMATH:
2029 if (ir->op2 == IRFPM_EXP2 && asm_fpjoin_pow(as, ir))
2030 break;
2031 if (ir->op2 == IRFPM_SQRT && (as->flags & JIT_F_SQRT))
2032 asm_fpunary(as, ir, PPCI_FSQRT);
2033 else
2034 asm_callid(as, ir, IRCALL_lj_vm_floor + ir->op2);
2035 break;
2036
2037 /* Overflow-checking arithmetic ops. */
2038 case IR_ADDOV: asm_arithov(as, ir, PPCI_ADDO); break;
2039 case IR_SUBOV: asm_arithov(as, ir, PPCI_SUBFO); break;
2040 case IR_MULOV: asm_arithov(as, ir, PPCI_MULLWO); break;
2041
2042 /* Memory references. */
2043 case IR_AREF: asm_aref(as, ir); break;
2044 case IR_HREF: asm_href(as, ir, 0); break;
2045 case IR_HREFK: asm_hrefk(as, ir); break;
2046 case IR_NEWREF: asm_newref(as, ir); break;
2047 case IR_UREFO: case IR_UREFC: asm_uref(as, ir); break;
2048 case IR_FREF: asm_fref(as, ir); break;
2049 case IR_STRREF: asm_strref(as, ir); break;
2050
2051 /* Loads and stores. */
2052 case IR_ALOAD: case IR_HLOAD: case IR_ULOAD: case IR_VLOAD:
2053 asm_ahuvload(as, ir);
2054 break;
2055 case IR_FLOAD: asm_fload(as, ir); break;
2056 case IR_XLOAD: asm_xload(as, ir); break;
2057 case IR_SLOAD: asm_sload(as, ir); break;
2058
2059 case IR_ASTORE: case IR_HSTORE: case IR_USTORE: asm_ahustore(as, ir); break;
2060 case IR_FSTORE: asm_fstore(as, ir); break;
2061 case IR_XSTORE: asm_xstore(as, ir, 0); break;
2062
2063 /* Allocations. */
2064 case IR_SNEW: case IR_XSNEW: asm_snew(as, ir); break;
2065 case IR_TNEW: asm_tnew(as, ir); break;
2066 case IR_TDUP: asm_tdup(as, ir); break;
2067 case IR_CNEW: case IR_CNEWI: asm_cnew(as, ir); break;
2068
2069 /* Write barriers. */
2070 case IR_TBAR: asm_tbar(as, ir); break;
2071 case IR_OBAR: asm_obar(as, ir); break;
2072
2073 /* Type conversions. */
2074 case IR_CONV: asm_conv(as, ir); break;
2075 case IR_TOBIT: asm_tobit(as, ir); break;
2076 case IR_TOSTR: asm_tostr(as, ir); break;
2077 case IR_STRTO: asm_strto(as, ir); break;
2078
2079 /* Calls. */
2080 case IR_CALLN: case IR_CALLL: case IR_CALLS: asm_call(as, ir); break;
2081 case IR_CALLXS: asm_callx(as, ir); break;
2082 case IR_CARG: break;
2083
2084 default:
2085 setintV(&as->J->errinfo, ir->o);
2086 lj_trace_err_info(as->J, LJ_TRERR_NYIIR);
2087 break;
2088 }
2089 }
2090
2091 /* -- Trace setup --------------------------------------------------------- */
2092
2093 /* Ensure there are enough stack slots for call arguments. */
asm_setup_call_slots(ASMState * as,IRIns * ir,const CCallInfo * ci)2094 static Reg asm_setup_call_slots(ASMState *as, IRIns *ir, const CCallInfo *ci)
2095 {
2096 IRRef args[CCI_NARGS_MAX*2];
2097 uint32_t i, nargs = (int)CCI_NARGS(ci);
2098 int nslots = 2, ngpr = REGARG_NUMGPR, nfpr = REGARG_NUMFPR;
2099 asm_collectargs(as, ir, ci, args);
2100 for (i = 0; i < nargs; i++)
2101 if (args[i] && irt_isfp(IR(args[i])->t)) {
2102 if (nfpr > 0) nfpr--; else nslots = (nslots+3) & ~1;
2103 } else {
2104 if (ngpr > 0) ngpr--; else nslots++;
2105 }
2106 if (nslots > as->evenspill) /* Leave room for args in stack slots. */
2107 as->evenspill = nslots;
2108 return irt_isfp(ir->t) ? REGSP_HINT(RID_FPRET) : REGSP_HINT(RID_RET);
2109 }
2110
asm_setup_target(ASMState * as)2111 static void asm_setup_target(ASMState *as)
2112 {
2113 asm_exitstub_setup(as, as->T->nsnap + (as->parent ? 1 : 0));
2114 }
2115
2116 /* -- Trace patching ------------------------------------------------------ */
2117
2118 /* Patch exit jumps of existing machine code to a new target. */
lj_asm_patchexit(jit_State * J,GCtrace * T,ExitNo exitno,MCode * target)2119 void lj_asm_patchexit(jit_State *J, GCtrace *T, ExitNo exitno, MCode *target)
2120 {
2121 MCode *p = T->mcode;
2122 MCode *pe = (MCode *)((char *)p + T->szmcode);
2123 MCode *px = exitstub_trace_addr(T, exitno);
2124 MCode *cstart = NULL;
2125 MCode *mcarea = lj_mcode_patch(J, p, 0);
2126 int clearso = 0;
2127 for (; p < pe; p++) {
2128 /* Look for exitstub branch, try to replace with branch to target. */
2129 uint32_t ins = *p;
2130 if ((ins & 0xfc000000u) == 0x40000000u &&
2131 ((ins ^ ((char *)px-(char *)p)) & 0xffffu) == 0) {
2132 ptrdiff_t delta = (char *)target - (char *)p;
2133 if (((ins >> 16) & 3) == (CC_SO&3)) {
2134 clearso = sizeof(MCode);
2135 delta -= sizeof(MCode);
2136 }
2137 /* Many, but not all short-range branches can be patched directly. */
2138 if (((delta + 0x8000) >> 16) == 0) {
2139 *p = (ins & 0xffdf0000u) | ((uint32_t)delta & 0xffffu) |
2140 ((delta & 0x8000) * (PPCF_Y/0x8000));
2141 if (!cstart) cstart = p;
2142 }
2143 } else if ((ins & 0xfc000000u) == PPCI_B &&
2144 ((ins ^ ((char *)px-(char *)p)) & 0x03ffffffu) == 0) {
2145 ptrdiff_t delta = (char *)target - (char *)p;
2146 lua_assert(((delta + 0x02000000) >> 26) == 0);
2147 *p = PPCI_B | ((uint32_t)delta & 0x03ffffffu);
2148 if (!cstart) cstart = p;
2149 }
2150 }
2151 { /* Always patch long-range branch in exit stub itself. */
2152 ptrdiff_t delta = (char *)target - (char *)px - clearso;
2153 lua_assert(((delta + 0x02000000) >> 26) == 0);
2154 *px = PPCI_B | ((uint32_t)delta & 0x03ffffffu);
2155 }
2156 if (!cstart) cstart = px;
2157 lj_mcode_sync(cstart, px+1);
2158 if (clearso) { /* Extend the current trace. Ugly workaround. */
2159 MCode *pp = J->cur.mcode;
2160 J->cur.szmcode += sizeof(MCode);
2161 *--pp = PPCI_MCRXR; /* Clear SO flag. */
2162 J->cur.mcode = pp;
2163 lj_mcode_sync(pp, pp+1);
2164 }
2165 lj_mcode_patch(J, mcarea, 1);
2166 }
2167
2168