1 //===-- llvm/Target/TargetInstrDesc.h - Instruction Descriptors -*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the TargetOperandInfo and TargetInstrDesc classes, which 11 // are used to describe target instructions and their operands. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef LLVM_TARGET_TARGETINSTRDESC_H 16 #define LLVM_TARGET_TARGETINSTRDESC_H 17 18 #include "llvm/System/DataTypes.h" 19 20 namespace llvm { 21 22 class TargetRegisterClass; 23 class TargetRegisterInfo; 24 25 //===----------------------------------------------------------------------===// 26 // Machine Operand Flags and Description 27 //===----------------------------------------------------------------------===// 28 29 namespace TOI { 30 // Operand constraints 31 enum OperandConstraint { 32 TIED_TO = 0, // Must be allocated the same register as. 33 EARLY_CLOBBER // Operand is an early clobber register operand 34 }; 35 36 /// OperandFlags - These are flags set on operands, but should be considered 37 /// private, all access should go through the TargetOperandInfo accessors. 38 /// See the accessors for a description of what these are. 39 enum OperandFlags { 40 LookupPtrRegClass = 0, 41 Predicate, 42 OptionalDef 43 }; 44 } 45 46 /// TargetOperandInfo - This holds information about one operand of a machine 47 /// instruction, indicating the register class for register operands, etc. 48 /// 49 class TargetOperandInfo { 50 public: 51 /// RegClass - This specifies the register class enumeration of the operand 52 /// if the operand is a register. If isLookupPtrRegClass is set, then this is 53 /// an index that is passed to TargetRegisterInfo::getPointerRegClass(x) to 54 /// get a dynamic register class. 55 /// 56 /// NOTE: This member should be considered to be private, all access should go 57 /// through "getRegClass(TRI)" below. 58 short RegClass; 59 60 /// Flags - These are flags from the TOI::OperandFlags enum. 61 unsigned short Flags; 62 63 /// Lower 16 bits are used to specify which constraints are set. The higher 16 64 /// bits are used to specify the value of constraints (4 bits each). 65 unsigned Constraints; 66 /// Currently no other information. 67 68 /// getRegClass - Get the register class for the operand, handling resolution 69 /// of "symbolic" pointer register classes etc. If this is not a register 70 /// operand, this returns null. 71 const TargetRegisterClass *getRegClass(const TargetRegisterInfo *TRI) const; 72 73 74 /// isLookupPtrRegClass - Set if this operand is a pointer value and it 75 /// requires a callback to look up its register class. isLookupPtrRegClass()76 bool isLookupPtrRegClass() const { return Flags&(1 <<TOI::LookupPtrRegClass);} 77 78 /// isPredicate - Set if this is one of the operands that made up of 79 /// the predicate operand that controls an isPredicable() instruction. isPredicate()80 bool isPredicate() const { return Flags & (1 << TOI::Predicate); } 81 82 /// isOptionalDef - Set if this operand is a optional def. 83 /// isOptionalDef()84 bool isOptionalDef() const { return Flags & (1 << TOI::OptionalDef); } 85 }; 86 87 88 //===----------------------------------------------------------------------===// 89 // Machine Instruction Flags and Description 90 //===----------------------------------------------------------------------===// 91 92 /// TargetInstrDesc flags - These should be considered private to the 93 /// implementation of the TargetInstrDesc class. Clients should use the 94 /// predicate methods on TargetInstrDesc, not use these directly. These 95 /// all correspond to bitfields in the TargetInstrDesc::Flags field. 96 namespace TID { 97 enum { 98 Variadic = 0, 99 HasOptionalDef, 100 Return, 101 Call, 102 Barrier, 103 Terminator, 104 Branch, 105 IndirectBranch, 106 Predicable, 107 NotDuplicable, 108 Compare, 109 DelaySlot, 110 FoldableAsLoad, 111 MayLoad, 112 MayStore, 113 UnmodeledSideEffects, 114 Commutable, 115 ConvertibleTo3Addr, 116 UsesCustomInserter, 117 Rematerializable, 118 CheapAsAMove, 119 ExtraSrcRegAllocReq, 120 ExtraDefRegAllocReq 121 }; 122 } 123 124 /// TargetInstrDesc - Describe properties that are true of each 125 /// instruction in the target description file. This captures information about 126 /// side effects, register use and many other things. There is one instance of 127 /// this struct for each target instruction class, and the MachineInstr class 128 /// points to this struct directly to describe itself. 129 class TargetInstrDesc { 130 public: 131 unsigned short Opcode; // The opcode number 132 unsigned short NumOperands; // Num of args (may be more if variable_ops) 133 unsigned short NumDefs; // Num of args that are definitions 134 unsigned short SchedClass; // enum identifying instr sched class 135 const char * Name; // Name of the instruction record in td file 136 unsigned Flags; // Flags identifying machine instr class 137 uint64_t TSFlags; // Target Specific Flag values 138 const unsigned *ImplicitUses; // Registers implicitly read by this instr 139 const unsigned *ImplicitDefs; // Registers implicitly defined by this instr 140 const TargetRegisterClass **RCBarriers; // Reg classes completely "clobbered" 141 const TargetOperandInfo *OpInfo; // 'NumOperands' entries about operands 142 143 /// getOperandConstraint - Returns the value of the specific constraint if 144 /// it is set. Returns -1 if it is not set. getOperandConstraint(unsigned OpNum,TOI::OperandConstraint Constraint)145 int getOperandConstraint(unsigned OpNum, 146 TOI::OperandConstraint Constraint) const { 147 if (OpNum < NumOperands && 148 (OpInfo[OpNum].Constraints & (1 << Constraint))) { 149 unsigned Pos = 16 + Constraint * 4; 150 return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf; 151 } 152 return -1; 153 } 154 155 /// getRegClass - Returns the register class constraint for OpNum, or NULL. getRegClass(unsigned OpNum,const TargetRegisterInfo * TRI)156 const TargetRegisterClass *getRegClass(unsigned OpNum, 157 const TargetRegisterInfo *TRI) const { 158 return OpNum < NumOperands ? OpInfo[OpNum].getRegClass(TRI) : 0; 159 } 160 161 /// getOpcode - Return the opcode number for this descriptor. getOpcode()162 unsigned getOpcode() const { 163 return Opcode; 164 } 165 166 /// getName - Return the name of the record in the .td file for this 167 /// instruction, for example "ADD8ri". getName()168 const char *getName() const { 169 return Name; 170 } 171 172 /// getNumOperands - Return the number of declared MachineOperands for this 173 /// MachineInstruction. Note that variadic (isVariadic() returns true) 174 /// instructions may have additional operands at the end of the list, and note 175 /// that the machine instruction may include implicit register def/uses as 176 /// well. getNumOperands()177 unsigned getNumOperands() const { 178 return NumOperands; 179 } 180 181 /// getNumDefs - Return the number of MachineOperands that are register 182 /// definitions. Register definitions always occur at the start of the 183 /// machine operand list. This is the number of "outs" in the .td file, 184 /// and does not include implicit defs. getNumDefs()185 unsigned getNumDefs() const { 186 return NumDefs; 187 } 188 189 /// isVariadic - Return true if this instruction can have a variable number of 190 /// operands. In this case, the variable operands will be after the normal 191 /// operands but before the implicit definitions and uses (if any are 192 /// present). isVariadic()193 bool isVariadic() const { 194 return Flags & (1 << TID::Variadic); 195 } 196 197 /// hasOptionalDef - Set if this instruction has an optional definition, e.g. 198 /// ARM instructions which can set condition code if 's' bit is set. hasOptionalDef()199 bool hasOptionalDef() const { 200 return Flags & (1 << TID::HasOptionalDef); 201 } 202 203 /// getImplicitUses - Return a list of registers that are potentially 204 /// read by any instance of this machine instruction. For example, on X86, 205 /// the "adc" instruction adds two register operands and adds the carry bit in 206 /// from the flags register. In this case, the instruction is marked as 207 /// implicitly reading the flags. Likewise, the variable shift instruction on 208 /// X86 is marked as implicitly reading the 'CL' register, which it always 209 /// does. 210 /// 211 /// This method returns null if the instruction has no implicit uses. getImplicitUses()212 const unsigned *getImplicitUses() const { 213 return ImplicitUses; 214 } 215 216 /// getNumImplicitUses - Return the number of implicit uses this instruction 217 /// has. getNumImplicitUses()218 unsigned getNumImplicitUses() const { 219 if (ImplicitUses == 0) return 0; 220 unsigned i = 0; 221 for (; ImplicitUses[i]; ++i) /*empty*/; 222 return i; 223 } 224 225 226 /// getImplicitDefs - Return a list of registers that are potentially 227 /// written by any instance of this machine instruction. For example, on X86, 228 /// many instructions implicitly set the flags register. In this case, they 229 /// are marked as setting the FLAGS. Likewise, many instructions always 230 /// deposit their result in a physical register. For example, the X86 divide 231 /// instruction always deposits the quotient and remainder in the EAX/EDX 232 /// registers. For that instruction, this will return a list containing the 233 /// EAX/EDX/EFLAGS registers. 234 /// 235 /// This method returns null if the instruction has no implicit defs. getImplicitDefs()236 const unsigned *getImplicitDefs() const { 237 return ImplicitDefs; 238 } 239 240 /// getNumImplicitDefs - Return the number of implicit defs this instruction 241 /// has. getNumImplicitDefs()242 unsigned getNumImplicitDefs() const { 243 if (ImplicitDefs == 0) return 0; 244 unsigned i = 0; 245 for (; ImplicitDefs[i]; ++i) /*empty*/; 246 return i; 247 } 248 249 /// hasImplicitUseOfPhysReg - Return true if this instruction implicitly 250 /// uses the specified physical register. hasImplicitUseOfPhysReg(unsigned Reg)251 bool hasImplicitUseOfPhysReg(unsigned Reg) const { 252 if (const unsigned *ImpUses = ImplicitUses) 253 for (; *ImpUses; ++ImpUses) 254 if (*ImpUses == Reg) return true; 255 return false; 256 } 257 258 /// hasImplicitDefOfPhysReg - Return true if this instruction implicitly 259 /// defines the specified physical register. hasImplicitDefOfPhysReg(unsigned Reg)260 bool hasImplicitDefOfPhysReg(unsigned Reg) const { 261 if (const unsigned *ImpDefs = ImplicitDefs) 262 for (; *ImpDefs; ++ImpDefs) 263 if (*ImpDefs == Reg) return true; 264 return false; 265 } 266 267 /// getRegClassBarriers - Return a list of register classes that are 268 /// completely clobbered by this machine instruction. For example, on X86 269 /// the call instructions will completely clobber all the registers in the 270 /// fp stack and XMM classes. 271 /// 272 /// This method returns null if the instruction doesn't completely clobber 273 /// any register class. getRegClassBarriers()274 const TargetRegisterClass **getRegClassBarriers() const { 275 return RCBarriers; 276 } 277 278 /// getSchedClass - Return the scheduling class for this instruction. The 279 /// scheduling class is an index into the InstrItineraryData table. This 280 /// returns zero if there is no known scheduling information for the 281 /// instruction. 282 /// getSchedClass()283 unsigned getSchedClass() const { 284 return SchedClass; 285 } 286 isReturn()287 bool isReturn() const { 288 return Flags & (1 << TID::Return); 289 } 290 isCall()291 bool isCall() const { 292 return Flags & (1 << TID::Call); 293 } 294 295 /// isBarrier - Returns true if the specified instruction stops control flow 296 /// from executing the instruction immediately following it. Examples include 297 /// unconditional branches and return instructions. isBarrier()298 bool isBarrier() const { 299 return Flags & (1 << TID::Barrier); 300 } 301 302 /// isTerminator - Returns true if this instruction part of the terminator for 303 /// a basic block. Typically this is things like return and branch 304 /// instructions. 305 /// 306 /// Various passes use this to insert code into the bottom of a basic block, 307 /// but before control flow occurs. isTerminator()308 bool isTerminator() const { 309 return Flags & (1 << TID::Terminator); 310 } 311 312 /// isBranch - Returns true if this is a conditional, unconditional, or 313 /// indirect branch. Predicates below can be used to discriminate between 314 /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to 315 /// get more information. isBranch()316 bool isBranch() const { 317 return Flags & (1 << TID::Branch); 318 } 319 320 /// isIndirectBranch - Return true if this is an indirect branch, such as a 321 /// branch through a register. isIndirectBranch()322 bool isIndirectBranch() const { 323 return Flags & (1 << TID::IndirectBranch); 324 } 325 326 /// isConditionalBranch - Return true if this is a branch which may fall 327 /// through to the next instruction or may transfer control flow to some other 328 /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more 329 /// information about this branch. isConditionalBranch()330 bool isConditionalBranch() const { 331 return isBranch() & !isBarrier() & !isIndirectBranch(); 332 } 333 334 /// isUnconditionalBranch - Return true if this is a branch which always 335 /// transfers control flow to some other block. The 336 /// TargetInstrInfo::AnalyzeBranch method can be used to get more information 337 /// about this branch. isUnconditionalBranch()338 bool isUnconditionalBranch() const { 339 return isBranch() & isBarrier() & !isIndirectBranch(); 340 } 341 342 // isPredicable - Return true if this instruction has a predicate operand that 343 // controls execution. It may be set to 'always', or may be set to other 344 /// values. There are various methods in TargetInstrInfo that can be used to 345 /// control and modify the predicate in this instruction. isPredicable()346 bool isPredicable() const { 347 return Flags & (1 << TID::Predicable); 348 } 349 350 /// isCompare - Return true if this instruction is a comparison. isCompare()351 bool isCompare() const { 352 return Flags & (1 << TID::Compare); 353 } 354 355 /// isNotDuplicable - Return true if this instruction cannot be safely 356 /// duplicated. For example, if the instruction has a unique labels attached 357 /// to it, duplicating it would cause multiple definition errors. isNotDuplicable()358 bool isNotDuplicable() const { 359 return Flags & (1 << TID::NotDuplicable); 360 } 361 362 /// hasDelaySlot - Returns true if the specified instruction has a delay slot 363 /// which must be filled by the code generator. hasDelaySlot()364 bool hasDelaySlot() const { 365 return Flags & (1 << TID::DelaySlot); 366 } 367 368 /// canFoldAsLoad - Return true for instructions that can be folded as 369 /// memory operands in other instructions. The most common use for this 370 /// is instructions that are simple loads from memory that don't modify 371 /// the loaded value in any way, but it can also be used for instructions 372 /// that can be expressed as constant-pool loads, such as V_SETALLONES 373 /// on x86, to allow them to be folded when it is beneficial. 374 /// This should only be set on instructions that return a value in their 375 /// only virtual register definition. canFoldAsLoad()376 bool canFoldAsLoad() const { 377 return Flags & (1 << TID::FoldableAsLoad); 378 } 379 380 //===--------------------------------------------------------------------===// 381 // Side Effect Analysis 382 //===--------------------------------------------------------------------===// 383 384 /// mayLoad - Return true if this instruction could possibly read memory. 385 /// Instructions with this flag set are not necessarily simple load 386 /// instructions, they may load a value and modify it, for example. mayLoad()387 bool mayLoad() const { 388 return Flags & (1 << TID::MayLoad); 389 } 390 391 392 /// mayStore - Return true if this instruction could possibly modify memory. 393 /// Instructions with this flag set are not necessarily simple store 394 /// instructions, they may store a modified value based on their operands, or 395 /// may not actually modify anything, for example. mayStore()396 bool mayStore() const { 397 return Flags & (1 << TID::MayStore); 398 } 399 400 /// hasUnmodeledSideEffects - Return true if this instruction has side 401 /// effects that are not modeled by other flags. This does not return true 402 /// for instructions whose effects are captured by: 403 /// 404 /// 1. Their operand list and implicit definition/use list. Register use/def 405 /// info is explicit for instructions. 406 /// 2. Memory accesses. Use mayLoad/mayStore. 407 /// 3. Calling, branching, returning: use isCall/isReturn/isBranch. 408 /// 409 /// Examples of side effects would be modifying 'invisible' machine state like 410 /// a control register, flushing a cache, modifying a register invisible to 411 /// LLVM, etc. 412 /// hasUnmodeledSideEffects()413 bool hasUnmodeledSideEffects() const { 414 return Flags & (1 << TID::UnmodeledSideEffects); 415 } 416 417 //===--------------------------------------------------------------------===// 418 // Flags that indicate whether an instruction can be modified by a method. 419 //===--------------------------------------------------------------------===// 420 421 /// isCommutable - Return true if this may be a 2- or 3-address 422 /// instruction (of the form "X = op Y, Z, ..."), which produces the same 423 /// result if Y and Z are exchanged. If this flag is set, then the 424 /// TargetInstrInfo::commuteInstruction method may be used to hack on the 425 /// instruction. 426 /// 427 /// Note that this flag may be set on instructions that are only commutable 428 /// sometimes. In these cases, the call to commuteInstruction will fail. 429 /// Also note that some instructions require non-trivial modification to 430 /// commute them. isCommutable()431 bool isCommutable() const { 432 return Flags & (1 << TID::Commutable); 433 } 434 435 /// isConvertibleTo3Addr - Return true if this is a 2-address instruction 436 /// which can be changed into a 3-address instruction if needed. Doing this 437 /// transformation can be profitable in the register allocator, because it 438 /// means that the instruction can use a 2-address form if possible, but 439 /// degrade into a less efficient form if the source and dest register cannot 440 /// be assigned to the same register. For example, this allows the x86 441 /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which 442 /// is the same speed as the shift but has bigger code size. 443 /// 444 /// If this returns true, then the target must implement the 445 /// TargetInstrInfo::convertToThreeAddress method for this instruction, which 446 /// is allowed to fail if the transformation isn't valid for this specific 447 /// instruction (e.g. shl reg, 4 on x86). 448 /// isConvertibleTo3Addr()449 bool isConvertibleTo3Addr() const { 450 return Flags & (1 << TID::ConvertibleTo3Addr); 451 } 452 453 /// usesCustomInsertionHook - Return true if this instruction requires 454 /// custom insertion support when the DAG scheduler is inserting it into a 455 /// machine basic block. If this is true for the instruction, it basically 456 /// means that it is a pseudo instruction used at SelectionDAG time that is 457 /// expanded out into magic code by the target when MachineInstrs are formed. 458 /// 459 /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method 460 /// is used to insert this into the MachineBasicBlock. usesCustomInsertionHook()461 bool usesCustomInsertionHook() const { 462 return Flags & (1 << TID::UsesCustomInserter); 463 } 464 465 /// isRematerializable - Returns true if this instruction is a candidate for 466 /// remat. This flag is deprecated, please don't use it anymore. If this 467 /// flag is set, the isReallyTriviallyReMaterializable() method is called to 468 /// verify the instruction is really rematable. isRematerializable()469 bool isRematerializable() const { 470 return Flags & (1 << TID::Rematerializable); 471 } 472 473 /// isAsCheapAsAMove - Returns true if this instruction has the same cost (or 474 /// less) than a move instruction. This is useful during certain types of 475 /// optimizations (e.g., remat during two-address conversion or machine licm) 476 /// where we would like to remat or hoist the instruction, but not if it costs 477 /// more than moving the instruction into the appropriate register. Note, we 478 /// are not marking copies from and to the same register class with this flag. isAsCheapAsAMove()479 bool isAsCheapAsAMove() const { 480 return Flags & (1 << TID::CheapAsAMove); 481 } 482 483 /// hasExtraSrcRegAllocReq - Returns true if this instruction source operands 484 /// have special register allocation requirements that are not captured by the 485 /// operand register classes. e.g. ARM::STRD's two source registers must be an 486 /// even / odd pair, ARM::STM registers have to be in ascending order. 487 /// Post-register allocation passes should not attempt to change allocations 488 /// for sources of instructions with this flag. hasExtraSrcRegAllocReq()489 bool hasExtraSrcRegAllocReq() const { 490 return Flags & (1 << TID::ExtraSrcRegAllocReq); 491 } 492 493 /// hasExtraDefRegAllocReq - Returns true if this instruction def operands 494 /// have special register allocation requirements that are not captured by the 495 /// operand register classes. e.g. ARM::LDRD's two def registers must be an 496 /// even / odd pair, ARM::LDM registers have to be in ascending order. 497 /// Post-register allocation passes should not attempt to change allocations 498 /// for definitions of instructions with this flag. hasExtraDefRegAllocReq()499 bool hasExtraDefRegAllocReq() const { 500 return Flags & (1 << TID::ExtraDefRegAllocReq); 501 } 502 }; 503 504 } // end namespace llvm 505 506 #endif 507