1 //===-- PPCISelDAGToDAG.cpp - PPC --pattern matching inst selector --------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines a pattern matching instruction selector for PowerPC,
11 // converting from a legalized dag to a PPC dag.
12 //
13 //===----------------------------------------------------------------------===//
14
15 #define DEBUG_TYPE "ppc-codegen"
16 #include "PPC.h"
17 #include "PPCPredicates.h"
18 #include "PPCTargetMachine.h"
19 #include "PPCHazardRecognizers.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/SelectionDAG.h"
25 #include "llvm/CodeGen/SelectionDAGISel.h"
26 #include "llvm/Target/TargetOptions.h"
27 #include "llvm/Constants.h"
28 #include "llvm/Function.h"
29 #include "llvm/GlobalValue.h"
30 #include "llvm/Intrinsics.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/MathExtras.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
35 using namespace llvm;
36
37 namespace {
38 //===--------------------------------------------------------------------===//
39 /// PPCDAGToDAGISel - PPC specific code to select PPC machine
40 /// instructions for SelectionDAG operations.
41 ///
42 class PPCDAGToDAGISel : public SelectionDAGISel {
43 const PPCTargetMachine &TM;
44 const PPCTargetLowering &PPCLowering;
45 const PPCSubtarget &PPCSubTarget;
46 unsigned GlobalBaseReg;
47 public:
PPCDAGToDAGISel(PPCTargetMachine & tm)48 explicit PPCDAGToDAGISel(PPCTargetMachine &tm)
49 : SelectionDAGISel(tm), TM(tm),
50 PPCLowering(*TM.getTargetLowering()),
51 PPCSubTarget(*TM.getSubtargetImpl()) {}
52
runOnMachineFunction(MachineFunction & MF)53 virtual bool runOnMachineFunction(MachineFunction &MF) {
54 // Make sure we re-emit a set of the global base reg if necessary
55 GlobalBaseReg = 0;
56 SelectionDAGISel::runOnMachineFunction(MF);
57
58 InsertVRSaveCode(MF);
59 return true;
60 }
61
62 /// getI32Imm - Return a target constant with the specified value, of type
63 /// i32.
getI32Imm(unsigned Imm)64 inline SDValue getI32Imm(unsigned Imm) {
65 return CurDAG->getTargetConstant(Imm, MVT::i32);
66 }
67
68 /// getI64Imm - Return a target constant with the specified value, of type
69 /// i64.
getI64Imm(uint64_t Imm)70 inline SDValue getI64Imm(uint64_t Imm) {
71 return CurDAG->getTargetConstant(Imm, MVT::i64);
72 }
73
74 /// getSmallIPtrImm - Return a target constant of pointer type.
getSmallIPtrImm(unsigned Imm)75 inline SDValue getSmallIPtrImm(unsigned Imm) {
76 return CurDAG->getTargetConstant(Imm, PPCLowering.getPointerTy());
77 }
78
79 /// isRunOfOnes - Returns true iff Val consists of one contiguous run of 1s
80 /// with any number of 0s on either side. The 1s are allowed to wrap from
81 /// LSB to MSB, so 0x000FFF0, 0x0000FFFF, and 0xFF0000FF are all runs.
82 /// 0x0F0F0000 is not, since all 1s are not contiguous.
83 static bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME);
84
85
86 /// isRotateAndMask - Returns true if Mask and Shift can be folded into a
87 /// rotate and mask opcode and mask operation.
88 static bool isRotateAndMask(SDNode *N, unsigned Mask, bool isShiftMask,
89 unsigned &SH, unsigned &MB, unsigned &ME);
90
91 /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
92 /// base register. Return the virtual register that holds this value.
93 SDNode *getGlobalBaseReg();
94
95 // Select - Convert the specified operand from a target-independent to a
96 // target-specific node if it hasn't already been changed.
97 SDNode *Select(SDNode *N);
98
99 SDNode *SelectBitfieldInsert(SDNode *N);
100
101 /// SelectCC - Select a comparison of the specified values with the
102 /// specified condition code, returning the CR# of the expression.
103 SDValue SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC, DebugLoc dl);
104
105 /// SelectAddrImm - Returns true if the address N can be represented by
106 /// a base register plus a signed 16-bit displacement [r+imm].
SelectAddrImm(SDNode * Op,SDValue N,SDValue & Disp,SDValue & Base)107 bool SelectAddrImm(SDNode *Op, SDValue N, SDValue &Disp,
108 SDValue &Base) {
109 return PPCLowering.SelectAddressRegImm(N, Disp, Base, *CurDAG);
110 }
111
112 /// SelectAddrImmOffs - Return true if the operand is valid for a preinc
113 /// immediate field. Because preinc imms have already been validated, just
114 /// accept it.
SelectAddrImmOffs(SDNode * Op,SDValue N,SDValue & Out) const115 bool SelectAddrImmOffs(SDNode *Op, SDValue N, SDValue &Out) const {
116 Out = N;
117 return true;
118 }
119
120 /// SelectAddrIdx - Given the specified addressed, check to see if it can be
121 /// represented as an indexed [r+r] operation. Returns false if it can
122 /// be represented by [r+imm], which are preferred.
SelectAddrIdx(SDNode * Op,SDValue N,SDValue & Base,SDValue & Index)123 bool SelectAddrIdx(SDNode *Op, SDValue N, SDValue &Base,
124 SDValue &Index) {
125 return PPCLowering.SelectAddressRegReg(N, Base, Index, *CurDAG);
126 }
127
128 /// SelectAddrIdxOnly - Given the specified addressed, force it to be
129 /// represented as an indexed [r+r] operation.
SelectAddrIdxOnly(SDNode * Op,SDValue N,SDValue & Base,SDValue & Index)130 bool SelectAddrIdxOnly(SDNode *Op, SDValue N, SDValue &Base,
131 SDValue &Index) {
132 return PPCLowering.SelectAddressRegRegOnly(N, Base, Index, *CurDAG);
133 }
134
135 /// SelectAddrImmShift - Returns true if the address N can be represented by
136 /// a base register plus a signed 14-bit displacement [r+imm*4]. Suitable
137 /// for use by STD and friends.
SelectAddrImmShift(SDNode * Op,SDValue N,SDValue & Disp,SDValue & Base)138 bool SelectAddrImmShift(SDNode *Op, SDValue N, SDValue &Disp,
139 SDValue &Base) {
140 return PPCLowering.SelectAddressRegImmShift(N, Disp, Base, *CurDAG);
141 }
142
143 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
144 /// inline asm expressions. It is always correct to compute the value into
145 /// a register. The case of adding a (possibly relocatable) constant to a
146 /// register can be improved, but it is wrong to substitute Reg+Reg for
147 /// Reg in an asm, because the load or store opcode would have to change.
SelectInlineAsmMemoryOperand(const SDValue & Op,char ConstraintCode,std::vector<SDValue> & OutOps)148 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
149 char ConstraintCode,
150 std::vector<SDValue> &OutOps) {
151 OutOps.push_back(Op);
152 return false;
153 }
154
155 SDValue BuildSDIVSequence(SDNode *N);
156 SDValue BuildUDIVSequence(SDNode *N);
157
158 void InsertVRSaveCode(MachineFunction &MF);
159
getPassName() const160 virtual const char *getPassName() const {
161 return "PowerPC DAG->DAG Pattern Instruction Selection";
162 }
163
164 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
165 /// this target when scheduling the DAG.
CreateTargetHazardRecognizer()166 virtual ScheduleHazardRecognizer *CreateTargetHazardRecognizer() {
167 // Should use subtarget info to pick the right hazard recognizer. For
168 // now, always return a PPC970 recognizer.
169 const TargetInstrInfo *II = TM.getInstrInfo();
170 assert(II && "No InstrInfo?");
171 return new PPCHazardRecognizer970(*II);
172 }
173
174 // Include the pieces autogenerated from the target description.
175 #include "PPCGenDAGISel.inc"
176
177 private:
178 SDNode *SelectSETCC(SDNode *N);
179 };
180 }
181
182 /// InsertVRSaveCode - Once the entire function has been instruction selected,
183 /// all virtual registers are created and all machine instructions are built,
184 /// check to see if we need to save/restore VRSAVE. If so, do it.
InsertVRSaveCode(MachineFunction & Fn)185 void PPCDAGToDAGISel::InsertVRSaveCode(MachineFunction &Fn) {
186 // Check to see if this function uses vector registers, which means we have to
187 // save and restore the VRSAVE register and update it with the regs we use.
188 //
189 // In this case, there will be virtual registers of vector type created
190 // by the scheduler. Detect them now.
191 bool HasVectorVReg = false;
192 for (unsigned i = TargetRegisterInfo::FirstVirtualRegister,
193 e = RegInfo->getLastVirtReg()+1; i != e; ++i)
194 if (RegInfo->getRegClass(i) == &PPC::VRRCRegClass) {
195 HasVectorVReg = true;
196 break;
197 }
198 if (!HasVectorVReg) return; // nothing to do.
199
200 // If we have a vector register, we want to emit code into the entry and exit
201 // blocks to save and restore the VRSAVE register. We do this here (instead
202 // of marking all vector instructions as clobbering VRSAVE) for two reasons:
203 //
204 // 1. This (trivially) reduces the load on the register allocator, by not
205 // having to represent the live range of the VRSAVE register.
206 // 2. This (more significantly) allows us to create a temporary virtual
207 // register to hold the saved VRSAVE value, allowing this temporary to be
208 // register allocated, instead of forcing it to be spilled to the stack.
209
210 // Create two vregs - one to hold the VRSAVE register that is live-in to the
211 // function and one for the value after having bits or'd into it.
212 unsigned InVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
213 unsigned UpdatedVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
214
215 const TargetInstrInfo &TII = *TM.getInstrInfo();
216 MachineBasicBlock &EntryBB = *Fn.begin();
217 DebugLoc dl;
218 // Emit the following code into the entry block:
219 // InVRSAVE = MFVRSAVE
220 // UpdatedVRSAVE = UPDATE_VRSAVE InVRSAVE
221 // MTVRSAVE UpdatedVRSAVE
222 MachineBasicBlock::iterator IP = EntryBB.begin(); // Insert Point
223 BuildMI(EntryBB, IP, dl, TII.get(PPC::MFVRSAVE), InVRSAVE);
224 BuildMI(EntryBB, IP, dl, TII.get(PPC::UPDATE_VRSAVE),
225 UpdatedVRSAVE).addReg(InVRSAVE);
226 BuildMI(EntryBB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(UpdatedVRSAVE);
227
228 // Find all return blocks, outputting a restore in each epilog.
229 for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
230 if (!BB->empty() && BB->back().getDesc().isReturn()) {
231 IP = BB->end(); --IP;
232
233 // Skip over all terminator instructions, which are part of the return
234 // sequence.
235 MachineBasicBlock::iterator I2 = IP;
236 while (I2 != BB->begin() && (--I2)->getDesc().isTerminator())
237 IP = I2;
238
239 // Emit: MTVRSAVE InVRSave
240 BuildMI(*BB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(InVRSAVE);
241 }
242 }
243 }
244
245
246 /// getGlobalBaseReg - Output the instructions required to put the
247 /// base address to use for accessing globals into a register.
248 ///
getGlobalBaseReg()249 SDNode *PPCDAGToDAGISel::getGlobalBaseReg() {
250 if (!GlobalBaseReg) {
251 const TargetInstrInfo &TII = *TM.getInstrInfo();
252 // Insert the set of GlobalBaseReg into the first MBB of the function
253 MachineBasicBlock &FirstMBB = MF->front();
254 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
255 DebugLoc dl;
256
257 if (PPCLowering.getPointerTy() == MVT::i32) {
258 GlobalBaseReg = RegInfo->createVirtualRegister(PPC::GPRCRegisterClass);
259 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR), PPC::LR);
260 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg);
261 } else {
262 GlobalBaseReg = RegInfo->createVirtualRegister(PPC::G8RCRegisterClass);
263 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR8), PPC::LR8);
264 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR8), GlobalBaseReg);
265 }
266 }
267 return CurDAG->getRegister(GlobalBaseReg,
268 PPCLowering.getPointerTy()).getNode();
269 }
270
271 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
272 /// or 64-bit immediate, and if the value can be accurately represented as a
273 /// sign extension from a 16-bit value. If so, this returns true and the
274 /// immediate.
isIntS16Immediate(SDNode * N,short & Imm)275 static bool isIntS16Immediate(SDNode *N, short &Imm) {
276 if (N->getOpcode() != ISD::Constant)
277 return false;
278
279 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
280 if (N->getValueType(0) == MVT::i32)
281 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
282 else
283 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
284 }
285
isIntS16Immediate(SDValue Op,short & Imm)286 static bool isIntS16Immediate(SDValue Op, short &Imm) {
287 return isIntS16Immediate(Op.getNode(), Imm);
288 }
289
290
291 /// isInt32Immediate - This method tests to see if the node is a 32-bit constant
292 /// operand. If so Imm will receive the 32-bit value.
isInt32Immediate(SDNode * N,unsigned & Imm)293 static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
294 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
295 Imm = cast<ConstantSDNode>(N)->getZExtValue();
296 return true;
297 }
298 return false;
299 }
300
301 /// isInt64Immediate - This method tests to see if the node is a 64-bit constant
302 /// operand. If so Imm will receive the 64-bit value.
isInt64Immediate(SDNode * N,uint64_t & Imm)303 static bool isInt64Immediate(SDNode *N, uint64_t &Imm) {
304 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i64) {
305 Imm = cast<ConstantSDNode>(N)->getZExtValue();
306 return true;
307 }
308 return false;
309 }
310
311 // isInt32Immediate - This method tests to see if a constant operand.
312 // If so Imm will receive the 32 bit value.
isInt32Immediate(SDValue N,unsigned & Imm)313 static bool isInt32Immediate(SDValue N, unsigned &Imm) {
314 return isInt32Immediate(N.getNode(), Imm);
315 }
316
317
318 // isOpcWithIntImmediate - This method tests to see if the node is a specific
319 // opcode and that it has a immediate integer right operand.
320 // If so Imm will receive the 32 bit value.
isOpcWithIntImmediate(SDNode * N,unsigned Opc,unsigned & Imm)321 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
322 return N->getOpcode() == Opc
323 && isInt32Immediate(N->getOperand(1).getNode(), Imm);
324 }
325
isRunOfOnes(unsigned Val,unsigned & MB,unsigned & ME)326 bool PPCDAGToDAGISel::isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) {
327 if (isShiftedMask_32(Val)) {
328 // look for the first non-zero bit
329 MB = CountLeadingZeros_32(Val);
330 // look for the first zero bit after the run of ones
331 ME = CountLeadingZeros_32((Val - 1) ^ Val);
332 return true;
333 } else {
334 Val = ~Val; // invert mask
335 if (isShiftedMask_32(Val)) {
336 // effectively look for the first zero bit
337 ME = CountLeadingZeros_32(Val) - 1;
338 // effectively look for the first one bit after the run of zeros
339 MB = CountLeadingZeros_32((Val - 1) ^ Val) + 1;
340 return true;
341 }
342 }
343 // no run present
344 return false;
345 }
346
isRotateAndMask(SDNode * N,unsigned Mask,bool isShiftMask,unsigned & SH,unsigned & MB,unsigned & ME)347 bool PPCDAGToDAGISel::isRotateAndMask(SDNode *N, unsigned Mask,
348 bool isShiftMask, unsigned &SH,
349 unsigned &MB, unsigned &ME) {
350 // Don't even go down this path for i64, since different logic will be
351 // necessary for rldicl/rldicr/rldimi.
352 if (N->getValueType(0) != MVT::i32)
353 return false;
354
355 unsigned Shift = 32;
356 unsigned Indeterminant = ~0; // bit mask marking indeterminant results
357 unsigned Opcode = N->getOpcode();
358 if (N->getNumOperands() != 2 ||
359 !isInt32Immediate(N->getOperand(1).getNode(), Shift) || (Shift > 31))
360 return false;
361
362 if (Opcode == ISD::SHL) {
363 // apply shift left to mask if it comes first
364 if (isShiftMask) Mask = Mask << Shift;
365 // determine which bits are made indeterminant by shift
366 Indeterminant = ~(0xFFFFFFFFu << Shift);
367 } else if (Opcode == ISD::SRL) {
368 // apply shift right to mask if it comes first
369 if (isShiftMask) Mask = Mask >> Shift;
370 // determine which bits are made indeterminant by shift
371 Indeterminant = ~(0xFFFFFFFFu >> Shift);
372 // adjust for the left rotate
373 Shift = 32 - Shift;
374 } else if (Opcode == ISD::ROTL) {
375 Indeterminant = 0;
376 } else {
377 return false;
378 }
379
380 // if the mask doesn't intersect any Indeterminant bits
381 if (Mask && !(Mask & Indeterminant)) {
382 SH = Shift & 31;
383 // make sure the mask is still a mask (wrap arounds may not be)
384 return isRunOfOnes(Mask, MB, ME);
385 }
386 return false;
387 }
388
389 /// SelectBitfieldInsert - turn an or of two masked values into
390 /// the rotate left word immediate then mask insert (rlwimi) instruction.
SelectBitfieldInsert(SDNode * N)391 SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) {
392 SDValue Op0 = N->getOperand(0);
393 SDValue Op1 = N->getOperand(1);
394 DebugLoc dl = N->getDebugLoc();
395
396 APInt LKZ, LKO, RKZ, RKO;
397 CurDAG->ComputeMaskedBits(Op0, APInt::getAllOnesValue(32), LKZ, LKO);
398 CurDAG->ComputeMaskedBits(Op1, APInt::getAllOnesValue(32), RKZ, RKO);
399
400 unsigned TargetMask = LKZ.getZExtValue();
401 unsigned InsertMask = RKZ.getZExtValue();
402
403 if ((TargetMask | InsertMask) == 0xFFFFFFFF) {
404 unsigned Op0Opc = Op0.getOpcode();
405 unsigned Op1Opc = Op1.getOpcode();
406 unsigned Value, SH = 0;
407 TargetMask = ~TargetMask;
408 InsertMask = ~InsertMask;
409
410 // If the LHS has a foldable shift and the RHS does not, then swap it to the
411 // RHS so that we can fold the shift into the insert.
412 if (Op0Opc == ISD::AND && Op1Opc == ISD::AND) {
413 if (Op0.getOperand(0).getOpcode() == ISD::SHL ||
414 Op0.getOperand(0).getOpcode() == ISD::SRL) {
415 if (Op1.getOperand(0).getOpcode() != ISD::SHL &&
416 Op1.getOperand(0).getOpcode() != ISD::SRL) {
417 std::swap(Op0, Op1);
418 std::swap(Op0Opc, Op1Opc);
419 std::swap(TargetMask, InsertMask);
420 }
421 }
422 } else if (Op0Opc == ISD::SHL || Op0Opc == ISD::SRL) {
423 if (Op1Opc == ISD::AND && Op1.getOperand(0).getOpcode() != ISD::SHL &&
424 Op1.getOperand(0).getOpcode() != ISD::SRL) {
425 std::swap(Op0, Op1);
426 std::swap(Op0Opc, Op1Opc);
427 std::swap(TargetMask, InsertMask);
428 }
429 }
430
431 unsigned MB, ME;
432 if (InsertMask && isRunOfOnes(InsertMask, MB, ME)) {
433 SDValue Tmp1, Tmp2;
434
435 if ((Op1Opc == ISD::SHL || Op1Opc == ISD::SRL) &&
436 isInt32Immediate(Op1.getOperand(1), Value)) {
437 Op1 = Op1.getOperand(0);
438 SH = (Op1Opc == ISD::SHL) ? Value : 32 - Value;
439 }
440 if (Op1Opc == ISD::AND) {
441 unsigned SHOpc = Op1.getOperand(0).getOpcode();
442 if ((SHOpc == ISD::SHL || SHOpc == ISD::SRL) &&
443 isInt32Immediate(Op1.getOperand(0).getOperand(1), Value)) {
444 Op1 = Op1.getOperand(0).getOperand(0);
445 SH = (SHOpc == ISD::SHL) ? Value : 32 - Value;
446 } else {
447 Op1 = Op1.getOperand(0);
448 }
449 }
450
451 SH &= 31;
452 SDValue Ops[] = { Op0, Op1, getI32Imm(SH), getI32Imm(MB),
453 getI32Imm(ME) };
454 return CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops, 5);
455 }
456 }
457 return 0;
458 }
459
460 /// SelectCC - Select a comparison of the specified values with the specified
461 /// condition code, returning the CR# of the expression.
SelectCC(SDValue LHS,SDValue RHS,ISD::CondCode CC,DebugLoc dl)462 SDValue PPCDAGToDAGISel::SelectCC(SDValue LHS, SDValue RHS,
463 ISD::CondCode CC, DebugLoc dl) {
464 // Always select the LHS.
465 unsigned Opc;
466
467 if (LHS.getValueType() == MVT::i32) {
468 unsigned Imm;
469 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
470 if (isInt32Immediate(RHS, Imm)) {
471 // SETEQ/SETNE comparison with 16-bit immediate, fold it.
472 if (isUInt<16>(Imm))
473 return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, LHS,
474 getI32Imm(Imm & 0xFFFF)), 0);
475 // If this is a 16-bit signed immediate, fold it.
476 if (isInt<16>((int)Imm))
477 return SDValue(CurDAG->getMachineNode(PPC::CMPWI, dl, MVT::i32, LHS,
478 getI32Imm(Imm & 0xFFFF)), 0);
479
480 // For non-equality comparisons, the default code would materialize the
481 // constant, then compare against it, like this:
482 // lis r2, 4660
483 // ori r2, r2, 22136
484 // cmpw cr0, r3, r2
485 // Since we are just comparing for equality, we can emit this instead:
486 // xoris r0,r3,0x1234
487 // cmplwi cr0,r0,0x5678
488 // beq cr0,L6
489 SDValue Xor(CurDAG->getMachineNode(PPC::XORIS, dl, MVT::i32, LHS,
490 getI32Imm(Imm >> 16)), 0);
491 return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, Xor,
492 getI32Imm(Imm & 0xFFFF)), 0);
493 }
494 Opc = PPC::CMPLW;
495 } else if (ISD::isUnsignedIntSetCC(CC)) {
496 if (isInt32Immediate(RHS, Imm) && isUInt<16>(Imm))
497 return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, LHS,
498 getI32Imm(Imm & 0xFFFF)), 0);
499 Opc = PPC::CMPLW;
500 } else {
501 short SImm;
502 if (isIntS16Immediate(RHS, SImm))
503 return SDValue(CurDAG->getMachineNode(PPC::CMPWI, dl, MVT::i32, LHS,
504 getI32Imm((int)SImm & 0xFFFF)),
505 0);
506 Opc = PPC::CMPW;
507 }
508 } else if (LHS.getValueType() == MVT::i64) {
509 uint64_t Imm;
510 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
511 if (isInt64Immediate(RHS.getNode(), Imm)) {
512 // SETEQ/SETNE comparison with 16-bit immediate, fold it.
513 if (isUInt<16>(Imm))
514 return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, LHS,
515 getI32Imm(Imm & 0xFFFF)), 0);
516 // If this is a 16-bit signed immediate, fold it.
517 if (isInt<16>(Imm))
518 return SDValue(CurDAG->getMachineNode(PPC::CMPDI, dl, MVT::i64, LHS,
519 getI32Imm(Imm & 0xFFFF)), 0);
520
521 // For non-equality comparisons, the default code would materialize the
522 // constant, then compare against it, like this:
523 // lis r2, 4660
524 // ori r2, r2, 22136
525 // cmpd cr0, r3, r2
526 // Since we are just comparing for equality, we can emit this instead:
527 // xoris r0,r3,0x1234
528 // cmpldi cr0,r0,0x5678
529 // beq cr0,L6
530 if (isUInt<32>(Imm)) {
531 SDValue Xor(CurDAG->getMachineNode(PPC::XORIS8, dl, MVT::i64, LHS,
532 getI64Imm(Imm >> 16)), 0);
533 return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, Xor,
534 getI64Imm(Imm & 0xFFFF)), 0);
535 }
536 }
537 Opc = PPC::CMPLD;
538 } else if (ISD::isUnsignedIntSetCC(CC)) {
539 if (isInt64Immediate(RHS.getNode(), Imm) && isUInt<16>(Imm))
540 return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, LHS,
541 getI64Imm(Imm & 0xFFFF)), 0);
542 Opc = PPC::CMPLD;
543 } else {
544 short SImm;
545 if (isIntS16Immediate(RHS, SImm))
546 return SDValue(CurDAG->getMachineNode(PPC::CMPDI, dl, MVT::i64, LHS,
547 getI64Imm(SImm & 0xFFFF)),
548 0);
549 Opc = PPC::CMPD;
550 }
551 } else if (LHS.getValueType() == MVT::f32) {
552 Opc = PPC::FCMPUS;
553 } else {
554 assert(LHS.getValueType() == MVT::f64 && "Unknown vt!");
555 Opc = PPC::FCMPUD;
556 }
557 return SDValue(CurDAG->getMachineNode(Opc, dl, MVT::i32, LHS, RHS), 0);
558 }
559
getPredicateForSetCC(ISD::CondCode CC)560 static PPC::Predicate getPredicateForSetCC(ISD::CondCode CC) {
561 switch (CC) {
562 case ISD::SETUEQ:
563 case ISD::SETONE:
564 case ISD::SETOLE:
565 case ISD::SETOGE:
566 llvm_unreachable("Should be lowered by legalize!");
567 default: llvm_unreachable("Unknown condition!");
568 case ISD::SETOEQ:
569 case ISD::SETEQ: return PPC::PRED_EQ;
570 case ISD::SETUNE:
571 case ISD::SETNE: return PPC::PRED_NE;
572 case ISD::SETOLT:
573 case ISD::SETLT: return PPC::PRED_LT;
574 case ISD::SETULE:
575 case ISD::SETLE: return PPC::PRED_LE;
576 case ISD::SETOGT:
577 case ISD::SETGT: return PPC::PRED_GT;
578 case ISD::SETUGE:
579 case ISD::SETGE: return PPC::PRED_GE;
580 case ISD::SETO: return PPC::PRED_NU;
581 case ISD::SETUO: return PPC::PRED_UN;
582 // These two are invalid for floating point. Assume we have int.
583 case ISD::SETULT: return PPC::PRED_LT;
584 case ISD::SETUGT: return PPC::PRED_GT;
585 }
586 }
587
588 /// getCRIdxForSetCC - Return the index of the condition register field
589 /// associated with the SetCC condition, and whether or not the field is
590 /// treated as inverted. That is, lt = 0; ge = 0 inverted.
591 ///
592 /// If this returns with Other != -1, then the returned comparison is an or of
593 /// two simpler comparisons. In this case, Invert is guaranteed to be false.
getCRIdxForSetCC(ISD::CondCode CC,bool & Invert,int & Other)594 static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool &Invert, int &Other) {
595 Invert = false;
596 Other = -1;
597 switch (CC) {
598 default: llvm_unreachable("Unknown condition!");
599 case ISD::SETOLT:
600 case ISD::SETLT: return 0; // Bit #0 = SETOLT
601 case ISD::SETOGT:
602 case ISD::SETGT: return 1; // Bit #1 = SETOGT
603 case ISD::SETOEQ:
604 case ISD::SETEQ: return 2; // Bit #2 = SETOEQ
605 case ISD::SETUO: return 3; // Bit #3 = SETUO
606 case ISD::SETUGE:
607 case ISD::SETGE: Invert = true; return 0; // !Bit #0 = SETUGE
608 case ISD::SETULE:
609 case ISD::SETLE: Invert = true; return 1; // !Bit #1 = SETULE
610 case ISD::SETUNE:
611 case ISD::SETNE: Invert = true; return 2; // !Bit #2 = SETUNE
612 case ISD::SETO: Invert = true; return 3; // !Bit #3 = SETO
613 case ISD::SETUEQ:
614 case ISD::SETOGE:
615 case ISD::SETOLE:
616 case ISD::SETONE:
617 llvm_unreachable("Invalid branch code: should be expanded by legalize");
618 // These are invalid for floating point. Assume integer.
619 case ISD::SETULT: return 0;
620 case ISD::SETUGT: return 1;
621 }
622 return 0;
623 }
624
SelectSETCC(SDNode * N)625 SDNode *PPCDAGToDAGISel::SelectSETCC(SDNode *N) {
626 DebugLoc dl = N->getDebugLoc();
627 unsigned Imm;
628 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
629 if (isInt32Immediate(N->getOperand(1), Imm)) {
630 // We can codegen setcc op, imm very efficiently compared to a brcond.
631 // Check for those cases here.
632 // setcc op, 0
633 if (Imm == 0) {
634 SDValue Op = N->getOperand(0);
635 switch (CC) {
636 default: break;
637 case ISD::SETEQ: {
638 Op = SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, Op), 0);
639 SDValue Ops[] = { Op, getI32Imm(27), getI32Imm(5), getI32Imm(31) };
640 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
641 }
642 case ISD::SETNE: {
643 SDValue AD =
644 SDValue(CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Flag,
645 Op, getI32Imm(~0U)), 0);
646 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op,
647 AD.getValue(1));
648 }
649 case ISD::SETLT: {
650 SDValue Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
651 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
652 }
653 case ISD::SETGT: {
654 SDValue T =
655 SDValue(CurDAG->getMachineNode(PPC::NEG, dl, MVT::i32, Op), 0);
656 T = SDValue(CurDAG->getMachineNode(PPC::ANDC, dl, MVT::i32, T, Op), 0);
657 SDValue Ops[] = { T, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
658 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
659 }
660 }
661 } else if (Imm == ~0U) { // setcc op, -1
662 SDValue Op = N->getOperand(0);
663 switch (CC) {
664 default: break;
665 case ISD::SETEQ:
666 Op = SDValue(CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Flag,
667 Op, getI32Imm(1)), 0);
668 return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
669 SDValue(CurDAG->getMachineNode(PPC::LI, dl,
670 MVT::i32,
671 getI32Imm(0)), 0),
672 Op.getValue(1));
673 case ISD::SETNE: {
674 Op = SDValue(CurDAG->getMachineNode(PPC::NOR, dl, MVT::i32, Op, Op), 0);
675 SDNode *AD = CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Flag,
676 Op, getI32Imm(~0U));
677 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, SDValue(AD, 0),
678 Op, SDValue(AD, 1));
679 }
680 case ISD::SETLT: {
681 SDValue AD = SDValue(CurDAG->getMachineNode(PPC::ADDI, dl, MVT::i32, Op,
682 getI32Imm(1)), 0);
683 SDValue AN = SDValue(CurDAG->getMachineNode(PPC::AND, dl, MVT::i32, AD,
684 Op), 0);
685 SDValue Ops[] = { AN, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
686 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
687 }
688 case ISD::SETGT: {
689 SDValue Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
690 Op = SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops, 4),
691 0);
692 return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op,
693 getI32Imm(1));
694 }
695 }
696 }
697 }
698
699 bool Inv;
700 int OtherCondIdx;
701 unsigned Idx = getCRIdxForSetCC(CC, Inv, OtherCondIdx);
702 SDValue CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC, dl);
703 SDValue IntCR;
704
705 // Force the ccreg into CR7.
706 SDValue CR7Reg = CurDAG->getRegister(PPC::CR7, MVT::i32);
707
708 SDValue InFlag(0, 0); // Null incoming flag value.
709 CCReg = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, CR7Reg, CCReg,
710 InFlag).getValue(1);
711
712 if (PPCSubTarget.isGigaProcessor() && OtherCondIdx == -1)
713 IntCR = SDValue(CurDAG->getMachineNode(PPC::MFOCRF, dl, MVT::i32, CR7Reg,
714 CCReg), 0);
715 else
716 IntCR = SDValue(CurDAG->getMachineNode(PPC::MFCRpseud, dl, MVT::i32,
717 CR7Reg, CCReg), 0);
718
719 SDValue Ops[] = { IntCR, getI32Imm((32-(3-Idx)) & 31),
720 getI32Imm(31), getI32Imm(31) };
721 if (OtherCondIdx == -1 && !Inv)
722 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
723
724 // Get the specified bit.
725 SDValue Tmp =
726 SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops, 4), 0);
727 if (Inv) {
728 assert(OtherCondIdx == -1 && "Can't have split plus negation");
729 return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1));
730 }
731
732 // Otherwise, we have to turn an operation like SETONE -> SETOLT | SETOGT.
733 // We already got the bit for the first part of the comparison (e.g. SETULE).
734
735 // Get the other bit of the comparison.
736 Ops[1] = getI32Imm((32-(3-OtherCondIdx)) & 31);
737 SDValue OtherCond =
738 SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops, 4), 0);
739
740 return CurDAG->SelectNodeTo(N, PPC::OR, MVT::i32, Tmp, OtherCond);
741 }
742
743
744 // Select - Convert the specified operand from a target-independent to a
745 // target-specific node if it hasn't already been changed.
Select(SDNode * N)746 SDNode *PPCDAGToDAGISel::Select(SDNode *N) {
747 DebugLoc dl = N->getDebugLoc();
748 if (N->isMachineOpcode())
749 return NULL; // Already selected.
750
751 switch (N->getOpcode()) {
752 default: break;
753
754 case ISD::Constant: {
755 if (N->getValueType(0) == MVT::i64) {
756 // Get 64 bit value.
757 int64_t Imm = cast<ConstantSDNode>(N)->getZExtValue();
758 // Assume no remaining bits.
759 unsigned Remainder = 0;
760 // Assume no shift required.
761 unsigned Shift = 0;
762
763 // If it can't be represented as a 32 bit value.
764 if (!isInt<32>(Imm)) {
765 Shift = CountTrailingZeros_64(Imm);
766 int64_t ImmSh = static_cast<uint64_t>(Imm) >> Shift;
767
768 // If the shifted value fits 32 bits.
769 if (isInt<32>(ImmSh)) {
770 // Go with the shifted value.
771 Imm = ImmSh;
772 } else {
773 // Still stuck with a 64 bit value.
774 Remainder = Imm;
775 Shift = 32;
776 Imm >>= 32;
777 }
778 }
779
780 // Intermediate operand.
781 SDNode *Result;
782
783 // Handle first 32 bits.
784 unsigned Lo = Imm & 0xFFFF;
785 unsigned Hi = (Imm >> 16) & 0xFFFF;
786
787 // Simple value.
788 if (isInt<16>(Imm)) {
789 // Just the Lo bits.
790 Result = CurDAG->getMachineNode(PPC::LI8, dl, MVT::i64, getI32Imm(Lo));
791 } else if (Lo) {
792 // Handle the Hi bits.
793 unsigned OpC = Hi ? PPC::LIS8 : PPC::LI8;
794 Result = CurDAG->getMachineNode(OpC, dl, MVT::i64, getI32Imm(Hi));
795 // And Lo bits.
796 Result = CurDAG->getMachineNode(PPC::ORI8, dl, MVT::i64,
797 SDValue(Result, 0), getI32Imm(Lo));
798 } else {
799 // Just the Hi bits.
800 Result = CurDAG->getMachineNode(PPC::LIS8, dl, MVT::i64, getI32Imm(Hi));
801 }
802
803 // If no shift, we're done.
804 if (!Shift) return Result;
805
806 // Shift for next step if the upper 32-bits were not zero.
807 if (Imm) {
808 Result = CurDAG->getMachineNode(PPC::RLDICR, dl, MVT::i64,
809 SDValue(Result, 0),
810 getI32Imm(Shift),
811 getI32Imm(63 - Shift));
812 }
813
814 // Add in the last bits as required.
815 if ((Hi = (Remainder >> 16) & 0xFFFF)) {
816 Result = CurDAG->getMachineNode(PPC::ORIS8, dl, MVT::i64,
817 SDValue(Result, 0), getI32Imm(Hi));
818 }
819 if ((Lo = Remainder & 0xFFFF)) {
820 Result = CurDAG->getMachineNode(PPC::ORI8, dl, MVT::i64,
821 SDValue(Result, 0), getI32Imm(Lo));
822 }
823
824 return Result;
825 }
826 break;
827 }
828
829 case ISD::SETCC:
830 return SelectSETCC(N);
831 case PPCISD::GlobalBaseReg:
832 return getGlobalBaseReg();
833
834 case ISD::FrameIndex: {
835 int FI = cast<FrameIndexSDNode>(N)->getIndex();
836 SDValue TFI = CurDAG->getTargetFrameIndex(FI, N->getValueType(0));
837 unsigned Opc = N->getValueType(0) == MVT::i32 ? PPC::ADDI : PPC::ADDI8;
838 if (N->hasOneUse())
839 return CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), TFI,
840 getSmallIPtrImm(0));
841 return CurDAG->getMachineNode(Opc, dl, N->getValueType(0), TFI,
842 getSmallIPtrImm(0));
843 }
844
845 case PPCISD::MFCR: {
846 SDValue InFlag = N->getOperand(1);
847 // Use MFOCRF if supported.
848 if (PPCSubTarget.isGigaProcessor())
849 return CurDAG->getMachineNode(PPC::MFOCRF, dl, MVT::i32,
850 N->getOperand(0), InFlag);
851 else
852 return CurDAG->getMachineNode(PPC::MFCRpseud, dl, MVT::i32,
853 N->getOperand(0), InFlag);
854 }
855
856 case ISD::SDIV: {
857 // FIXME: since this depends on the setting of the carry flag from the srawi
858 // we should really be making notes about that for the scheduler.
859 // FIXME: It sure would be nice if we could cheaply recognize the
860 // srl/add/sra pattern the dag combiner will generate for this as
861 // sra/addze rather than having to handle sdiv ourselves. oh well.
862 unsigned Imm;
863 if (isInt32Immediate(N->getOperand(1), Imm)) {
864 SDValue N0 = N->getOperand(0);
865 if ((signed)Imm > 0 && isPowerOf2_32(Imm)) {
866 SDNode *Op =
867 CurDAG->getMachineNode(PPC::SRAWI, dl, MVT::i32, MVT::Flag,
868 N0, getI32Imm(Log2_32(Imm)));
869 return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
870 SDValue(Op, 0), SDValue(Op, 1));
871 } else if ((signed)Imm < 0 && isPowerOf2_32(-Imm)) {
872 SDNode *Op =
873 CurDAG->getMachineNode(PPC::SRAWI, dl, MVT::i32, MVT::Flag,
874 N0, getI32Imm(Log2_32(-Imm)));
875 SDValue PT =
876 SDValue(CurDAG->getMachineNode(PPC::ADDZE, dl, MVT::i32,
877 SDValue(Op, 0), SDValue(Op, 1)),
878 0);
879 return CurDAG->SelectNodeTo(N, PPC::NEG, MVT::i32, PT);
880 }
881 }
882
883 // Other cases are autogenerated.
884 break;
885 }
886
887 case ISD::LOAD: {
888 // Handle preincrement loads.
889 LoadSDNode *LD = cast<LoadSDNode>(N);
890 EVT LoadedVT = LD->getMemoryVT();
891
892 // Normal loads are handled by code generated from the .td file.
893 if (LD->getAddressingMode() != ISD::PRE_INC)
894 break;
895
896 SDValue Offset = LD->getOffset();
897 if (isa<ConstantSDNode>(Offset) ||
898 Offset.getOpcode() == ISD::TargetGlobalAddress) {
899
900 unsigned Opcode;
901 bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD;
902 if (LD->getValueType(0) != MVT::i64) {
903 // Handle PPC32 integer and normal FP loads.
904 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
905 switch (LoadedVT.getSimpleVT().SimpleTy) {
906 default: llvm_unreachable("Invalid PPC load type!");
907 case MVT::f64: Opcode = PPC::LFDU; break;
908 case MVT::f32: Opcode = PPC::LFSU; break;
909 case MVT::i32: Opcode = PPC::LWZU; break;
910 case MVT::i16: Opcode = isSExt ? PPC::LHAU : PPC::LHZU; break;
911 case MVT::i1:
912 case MVT::i8: Opcode = PPC::LBZU; break;
913 }
914 } else {
915 assert(LD->getValueType(0) == MVT::i64 && "Unknown load result type!");
916 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
917 switch (LoadedVT.getSimpleVT().SimpleTy) {
918 default: llvm_unreachable("Invalid PPC load type!");
919 case MVT::i64: Opcode = PPC::LDU; break;
920 case MVT::i32: Opcode = PPC::LWZU8; break;
921 case MVT::i16: Opcode = isSExt ? PPC::LHAU8 : PPC::LHZU8; break;
922 case MVT::i1:
923 case MVT::i8: Opcode = PPC::LBZU8; break;
924 }
925 }
926
927 SDValue Chain = LD->getChain();
928 SDValue Base = LD->getBasePtr();
929 SDValue Ops[] = { Offset, Base, Chain };
930 // FIXME: PPC64
931 return CurDAG->getMachineNode(Opcode, dl, LD->getValueType(0),
932 PPCLowering.getPointerTy(),
933 MVT::Other, Ops, 3);
934 } else {
935 llvm_unreachable("R+R preindex loads not supported yet!");
936 }
937 }
938
939 case ISD::AND: {
940 unsigned Imm, Imm2, SH, MB, ME;
941
942 // If this is an and of a value rotated between 0 and 31 bits and then and'd
943 // with a mask, emit rlwinm
944 if (isInt32Immediate(N->getOperand(1), Imm) &&
945 isRotateAndMask(N->getOperand(0).getNode(), Imm, false, SH, MB, ME)) {
946 SDValue Val = N->getOperand(0).getOperand(0);
947 SDValue Ops[] = { Val, getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
948 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
949 }
950 // If this is just a masked value where the input is not handled above, and
951 // is not a rotate-left (handled by a pattern in the .td file), emit rlwinm
952 if (isInt32Immediate(N->getOperand(1), Imm) &&
953 isRunOfOnes(Imm, MB, ME) &&
954 N->getOperand(0).getOpcode() != ISD::ROTL) {
955 SDValue Val = N->getOperand(0);
956 SDValue Ops[] = { Val, getI32Imm(0), getI32Imm(MB), getI32Imm(ME) };
957 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
958 }
959 // AND X, 0 -> 0, not "rlwinm 32".
960 if (isInt32Immediate(N->getOperand(1), Imm) && (Imm == 0)) {
961 ReplaceUses(SDValue(N, 0), N->getOperand(1));
962 return NULL;
963 }
964 // ISD::OR doesn't get all the bitfield insertion fun.
965 // (and (or x, c1), c2) where isRunOfOnes(~(c1^c2)) is a bitfield insert
966 if (isInt32Immediate(N->getOperand(1), Imm) &&
967 N->getOperand(0).getOpcode() == ISD::OR &&
968 isInt32Immediate(N->getOperand(0).getOperand(1), Imm2)) {
969 unsigned MB, ME;
970 Imm = ~(Imm^Imm2);
971 if (isRunOfOnes(Imm, MB, ME)) {
972 SDValue Ops[] = { N->getOperand(0).getOperand(0),
973 N->getOperand(0).getOperand(1),
974 getI32Imm(0), getI32Imm(MB),getI32Imm(ME) };
975 return CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops, 5);
976 }
977 }
978
979 // Other cases are autogenerated.
980 break;
981 }
982 case ISD::OR:
983 if (N->getValueType(0) == MVT::i32)
984 if (SDNode *I = SelectBitfieldInsert(N))
985 return I;
986
987 // Other cases are autogenerated.
988 break;
989 case ISD::SHL: {
990 unsigned Imm, SH, MB, ME;
991 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, Imm) &&
992 isRotateAndMask(N, Imm, true, SH, MB, ME)) {
993 SDValue Ops[] = { N->getOperand(0).getOperand(0),
994 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
995 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
996 }
997
998 // Other cases are autogenerated.
999 break;
1000 }
1001 case ISD::SRL: {
1002 unsigned Imm, SH, MB, ME;
1003 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, Imm) &&
1004 isRotateAndMask(N, Imm, true, SH, MB, ME)) {
1005 SDValue Ops[] = { N->getOperand(0).getOperand(0),
1006 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
1007 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
1008 }
1009
1010 // Other cases are autogenerated.
1011 break;
1012 }
1013 case ISD::SELECT_CC: {
1014 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
1015
1016 // Handle the setcc cases here. select_cc lhs, 0, 1, 0, cc
1017 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1018 if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N->getOperand(2)))
1019 if (ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N->getOperand(3)))
1020 if (N1C->isNullValue() && N3C->isNullValue() &&
1021 N2C->getZExtValue() == 1ULL && CC == ISD::SETNE &&
1022 // FIXME: Implement this optzn for PPC64.
1023 N->getValueType(0) == MVT::i32) {
1024 SDNode *Tmp =
1025 CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Flag,
1026 N->getOperand(0), getI32Imm(~0U));
1027 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32,
1028 SDValue(Tmp, 0), N->getOperand(0),
1029 SDValue(Tmp, 1));
1030 }
1031
1032 SDValue CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC, dl);
1033 unsigned BROpc = getPredicateForSetCC(CC);
1034
1035 unsigned SelectCCOp;
1036 if (N->getValueType(0) == MVT::i32)
1037 SelectCCOp = PPC::SELECT_CC_I4;
1038 else if (N->getValueType(0) == MVT::i64)
1039 SelectCCOp = PPC::SELECT_CC_I8;
1040 else if (N->getValueType(0) == MVT::f32)
1041 SelectCCOp = PPC::SELECT_CC_F4;
1042 else if (N->getValueType(0) == MVT::f64)
1043 SelectCCOp = PPC::SELECT_CC_F8;
1044 else
1045 SelectCCOp = PPC::SELECT_CC_VRRC;
1046
1047 SDValue Ops[] = { CCReg, N->getOperand(2), N->getOperand(3),
1048 getI32Imm(BROpc) };
1049 return CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), Ops, 4);
1050 }
1051 case PPCISD::COND_BRANCH: {
1052 // Op #0 is the Chain.
1053 // Op #1 is the PPC::PRED_* number.
1054 // Op #2 is the CR#
1055 // Op #3 is the Dest MBB
1056 // Op #4 is the Flag.
1057 // Prevent PPC::PRED_* from being selected into LI.
1058 SDValue Pred =
1059 getI32Imm(cast<ConstantSDNode>(N->getOperand(1))->getZExtValue());
1060 SDValue Ops[] = { Pred, N->getOperand(2), N->getOperand(3),
1061 N->getOperand(0), N->getOperand(4) };
1062 return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops, 5);
1063 }
1064 case ISD::BR_CC: {
1065 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
1066 SDValue CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC, dl);
1067 SDValue Ops[] = { getI32Imm(getPredicateForSetCC(CC)), CondCode,
1068 N->getOperand(4), N->getOperand(0) };
1069 return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops, 4);
1070 }
1071 case ISD::BRIND: {
1072 // FIXME: Should custom lower this.
1073 SDValue Chain = N->getOperand(0);
1074 SDValue Target = N->getOperand(1);
1075 unsigned Opc = Target.getValueType() == MVT::i32 ? PPC::MTCTR : PPC::MTCTR8;
1076 Chain = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Target,
1077 Chain), 0);
1078 return CurDAG->SelectNodeTo(N, PPC::BCTR, MVT::Other, Chain);
1079 }
1080 }
1081
1082 return SelectCode(N);
1083 }
1084
1085
1086
1087 /// createPPCISelDag - This pass converts a legalized DAG into a
1088 /// PowerPC-specific DAG, ready for instruction scheduling.
1089 ///
createPPCISelDag(PPCTargetMachine & TM)1090 FunctionPass *llvm::createPPCISelDag(PPCTargetMachine &TM) {
1091 return new PPCDAGToDAGISel(TM);
1092 }
1093
1094