1`timescale 1ns / 1ps 2/* 3 * This software is Copyright (c) 2016,2019 Denis Burykin 4 * [denis_burykin yahoo com], [denis-burykin2014 yandex ru] 5 * and it is hereby released to the general public under the following terms: 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted. 8 * 9 */ 10 11 12module bcrypt_test(); 13 14 reg READ_ALL_FROM_OUTPUT_FIFO = 0; 15 16 genvar i; 17 integer k, k1, k2; 18 19 20 initial begin 21 // ***************************************************************** 22 // 23 // Send data packets exactly as they arrive from USB controller. 24 // 25 // Output packets appear in output_fifo.fifo_output0.ram 26 // exactly as before they leave FPGA. 27 // On errors it sets pkt_comm_status and app_status available 28 // via low-speed interface. 29 // 30 // It has no internal check for the count of rounds. 31 // 32 // ***************************************************************** 33 #1000; 34 35 // ***************************************************************** 36 // 37 // Test #1. 38 // 39 // {"$2a$00$////////..............XiwFBK8OLIKiLUZR11iwkDeHZvypH9y", 40 // "abcde"}, 41 // 42 // Hash (network byte order, 0 to 23): 43 // 0c 87 4c 66 a3 34 90 cf d3 66 35 24 98 32 79 df 1d 6f 09 58 ca fd 27 2b 44 // 45 // ***************************************************************** 46 47 // Usage: cmp_config_create(cnt,salt_len,"salt"); 48 // Note: in bcrypt, salt is not sent in ASCII but encoded. 49 // 50 bcrypt_cmp_config_create(32,{8'h04, 8'h41, 8'h10, 8'h04, 51 8'h00, 8'h00, 8'h41, 8'h10, {8{8'h00}} }); 52 cmp_config_add_hash(32'h_664c_870c); 53 send_bcrypt_cmp_config(); 54 55 send_empty_word_gen(16'h1234); 56/* 57 word_list_add("keylen7"); 58 word_list_add("mypwd123"); 59 word_list_add("mypwd1234"); 60 word_list_add("mypwd12345"); 61 word_list_add("pass_len_is15.."); 62 63 for (k=0; k < 30; k=k+1) 64 word_list_add("11111110-b"); 65 66 word_list_add("11111111"); 67 word_list_add("11111101"); 68 word_list_add("11111011"); 69*/ 70 word_list_add("abcde"); 71 72 send_word_list(); 73 74 end 75 76 // ***************************************************************** 77 // 78 // Test #2. 79 // 80 // {"$2a$01$////////..............fgo7Kiqupvy1qW.K1sadl0ELN2AVYb.", 81 // "aaa"}, 82 // 83 // ***************************************************************** 84 85 86 // ****************************************************************** 87 // 88 // Simulating input from USB controller over high-speed interface 89 // 90 // ****************************************************************** 91 reg CORE_CLK = 0, IFCLK = 0; 92 93 reg [7:0] din; 94 reg wr_en = 0; 95 96`include "../pkt_comm/pkt_comm_test_helper.vh" 97 98 wire [7:0] app_mode = 0; 99 100 wire [7:0] input_dout; 101 102 fifo_sync_small #( .D_WIDTH(8), .A_WIDTH(15) 103 ) fifo_sync_small_in( 104 .CLK(CORE_CLK), 105 .din(din), .wr_en(wr_en), .full(), 106 .dout(input_dout), .rd_en(hs_input_rd_en), .empty(hs_input_empty) 107 ); 108 109 reg [15:0] hs_input_din; 110 reg [1:0] state = 0; 111 112 always @(posedge CORE_CLK) begin 113 case(state) 114 0: if (~hs_input_empty) begin 115 hs_input_din[7:0] <= input_dout; 116 state <= 1; 117 end 118 1: if (~hs_input_empty) begin 119 hs_input_din[15:8] <= input_dout; 120 state <= 2; 121 end 122 2: if (~hs_input_almost_full) 123 state <= 0; 124 endcase 125 end 126 127 assign hs_input_rd_en = ~hs_input_empty & (state == 0 || state == 1); 128 assign hs_input_wr_en = ~hs_input_almost_full & state == 2; 129 // 130 // End simulation input from USB controller 131 132 133 localparam NUM_PROXIES = 2; 134 135 localparam NUM_WRAPPERS = 1; 136 137 localparam [32*NUM_WRAPPERS-1 :0] WRAPPERS_CONF = { 138 // is_dummy |reserved |start_proxy_num |end_proxy_num 139 1'b0, 15'b0, 8'd2, 8'd3, // wrapper #1: proxies 2-3 140 1'b0, 15'b0, 8'd0, 8'd1 // wrapper #0: proxies 0-1 141 }; 142 143 parameter [32*NUM_PROXIES-1 :0] PROXY_CONF = { 144 // is_dummy |reserved |regs |num_cores 145 1'b0, 19'b0, 4'd2, 8'd1, // proxy #3: 2 regs, 1 cores 146 1'b0, 19'b0, 4'd1, 8'd1, // proxy #2: 1 regs, 1 cores 147 1'b0, 19'b0, 4'd2, 8'd1,//9, // proxy #1 (0_1): 2 regs, 9 cores 148 1'b0, 19'b0, 4'd1, 8'd1//10 // proxy #0 (0_0): 1 regs, 10 cores 149 }; 150 151 152 // ******************************************************** 153 // 154 // bcrypt application 155 // 8-bit input, 16-bit output 156 // 157 // ******************************************************** 158 wire [7:0] app_status, pkt_comm_status; 159 160 (* KEEP="true" *) wire mode_cmp = ~app_mode[6]; 161 162 wire [7:0] core_din; 163 wire [1:0] core_ctrl; 164 wire [NUM_PROXIES-1:0] core_wr_en, core_init_ready, core_crypt_ready; 165 wire [NUM_PROXIES-1:0] core_rd_en, core_empty, core_dout; 166 167 bcrypt #( 168 .NUM_CORES(NUM_PROXIES), 169 .SIMULATION(1) 170 ) pkt_comm( 171 .CORE_CLK(CORE_CLK), 172 // Moved buffers to inside pkt_comm 173 // for better usage of Hierarchial Design Methodology 174 .IFCLK(CORE_CLK),//IFCLK), 175 .hs_input_din( {hs_input_din[7:0],hs_input_din[15:8]} ), 176 .hs_input_wr_en(hs_input_wr_en), 177 .hs_input_almost_full(hs_input_almost_full), 178 .hs_input_prog_full(hs_input_prog_full), 179 180 .output_dout(),//app_dout), 181 .output_rd_en(READ_ALL_FROM_OUTPUT_FIFO),//app_rd_en), 182 .output_empty(),//app_empty), 183 .output_limit(),//output_limit), 184 .output_limit_not_done(),//output_limit_not_done), 185 .output_mode_limit(1'b0),//output_mode_limit), 186 .reg_output_limit(1'b0),//reg_output_limit), 187 188 // Status signals for internal usage (PKT_COMM_CLK) 189 .idle(app_idle), .error_r(error_r), 190 // Application control (via VCR I/O). Set with fpga_set_app_mode() 191 .app_mode(app_mode), 192 // Application status (via VCR I/O). Available at fpga->wr.io_state.app_status 193 .pkt_comm_status(pkt_comm_status), 194 .app_status(app_status), 195 .debug2(), .debug3(), 196 //.debug(), 197 198 // Wrappers and cores are moved to top level module 199 // for better usage of Hierarchial Design Methodology 200 .mode_cmp(mode_cmp), 201 // 10 broadcast signals 202 .core_din(core_din), .core_ctrl(core_ctrl), 203 // 2 x NUM_PROXIES signals to cores, 4 x NUM_PROXIES from cores 204 .core_wr_en(core_wr_en), .core_init_ready(core_init_ready), .core_crypt_ready(core_crypt_ready), 205 .core_rd_en(core_rd_en), .core_empty(core_empty), .core_dout(core_dout) 206 ); 207 208 // 209 // Signals to/from cores, including broadcast signals, 210 // enter distribution network. 211 // 212 generate 213 for (i=0; i < NUM_WRAPPERS; i=i+1) begin:wrappers 214 215 localparam START_PROXY_NUM = WRAPPERS_CONF[32*i+15 -:8]; 216 localparam END_PROXY_NUM = WRAPPERS_CONF[32*i+7 -:8]; 217 localparam IS_DUMMY = WRAPPERS_CONF[32*i+31]; 218 219 bcrypt_wrapper #( 220 .NUM_PROXIES(END_PROXY_NUM - START_PROXY_NUM + 1), 221 .PROXY_CONF(PROXY_CONF [32*END_PROXY_NUM+31 : 32*START_PROXY_NUM]) 222 ) wrapper( 223 .CLK(CORE_CLK), .mode_cmp(mode_cmp), 224 .din(core_din), .ctrl(core_ctrl), 225 .wr_en(core_wr_en [END_PROXY_NUM : START_PROXY_NUM]), 226 .init_ready(core_init_ready [END_PROXY_NUM : START_PROXY_NUM]), 227 .crypt_ready(core_crypt_ready [END_PROXY_NUM : START_PROXY_NUM]), 228 .rd_en(core_rd_en [END_PROXY_NUM : START_PROXY_NUM]), 229 .empty(core_empty [END_PROXY_NUM : START_PROXY_NUM]), 230 .dout(core_dout [END_PROXY_NUM : START_PROXY_NUM]) 231 ); 232 233 end 234 endgenerate 235 236 237 238 239 // This does not reflect actual timing 240 initial begin 241 #5; 242 while (1) begin 243 CORE_CLK <= ~CORE_CLK; #10; 244 end 245 end 246 247 initial begin 248 #35; 249 while (1) begin 250 IFCLK <= ~IFCLK; #70; 251 end 252 end 253 254endmodule 255