1 /**
2 ******************************************************************************
3 * @file stm32l1xx_ll_tim.h
4 * @author MCD Application Team
5 * @version V1.2.0
6 * @date 01-July-2016
7 * @brief Header file of TIM LL module.
8 ******************************************************************************
9 * @attention
10 *
11 * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
12 *
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 ******************************************************************************
36 */
37
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32L1xx_LL_TIM_H
40 #define __STM32L1xx_LL_TIM_H
41
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45
46 /* Includes ------------------------------------------------------------------*/
47 #include "stm32l1xx.h"
48
49 /** @addtogroup STM32L1xx_LL_Driver
50 * @{
51 */
52
53 #if defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM9) || defined (TIM10) || defined (TIM11) || defined (TIM6) || defined (TIM7)
54
55 /** @defgroup TIM_LL TIM
56 * @{
57 */
58
59 /* Private types -------------------------------------------------------------*/
60 /* Private variables ---------------------------------------------------------*/
61 /** @defgroup TIM_LL_Private_Variables TIM Private Variables
62 * @{
63 */
64 static const uint8_t OFFSET_TAB_CCMRx[] =
65 {
66 0x00U, /* 0: TIMx_CH1 */
67 0x00U, /* 1: NA */
68 0x00U, /* 2: TIMx_CH2 */
69 0x00U, /* 3: NA */
70 0x04U, /* 4: TIMx_CH3 */
71 0x00U, /* 5: NA */
72 0x04U /* 6: TIMx_CH4 */
73 };
74
75 static const uint8_t SHIFT_TAB_OCxx[] =
76 {
77 0U, /* 0: OC1M, OC1FE, OC1PE */
78 0U, /* 1: - NA */
79 8U, /* 2: OC2M, OC2FE, OC2PE */
80 0U, /* 3: - NA */
81 0U, /* 4: OC3M, OC3FE, OC3PE */
82 0U, /* 5: - NA */
83 8U /* 6: OC4M, OC4FE, OC4PE */
84 };
85
86 static const uint8_t SHIFT_TAB_ICxx[] =
87 {
88 0U, /* 0: CC1S, IC1PSC, IC1F */
89 0U, /* 1: - NA */
90 8U, /* 2: CC2S, IC2PSC, IC2F */
91 0U, /* 3: - NA */
92 0U, /* 4: CC3S, IC3PSC, IC3F */
93 0U, /* 5: - NA */
94 8U /* 6: CC4S, IC4PSC, IC4F */
95 };
96
97 static const uint8_t SHIFT_TAB_CCxP[] =
98 {
99 0U, /* 0: CC1P */
100 0U, /* 1: NA */
101 4U, /* 2: CC2P */
102 0U, /* 3: NA */
103 8U, /* 4: CC3P */
104 0U, /* 5: NA */
105 12U /* 6: CC4P */
106 };
107
108 /**
109 * @}
110 */
111
112
113 /* Private constants ---------------------------------------------------------*/
114 /** @defgroup TIM_LL_Private_Constants TIM Private Constants
115 * @{
116 */
117
118
119 #define TIMx_OR_RMP_SHIFT ((uint32_t)16U)
120 #define TIMx_OR_RMP_MASK ((uint32_t)0x0000FFFFU)
121 #define TIM_OR_RMP_MASK ((uint32_t)((TIM_OR_TI1RMP | TIM_OR_ETR_RMP | TIM_OR_TI1_RMP_RI) << TIMx_OR_RMP_SHIFT))
122 #define TIM9_OR_RMP_MASK ((uint32_t)((TIM_OR_TI1RMP | TIM9_OR_ITR1_RMP) << TIMx_OR_RMP_SHIFT))
123 #define TIM2_OR_RMP_MASK ((uint32_t)(TIM2_OR_ITR1_RMP << TIMx_OR_RMP_SHIFT))
124 #define TIM3_OR_RMP_MASK ((uint32_t)(TIM3_OR_ITR2_RMP << TIMx_OR_RMP_SHIFT))
125
126
127
128 /**
129 * @}
130 */
131
132
133 /* Private macros ------------------------------------------------------------*/
134 /** @defgroup TIM_LL_Private_Macros TIM Private Macros
135 * @{
136 */
137 /** @brief Convert channel id into channel index.
138 * @param __CHANNEL__ This parameter can be one of the following values:
139 * @arg @ref LL_TIM_CHANNEL_CH1
140 * @arg @ref LL_TIM_CHANNEL_CH2
141 * @arg @ref LL_TIM_CHANNEL_CH3
142 * @arg @ref LL_TIM_CHANNEL_CH4
143 * @retval none
144 */
145 #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
146 (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
147 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
148 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U : 6U)
149
150 /**
151 * @}
152 */
153
154
155 /* Exported types ------------------------------------------------------------*/
156 #if defined(USE_FULL_LL_DRIVER)
157 /** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
158 * @{
159 */
160
161 /**
162 * @brief TIM Time Base configuration structure definition.
163 */
164 typedef struct
165 {
166 uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
167 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
168
169 This feature can be modified afterwards using unitary function @ref LL_TIM_SetPrescaler().*/
170
171 uint32_t CounterMode; /*!< Specifies the counter mode.
172 This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
173
174 This feature can be modified afterwards using unitary function @ref LL_TIM_SetCounterMode().*/
175
176 uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
177 Auto-Reload Register at the next update event.
178 This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
179 Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF.
180
181 This feature can be modified afterwards using unitary function @ref LL_TIM_SetAutoReload().*/
182
183 uint32_t ClockDivision; /*!< Specifies the clock division.
184 This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
185
186 This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/
187 } LL_TIM_InitTypeDef;
188
189 /**
190 * @brief TIM Output Compare configuration structure definition.
191 */
192 typedef struct
193 {
194 uint32_t OCMode; /*!< Specifies the output mode.
195 This parameter can be a value of @ref TIM_LL_EC_OCMODE.
196
197 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetMode().*/
198
199 uint32_t OCState; /*!< Specifies the TIM Output Compare state.
200 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
201
202 This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
203
204 uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
205 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
206
207 This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCHx (x=1..6).*/
208
209 uint32_t OCPolarity; /*!< Specifies the output polarity.
210 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
211
212 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
213
214 } LL_TIM_OC_InitTypeDef;
215
216 /**
217 * @brief TIM Input Capture configuration structure definition.
218 */
219
220 typedef struct
221 {
222
223 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
224 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
225
226 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
227
228 uint32_t ICActiveInput; /*!< Specifies the input.
229 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
230
231 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
232
233 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
234 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
235
236 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
237
238 uint32_t ICFilter; /*!< Specifies the input capture filter.
239 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
240
241 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
242 } LL_TIM_IC_InitTypeDef;
243
244
245 /**
246 * @brief TIM Encoder interface configuration structure definition.
247 */
248 typedef struct
249 {
250 uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
251 This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
252
253 This feature can be modified afterwards using unitary function @ref LL_TIM_SetEncoderMode().*/
254
255 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
256 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
257
258 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
259
260 uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
261 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
262
263 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
264
265 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
266 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
267
268 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
269
270 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
271 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
272
273 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
274
275 uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
276 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
277
278 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
279
280 uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
281 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
282
283 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
284
285 uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
286 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
287
288 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
289
290 uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
291 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
292
293 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
294
295 } LL_TIM_ENCODER_InitTypeDef;
296
297
298 /**
299 * @}
300 */
301 #endif /* USE_FULL_LL_DRIVER */
302
303 /* Exported constants --------------------------------------------------------*/
304 /** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
305 * @{
306 */
307
308 /** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
309 * @brief Flags defines which can be used with LL_TIM_ReadReg function.
310 * @{
311 */
312 #define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */
313 #define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */
314 #define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */
315 #define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */
316 #define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */
317 #define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */
318 #define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */
319 #define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */
320 #define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */
321 #define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */
322 /**
323 * @}
324 */
325
326 /** @defgroup TIM_LL_EC_IT IT Defines
327 * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
328 * @{
329 */
330 #define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */
331 #define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */
332 #define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */
333 #define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */
334 #define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */
335 #define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */
336 /**
337 * @}
338 */
339
340 /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
341 * @{
342 */
343 #define LL_TIM_UPDATESOURCE_REGULAR ((uint32_t)0x00000000U) /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
344 #define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */
345 /**
346 * @}
347 */
348
349 /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
350 * @{
351 */
352 #define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter is not stopped at update event */
353 #define LL_TIM_ONEPULSEMODE_REPETITIVE ((uint32_t)0x00000000U) /*!< Counter stops counting at the next update event */
354 /**
355 * @}
356 */
357
358 /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
359 * @{
360 */
361 #define LL_TIM_COUNTERMODE_UP ((uint32_t)0x00000000U) /*!<Counter used as upcounter */
362 #define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */
363 #define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */
364 #define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_1 /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */
365 #define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */
366 /**
367 * @}
368 */
369
370 /** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
371 * @{
372 */
373 #define LL_TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x00000000U) /*!< tDTS=tCK_INT */
374 #define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */
375 #define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */
376 /**
377 * @}
378 */
379
380 /** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
381 * @{
382 */
383 #define LL_TIM_COUNTERDIRECTION_UP ((uint32_t)0x00000000U) /*!< Timer counter counts up */
384 #define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down */
385 /**
386 * @}
387 */
388
389
390 /** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
391 * @{
392 */
393 #define LL_TIM_CCDMAREQUEST_CC ((uint32_t)0x00000000U) /*!< CCx DMA request sent when CCx event occurs */
394 #define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */
395 /**
396 * @}
397 */
398
399
400 /** @defgroup TIM_LL_EC_CHANNEL Channel
401 * @{
402 */
403 #define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */
404 #define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */
405 #define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */
406 #define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */
407 /**
408 * @}
409 */
410
411 #if defined(USE_FULL_LL_DRIVER)
412 /** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
413 * @{
414 */
415 #define LL_TIM_OCSTATE_DISABLE ((uint32_t)0x00000000U) /*!< OCx is not active */
416 #define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on the corresponding output pin */
417 /**
418 * @}
419 */
420 #endif /* USE_FULL_LL_DRIVER */
421
422 /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
423 * @{
424 */
425 #define LL_TIM_OCMODE_FROZEN ((uint32_t)0x00000000U) /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */
426 #define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!<OCyREF is forced high on compare match*/
427 #define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!<OCyREF is forced low on compare match*/
428 #define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<OCyREF toggles on compare match*/
429 #define LL_TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2) /*!<OCyREF is forced low*/
430 #define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!<OCyREF is forced high*/
431 #define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/
432 #define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/
433 /**
434 * @}
435 */
436
437 /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
438 * @{
439 */
440 #define LL_TIM_OCPOLARITY_HIGH ((uint32_t)0x00000000U) /*!< OCxactive high*/
441 #define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/
442 /**
443 * @}
444 */
445
446
447
448 /** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
449 * @{
450 */
451 #define LL_TIM_ACTIVEINPUT_DIRECTTI (uint32_t)(TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */
452 #define LL_TIM_ACTIVEINPUT_INDIRECTTI (uint32_t)(TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */
453 #define LL_TIM_ACTIVEINPUT_TRC (uint32_t)(TIM_CCMR1_CC1S << 16U) /*!< ICx is mapped on TRC */
454 /**
455 * @}
456 */
457
458 /** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
459 * @{
460 */
461 #define LL_TIM_ICPSC_DIV1 ((uint32_t)0x00000000U) /*!< No prescaler, capture is done each time an edge is detected on the capture input */
462 #define LL_TIM_ICPSC_DIV2 (uint32_t)(TIM_CCMR1_IC1PSC_0 << 16U) /*!< Capture is done once every 2 events */
463 #define LL_TIM_ICPSC_DIV4 (uint32_t)(TIM_CCMR1_IC1PSC_1 << 16U) /*!< Capture is done once every 4 events */
464 #define LL_TIM_ICPSC_DIV8 (uint32_t)(TIM_CCMR1_IC1PSC << 16U) /*!< Capture is done once every 8 events */
465 /**
466 * @}
467 */
468
469 /** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
470 * @{
471 */
472 #define LL_TIM_IC_FILTER_FDIV1 ((uint32_t)0x00000000U) /*!< No filter, sampling is done at fDTS */
473 #define LL_TIM_IC_FILTER_FDIV1_N2 (uint32_t)(TIM_CCMR1_IC1F_0 << 16U) /*!< fSAMPLING=fCK_INT, N=2 */
474 #define LL_TIM_IC_FILTER_FDIV1_N4 (uint32_t)(TIM_CCMR1_IC1F_1 << 16U) /*!< fSAMPLING=fCK_INT, N=4 */
475 #define LL_TIM_IC_FILTER_FDIV1_N8 (uint32_t)((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fCK_INT, N=8 */
476 #define LL_TIM_IC_FILTER_FDIV2_N6 (uint32_t)(TIM_CCMR1_IC1F_2 << 16U) /*!< fSAMPLING=fDTS/2, N=6 */
477 #define LL_TIM_IC_FILTER_FDIV2_N8 (uint32_t)((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/2, N=8 */
478 #define LL_TIM_IC_FILTER_FDIV4_N6 (uint32_t)((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/4, N=6 */
479 #define LL_TIM_IC_FILTER_FDIV4_N8 (uint32_t)((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/4, N=8 */
480 #define LL_TIM_IC_FILTER_FDIV8_N6 (uint32_t)(TIM_CCMR1_IC1F_3 << 16U) /*!< fSAMPLING=fDTS/8, N=6 */
481 #define LL_TIM_IC_FILTER_FDIV8_N8 (uint32_t)((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/8, N=8 */
482 #define LL_TIM_IC_FILTER_FDIV16_N5 (uint32_t)((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/16, N=5 */
483 #define LL_TIM_IC_FILTER_FDIV16_N6 (uint32_t)((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/16, N=6 */
484 #define LL_TIM_IC_FILTER_FDIV16_N8 (uint32_t)((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U) /*!< fSAMPLING=fDTS/16, N=8 */
485 #define LL_TIM_IC_FILTER_FDIV32_N5 (uint32_t)((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/32, N=5 */
486 #define LL_TIM_IC_FILTER_FDIV32_N6 (uint32_t)((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/32, N=6 */
487 #define LL_TIM_IC_FILTER_FDIV32_N8 (uint32_t)(TIM_CCMR1_IC1F << 16U) /*!< fSAMPLING=fDTS/32, N=8 */
488 /**
489 * @}
490 */
491
492 /** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
493 * @{
494 */
495 #define LL_TIM_IC_POLARITY_RISING ((uint32_t)0x00000000U) /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */
496 #define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */
497 #define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */
498 /**
499 * @}
500 */
501
502 /** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
503 * @{
504 */
505 #define LL_TIM_CLOCKSOURCE_INTERNAL ((uint32_t)0x00000000U) /*!< The timer is clocked by the internal clock provided from the RCC */
506 #define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0 ) /*!< Counter counts at each rising or falling edge on a selected inpu t*/
507 #define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
508 /**
509 * @}
510 */
511
512 /** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
513 * @{
514 */
515 #define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /*!< Encoder mode 1 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
516 #define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /*!< Encoder mode 2 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
517 #define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input l */
518 /**
519 * @}
520 */
521
522 /** @defgroup TIM_LL_EC_TRGO Trigger Output
523 * @{
524 */
525 #define LL_TIM_TRGO_RESET ((uint32_t)0x00000000U) /*!< UG bit from the TIMx_EGR register is used as trigger output */
526 #define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output */
527 #define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output */
528 #define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< CC1 capture or a compare match is used as trigger output */
529 #define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output */
530 #define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output */
531 #define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output */
532 #define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */
533 /**
534 * @}
535 */
536
537
538 /** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
539 * @{
540 */
541 #define LL_TIM_SLAVEMODE_DISABLED ((uint32_t)0x00000000U) /*!< Slave mode disabled */
542 #define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */
543 #define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */
544 #define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */
545 /**
546 * @}
547 */
548
549 /** @defgroup TIM_LL_EC_TS Trigger Selection
550 * @{
551 */
552 #define LL_TIM_TS_ITR0 ((uint32_t)0x00000000U) /*!< Internal Trigger 0 (ITR0) is used as trigger input */
553 #define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */
554 #define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */
555 #define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */
556 #define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
557 #define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
558 #define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
559 #define LL_TIM_TS_ETRF TIM_SMCR_TS /*!< Filtered external Trigger (ETRF) is used as trigger input */
560 /**
561 * @}
562 */
563
564 /** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
565 * @{
566 */
567 #define LL_TIM_ETR_POLARITY_NONINVERTED ((uint32_t)0x00000000U) /*!< ETR is non-inverted, active at high level or rising edge */
568 #define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /*!< ETR is inverted, active at low level or falling edge */
569 /**
570 * @}
571 */
572
573 /** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
574 * @{
575 */
576 #define LL_TIM_ETR_PRESCALER_DIV1 ((uint32_t)0x00000000U) /*!< ETR prescaler OFF */
577 #define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR frequency is divided by 2 */
578 #define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR frequency is divided by 4 */
579 #define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR frequency is divided by 8 */
580 /**
581 * @}
582 */
583
584 /** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
585 * @{
586 */
587 #define LL_TIM_ETR_FILTER_FDIV1 ((uint32_t)0x00000000U) /*!< No filter, sampling is done at fDTS */
588 #define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /*!< fSAMPLING=fCK_INT, N=2 */
589 #define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /*!< fSAMPLING=fCK_INT, N=4 */
590 #define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fCK_INT, N=8 */
591 #define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /*!< fSAMPLING=fDTS/2, N=6 */
592 #define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/2, N=8 */
593 #define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 ) /*!< fSAMPLING=fDTS/4, N=6 */
594 #define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/4, N=8 */
595 #define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=8 */
596 #define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=5 */
597 #define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 ) /*!< fSAMPLING=fDTS/16, N=6 */
598 #define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */
599 #define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 ) /*!< fSAMPLING=fDTS/16, N=5 */
600 #define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/32, N=5 */
601 #define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/32, N=6 */
602 #define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /*!< fSAMPLING=fDTS/32, N=8 */
603 /**
604 * @}
605 */
606
607
608
609
610
611
612
613 /** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
614 * @{
615 */
616 #define LL_TIM_DMABURST_BASEADDR_CR1 ((uint32_t)0x00000000U) /*!< TIMx_CR1 register is the DMA base address for DMA burst */
617 #define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /*!< TIMx_CR2 register is the DMA base address for DMA burst */
618 #define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /*!< TIMx_SMCR register is the DMA base address for DMA burst */
619 #define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_DIER register is the DMA base address for DMA burst */
620 #define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /*!< TIMx_SR register is the DMA base address for DMA burst */
621 #define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_EGR register is the DMA base address for DMA burst */
622 #define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */
623 #define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */
624 #define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /*!< TIMx_CCER register is the DMA base address for DMA burst */
625 #define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_CNT register is the DMA base address for DMA burst */
626 #define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_PSC register is the DMA base address for DMA burst */
627 #define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_ARR register is the DMA base address for DMA burst */
628 #define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCR1 register is the DMA base address for DMA burst */
629 #define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR2 register is the DMA base address for DMA burst */
630 #define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR3 register is the DMA base address for DMA burst */
631 #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /*!< TIMx_CCR4 register is the DMA base address for DMA burst */
632 #define LL_TIM_DMABURST_BASEADDR_OR (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_OR register is the DMA base address for DMA burst */
633 /**
634 * @}
635 */
636
637 /** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
638 * @{
639 */
640 #define LL_TIM_DMABURST_LENGTH_1TRANSFER ((uint32_t)0x00000000U) /*!< Transfer is done to 1 register starting from the DMA burst base address */
641 #define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /*!< Transfer is done to 2 registers starting from the DMA burst base address */
642 #define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /*!< Transfer is done to 3 registers starting from the DMA burst base address */
643 #define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 4 registers starting from the DMA burst base address */
644 #define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /*!< Transfer is done to 5 registers starting from the DMA burst base address */
645 #define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 6 registers starting from the DMA burst base address */
646 #define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 7 registers starting from the DMA burst base address */
647 #define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 1 registers starting from the DMA burst base address */
648 #define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /*!< Transfer is done to 9 registers starting from the DMA burst base address */
649 #define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 10 registers starting from the DMA burst base address */
650 #define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1) /*!< Transfer is done to 11 registers starting from the DMA burst base address */
651 #define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 12 registers starting from the DMA burst base address */
652 #define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2) /*!< Transfer is done to 13 registers starting from the DMA burst base address */
653 #define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 14 registers starting from the DMA burst base address */
654 #define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 15 registers starting from the DMA burst base address */
655 #define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */
656 #define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /*!< Transfer is done to 17 registers starting from the DMA burst base address */
657 #define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0) /*!< Transfer is done to 18 registers starting from the DMA burst base address */
658 /**
659 * @}
660 */
661
662 /** @defgroup TIM_LL_EC_TIM10_TI1_RMP TIM10 input 1 remapping capability
663 * @{
664 */
665 #define LL_TIM_TIM10_TI1_RMP_GPIO ((uint32_t)0x00000000U | TIM_OR_RMP_MASK) /*!< TIM10 channel1 is connected to GPIO */
666 #define LL_TIM_TIM10_TI1_RMP_LSI (TIM_OR_TI1RMP_0 | TIM_OR_RMP_MASK) /*!< TIM10 channel1 is connected to LSI internal clock */
667 #define LL_TIM_TIM10_TI1_RMP_LSE (TIM_OR_TI1RMP_1 | TIM_OR_RMP_MASK) /*!< TIM10 channel1 is connected to LSE internal clock */
668 #define LL_TIM_TIM10_TI1_RMP_RTC (TIM_OR_TI1RMP_0 | TIM_OR_TI1RMP_1 | TIM_OR_RMP_MASK) /*!< TIM10 channel1 is connected to RTC wakeup interrupt signal */
669 /**
670 * @}
671 */
672
673 /** @defgroup TIM_LL_EC_TIM10_ETR_RMP TIM10 ETR remap
674 * @{
675 */
676 #define LL_TIM_TIM10_ETR_RMP_LSE ((uint32_t)0x00000000U | TIM_OR_RMP_MASK) /*!< TIM10 ETR input is connected to LSE */
677 #define LL_TIM_TIM10_ETR_RMP_TIM9_TGO (TIM_OR_ETR_RMP | TIM_OR_RMP_MASK) /*!< TIM10 ETR input is connected to TIM9 TGO */
678 /**
679 * @}
680 */
681
682 /** @defgroup TIM_LL_EC_TIM10_TI1_RMP_RI TIM10 Input 1 remap for Routing Interface (RI)
683 * @{
684 */
685 #define LL_TIM_TIM10_TI1_RMP ((uint32_t)0x00000000U | TIM_OR_RMP_MASK) /*!< TIM10 Channel1 connection depends on TI1_RMP[1:0] bit values */
686 #define LL_TIM_TIM10_TI1_RMP_RI (TIM_OR_TI1_RMP_RI | TIM_OR_RMP_MASK) /*!< TIM10 channel1 is connected to RI */
687 /**
688 * @}
689 */
690
691 /** @defgroup TIM_LL_EC_TIM11_TI1_RMP TIM11 input 1 remapping capability
692 * @{
693 */
694 #define LL_TIM_TIM11_TI1_RMP_GPIO ((uint32_t)0x00000000U | TIM_OR_RMP_MASK) /*!< TIM11 channel1 is connected to GPIO */
695 #define LL_TIM_TIM11_TI1_RMP_MSI (TIM_OR_TI1RMP_0 | TIM_OR_RMP_MASK) /*!< TIM11 channel1 is connected to MSI internal clock */
696 #define LL_TIM_TIM11_TI1_RMP_HSE_RTC (TIM_OR_TI1RMP_1 | TIM_OR_RMP_MASK) /*!< TIM11 channel1 is connected to HSE RTC clock */
697 #define LL_TIM_TIM11_TI1_RMP_GPIO1 (TIM_OR_TI1RMP_0 | TIM_OR_TI1RMP_1 | TIM_OR_RMP_MASK) /*!< TIM11 channel1 is connected to GPIO */
698 /**
699 * @}
700 */
701
702 /** @defgroup TIM_LL_EC_TIM11_ETR_RMP TIM11 ETR remap
703 * @{
704 */
705 #define LL_TIM_TIM11_ETR_RMP_LSE ((uint32_t)0x00000000U | TIM_OR_RMP_MASK) /*!< TIM11 ETR input is connected to LSE */
706 #define LL_TIM_TIM11_ETR_RMP_TIM9_TGO (TIM_OR_ETR_RMP | TIM_OR_RMP_MASK) /*!< TIM11 ETR input is connected to TIM9 TGO clock */
707 /**
708 * @}
709 */
710
711 /** @defgroup TIM_LL_EC_TIM11_TI1_RMP_RI TIM11 Input 1 remap for Routing Interface (RI)
712 * @{
713 */
714 #define LL_TIM_TIM11_TI1_RMP ((uint32_t)0x00000000U | TIM_OR_RMP_MASK) /*!< TIM11 Channel1 connection depends on TI1_RMP[1:0] bit values */
715 #define LL_TIM_TIM11_TI1_RMP_RI (TIM_OR_TI1_RMP_RI | TIM_OR_RMP_MASK) /*!< TIM11 channel1 is connected to RI */
716 /**
717 * @}
718 */
719
720 /** @defgroup TIM_LL_EC_TIM9_TI1_RMP TIM9 Input 1 remap
721 * @{
722 */
723 #define LL_TIM_TIM9_TI1_RMP_GPIO ((uint32_t)0x00000000U | TIM9_OR_RMP_MASK) /*!< TIM9 channel1 is connected to GPIO */
724 #define LL_TIM_TIM9_TI1_RMP_LSE (TIM_OR_TI1RMP_0 | TIM9_OR_RMP_MASK) /*!< TIM9 channel1 is connected to LSE internal clock */
725 #define LL_TIM_TIM9_TI1_RMP_GPIO1 (TIM_OR_TI1RMP_1 | TIM9_OR_RMP_MASK) /*!< TIM9 channel1 is connected to GPIO */
726 #define LL_TIM_TIM9_TI1_RMP_GPIO2 (TIM_OR_TI1RMP_0 | TIM_OR_TI1RMP_1 | TIM9_OR_RMP_MASK) /*!< TIM9 channel1 is connected to GPIO */
727 /**
728 * @}
729 */
730
731 /** @defgroup TIM_LL_EC_TIM9_ITR1_RMP TIM9 ITR1 remap
732 * @{
733 */
734 #define LL_TIM_TIM9_ITR1_RMP_TIM3_TGO ((uint32_t)0x00000000U | TIM9_OR_RMP_MASK) /*!< TIM9 channel1 is connected to TIM3 TGO signal */
735 #define LL_TIM_TIM9_ITR1_RMP_TOUCH_IO (TIM9_OR_ITR1_RMP | TIM9_OR_RMP_MASK) /*!< TIM9 channel1 is connected to touch sensing I/O */
736 /**
737 * @}
738 */
739
740 /** @defgroup TIM_LL_EC_TIM2_ITR1_RMP TIM2 internal trigger 1 remap
741 * @{
742 */
743 #define LL_TIM_TIM2_TIR1_RMP_TIM10_OC ((uint32_t)0x00000000U | TIM9_OR_RMP_MASK) /*!< TIM2 ITR1 input is connected to TIM10 OC*/
744 #define LL_TIM_TIM2_TIR1_RMP_TIM5_TGO (TIM2_OR_ITR1_RMP | TIM9_OR_RMP_MASK) /*!< TIM2 ITR1 input is connected to TIM5 TGO */
745 /**
746 * @}
747 */
748
749 /** @defgroup TIM_LL_EC_TIM3_ITR2_RMP TIM3 internal trigger 2 remap
750 * @{
751 */
752 #define LL_TIM_TIM3_TIR2_RMP_TIM11_OC ((uint32_t)0x00000000U | TIM9_OR_RMP_MASK) /*!< TIM3 ITR2 input is connected to TIM11 OC */
753 #define LL_TIM_TIM3_TIR2_RMP_TIM5_TGO (TIM3_OR_ITR2_RMP | TIM9_OR_RMP_MASK) /*!< TIM3 ITR2 input is connected to TIM5 TGO */
754 /**
755 * @}
756 */
757
758
759 /** @defgroup TIM_LL_EC_OCREF_CLR_INT OCREF clear input selection
760 * @{
761 */
762 #define LL_TIM_OCREF_CLR_INT_OCREF_CLR ((uint32_t)0x00000000U ) /*!< OCREF_CLR_INT is connected to the OCREF_CLR input */
763 #define LL_TIM_OCREF_CLR_INT_ETR TIM_SMCR_OCCS /*!< OCREF_CLR_INT is connected to ETRF */
764 /**
765 * @}
766 */
767
768
769 /**
770 * @}
771 */
772
773 /* Exported macro ------------------------------------------------------------*/
774 /** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
775 * @{
776 */
777
778 /** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
779 * @{
780 */
781 /**
782 * @brief Write a value in TIM register.
783 * @param __INSTANCE__ TIM Instance
784 * @param __REG__ Register to be written
785 * @param __VALUE__ Value to be written in the register
786 * @retval None
787 */
788 #define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
789
790 /**
791 * @brief Read a value in TIM register.
792 * @param __INSTANCE__ TIM Instance
793 * @param __REG__ Register to be read
794 * @retval Register value
795 */
796 #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
797 /**
798 * @}
799 */
800
801 /** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros
802 * @{
803 */
804
805
806 /**
807 * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
808 * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
809 * @param __TIMCLK__ timer input clock frequency (in Hz)
810 * @param __CNTCLK__ counter clock frequency (in Hz)
811 * @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
812 */
813 #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
814 ((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((__TIMCLK__)/(__CNTCLK__) - 1U) : 0U
815
816 /**
817 * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
818 * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
819 * @param __TIMCLK__ timer input clock frequency (in Hz)
820 * @param __PSC__ prescaler
821 * @param __FREQ__ output signal frequency (in Hz)
822 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
823 */
824 #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
825 (((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? ((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U)) - 1U) : 0U
826
827 /**
828 * @brief HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.
829 * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
830 * @param __TIMCLK__ timer input clock frequency (in Hz)
831 * @param __PSC__ prescaler
832 * @param __DELAY__ timer output compare active/inactive delay (in us)
833 * @retval Compare value (between Min_Data=0 and Max_Data=65535)
834 */
835 #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
836 ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
837 / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
838
839 /**
840 * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).
841 * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
842 * @param __TIMCLK__ timer input clock frequency (in Hz)
843 * @param __PSC__ prescaler
844 * @param __DELAY__ timer output compare active/inactive delay (in us)
845 * @param __PULSE__ pulse duration (in us)
846 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
847 */
848 #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
849 ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
850 + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
851
852 /**
853 * @brief HELPER macro retrieving the ratio of the input capture prescaler
854 * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
855 * @param __ICPSC__ This parameter can be one of the following values:
856 * @arg @ref LL_TIM_ICPSC_DIV1
857 * @arg @ref LL_TIM_ICPSC_DIV2
858 * @arg @ref LL_TIM_ICPSC_DIV4
859 * @arg @ref LL_TIM_ICPSC_DIV8
860 * @retval Input capture prescaler ratio (1, 2, 4 or 8)
861 */
862 #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
863 ((uint32_t)((uint32_t)0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
864
865
866 /**
867 * @}
868 */
869
870
871 /**
872 * @}
873 */
874
875 /* Exported functions --------------------------------------------------------*/
876 /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
877 * @{
878 */
879
880 /** @defgroup TIM_LL_EF_Time_Base Time Base configuration
881 * @{
882 */
883 /**
884 * @brief Enable timer counter.
885 * @rmtoll CR1 CEN LL_TIM_EnableCounter
886 * @param TIMx Timer instance
887 * @retval None
888 */
LL_TIM_EnableCounter(TIM_TypeDef * TIMx)889 __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
890 {
891 SET_BIT(TIMx->CR1, TIM_CR1_CEN);
892 }
893
894 /**
895 * @brief Disable timer counter.
896 * @rmtoll CR1 CEN LL_TIM_DisableCounter
897 * @param TIMx Timer instance
898 * @retval None
899 */
LL_TIM_DisableCounter(TIM_TypeDef * TIMx)900 __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
901 {
902 CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
903 }
904
905 /**
906 * @brief Indicates whether the timer counter is enabled.
907 * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
908 * @param TIMx Timer instance
909 * @retval State of bit (1 or 0).
910 */
LL_TIM_IsEnabledCounter(TIM_TypeDef * TIMx)911 __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx)
912 {
913 return (READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN));
914 }
915
916 /**
917 * @brief Enable update event generation.
918 * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
919 * @param TIMx Timer instance
920 * @retval None
921 */
LL_TIM_EnableUpdateEvent(TIM_TypeDef * TIMx)922 __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
923 {
924 SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
925 }
926
927 /**
928 * @brief Disable update event generation.
929 * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
930 * @param TIMx Timer instance
931 * @retval None
932 */
LL_TIM_DisableUpdateEvent(TIM_TypeDef * TIMx)933 __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
934 {
935 CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
936 }
937
938 /**
939 * @brief Indicates whether update event generation is enabled.
940 * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
941 * @param TIMx Timer instance
942 * @retval State of bit (1 or 0).
943 */
LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef * TIMx)944 __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx)
945 {
946 return (READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (TIM_CR1_UDIS));
947 }
948
949 /**
950 * @brief Set update event source
951 * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
952 * generate an update interrupt or DMA request if enabled:
953 * - Counter overflow/underflow
954 * - Setting the UG bit
955 * - Update generation through the slave mode controller
956 * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
957 * overflow/underflow generates an update interrupt or DMA request if enabled.
958 * @rmtoll CR1 URS LL_TIM_SetUpdateSource
959 * @param TIMx Timer instance
960 * @param UpdateSource This parameter can be one of the following values:
961 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
962 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
963 * @retval None
964 */
LL_TIM_SetUpdateSource(TIM_TypeDef * TIMx,uint32_t UpdateSource)965 __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
966 {
967 MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
968 }
969
970 /**
971 * @brief Get actual event update source
972 * @rmtoll CR1 URS LL_TIM_GetUpdateSource
973 * @param TIMx Timer instance
974 * @retval Returned value can be one of the following values:
975 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
976 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
977 */
LL_TIM_GetUpdateSource(TIM_TypeDef * TIMx)978 __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx)
979 {
980 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
981 }
982
983 /**
984 * @brief Set one pulse mode (one shot v.s. repetitive).
985 * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
986 * @param TIMx Timer instance
987 * @param OnePulseMode This parameter can be one of the following values:
988 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
989 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
990 * @retval None
991 */
LL_TIM_SetOnePulseMode(TIM_TypeDef * TIMx,uint32_t OnePulseMode)992 __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
993 {
994 MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
995 }
996
997 /**
998 * @brief Get actual one pulse mode.
999 * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
1000 * @param TIMx Timer instance
1001 * @retval Returned value can be one of the following values:
1002 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1003 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1004 */
LL_TIM_GetOnePulseMode(TIM_TypeDef * TIMx)1005 __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx)
1006 {
1007 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
1008 }
1009
1010 /**
1011 * @brief Set the timer counter counting mode.
1012 * @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1013 * check whether or not the counter mode selection feature is supported
1014 * by a timer instance.
1015 * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
1016 * CR1 CMS LL_TIM_SetCounterMode
1017 * @param TIMx Timer instance
1018 * @param CounterMode This parameter can be one of the following values:
1019 * @arg @ref LL_TIM_COUNTERMODE_UP
1020 * @arg @ref LL_TIM_COUNTERMODE_DOWN
1021 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1022 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1023 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1024 * @retval None
1025 */
LL_TIM_SetCounterMode(TIM_TypeDef * TIMx,uint32_t CounterMode)1026 __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
1027 {
1028 MODIFY_REG(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS, CounterMode);
1029 }
1030
1031 /**
1032 * @brief Get actual counter mode.
1033 * @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1034 * check whether or not the counter mode selection feature is supported
1035 * by a timer instance.
1036 * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
1037 * CR1 CMS LL_TIM_GetCounterMode
1038 * @param TIMx Timer instance
1039 * @retval Returned value can be one of the following values:
1040 * @arg @ref LL_TIM_COUNTERMODE_UP
1041 * @arg @ref LL_TIM_COUNTERMODE_DOWN
1042 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1043 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1044 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1045 */
LL_TIM_GetCounterMode(TIM_TypeDef * TIMx)1046 __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx)
1047 {
1048 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS));
1049 }
1050
1051 /**
1052 * @brief Enable auto-reload (ARR) preload.
1053 * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
1054 * @param TIMx Timer instance
1055 * @retval None
1056 */
LL_TIM_EnableARRPreload(TIM_TypeDef * TIMx)1057 __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
1058 {
1059 SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
1060 }
1061
1062 /**
1063 * @brief Disable auto-reload (ARR) preload.
1064 * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
1065 * @param TIMx Timer instance
1066 * @retval None
1067 */
LL_TIM_DisableARRPreload(TIM_TypeDef * TIMx)1068 __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
1069 {
1070 CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
1071 }
1072
1073 /**
1074 * @brief Indicates whether auto-reload (ARR) preload is enabled.
1075 * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
1076 * @param TIMx Timer instance
1077 * @retval State of bit (1 or 0).
1078 */
LL_TIM_IsEnabledARRPreload(TIM_TypeDef * TIMx)1079 __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx)
1080 {
1081 return (READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE));
1082 }
1083
1084 /**
1085 * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
1086 * @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1087 * whether or not the clock division feature is supported by the timer
1088 * instance.
1089 * @rmtoll CR1 CKD LL_TIM_SetClockDivision
1090 * @param TIMx Timer instance
1091 * @param ClockDivision This parameter can be one of the following values:
1092 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1093 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1094 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1095 * @retval None
1096 */
LL_TIM_SetClockDivision(TIM_TypeDef * TIMx,uint32_t ClockDivision)1097 __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
1098 {
1099 MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
1100 }
1101
1102 /**
1103 * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
1104 * @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1105 * whether or not the clock division feature is supported by the timer
1106 * instance.
1107 * @rmtoll CR1 CKD LL_TIM_GetClockDivision
1108 * @param TIMx Timer instance
1109 * @retval Returned value can be one of the following values:
1110 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1111 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1112 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1113 */
LL_TIM_GetClockDivision(TIM_TypeDef * TIMx)1114 __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx)
1115 {
1116 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
1117 }
1118
1119 /**
1120 * @brief Set the counter value.
1121 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1122 * whether or not a timer instance supports a 32 bits counter.
1123 * @rmtoll CNT CNT LL_TIM_SetCounter
1124 * @param TIMx Timer instance
1125 * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
1126 * @retval None
1127 */
LL_TIM_SetCounter(TIM_TypeDef * TIMx,uint32_t Counter)1128 __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
1129 {
1130 WRITE_REG(TIMx->CNT, Counter);
1131 }
1132
1133 /**
1134 * @brief Get the counter value.
1135 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1136 * whether or not a timer instance supports a 32 bits counter.
1137 * @rmtoll CNT CNT LL_TIM_GetCounter
1138 * @param TIMx Timer instance
1139 * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
1140 */
LL_TIM_GetCounter(TIM_TypeDef * TIMx)1141 __STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx)
1142 {
1143 return (uint32_t)(READ_REG(TIMx->CNT));
1144 }
1145
1146 /**
1147 * @brief Get the current direction of the counter
1148 * @rmtoll CR1 DIR LL_TIM_GetDirection
1149 * @param TIMx Timer instance
1150 * @retval Returned value can be one of the following values:
1151 * @arg @ref LL_TIM_COUNTERDIRECTION_UP
1152 * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
1153 */
LL_TIM_GetDirection(TIM_TypeDef * TIMx)1154 __STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx)
1155 {
1156 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
1157 }
1158
1159 /**
1160 * @brief Set the prescaler value.
1161 * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
1162 * @note The prescaler can be changed on the fly as this control register is buffered. The new
1163 * prescaler ratio is taken into account at the next update event.
1164 * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
1165 * @rmtoll PSC PSC LL_TIM_SetPrescaler
1166 * @param TIMx Timer instance
1167 * @param Prescaler between Min_Data=0 and Max_Data=65535
1168 * @retval None
1169 */
LL_TIM_SetPrescaler(TIM_TypeDef * TIMx,uint32_t Prescaler)1170 __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
1171 {
1172 WRITE_REG(TIMx->PSC, Prescaler);
1173 }
1174
1175 /**
1176 * @brief Get the prescaler value.
1177 * @rmtoll PSC PSC LL_TIM_GetPrescaler
1178 * @param TIMx Timer instance
1179 * @retval Prescaler value between Min_Data=0 and Max_Data=65535
1180 */
LL_TIM_GetPrescaler(TIM_TypeDef * TIMx)1181 __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx)
1182 {
1183 return (uint32_t)(READ_REG(TIMx->PSC));
1184 }
1185
1186 /**
1187 * @brief Set the auto-reload value.
1188 * @note The counter is blocked while the auto-reload value is null.
1189 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1190 * whether or not a timer instance supports a 32 bits counter.
1191 * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
1192 * @rmtoll ARR ARR LL_TIM_SetAutoReload
1193 * @param TIMx Timer instance
1194 * @param AutoReload between Min_Data=0 and Max_Data=65535
1195 * @retval None
1196 */
LL_TIM_SetAutoReload(TIM_TypeDef * TIMx,uint32_t AutoReload)1197 __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
1198 {
1199 WRITE_REG(TIMx->ARR, AutoReload);
1200 }
1201
1202 /**
1203 * @brief Get the auto-reload value.
1204 * @rmtoll ARR ARR LL_TIM_GetAutoReload
1205 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1206 * whether or not a timer instance supports a 32 bits counter.
1207 * @param TIMx Timer instance
1208 * @retval Auto-reload value
1209 */
LL_TIM_GetAutoReload(TIM_TypeDef * TIMx)1210 __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx)
1211 {
1212 return (uint32_t)(READ_REG(TIMx->ARR));
1213 }
1214
1215 /**
1216 * @}
1217 */
1218
1219 /** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
1220 * @{
1221 */
1222 /**
1223 * @brief Set the trigger of the capture/compare DMA request.
1224 * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
1225 * @param TIMx Timer instance
1226 * @param DMAReqTrigger This parameter can be one of the following values:
1227 * @arg @ref LL_TIM_CCDMAREQUEST_CC
1228 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
1229 * @retval None
1230 */
LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef * TIMx,uint32_t DMAReqTrigger)1231 __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
1232 {
1233 MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
1234 }
1235
1236 /**
1237 * @brief Get actual trigger of the capture/compare DMA request.
1238 * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
1239 * @param TIMx Timer instance
1240 * @retval Returned value can be one of the following values:
1241 * @arg @ref LL_TIM_CCDMAREQUEST_CC
1242 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
1243 */
LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef * TIMx)1244 __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx)
1245 {
1246 return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
1247 }
1248
1249 /**
1250 * @brief Enable capture/compare channels.
1251 * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
1252 * CCER CC2E LL_TIM_CC_EnableChannel\n
1253 * CCER CC3E LL_TIM_CC_EnableChannel\n
1254 * CCER CC4E LL_TIM_CC_EnableChannel
1255 * @param TIMx Timer instance
1256 * @param Channels This parameter can be a combination of the following values:
1257 * @arg @ref LL_TIM_CHANNEL_CH1
1258 * @arg @ref LL_TIM_CHANNEL_CH2
1259 * @arg @ref LL_TIM_CHANNEL_CH3
1260 * @arg @ref LL_TIM_CHANNEL_CH4
1261 * @retval None
1262 */
LL_TIM_CC_EnableChannel(TIM_TypeDef * TIMx,uint32_t Channels)1263 __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
1264 {
1265 SET_BIT(TIMx->CCER, Channels);
1266 }
1267
1268 /**
1269 * @brief Disable capture/compare channels.
1270 * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
1271 * CCER CC2E LL_TIM_CC_DisableChannel\n
1272 * CCER CC3E LL_TIM_CC_DisableChannel\n
1273 * CCER CC4E LL_TIM_CC_DisableChannel
1274 * @param TIMx Timer instance
1275 * @param Channels This parameter can be a combination of the following values:
1276 * @arg @ref LL_TIM_CHANNEL_CH1
1277 * @arg @ref LL_TIM_CHANNEL_CH2
1278 * @arg @ref LL_TIM_CHANNEL_CH3
1279 * @arg @ref LL_TIM_CHANNEL_CH4
1280 * @retval None
1281 */
LL_TIM_CC_DisableChannel(TIM_TypeDef * TIMx,uint32_t Channels)1282 __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
1283 {
1284 CLEAR_BIT(TIMx->CCER, Channels);
1285 }
1286
1287 /**
1288 * @brief Indicate whether channel(s) is(are) enabled.
1289 * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
1290 * CCER CC2E LL_TIM_CC_IsEnabledChannel\n
1291 * CCER CC3E LL_TIM_CC_IsEnabledChannel\n
1292 * CCER CC4E LL_TIM_CC_IsEnabledChannel
1293 * @param TIMx Timer instance
1294 * @param Channels This parameter can be a combination of the following values:
1295 * @arg @ref LL_TIM_CHANNEL_CH1
1296 * @arg @ref LL_TIM_CHANNEL_CH2
1297 * @arg @ref LL_TIM_CHANNEL_CH3
1298 * @arg @ref LL_TIM_CHANNEL_CH4
1299 * @retval State of bit (1 or 0).
1300 */
LL_TIM_CC_IsEnabledChannel(TIM_TypeDef * TIMx,uint32_t Channels)1301 __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
1302 {
1303 return (READ_BIT(TIMx->CCER, Channels) == (Channels));
1304 }
1305
1306 /**
1307 * @}
1308 */
1309
1310 /** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
1311 * @{
1312 */
1313 /**
1314 * @brief Configure an output channel.
1315 * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
1316 * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
1317 * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
1318 * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
1319 * CCER CC1P LL_TIM_OC_ConfigOutput\n
1320 * CCER CC2P LL_TIM_OC_ConfigOutput\n
1321 * CCER CC3P LL_TIM_OC_ConfigOutput\n
1322 * CCER CC4P LL_TIM_OC_ConfigOutput\n
1323 * @param TIMx Timer instance
1324 * @param Channel This parameter can be one of the following values:
1325 * @arg @ref LL_TIM_CHANNEL_CH1
1326 * @arg @ref LL_TIM_CHANNEL_CH2
1327 * @arg @ref LL_TIM_CHANNEL_CH3
1328 * @arg @ref LL_TIM_CHANNEL_CH4
1329 * @param Configuration This parameter must be a combination of all the following values:
1330 * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
1331 * @retval None
1332 */
LL_TIM_OC_ConfigOutput(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Configuration)1333 __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
1334 {
1335 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1336 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1337 CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
1338 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
1339 (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
1340 }
1341
1342 /**
1343 * @brief Define the behavior of the output reference signal OCxREF from which
1344 * OCx and OCxN (when relevant) are derived.
1345 * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
1346 * CCMR1 OC2M LL_TIM_OC_SetMode\n
1347 * CCMR2 OC3M LL_TIM_OC_SetMode\n
1348 * CCMR2 OC4M LL_TIM_OC_SetMode
1349 * @param TIMx Timer instance
1350 * @param Channel This parameter can be one of the following values:
1351 * @arg @ref LL_TIM_CHANNEL_CH1
1352 * @arg @ref LL_TIM_CHANNEL_CH2
1353 * @arg @ref LL_TIM_CHANNEL_CH3
1354 * @arg @ref LL_TIM_CHANNEL_CH4
1355 * @param Mode This parameter can be one of the following values:
1356 * @arg @ref LL_TIM_OCMODE_FROZEN
1357 * @arg @ref LL_TIM_OCMODE_ACTIVE
1358 * @arg @ref LL_TIM_OCMODE_INACTIVE
1359 * @arg @ref LL_TIM_OCMODE_TOGGLE
1360 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
1361 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
1362 * @arg @ref LL_TIM_OCMODE_PWM1
1363 * @arg @ref LL_TIM_OCMODE_PWM2
1364 * @retval None
1365 */
LL_TIM_OC_SetMode(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Mode)1366 __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
1367 {
1368 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1369 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1370 MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
1371 }
1372
1373 /**
1374 * @brief Get the output compare mode of an output channel.
1375 * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
1376 * CCMR1 OC2M LL_TIM_OC_GetMode\n
1377 * CCMR2 OC3M LL_TIM_OC_GetMode\n
1378 * CCMR2 OC4M LL_TIM_OC_GetMode
1379 * @param TIMx Timer instance
1380 * @param Channel This parameter can be one of the following values:
1381 * @arg @ref LL_TIM_CHANNEL_CH1
1382 * @arg @ref LL_TIM_CHANNEL_CH2
1383 * @arg @ref LL_TIM_CHANNEL_CH3
1384 * @arg @ref LL_TIM_CHANNEL_CH4
1385 * @retval Returned value can be one of the following values:
1386 * @arg @ref LL_TIM_OCMODE_FROZEN
1387 * @arg @ref LL_TIM_OCMODE_ACTIVE
1388 * @arg @ref LL_TIM_OCMODE_INACTIVE
1389 * @arg @ref LL_TIM_OCMODE_TOGGLE
1390 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
1391 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
1392 * @arg @ref LL_TIM_OCMODE_PWM1
1393 * @arg @ref LL_TIM_OCMODE_PWM2
1394 */
LL_TIM_OC_GetMode(TIM_TypeDef * TIMx,uint32_t Channel)1395 __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
1396 {
1397 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1398 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1399 return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
1400 }
1401
1402 /**
1403 * @brief Set the polarity of an output channel.
1404 * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
1405 * CCER CC2P LL_TIM_OC_SetPolarity\n
1406 * CCER CC3P LL_TIM_OC_SetPolarity\n
1407 * CCER CC4P LL_TIM_OC_SetPolarity
1408 * @param TIMx Timer instance
1409 * @param Channel This parameter can be one of the following values:
1410 * @arg @ref LL_TIM_CHANNEL_CH1
1411 * @arg @ref LL_TIM_CHANNEL_CH2
1412 * @arg @ref LL_TIM_CHANNEL_CH3
1413 * @arg @ref LL_TIM_CHANNEL_CH4
1414 * @param Polarity This parameter can be one of the following values:
1415 * @arg @ref LL_TIM_OCPOLARITY_HIGH
1416 * @arg @ref LL_TIM_OCPOLARITY_LOW
1417 * @retval None
1418 */
LL_TIM_OC_SetPolarity(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Polarity)1419 __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
1420 {
1421 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1422 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
1423 }
1424
1425 /**
1426 * @brief Get the polarity of an output channel.
1427 * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
1428 * CCER CC2P LL_TIM_OC_GetPolarity\n
1429 * CCER CC3P LL_TIM_OC_GetPolarity\n
1430 * CCER CC4P LL_TIM_OC_GetPolarity
1431 * @param TIMx Timer instance
1432 * @param Channel This parameter can be one of the following values:
1433 * @arg @ref LL_TIM_CHANNEL_CH1
1434 * @arg @ref LL_TIM_CHANNEL_CH2
1435 * @arg @ref LL_TIM_CHANNEL_CH3
1436 * @arg @ref LL_TIM_CHANNEL_CH4
1437 * @retval Returned value can be one of the following values:
1438 * @arg @ref LL_TIM_OCPOLARITY_HIGH
1439 * @arg @ref LL_TIM_OCPOLARITY_LOW
1440 */
LL_TIM_OC_GetPolarity(TIM_TypeDef * TIMx,uint32_t Channel)1441 __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
1442 {
1443 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1444 return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
1445 }
1446
1447 /**
1448 * @brief Enable fast mode for the output channel.
1449 * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
1450 * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
1451 * CCMR1 OC2FE LL_TIM_OC_EnableFast\n
1452 * CCMR2 OC3FE LL_TIM_OC_EnableFast\n
1453 * CCMR2 OC4FE LL_TIM_OC_EnableFast
1454 * @param TIMx Timer instance
1455 * @param Channel This parameter can be one of the following values:
1456 * @arg @ref LL_TIM_CHANNEL_CH1
1457 * @arg @ref LL_TIM_CHANNEL_CH2
1458 * @arg @ref LL_TIM_CHANNEL_CH3
1459 * @arg @ref LL_TIM_CHANNEL_CH4
1460 * @retval None
1461 */
LL_TIM_OC_EnableFast(TIM_TypeDef * TIMx,uint32_t Channel)1462 __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
1463 {
1464 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1465 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1466 SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
1467
1468 }
1469
1470 /**
1471 * @brief Disable fast mode for the output channel.
1472 * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
1473 * CCMR1 OC2FE LL_TIM_OC_DisableFast\n
1474 * CCMR2 OC3FE LL_TIM_OC_DisableFast\n
1475 * CCMR2 OC4FE LL_TIM_OC_DisableFast
1476 * @param TIMx Timer instance
1477 * @param Channel This parameter can be one of the following values:
1478 * @arg @ref LL_TIM_CHANNEL_CH1
1479 * @arg @ref LL_TIM_CHANNEL_CH2
1480 * @arg @ref LL_TIM_CHANNEL_CH3
1481 * @arg @ref LL_TIM_CHANNEL_CH4
1482 * @retval None
1483 */
LL_TIM_OC_DisableFast(TIM_TypeDef * TIMx,uint32_t Channel)1484 __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
1485 {
1486 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1487 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1488 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
1489
1490 }
1491
1492 /**
1493 * @brief Indicates whether fast mode is enabled for the output channel.
1494 * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
1495 * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
1496 * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
1497 * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
1498 * @param TIMx Timer instance
1499 * @param Channel This parameter can be one of the following values:
1500 * @arg @ref LL_TIM_CHANNEL_CH1
1501 * @arg @ref LL_TIM_CHANNEL_CH2
1502 * @arg @ref LL_TIM_CHANNEL_CH3
1503 * @arg @ref LL_TIM_CHANNEL_CH4
1504 * @retval State of bit (1 or 0).
1505 */
LL_TIM_OC_IsEnabledFast(TIM_TypeDef * TIMx,uint32_t Channel)1506 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
1507 {
1508 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1509 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1510 register uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
1511 return (READ_BIT(*pReg, bitfield) == bitfield);
1512 }
1513
1514 /**
1515 * @brief Enable compare register (TIMx_CCRx) preload for the output channel.
1516 * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
1517 * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
1518 * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
1519 * CCMR2 OC4PE LL_TIM_OC_EnablePreload
1520 * @param TIMx Timer instance
1521 * @param Channel This parameter can be one of the following values:
1522 * @arg @ref LL_TIM_CHANNEL_CH1
1523 * @arg @ref LL_TIM_CHANNEL_CH2
1524 * @arg @ref LL_TIM_CHANNEL_CH3
1525 * @arg @ref LL_TIM_CHANNEL_CH4
1526 * @retval None
1527 */
LL_TIM_OC_EnablePreload(TIM_TypeDef * TIMx,uint32_t Channel)1528 __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
1529 {
1530 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1531 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1532 SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
1533 }
1534
1535 /**
1536 * @brief Disable compare register (TIMx_CCRx) preload for the output channel.
1537 * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
1538 * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
1539 * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
1540 * CCMR2 OC4PE LL_TIM_OC_DisablePreload
1541 * @param TIMx Timer instance
1542 * @param Channel This parameter can be one of the following values:
1543 * @arg @ref LL_TIM_CHANNEL_CH1
1544 * @arg @ref LL_TIM_CHANNEL_CH2
1545 * @arg @ref LL_TIM_CHANNEL_CH3
1546 * @arg @ref LL_TIM_CHANNEL_CH4
1547 * @retval None
1548 */
LL_TIM_OC_DisablePreload(TIM_TypeDef * TIMx,uint32_t Channel)1549 __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
1550 {
1551 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1552 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1553 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
1554 }
1555
1556 /**
1557 * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
1558 * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
1559 * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
1560 * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
1561 * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
1562 * @param TIMx Timer instance
1563 * @param Channel This parameter can be one of the following values:
1564 * @arg @ref LL_TIM_CHANNEL_CH1
1565 * @arg @ref LL_TIM_CHANNEL_CH2
1566 * @arg @ref LL_TIM_CHANNEL_CH3
1567 * @arg @ref LL_TIM_CHANNEL_CH4
1568 * @retval State of bit (1 or 0).
1569 */
LL_TIM_OC_IsEnabledPreload(TIM_TypeDef * TIMx,uint32_t Channel)1570 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
1571 {
1572 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1573 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1574 register uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
1575 return (READ_BIT(*pReg, bitfield) == bitfield);
1576 }
1577
1578 /**
1579 * @brief Enable clearing the output channel on an external event.
1580 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
1581 * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
1582 * or not a timer instance can clear the OCxREF signal on an external event.
1583 * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
1584 * CCMR1 OC2CE LL_TIM_OC_EnableClear\n
1585 * CCMR2 OC3CE LL_TIM_OC_EnableClear\n
1586 * CCMR2 OC4CE LL_TIM_OC_EnableClear
1587 * @param TIMx Timer instance
1588 * @param Channel This parameter can be one of the following values:
1589 * @arg @ref LL_TIM_CHANNEL_CH1
1590 * @arg @ref LL_TIM_CHANNEL_CH2
1591 * @arg @ref LL_TIM_CHANNEL_CH3
1592 * @arg @ref LL_TIM_CHANNEL_CH4
1593 * @retval None
1594 */
LL_TIM_OC_EnableClear(TIM_TypeDef * TIMx,uint32_t Channel)1595 __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
1596 {
1597 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1598 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1599 SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
1600 }
1601
1602 /**
1603 * @brief Disable clearing the output channel on an external event.
1604 * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
1605 * or not a timer instance can clear the OCxREF signal on an external event.
1606 * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
1607 * CCMR1 OC2CE LL_TIM_OC_DisableClear\n
1608 * CCMR2 OC3CE LL_TIM_OC_DisableClear\n
1609 * CCMR2 OC4CE LL_TIM_OC_DisableClear
1610 * @param TIMx Timer instance
1611 * @param Channel This parameter can be one of the following values:
1612 * @arg @ref LL_TIM_CHANNEL_CH1
1613 * @arg @ref LL_TIM_CHANNEL_CH2
1614 * @arg @ref LL_TIM_CHANNEL_CH3
1615 * @arg @ref LL_TIM_CHANNEL_CH4
1616 * @retval None
1617 */
LL_TIM_OC_DisableClear(TIM_TypeDef * TIMx,uint32_t Channel)1618 __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
1619 {
1620 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1621 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1622 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
1623 }
1624
1625 /**
1626 * @brief Indicates clearing the output channel on an external event is enabled for the output channel.
1627 * @note This function enables clearing the output channel on an external event.
1628 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
1629 * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
1630 * or not a timer instance can clear the OCxREF signal on an external event.
1631 * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
1632 * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
1633 * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
1634 * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
1635 * @param TIMx Timer instance
1636 * @param Channel This parameter can be one of the following values:
1637 * @arg @ref LL_TIM_CHANNEL_CH1
1638 * @arg @ref LL_TIM_CHANNEL_CH2
1639 * @arg @ref LL_TIM_CHANNEL_CH3
1640 * @arg @ref LL_TIM_CHANNEL_CH4
1641 * @retval State of bit (1 or 0).
1642 */
LL_TIM_OC_IsEnabledClear(TIM_TypeDef * TIMx,uint32_t Channel)1643 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
1644 {
1645 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1646 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1647 register uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
1648 return (READ_BIT(*pReg, bitfield) == bitfield);
1649 }
1650
1651 /**
1652 * @brief Set compare value for output channel 1 (TIMx_CCR1).
1653 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
1654 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1655 * whether or not a timer instance supports a 32 bits counter.
1656 * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
1657 * output channel 1 is supported by a timer instance.
1658 * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
1659 * @param TIMx Timer instance
1660 * @param CompareValue between Min_Data=0 and Max_Data=65535
1661 * @retval None
1662 */
LL_TIM_OC_SetCompareCH1(TIM_TypeDef * TIMx,uint32_t CompareValue)1663 __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
1664 {
1665 WRITE_REG(TIMx->CCR1, CompareValue);
1666 }
1667
1668 /**
1669 * @brief Set compare value for output channel 2 (TIMx_CCR2).
1670 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
1671 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1672 * whether or not a timer instance supports a 32 bits counter.
1673 * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
1674 * output channel 2 is supported by a timer instance.
1675 * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
1676 * @param TIMx Timer instance
1677 * @param CompareValue between Min_Data=0 and Max_Data=65535
1678 * @retval None
1679 */
LL_TIM_OC_SetCompareCH2(TIM_TypeDef * TIMx,uint32_t CompareValue)1680 __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
1681 {
1682 WRITE_REG(TIMx->CCR2, CompareValue);
1683 }
1684
1685 /**
1686 * @brief Set compare value for output channel 3 (TIMx_CCR3).
1687 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
1688 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1689 * whether or not a timer instance supports a 32 bits counter.
1690 * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
1691 * output channel is supported by a timer instance.
1692 * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
1693 * @param TIMx Timer instance
1694 * @param CompareValue between Min_Data=0 and Max_Data=65535
1695 * @retval None
1696 */
LL_TIM_OC_SetCompareCH3(TIM_TypeDef * TIMx,uint32_t CompareValue)1697 __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
1698 {
1699 WRITE_REG(TIMx->CCR3, CompareValue);
1700 }
1701
1702 /**
1703 * @brief Set compare value for output channel 4 (TIMx_CCR4).
1704 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
1705 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1706 * whether or not a timer instance supports a 32 bits counter.
1707 * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
1708 * output channel 4 is supported by a timer instance.
1709 * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
1710 * @param TIMx Timer instance
1711 * @param CompareValue between Min_Data=0 and Max_Data=65535
1712 * @retval None
1713 */
LL_TIM_OC_SetCompareCH4(TIM_TypeDef * TIMx,uint32_t CompareValue)1714 __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
1715 {
1716 WRITE_REG(TIMx->CCR4, CompareValue);
1717 }
1718
1719 /**
1720 * @brief Get compare value (TIMx_CCR1) set for output channel 1.
1721 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
1722 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1723 * whether or not a timer instance supports a 32 bits counter.
1724 * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
1725 * output channel 1 is supported by a timer instance.
1726 * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
1727 * @param TIMx Timer instance
1728 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
1729 */
LL_TIM_OC_GetCompareCH1(TIM_TypeDef * TIMx)1730 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx)
1731 {
1732 return (uint32_t)(READ_REG(TIMx->CCR1));
1733 }
1734
1735 /**
1736 * @brief Get compare value (TIMx_CCR2) set for output channel 2.
1737 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
1738 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1739 * whether or not a timer instance supports a 32 bits counter.
1740 * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
1741 * output channel 2 is supported by a timer instance.
1742 * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
1743 * @param TIMx Timer instance
1744 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
1745 */
LL_TIM_OC_GetCompareCH2(TIM_TypeDef * TIMx)1746 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx)
1747 {
1748 return (uint32_t)(READ_REG(TIMx->CCR2));
1749 }
1750
1751 /**
1752 * @brief Get compare value (TIMx_CCR3) set for output channel 3.
1753 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
1754 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1755 * whether or not a timer instance supports a 32 bits counter.
1756 * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
1757 * output channel 3 is supported by a timer instance.
1758 * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
1759 * @param TIMx Timer instance
1760 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
1761 */
LL_TIM_OC_GetCompareCH3(TIM_TypeDef * TIMx)1762 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx)
1763 {
1764 return (uint32_t)(READ_REG(TIMx->CCR3));
1765 }
1766
1767 /**
1768 * @brief Get compare value (TIMx_CCR4) set for output channel 4.
1769 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
1770 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1771 * whether or not a timer instance supports a 32 bits counter.
1772 * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
1773 * output channel 4 is supported by a timer instance.
1774 * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
1775 * @param TIMx Timer instance
1776 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
1777 */
LL_TIM_OC_GetCompareCH4(TIM_TypeDef * TIMx)1778 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx)
1779 {
1780 return (uint32_t)(READ_REG(TIMx->CCR4));
1781 }
1782
1783 /**
1784 * @}
1785 */
1786
1787 /** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
1788 * @{
1789 */
1790 /**
1791 * @brief Configure input channel.
1792 * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
1793 * CCMR1 IC1PSC LL_TIM_IC_Config\n
1794 * CCMR1 IC1F LL_TIM_IC_Config\n
1795 * CCMR1 CC2S LL_TIM_IC_Config\n
1796 * CCMR1 IC2PSC LL_TIM_IC_Config\n
1797 * CCMR1 IC2F LL_TIM_IC_Config\n
1798 * CCMR2 CC3S LL_TIM_IC_Config\n
1799 * CCMR2 IC3PSC LL_TIM_IC_Config\n
1800 * CCMR2 IC3F LL_TIM_IC_Config\n
1801 * CCMR2 CC4S LL_TIM_IC_Config\n
1802 * CCMR2 IC4PSC LL_TIM_IC_Config\n
1803 * CCMR2 IC4F LL_TIM_IC_Config\n
1804 * CCER CC1P LL_TIM_IC_Config\n
1805 * CCER CC1NP LL_TIM_IC_Config\n
1806 * CCER CC2P LL_TIM_IC_Config\n
1807 * CCER CC2NP LL_TIM_IC_Config\n
1808 * CCER CC3P LL_TIM_IC_Config\n
1809 * CCER CC3NP LL_TIM_IC_Config\n
1810 * CCER CC4P LL_TIM_IC_Config\n
1811 * CCER CC4NP LL_TIM_IC_Config
1812 * @param TIMx Timer instance
1813 * @param Channel This parameter can be one of the following values:
1814 * @arg @ref LL_TIM_CHANNEL_CH1
1815 * @arg @ref LL_TIM_CHANNEL_CH2
1816 * @arg @ref LL_TIM_CHANNEL_CH3
1817 * @arg @ref LL_TIM_CHANNEL_CH4
1818 * @param Configuration This parameter must be a combination of all the following values:
1819 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
1820 * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
1821 * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
1822 * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
1823 * @retval None
1824 */
LL_TIM_IC_Config(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Configuration)1825 __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
1826 {
1827 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1828 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1829 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
1830 ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]);
1831 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
1832 (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
1833 }
1834
1835 /**
1836 * @brief Set the active input.
1837 * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
1838 * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
1839 * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
1840 * CCMR2 CC4S LL_TIM_IC_SetActiveInput
1841 * @param TIMx Timer instance
1842 * @param Channel This parameter can be one of the following values:
1843 * @arg @ref LL_TIM_CHANNEL_CH1
1844 * @arg @ref LL_TIM_CHANNEL_CH2
1845 * @arg @ref LL_TIM_CHANNEL_CH3
1846 * @arg @ref LL_TIM_CHANNEL_CH4
1847 * @param ICActiveInput This parameter can be one of the following values:
1848 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
1849 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
1850 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
1851 * @retval None
1852 */
LL_TIM_IC_SetActiveInput(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICActiveInput)1853 __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
1854 {
1855 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1856 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1857 MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
1858 }
1859
1860 /**
1861 * @brief Get the current active input.
1862 * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
1863 * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
1864 * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
1865 * CCMR2 CC4S LL_TIM_IC_GetActiveInput
1866 * @param TIMx Timer instance
1867 * @param Channel This parameter can be one of the following values:
1868 * @arg @ref LL_TIM_CHANNEL_CH1
1869 * @arg @ref LL_TIM_CHANNEL_CH2
1870 * @arg @ref LL_TIM_CHANNEL_CH3
1871 * @arg @ref LL_TIM_CHANNEL_CH4
1872 * @retval Returned value can be one of the following values:
1873 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
1874 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
1875 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
1876 */
LL_TIM_IC_GetActiveInput(TIM_TypeDef * TIMx,uint32_t Channel)1877 __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)
1878 {
1879 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1880 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1881 return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
1882 }
1883
1884 /**
1885 * @brief Set the prescaler of input channel.
1886 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
1887 * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
1888 * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
1889 * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
1890 * @param TIMx Timer instance
1891 * @param Channel This parameter can be one of the following values:
1892 * @arg @ref LL_TIM_CHANNEL_CH1
1893 * @arg @ref LL_TIM_CHANNEL_CH2
1894 * @arg @ref LL_TIM_CHANNEL_CH3
1895 * @arg @ref LL_TIM_CHANNEL_CH4
1896 * @param ICPrescaler This parameter can be one of the following values:
1897 * @arg @ref LL_TIM_ICPSC_DIV1
1898 * @arg @ref LL_TIM_ICPSC_DIV2
1899 * @arg @ref LL_TIM_ICPSC_DIV4
1900 * @arg @ref LL_TIM_ICPSC_DIV8
1901 * @retval None
1902 */
LL_TIM_IC_SetPrescaler(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICPrescaler)1903 __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
1904 {
1905 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1906 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1907 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
1908 }
1909
1910 /**
1911 * @brief Get the current prescaler value acting on an input channel.
1912 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
1913 * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
1914 * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
1915 * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
1916 * @param TIMx Timer instance
1917 * @param Channel This parameter can be one of the following values:
1918 * @arg @ref LL_TIM_CHANNEL_CH1
1919 * @arg @ref LL_TIM_CHANNEL_CH2
1920 * @arg @ref LL_TIM_CHANNEL_CH3
1921 * @arg @ref LL_TIM_CHANNEL_CH4
1922 * @retval Returned value can be one of the following values:
1923 * @arg @ref LL_TIM_ICPSC_DIV1
1924 * @arg @ref LL_TIM_ICPSC_DIV2
1925 * @arg @ref LL_TIM_ICPSC_DIV4
1926 * @arg @ref LL_TIM_ICPSC_DIV8
1927 */
LL_TIM_IC_GetPrescaler(TIM_TypeDef * TIMx,uint32_t Channel)1928 __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)
1929 {
1930 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1931 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1932 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
1933 }
1934
1935 /**
1936 * @brief Set the input filter duration.
1937 * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
1938 * CCMR1 IC2F LL_TIM_IC_SetFilter\n
1939 * CCMR2 IC3F LL_TIM_IC_SetFilter\n
1940 * CCMR2 IC4F LL_TIM_IC_SetFilter
1941 * @param TIMx Timer instance
1942 * @param Channel This parameter can be one of the following values:
1943 * @arg @ref LL_TIM_CHANNEL_CH1
1944 * @arg @ref LL_TIM_CHANNEL_CH2
1945 * @arg @ref LL_TIM_CHANNEL_CH3
1946 * @arg @ref LL_TIM_CHANNEL_CH4
1947 * @param ICFilter This parameter can be one of the following values:
1948 * @arg @ref LL_TIM_IC_FILTER_FDIV1
1949 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
1950 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
1951 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
1952 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
1953 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
1954 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
1955 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
1956 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
1957 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
1958 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
1959 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
1960 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
1961 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
1962 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
1963 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
1964 * @retval None
1965 */
LL_TIM_IC_SetFilter(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICFilter)1966 __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
1967 {
1968 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1969 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1970 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
1971 }
1972
1973 /**
1974 * @brief Get the input filter duration.
1975 * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
1976 * CCMR1 IC2F LL_TIM_IC_GetFilter\n
1977 * CCMR2 IC3F LL_TIM_IC_GetFilter\n
1978 * CCMR2 IC4F LL_TIM_IC_GetFilter
1979 * @param TIMx Timer instance
1980 * @param Channel This parameter can be one of the following values:
1981 * @arg @ref LL_TIM_CHANNEL_CH1
1982 * @arg @ref LL_TIM_CHANNEL_CH2
1983 * @arg @ref LL_TIM_CHANNEL_CH3
1984 * @arg @ref LL_TIM_CHANNEL_CH4
1985 * @retval Returned value can be one of the following values:
1986 * @arg @ref LL_TIM_IC_FILTER_FDIV1
1987 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
1988 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
1989 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
1990 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
1991 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
1992 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
1993 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
1994 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
1995 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
1996 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
1997 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
1998 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
1999 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
2000 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
2001 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
2002 */
LL_TIM_IC_GetFilter(TIM_TypeDef * TIMx,uint32_t Channel)2003 __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)
2004 {
2005 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2006 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2007 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2008 }
2009
2010 /**
2011 * @brief Set the input channel polarity.
2012 * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
2013 * CCER CC1NP LL_TIM_IC_SetPolarity\n
2014 * CCER CC2P LL_TIM_IC_SetPolarity\n
2015 * CCER CC2NP LL_TIM_IC_SetPolarity\n
2016 * CCER CC3P LL_TIM_IC_SetPolarity\n
2017 * CCER CC3NP LL_TIM_IC_SetPolarity\n
2018 * CCER CC4P LL_TIM_IC_SetPolarity\n
2019 * CCER CC4NP LL_TIM_IC_SetPolarity
2020 * @param TIMx Timer instance
2021 * @param Channel This parameter can be one of the following values:
2022 * @arg @ref LL_TIM_CHANNEL_CH1
2023 * @arg @ref LL_TIM_CHANNEL_CH2
2024 * @arg @ref LL_TIM_CHANNEL_CH3
2025 * @arg @ref LL_TIM_CHANNEL_CH4
2026 * @param ICPolarity This parameter can be one of the following values:
2027 * @arg @ref LL_TIM_IC_POLARITY_RISING
2028 * @arg @ref LL_TIM_IC_POLARITY_FALLING
2029 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
2030 * @retval None
2031 */
LL_TIM_IC_SetPolarity(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICPolarity)2032 __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
2033 {
2034 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2035 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
2036 ICPolarity << SHIFT_TAB_CCxP[iChannel]);
2037 }
2038
2039 /**
2040 * @brief Get the current input channel polarity.
2041 * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
2042 * CCER CC1NP LL_TIM_IC_GetPolarity\n
2043 * CCER CC2P LL_TIM_IC_GetPolarity\n
2044 * CCER CC2NP LL_TIM_IC_GetPolarity\n
2045 * CCER CC3P LL_TIM_IC_GetPolarity\n
2046 * CCER CC3NP LL_TIM_IC_GetPolarity\n
2047 * CCER CC4P LL_TIM_IC_GetPolarity\n
2048 * CCER CC4NP LL_TIM_IC_GetPolarity
2049 * @param TIMx Timer instance
2050 * @param Channel This parameter can be one of the following values:
2051 * @arg @ref LL_TIM_CHANNEL_CH1
2052 * @arg @ref LL_TIM_CHANNEL_CH2
2053 * @arg @ref LL_TIM_CHANNEL_CH3
2054 * @arg @ref LL_TIM_CHANNEL_CH4
2055 * @retval Returned value can be one of the following values:
2056 * @arg @ref LL_TIM_IC_POLARITY_RISING
2057 * @arg @ref LL_TIM_IC_POLARITY_FALLING
2058 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
2059 */
LL_TIM_IC_GetPolarity(TIM_TypeDef * TIMx,uint32_t Channel)2060 __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
2061 {
2062 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2063 return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
2064 SHIFT_TAB_CCxP[iChannel]);
2065 }
2066
2067 /**
2068 * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
2069 * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
2070 * a timer instance provides an XOR input.
2071 * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
2072 * @param TIMx Timer instance
2073 * @retval None
2074 */
LL_TIM_IC_EnableXORCombination(TIM_TypeDef * TIMx)2075 __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
2076 {
2077 SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
2078 }
2079
2080 /**
2081 * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
2082 * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
2083 * a timer instance provides an XOR input.
2084 * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
2085 * @param TIMx Timer instance
2086 * @retval None
2087 */
LL_TIM_IC_DisableXORCombination(TIM_TypeDef * TIMx)2088 __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
2089 {
2090 CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
2091 }
2092
2093 /**
2094 * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
2095 * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
2096 * a timer instance provides an XOR input.
2097 * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
2098 * @param TIMx Timer instance
2099 * @retval State of bit (1 or 0).
2100 */
LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef * TIMx)2101 __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
2102 {
2103 return (READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S));
2104 }
2105
2106 /**
2107 * @brief Get captured value for input channel 1.
2108 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
2109 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2110 * whether or not a timer instance supports a 32 bits counter.
2111 * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2112 * input channel 1 is supported by a timer instance.
2113 * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
2114 * @param TIMx Timer instance
2115 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
2116 */
LL_TIM_IC_GetCaptureCH1(TIM_TypeDef * TIMx)2117 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx)
2118 {
2119 return (uint32_t)(READ_REG(TIMx->CCR1));
2120 }
2121
2122 /**
2123 * @brief Get captured value for input channel 2.
2124 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
2125 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2126 * whether or not a timer instance supports a 32 bits counter.
2127 * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2128 * input channel 2 is supported by a timer instance.
2129 * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
2130 * @param TIMx Timer instance
2131 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
2132 */
LL_TIM_IC_GetCaptureCH2(TIM_TypeDef * TIMx)2133 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx)
2134 {
2135 return (uint32_t)(READ_REG(TIMx->CCR2));
2136 }
2137
2138 /**
2139 * @brief Get captured value for input channel 3.
2140 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
2141 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2142 * whether or not a timer instance supports a 32 bits counter.
2143 * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2144 * input channel 3 is supported by a timer instance.
2145 * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
2146 * @param TIMx Timer instance
2147 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
2148 */
LL_TIM_IC_GetCaptureCH3(TIM_TypeDef * TIMx)2149 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx)
2150 {
2151 return (uint32_t)(READ_REG(TIMx->CCR3));
2152 }
2153
2154 /**
2155 * @brief Get captured value for input channel 4.
2156 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
2157 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2158 * whether or not a timer instance supports a 32 bits counter.
2159 * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2160 * input channel 4 is supported by a timer instance.
2161 * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
2162 * @param TIMx Timer instance
2163 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
2164 */
LL_TIM_IC_GetCaptureCH4(TIM_TypeDef * TIMx)2165 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx)
2166 {
2167 return (uint32_t)(READ_REG(TIMx->CCR4));
2168 }
2169
2170 /**
2171 * @}
2172 */
2173
2174 /** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
2175 * @{
2176 */
2177 /**
2178 * @brief Enable external clock mode 2.
2179 * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
2180 * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
2181 * whether or not a timer instance supports external clock mode2.
2182 * @rmtoll SMCR ECE LL_TIM_EnableExternalClock
2183 * @param TIMx Timer instance
2184 * @retval None
2185 */
LL_TIM_EnableExternalClock(TIM_TypeDef * TIMx)2186 __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
2187 {
2188 SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
2189 }
2190
2191 /**
2192 * @brief Disable external clock mode 2.
2193 * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
2194 * whether or not a timer instance supports external clock mode2.
2195 * @rmtoll SMCR ECE LL_TIM_DisableExternalClock
2196 * @param TIMx Timer instance
2197 * @retval None
2198 */
LL_TIM_DisableExternalClock(TIM_TypeDef * TIMx)2199 __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
2200 {
2201 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
2202 }
2203
2204 /**
2205 * @brief Indicate whether external clock mode 2 is enabled.
2206 * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
2207 * whether or not a timer instance supports external clock mode2.
2208 * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
2209 * @param TIMx Timer instance
2210 * @retval State of bit (1 or 0).
2211 */
LL_TIM_IsEnabledExternalClock(TIM_TypeDef * TIMx)2212 __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx)
2213 {
2214 return (READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE));
2215 }
2216
2217 /**
2218 * @brief Set the clock source of the counter clock.
2219 * @note when selected clock source is external clock mode 1, the timer input
2220 * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
2221 * function. This timer input must be configured by calling
2222 * the @ref LL_TIM_IC_Config() function.
2223 * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
2224 * whether or not a timer instance supports external clock mode1.
2225 * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
2226 * whether or not a timer instance supports external clock mode2.
2227 * @rmtoll SMCR SMS LL_TIM_SetClockSource\n
2228 * SMCR ECE LL_TIM_SetClockSource
2229 * @param TIMx Timer instance
2230 * @param ClockSource This parameter can be one of the following values:
2231 * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
2232 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
2233 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
2234 * @retval None
2235 */
LL_TIM_SetClockSource(TIM_TypeDef * TIMx,uint32_t ClockSource)2236 __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
2237 {
2238 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
2239 }
2240
2241 /**
2242 * @brief Set the encoder interface mode.
2243 * @note Macro @ref IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
2244 * whether or not a timer instance supports the encoder mode.
2245 * @rmtoll SMCR SMS LL_TIM_SetEncoderMode
2246 * @param TIMx Timer instance
2247 * @param EncoderMode This parameter can be one of the following values:
2248 * @arg @ref LL_TIM_ENCODERMODE_X2_TI1
2249 * @arg @ref LL_TIM_ENCODERMODE_X2_TI2
2250 * @arg @ref LL_TIM_ENCODERMODE_X4_TI12
2251 * @retval None
2252 */
LL_TIM_SetEncoderMode(TIM_TypeDef * TIMx,uint32_t EncoderMode)2253 __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
2254 {
2255 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
2256 }
2257
2258 /**
2259 * @}
2260 */
2261
2262 /** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
2263 * @{
2264 */
2265 /**
2266 * @brief Set the trigger output (TRGO) used for timer synchronization .
2267 * @note Macro @ref IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
2268 * whether or not a timer instance can operate as a master timer.
2269 * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
2270 * @param TIMx Timer instance
2271 * @param TimerSynchronization This parameter can be one of the following values:
2272 * @arg @ref LL_TIM_TRGO_RESET
2273 * @arg @ref LL_TIM_TRGO_ENABLE
2274 * @arg @ref LL_TIM_TRGO_UPDATE
2275 * @arg @ref LL_TIM_TRGO_CC1IF
2276 * @arg @ref LL_TIM_TRGO_OC1REF
2277 * @arg @ref LL_TIM_TRGO_OC2REF
2278 * @arg @ref LL_TIM_TRGO_OC3REF
2279 * @arg @ref LL_TIM_TRGO_OC4REF
2280 * @retval None
2281 */
LL_TIM_SetTriggerOutput(TIM_TypeDef * TIMx,uint32_t TimerSynchronization)2282 __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
2283 {
2284 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
2285 }
2286
2287 /**
2288 * @brief Set the synchronization mode of a slave timer.
2289 * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
2290 * a timer instance can operate as a slave timer.
2291 * @rmtoll SMCR SMS LL_TIM_SetSlaveMode
2292 * @param TIMx Timer instance
2293 * @param SlaveMode This parameter can be one of the following values:
2294 * @arg @ref LL_TIM_SLAVEMODE_DISABLED
2295 * @arg @ref LL_TIM_SLAVEMODE_RESET
2296 * @arg @ref LL_TIM_SLAVEMODE_GATED
2297 * @arg @ref LL_TIM_SLAVEMODE_TRIGGER
2298 * @retval None
2299 */
LL_TIM_SetSlaveMode(TIM_TypeDef * TIMx,uint32_t SlaveMode)2300 __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
2301 {
2302 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
2303 }
2304
2305 /**
2306 * @brief Set the selects the trigger input to be used to synchronize the counter.
2307 * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
2308 * a timer instance can operate as a slave timer.
2309 * @rmtoll SMCR TS LL_TIM_SetTriggerInput
2310 * @param TIMx Timer instance
2311 * @param TriggerInput This parameter can be one of the following values:
2312 * @arg @ref LL_TIM_TS_ITR0
2313 * @arg @ref LL_TIM_TS_ITR1
2314 * @arg @ref LL_TIM_TS_ITR2
2315 * @arg @ref LL_TIM_TS_ITR3
2316 * @arg @ref LL_TIM_TS_TI1F_ED
2317 * @arg @ref LL_TIM_TS_TI1FP1
2318 * @arg @ref LL_TIM_TS_TI2FP2
2319 * @arg @ref LL_TIM_TS_ETRF
2320 * @retval None
2321 */
LL_TIM_SetTriggerInput(TIM_TypeDef * TIMx,uint32_t TriggerInput)2322 __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
2323 {
2324 MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
2325 }
2326
2327 /**
2328 * @brief Enable the Master/Slave mode.
2329 * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
2330 * a timer instance can operate as a slave timer.
2331 * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
2332 * @param TIMx Timer instance
2333 * @retval None
2334 */
LL_TIM_EnableMasterSlaveMode(TIM_TypeDef * TIMx)2335 __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
2336 {
2337 SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
2338 }
2339
2340 /**
2341 * @brief Disable the Master/Slave mode.
2342 * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
2343 * a timer instance can operate as a slave timer.
2344 * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
2345 * @param TIMx Timer instance
2346 * @retval None
2347 */
LL_TIM_DisableMasterSlaveMode(TIM_TypeDef * TIMx)2348 __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
2349 {
2350 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
2351 }
2352
2353 /**
2354 * @brief Indicates whether the Master/Slave mode is enabled.
2355 * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
2356 * a timer instance can operate as a slave timer.
2357 * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
2358 * @param TIMx Timer instance
2359 * @retval State of bit (1 or 0).
2360 */
LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef * TIMx)2361 __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx)
2362 {
2363 return (READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM));
2364 }
2365
2366 /**
2367 * @brief Configure the external trigger (ETR) input.
2368 * @note Macro @ref IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
2369 * a timer instance provides an external trigger input.
2370 * @rmtoll SMCR ETP LL_TIM_ConfigETR\n
2371 * SMCR ETPS LL_TIM_ConfigETR\n
2372 * SMCR ETF LL_TIM_ConfigETR
2373 * @param TIMx Timer instance
2374 * @param ETRPolarity This parameter can be one of the following values:
2375 * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
2376 * @arg @ref LL_TIM_ETR_POLARITY_INVERTED
2377 * @param ETRPrescaler This parameter can be one of the following values:
2378 * @arg @ref LL_TIM_ETR_PRESCALER_DIV1
2379 * @arg @ref LL_TIM_ETR_PRESCALER_DIV2
2380 * @arg @ref LL_TIM_ETR_PRESCALER_DIV4
2381 * @arg @ref LL_TIM_ETR_PRESCALER_DIV8
2382 * @param ETRFilter This parameter can be one of the following values:
2383 * @arg @ref LL_TIM_ETR_FILTER_FDIV1
2384 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
2385 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
2386 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
2387 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
2388 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
2389 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
2390 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
2391 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
2392 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
2393 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
2394 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
2395 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
2396 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
2397 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
2398 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
2399 * @retval None
2400 */
LL_TIM_ConfigETR(TIM_TypeDef * TIMx,uint32_t ETRPolarity,uint32_t ETRPrescaler,uint32_t ETRFilter)2401 __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
2402 uint32_t ETRFilter)
2403 {
2404 MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter);
2405 }
2406
2407 /**
2408 * @}
2409 */
2410
2411 /** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
2412 * @{
2413 */
2414 /**
2415 * @brief Configures the timer DMA burst feature.
2416 * @note Macro @ref IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
2417 * not a timer instance supports the DMA burst mode.
2418 * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
2419 * DCR DBA LL_TIM_ConfigDMABurst
2420 * @param TIMx Timer instance
2421 * @param DMABurstBaseAddress This parameter can be one of the following values:
2422 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
2423 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
2424 * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
2425 * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
2426 * @arg @ref LL_TIM_DMABURST_BASEADDR_SR
2427 * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
2428 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
2429 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
2430 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
2431 * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
2432 * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
2433 * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
2434 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
2435 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
2436 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
2437 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
2438 * @arg @ref LL_TIM_DMABURST_BASEADDR_OR
2439 * @param DMABurstLength This parameter can be one of the following values:
2440 * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
2441 * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
2442 * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
2443 * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
2444 * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
2445 * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
2446 * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
2447 * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
2448 * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
2449 * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
2450 * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
2451 * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
2452 * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
2453 * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
2454 * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
2455 * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
2456 * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
2457 * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
2458 * @retval None
2459 */
LL_TIM_ConfigDMABurst(TIM_TypeDef * TIMx,uint32_t DMABurstBaseAddress,uint32_t DMABurstLength)2460 __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
2461 {
2462 MODIFY_REG(TIMx->DCR, TIM_DCR_DBL | TIM_DCR_DBA, DMABurstBaseAddress | DMABurstLength);
2463 }
2464
2465 /**
2466 * @}
2467 */
2468
2469 /** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
2470 * @{
2471 */
2472 /**
2473 * @brief Remap TIM inputs (input channel, internal/external triggers).
2474 * @note Macro @ref IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
2475 * a some timer inputs can be remapped.
2476 * @rmtoll TIM2_OR ITR1_RMP LL_TIM_SetRemap\n
2477 * TIM3_OR ITR2_RMP LL_TIM_SetRemap\n
2478 * TIM9_OR TI1_RMP LL_TIM_SetRemap\n
2479 * TIM9_OR ITR1_RMP LL_TIM_SetRemap\n
2480 * TIM10_OR TI1_RMP LL_TIM_SetRemap\n
2481 * TIM10_OR ETR_RMP LL_TIM_SetRemap\n
2482 * TIM10_OR TI1_RMP_RI LL_TIM_SetRemap\n
2483 * TIM11_OR TI1_RMP LL_TIM_SetRemap\n
2484 * TIM11_OR ETR_RMP LL_TIM_SetRemap\n
2485 * TIM11_OR TI1_RMP_RI LL_TIM_SetRemap
2486 * @param TIMx Timer instance
2487 * @param Remap Remap params depends on the TIMx. Description available only
2488 * in CHM version of the User Manual (not in .pdf).
2489 * Otherwise see Reference Manual description of OR registers.
2490 *
2491 * Below description summarizes "Timer Instance" and "Remap" param combinations:
2492 *
2493 * TIM2: any combination of ITR1_RMP where
2494 *
2495 * . . ITR1_RMP can be one of the following values
2496 * @arg @ref LL_TIM_TIM2_TIR1_RMP_TIM10_OC (**)
2497 * @arg @ref LL_TIM_TIM2_TIR1_RMP_TIM5_TGO (**)
2498 *
2499 * TIM3: any combination of ITR2_RMP where
2500 *
2501 * . . ITR2_RMP can be one of the following values
2502 * @arg @ref LL_TIM_TIM3_TIR2_RMP_TIM11_OC (**)
2503 * @arg @ref LL_TIM_TIM3_TIR2_RMP_TIM5_TGO (**)
2504 *
2505 * TIM9: any combination of TI1_RMP, ITR1_RMP where
2506 *
2507 * . . TI1_RMP can be one of the following values
2508 * @arg @ref LL_TIM_TIM9_TI1_RMP_LSE
2509 * @arg @ref LL_TIM_TIM9_TI1_RMP_GPIO
2510 *
2511 * . . ITR1_RMP can be one of the following values
2512 * @arg @ref LL_TIM_TIM9_ITR1_RMP_TIM3_TGO (*)
2513 * @arg @ref LL_TIM_TIM9_ITR1_RMP_TOUCH_IO (*)
2514 *
2515 *
2516 * TIM10: any combination of TI1_RMP, ETR_RMP, TI1_RMP_RI where
2517 *
2518 * . . TI1_RMP can be one of the following values
2519 * @arg @ref LL_TIM_TIM10_TI1_RMP_GPIO
2520 * @arg @ref LL_TIM_TIM10_TI1_RMP_LSI
2521 * @arg @ref LL_TIM_TIM10_TI1_RMP_LSE
2522 * @arg @ref LL_TIM_TIM10_TI1_RMP_RTC
2523 *
2524 * . . ETR_RMP can be one of the following values
2525 * @arg @ref LL_TIM_TIM10_ETR_RMP_TIM9_TGO (*)
2526 *
2527 * . . TI1_RMP_RI can be one of the following values
2528 * @arg @ref LL_TIM_TIM10_TI1_RMP_RI (*)
2529 *
2530 *
2531 * TIM11: any combination of TI1_RMP, ETR_RMP, TI1_RMP_RI where
2532 *
2533 * . . TI1_RMP can be one of the following values
2534 * @arg @ref LL_TIM_TIM11_TI1_RMP_MSI
2535 * @arg @ref LL_TIM_TIM11_TI1_RMP_HSE_RTC
2536 * @arg @ref LL_TIM_TIM11_TI1_RMP
2537 *
2538 * . . ETR_RMP can be one of the following values
2539 * @arg @ref LL_TIM_TIM11_ETR_RMP_TIM9_TGO (*)
2540 *
2541 * . . TI1_RMP_RI can be one of the following values
2542 * @arg @ref LL_TIM_TIM11_TI1_RMP_RI (*)
2543 *
2544 * (*) value not available in all devices categories
2545 * (**) register not available in all devices categories
2546 *
2547 * @note Option registers are available only for cat.3, cat.4 and cat.5 devices
2548 * @retval None
2549 */
LL_TIM_SetRemap(TIM_TypeDef * TIMx,uint32_t Remap)2550 __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
2551 {
2552 MODIFY_REG(TIMx->OR, (Remap >> TIMx_OR_RMP_SHIFT), (Remap & TIMx_OR_RMP_MASK));
2553 }
2554
2555 /**
2556 * @}
2557 */
2558
2559 /** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management
2560 * @{
2561 */
2562 /**
2563 * @brief Set the OCREF clear source
2564 * @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT
2565 * @note This function can only be used in Output compare and PWM modes.
2566 * @note the ETR signal can be connected to the output of a comparator to be used for current handling
2567 * @rmtoll SMCR OCCS LL_TIM_SetOCRefClearInputSource
2568 * @param TIMx Timer instance
2569 * @param OCRefClearInputSource This parameter can be one of the following values:
2570 * @arg @ref LL_TIM_OCREF_CLR_INT_OCREF_CLR
2571 * @arg @ref LL_TIM_OCREF_CLR_INT_ETR
2572 * @retval None
2573 */
LL_TIM_SetOCRefClearInputSource(TIM_TypeDef * TIMx,uint32_t OCRefClearInputSource)2574 __STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource)
2575 {
2576 MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS, OCRefClearInputSource);
2577 }
2578 /**
2579 * @}
2580 */
2581
2582 /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
2583 * @{
2584 */
2585 /**
2586 * @brief Clear the update interrupt flag (UIF).
2587 * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
2588 * @param TIMx Timer instance
2589 * @retval None
2590 */
LL_TIM_ClearFlag_UPDATE(TIM_TypeDef * TIMx)2591 __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
2592 {
2593 WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
2594 }
2595
2596 /**
2597 * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
2598 * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
2599 * @param TIMx Timer instance
2600 * @retval State of bit (1 or 0).
2601 */
LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef * TIMx)2602 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx)
2603 {
2604 return (READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF));
2605 }
2606
2607 /**
2608 * @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
2609 * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
2610 * @param TIMx Timer instance
2611 * @retval None
2612 */
LL_TIM_ClearFlag_CC1(TIM_TypeDef * TIMx)2613 __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
2614 {
2615 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
2616 }
2617
2618 /**
2619 * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
2620 * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
2621 * @param TIMx Timer instance
2622 * @retval State of bit (1 or 0).
2623 */
LL_TIM_IsActiveFlag_CC1(TIM_TypeDef * TIMx)2624 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx)
2625 {
2626 return (READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF));
2627 }
2628
2629 /**
2630 * @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
2631 * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
2632 * @param TIMx Timer instance
2633 * @retval None
2634 */
LL_TIM_ClearFlag_CC2(TIM_TypeDef * TIMx)2635 __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
2636 {
2637 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
2638 }
2639
2640 /**
2641 * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
2642 * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
2643 * @param TIMx Timer instance
2644 * @retval State of bit (1 or 0).
2645 */
LL_TIM_IsActiveFlag_CC2(TIM_TypeDef * TIMx)2646 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx)
2647 {
2648 return (READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF));
2649 }
2650
2651 /**
2652 * @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
2653 * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
2654 * @param TIMx Timer instance
2655 * @retval None
2656 */
LL_TIM_ClearFlag_CC3(TIM_TypeDef * TIMx)2657 __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
2658 {
2659 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
2660 }
2661
2662 /**
2663 * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
2664 * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
2665 * @param TIMx Timer instance
2666 * @retval State of bit (1 or 0).
2667 */
LL_TIM_IsActiveFlag_CC3(TIM_TypeDef * TIMx)2668 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx)
2669 {
2670 return (READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF));
2671 }
2672
2673 /**
2674 * @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
2675 * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
2676 * @param TIMx Timer instance
2677 * @retval None
2678 */
LL_TIM_ClearFlag_CC4(TIM_TypeDef * TIMx)2679 __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
2680 {
2681 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
2682 }
2683
2684 /**
2685 * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
2686 * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
2687 * @param TIMx Timer instance
2688 * @retval State of bit (1 or 0).
2689 */
LL_TIM_IsActiveFlag_CC4(TIM_TypeDef * TIMx)2690 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx)
2691 {
2692 return (READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF));
2693 }
2694
2695 /**
2696 * @brief Clear the trigger interrupt flag (TIF).
2697 * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
2698 * @param TIMx Timer instance
2699 * @retval None
2700 */
LL_TIM_ClearFlag_TRIG(TIM_TypeDef * TIMx)2701 __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
2702 {
2703 WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
2704 }
2705
2706 /**
2707 * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
2708 * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
2709 * @param TIMx Timer instance
2710 * @retval State of bit (1 or 0).
2711 */
LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef * TIMx)2712 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx)
2713 {
2714 return (READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF));
2715 }
2716
2717 /**
2718 * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
2719 * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
2720 * @param TIMx Timer instance
2721 * @retval None
2722 */
LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef * TIMx)2723 __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
2724 {
2725 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
2726 }
2727
2728 /**
2729 * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending).
2730 * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
2731 * @param TIMx Timer instance
2732 * @retval State of bit (1 or 0).
2733 */
LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef * TIMx)2734 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx)
2735 {
2736 return (READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF));
2737 }
2738
2739 /**
2740 * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
2741 * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
2742 * @param TIMx Timer instance
2743 * @retval None
2744 */
LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef * TIMx)2745 __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
2746 {
2747 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
2748 }
2749
2750 /**
2751 * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending).
2752 * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
2753 * @param TIMx Timer instance
2754 * @retval State of bit (1 or 0).
2755 */
LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef * TIMx)2756 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx)
2757 {
2758 return (READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF));
2759 }
2760
2761 /**
2762 * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
2763 * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
2764 * @param TIMx Timer instance
2765 * @retval None
2766 */
LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef * TIMx)2767 __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
2768 {
2769 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
2770 }
2771
2772 /**
2773 * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending).
2774 * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
2775 * @param TIMx Timer instance
2776 * @retval State of bit (1 or 0).
2777 */
LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef * TIMx)2778 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx)
2779 {
2780 return (READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF));
2781 }
2782
2783 /**
2784 * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
2785 * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
2786 * @param TIMx Timer instance
2787 * @retval None
2788 */
LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef * TIMx)2789 __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
2790 {
2791 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
2792 }
2793
2794 /**
2795 * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending).
2796 * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
2797 * @param TIMx Timer instance
2798 * @retval State of bit (1 or 0).
2799 */
LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef * TIMx)2800 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx)
2801 {
2802 return (READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF));
2803 }
2804
2805 /**
2806 * @}
2807 */
2808
2809 /** @defgroup TIM_LL_EF_IT_Management IT-Management
2810 * @{
2811 */
2812 /**
2813 * @brief Enable update interrupt (UIE).
2814 * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
2815 * @param TIMx Timer instance
2816 * @retval None
2817 */
LL_TIM_EnableIT_UPDATE(TIM_TypeDef * TIMx)2818 __STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
2819 {
2820 SET_BIT(TIMx->DIER, TIM_DIER_UIE);
2821 }
2822
2823 /**
2824 * @brief Disable update interrupt (UIE).
2825 * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
2826 * @param TIMx Timer instance
2827 * @retval None
2828 */
LL_TIM_DisableIT_UPDATE(TIM_TypeDef * TIMx)2829 __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
2830 {
2831 CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
2832 }
2833
2834 /**
2835 * @brief Indicates whether the update interrupt (UIE) is enabled.
2836 * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
2837 * @param TIMx Timer instance
2838 * @retval State of bit (1 or 0).
2839 */
LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef * TIMx)2840 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx)
2841 {
2842 return (READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE));
2843 }
2844
2845 /**
2846 * @brief Enable capture/compare 1 interrupt (CC1IE).
2847 * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
2848 * @param TIMx Timer instance
2849 * @retval None
2850 */
LL_TIM_EnableIT_CC1(TIM_TypeDef * TIMx)2851 __STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
2852 {
2853 SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
2854 }
2855
2856 /**
2857 * @brief Disable capture/compare 1 interrupt (CC1IE).
2858 * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
2859 * @param TIMx Timer instance
2860 * @retval None
2861 */
LL_TIM_DisableIT_CC1(TIM_TypeDef * TIMx)2862 __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
2863 {
2864 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
2865 }
2866
2867 /**
2868 * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
2869 * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
2870 * @param TIMx Timer instance
2871 * @retval State of bit (1 or 0).
2872 */
LL_TIM_IsEnabledIT_CC1(TIM_TypeDef * TIMx)2873 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx)
2874 {
2875 return (READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE));
2876 }
2877
2878 /**
2879 * @brief Enable capture/compare 2 interrupt (CC2IE).
2880 * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
2881 * @param TIMx Timer instance
2882 * @retval None
2883 */
LL_TIM_EnableIT_CC2(TIM_TypeDef * TIMx)2884 __STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
2885 {
2886 SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
2887 }
2888
2889 /**
2890 * @brief Disable capture/compare 2 interrupt (CC2IE).
2891 * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
2892 * @param TIMx Timer instance
2893 * @retval None
2894 */
LL_TIM_DisableIT_CC2(TIM_TypeDef * TIMx)2895 __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
2896 {
2897 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
2898 }
2899
2900 /**
2901 * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
2902 * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
2903 * @param TIMx Timer instance
2904 * @retval State of bit (1 or 0).
2905 */
LL_TIM_IsEnabledIT_CC2(TIM_TypeDef * TIMx)2906 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx)
2907 {
2908 return (READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE));
2909 }
2910
2911 /**
2912 * @brief Enable capture/compare 3 interrupt (CC3IE).
2913 * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
2914 * @param TIMx Timer instance
2915 * @retval None
2916 */
LL_TIM_EnableIT_CC3(TIM_TypeDef * TIMx)2917 __STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
2918 {
2919 SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
2920 }
2921
2922 /**
2923 * @brief Disable capture/compare 3 interrupt (CC3IE).
2924 * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
2925 * @param TIMx Timer instance
2926 * @retval None
2927 */
LL_TIM_DisableIT_CC3(TIM_TypeDef * TIMx)2928 __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
2929 {
2930 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
2931 }
2932
2933 /**
2934 * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
2935 * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
2936 * @param TIMx Timer instance
2937 * @retval State of bit (1 or 0).
2938 */
LL_TIM_IsEnabledIT_CC3(TIM_TypeDef * TIMx)2939 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx)
2940 {
2941 return (READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE));
2942 }
2943
2944 /**
2945 * @brief Enable capture/compare 4 interrupt (CC4IE).
2946 * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
2947 * @param TIMx Timer instance
2948 * @retval None
2949 */
LL_TIM_EnableIT_CC4(TIM_TypeDef * TIMx)2950 __STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
2951 {
2952 SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
2953 }
2954
2955 /**
2956 * @brief Disable capture/compare 4 interrupt (CC4IE).
2957 * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
2958 * @param TIMx Timer instance
2959 * @retval None
2960 */
LL_TIM_DisableIT_CC4(TIM_TypeDef * TIMx)2961 __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
2962 {
2963 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
2964 }
2965
2966 /**
2967 * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
2968 * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
2969 * @param TIMx Timer instance
2970 * @retval State of bit (1 or 0).
2971 */
LL_TIM_IsEnabledIT_CC4(TIM_TypeDef * TIMx)2972 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx)
2973 {
2974 return (READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE));
2975 }
2976
2977 /**
2978 * @brief Enable trigger interrupt (TIE).
2979 * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
2980 * @param TIMx Timer instance
2981 * @retval None
2982 */
LL_TIM_EnableIT_TRIG(TIM_TypeDef * TIMx)2983 __STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
2984 {
2985 SET_BIT(TIMx->DIER, TIM_DIER_TIE);
2986 }
2987
2988 /**
2989 * @brief Disable trigger interrupt (TIE).
2990 * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
2991 * @param TIMx Timer instance
2992 * @retval None
2993 */
LL_TIM_DisableIT_TRIG(TIM_TypeDef * TIMx)2994 __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
2995 {
2996 CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
2997 }
2998
2999 /**
3000 * @brief Indicates whether the trigger interrupt (TIE) is enabled.
3001 * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
3002 * @param TIMx Timer instance
3003 * @retval State of bit (1 or 0).
3004 */
LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef * TIMx)3005 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx)
3006 {
3007 return (READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE));
3008 }
3009
3010 /**
3011 * @}
3012 */
3013
3014 /** @defgroup TIM_LL_EF_DMA_Management DMA-Management
3015 * @{
3016 */
3017 /**
3018 * @brief Enable update DMA request (UDE).
3019 * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
3020 * @param TIMx Timer instance
3021 * @retval None
3022 */
LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef * TIMx)3023 __STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
3024 {
3025 SET_BIT(TIMx->DIER, TIM_DIER_UDE);
3026 }
3027
3028 /**
3029 * @brief Disable update DMA request (UDE).
3030 * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
3031 * @param TIMx Timer instance
3032 * @retval None
3033 */
LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef * TIMx)3034 __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
3035 {
3036 CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
3037 }
3038
3039 /**
3040 * @brief Indicates whether the update DMA request (UDE) is enabled.
3041 * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
3042 * @param TIMx Timer instance
3043 * @retval State of bit (1 or 0).
3044 */
LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef * TIMx)3045 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx)
3046 {
3047 return (READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE));
3048 }
3049
3050 /**
3051 * @brief Enable capture/compare 1 DMA request (CC1DE).
3052 * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
3053 * @param TIMx Timer instance
3054 * @retval None
3055 */
LL_TIM_EnableDMAReq_CC1(TIM_TypeDef * TIMx)3056 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
3057 {
3058 SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
3059 }
3060
3061 /**
3062 * @brief Disable capture/compare 1 DMA request (CC1DE).
3063 * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
3064 * @param TIMx Timer instance
3065 * @retval None
3066 */
LL_TIM_DisableDMAReq_CC1(TIM_TypeDef * TIMx)3067 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
3068 {
3069 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
3070 }
3071
3072 /**
3073 * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
3074 * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
3075 * @param TIMx Timer instance
3076 * @retval State of bit (1 or 0).
3077 */
LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef * TIMx)3078 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx)
3079 {
3080 return (READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE));
3081 }
3082
3083 /**
3084 * @brief Enable capture/compare 2 DMA request (CC2DE).
3085 * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
3086 * @param TIMx Timer instance
3087 * @retval None
3088 */
LL_TIM_EnableDMAReq_CC2(TIM_TypeDef * TIMx)3089 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
3090 {
3091 SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
3092 }
3093
3094 /**
3095 * @brief Disable capture/compare 2 DMA request (CC2DE).
3096 * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
3097 * @param TIMx Timer instance
3098 * @retval None
3099 */
LL_TIM_DisableDMAReq_CC2(TIM_TypeDef * TIMx)3100 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
3101 {
3102 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
3103 }
3104
3105 /**
3106 * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
3107 * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
3108 * @param TIMx Timer instance
3109 * @retval State of bit (1 or 0).
3110 */
LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef * TIMx)3111 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx)
3112 {
3113 return (READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE));
3114 }
3115
3116 /**
3117 * @brief Enable capture/compare 3 DMA request (CC3DE).
3118 * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
3119 * @param TIMx Timer instance
3120 * @retval None
3121 */
LL_TIM_EnableDMAReq_CC3(TIM_TypeDef * TIMx)3122 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
3123 {
3124 SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
3125 }
3126
3127 /**
3128 * @brief Disable capture/compare 3 DMA request (CC3DE).
3129 * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
3130 * @param TIMx Timer instance
3131 * @retval None
3132 */
LL_TIM_DisableDMAReq_CC3(TIM_TypeDef * TIMx)3133 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
3134 {
3135 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
3136 }
3137
3138 /**
3139 * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
3140 * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
3141 * @param TIMx Timer instance
3142 * @retval State of bit (1 or 0).
3143 */
LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef * TIMx)3144 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx)
3145 {
3146 return (READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE));
3147 }
3148
3149 /**
3150 * @brief Enable capture/compare 4 DMA request (CC4DE).
3151 * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
3152 * @param TIMx Timer instance
3153 * @retval None
3154 */
LL_TIM_EnableDMAReq_CC4(TIM_TypeDef * TIMx)3155 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
3156 {
3157 SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
3158 }
3159
3160 /**
3161 * @brief Disable capture/compare 4 DMA request (CC4DE).
3162 * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
3163 * @param TIMx Timer instance
3164 * @retval None
3165 */
LL_TIM_DisableDMAReq_CC4(TIM_TypeDef * TIMx)3166 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
3167 {
3168 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
3169 }
3170
3171 /**
3172 * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
3173 * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
3174 * @param TIMx Timer instance
3175 * @retval State of bit (1 or 0).
3176 */
LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef * TIMx)3177 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx)
3178 {
3179 return (READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE));
3180 }
3181
3182 /**
3183 * @brief Enable trigger interrupt (TDE).
3184 * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
3185 * @param TIMx Timer instance
3186 * @retval None
3187 */
LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef * TIMx)3188 __STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
3189 {
3190 SET_BIT(TIMx->DIER, TIM_DIER_TDE);
3191 }
3192
3193 /**
3194 * @brief Disable trigger interrupt (TDE).
3195 * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
3196 * @param TIMx Timer instance
3197 * @retval None
3198 */
LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef * TIMx)3199 __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
3200 {
3201 CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
3202 }
3203
3204 /**
3205 * @brief Indicates whether the trigger interrupt (TDE) is enabled.
3206 * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
3207 * @param TIMx Timer instance
3208 * @retval State of bit (1 or 0).
3209 */
LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef * TIMx)3210 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx)
3211 {
3212 return (READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE));
3213 }
3214
3215 /**
3216 * @}
3217 */
3218
3219 /** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
3220 * @{
3221 */
3222 /**
3223 * @brief Generate an update event.
3224 * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
3225 * @param TIMx Timer instance
3226 * @retval None
3227 */
LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef * TIMx)3228 __STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
3229 {
3230 SET_BIT(TIMx->EGR, TIM_EGR_UG);
3231 }
3232
3233 /**
3234 * @brief Generate Capture/Compare 1 event.
3235 * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
3236 * @param TIMx Timer instance
3237 * @retval None
3238 */
LL_TIM_GenerateEvent_CC1(TIM_TypeDef * TIMx)3239 __STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
3240 {
3241 SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
3242 }
3243
3244 /**
3245 * @brief Generate Capture/Compare 2 event.
3246 * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
3247 * @param TIMx Timer instance
3248 * @retval None
3249 */
LL_TIM_GenerateEvent_CC2(TIM_TypeDef * TIMx)3250 __STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
3251 {
3252 SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
3253 }
3254
3255 /**
3256 * @brief Generate Capture/Compare 3 event.
3257 * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
3258 * @param TIMx Timer instance
3259 * @retval None
3260 */
LL_TIM_GenerateEvent_CC3(TIM_TypeDef * TIMx)3261 __STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
3262 {
3263 SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
3264 }
3265
3266 /**
3267 * @brief Generate Capture/Compare 4 event.
3268 * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
3269 * @param TIMx Timer instance
3270 * @retval None
3271 */
LL_TIM_GenerateEvent_CC4(TIM_TypeDef * TIMx)3272 __STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
3273 {
3274 SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
3275 }
3276
3277 /**
3278 * @brief Generate trigger event.
3279 * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
3280 * @param TIMx Timer instance
3281 * @retval None
3282 */
LL_TIM_GenerateEvent_TRIG(TIM_TypeDef * TIMx)3283 __STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
3284 {
3285 SET_BIT(TIMx->EGR, TIM_EGR_TG);
3286 }
3287
3288 /**
3289 * @}
3290 */
3291
3292 #if defined(USE_FULL_LL_DRIVER)
3293 /** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
3294 * @{
3295 */
3296
3297 ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);
3298 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
3299 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct);
3300 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
3301 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
3302 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
3303 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
3304 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
3305 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
3306 /**
3307 * @}
3308 */
3309 #endif /* USE_FULL_LL_DRIVER */
3310
3311 /**
3312 * @}
3313 */
3314
3315 /**
3316 * @}
3317 */
3318
3319 #endif /* TIM2 || TIM3 || TIM4 || TIM5 || TIM9 || TIM10 || TIM11 TIM6 || TIM7 */
3320
3321 /**
3322 * @}
3323 */
3324
3325 #ifdef __cplusplus
3326 }
3327 #endif
3328
3329 #endif /* __STM32L1xx_LL_TIM_H */
3330
3331 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
3332