1 /** 2 ****************************************************************************** 3 * @file stm32l1xx_hal_adc.h 4 * @author MCD Application Team 5 * @version V1.2.0 6 * @date 01-July-2016 7 * @brief Header file containing functions prototypes of ADC HAL library. 8 ****************************************************************************** 9 * @attention 10 * 11 * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> 12 * 13 * Redistribution and use in source and binary forms, with or without modification, 14 * are permitted provided that the following conditions are met: 15 * 1. Redistributions of source code must retain the above copyright notice, 16 * this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright notice, 18 * this list of conditions and the following disclaimer in the documentation 19 * and/or other materials provided with the distribution. 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 ****************************************************************************** 36 */ 37 38 /* Define to prevent recursive inclusion -------------------------------------*/ 39 #ifndef __STM32L1xx_HAL_ADC_H 40 #define __STM32L1xx_HAL_ADC_H 41 42 #ifdef __cplusplus 43 extern "C" { 44 #endif 45 46 /* Includes ------------------------------------------------------------------*/ 47 #include "stm32l1xx_hal_def.h" 48 49 /** @addtogroup STM32L1xx_HAL_Driver 50 * @{ 51 */ 52 53 /** @addtogroup ADC 54 * @{ 55 */ 56 57 /* Exported types ------------------------------------------------------------*/ 58 /** @defgroup ADC_Exported_Types ADC Exported Types 59 * @{ 60 */ 61 62 /** 63 * @brief Structure definition of ADC and regular group initialization 64 * @note Parameters of this structure are shared within 2 scopes: 65 * - Scope entire ADC (affects regular and injected groups): ClockPrescaler, Resolution, ScanConvMode, DataAlign, ScanConvMode, EOCSelection, LowPowerAutoWait, LowPowerAutoPowerOff, ChannelsBank. 66 * - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv. 67 * @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state. 68 * ADC state can be either: 69 * - For all parameters: ADC disabled 70 * - For all parameters except 'Resolution', 'ScanConvMode', 'LowPowerAutoWait', 'LowPowerAutoPowerOff', 'DiscontinuousConvMode', 'NbrOfDiscConversion' : ADC enabled without conversion on going on regular group. 71 * - For parameters 'ExternalTrigConv' and 'ExternalTrigConvEdge': ADC enabled, even with conversion on going. 72 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed 73 * without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fullfills the ADC state condition) on the fly). 74 */ 75 typedef struct 76 { 77 uint32_t ClockPrescaler; /*!< Select ADC clock source (asynchronous clock derived from HSI RC oscillator) and clock prescaler. 78 This parameter can be a value of @ref ADC_ClockPrescaler 79 Note: In case of usage of channels on injected group, ADC frequency should be lower than AHB clock frequency /4 for resolution 12 or 10 bits, 80 AHB clock frequency /3 for resolution 8 bits, AHB clock frequency /2 for resolution 6 bits. 81 Note: HSI RC oscillator must be preliminarily enabled at RCC top level. */ 82 uint32_t Resolution; /*!< Configures the ADC resolution. 83 This parameter can be a value of @ref ADC_Resolution */ 84 uint32_t DataAlign; /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting) 85 or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3). 86 This parameter can be a value of @ref ADC_Data_align */ 87 uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups. 88 This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts. 89 If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1). 90 Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1). 91 If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank). 92 Scan direction is upward: from rank1 to rank 'n'. 93 This parameter can be a value of @ref ADC_Scan_mode */ 94 uint32_t EOCSelection; /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence. 95 This parameter can be a value of @ref ADC_EOCSelection. 96 Note: For injected group, end of conversion (flag&IT) is raised only at the end of the sequence. 97 Therefore, if end of conversion is set to end of each conversion, injected group should not be used with interruption (HAL_ADCEx_InjectedStart_IT) 98 or polling (HAL_ADCEx_InjectedStart and HAL_ADCEx_InjectedPollForConversion). By the way, polling is still possible since driver will use an estimated timing for end of injected conversion. 99 Note: If overrun feature is intended to be used, use ADC in mode 'interruption' (function HAL_ADC_Start_IT() ) with parameter EOCSelection set to end of each conversion or in mode 'transfer by DMA' (function HAL_ADC_Start_DMA()). 100 If overrun feature is intended to be bypassed, use ADC in mode 'polling' or 'interruption' with parameter EOCSelection must be set to end of sequence */ 101 uint32_t LowPowerAutoWait; /*!< Selects the dynamic low power Auto Delay: new conversion start only when the previous 102 conversion (for regular group) or previous sequence (for injected group) has been treated by user software, using function HAL_ADC_GetValue() or HAL_ADCEx_InjectedGetValue(). 103 This feature automatically adapts the speed of ADC to the speed of the system that reads the data. Moreover, this avoids risk of overrun for low frequency applications. 104 This parameter can be a value of @ref ADC_LowPowerAutoWait. 105 Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since they have to clear immediately the EOC flag to free the IRQ vector sequencer. 106 Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when conversion data is needed: use HAL_ADC_PollForConversion() to ensure that conversion is completed 107 and use HAL_ADC_GetValue() to retrieve conversion result and trig another conversion (in case of usage of injected group, use the equivalent functions HAL_ADCExInjected_Start(), HAL_ADCEx_InjectedGetValue(), ...). 108 Note: ADC clock latency and some timing constraints depending on clock prescaler have to be taken into account: refer to reference manual (register ADC_CR2 bit DELS description). */ 109 uint32_t LowPowerAutoPowerOff; /*!< Selects the auto-off mode: the ADC automatically powers-off after a conversion and automatically wakes-up when a new conversion is triggered (with startup time between trigger and start of sampling). 110 This feature can be combined with automatic wait mode (parameter 'LowPowerAutoWait'). 111 This parameter can be a value of @ref ADC_LowPowerAutoPowerOff. */ 112 uint32_t ChannelsBank; /*!< Selects the ADC channels bank. 113 This parameter can be a value of @ref ADC_ChannelsBank. 114 Note: Banks availability depends on devices categories. 115 Note: To change bank selection on the fly, without going through execution of 'HAL_ADC_Init()', macro '__HAL_ADC_CHANNELS_BANK()' can be used directly. */ 116 uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group, 117 after the selected trigger occurred (software start or external trigger). 118 This parameter can be set to ENABLE or DISABLE. */ 119 #if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) 120 uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer. 121 To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. 122 This parameter must be a number between Min_Data = 1 and Max_Data = 28. */ 123 #else 124 uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer. 125 To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. 126 This parameter must be a number between Min_Data = 1 and Max_Data = 27. */ 127 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 128 uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). 129 Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. 130 Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. 131 This parameter can be set to ENABLE or DISABLE. */ 132 uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of regular group (parameter NbrOfConversion) will be subdivided. 133 If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded. 134 This parameter must be a number between Min_Data = 1 and Max_Data = 8. */ 135 uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group. 136 If set to ADC_SOFTWARE_START, external triggers are disabled. 137 If set to external trigger source, triggering is on event rising edge by default. 138 This parameter can be a value of @ref ADC_External_trigger_source_Regular */ 139 uint32_t ExternalTrigConvEdge; /*!< Selects the external trigger edge of regular group. 140 If trigger is set to ADC_SOFTWARE_START, this parameter is discarded. 141 This parameter can be a value of @ref ADC_External_trigger_edge_Regular */ 142 uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached) 143 or in Continuous mode (DMA transfer unlimited, whatever number of conversions). 144 Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. 145 Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). 146 This parameter can be set to ENABLE or DISABLE. */ 147 }ADC_InitTypeDef; 148 149 /** 150 * @brief Structure definition of ADC channel for regular group 151 * @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state. 152 * ADC can be either disabled or enabled without conversion on going on regular group. 153 */ 154 typedef struct 155 { 156 uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group. 157 This parameter can be a value of @ref ADC_channels 158 Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. 159 Maximum number of channels by device category (without taking in account each device package constraints): 160 STM32L1 category 1, 2: 24 channels on external pins + 3 channels on internal measurement paths (VrefInt, Temp sensor, Vcomp): Channel 0 to channel 26. 161 STM32L1 category 3: 25 channels on external pins + 3 channels on internal measurement paths (VrefInt, Temp sensor, Vcomp): Channel 0 to channel 26, 1 additional channel in bank B. Note: OPAMP1 and OPAMP2 are connected internally but not increasing internal channels number: they are sharing ADC input with external channels ADC_IN3 and ADC_IN8. 162 STM32L1 category 4, 5: 40 channels on external pins + 3 channels on internal measurement paths (VrefInt, Temp sensor, Vcomp): Channel 0 to channel 31, 11 additional channels in bank B. Note: OPAMP1 and OPAMP2 are connected internally but not increasing internal channels number: they are sharing ADC input with external channels ADC_IN3 and ADC_IN8. 163 Note: In case of peripherals OPAMPx not used: 3 channels (3, 8, 13) can be configured as direct channels (fast channels). Refer to macro ' __HAL_ADC_CHANNEL_SPEED_FAST() '. 164 Note: In case of peripheral OPAMP3 and ADC channel OPAMP3 used (OPAMP3 available on STM32L1 devices Cat.4 only): the analog switch COMP1_SW1 must be closed. Refer to macro: ' __HAL_OPAMP_OPAMP3OUT_CONNECT_ADC_COMP1() '. */ 165 uint32_t Rank; /*!< Specifies the rank in the regular group sequencer. 166 This parameter can be a value of @ref ADC_regular_rank 167 Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */ 168 uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel. 169 Unit: ADC clock cycles 170 Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits). 171 This parameter can be a value of @ref ADC_sampling_times 172 Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups. 173 If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting. 174 Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), 175 sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) 176 Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */ 177 }ADC_ChannelConfTypeDef; 178 179 /** 180 * @brief ADC Configuration analog watchdog definition 181 * @note The setting of these parameters with function is conditioned to ADC state. 182 * ADC state can be either disabled or enabled without conversion on going on regular and injected groups. 183 */ 184 typedef struct 185 { 186 uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode: single/all channels, regular/injected group. 187 This parameter can be a value of @ref ADC_analog_watchdog_mode. */ 188 uint32_t Channel; /*!< Selects which ADC channel to monitor by analog watchdog. 189 This parameter has an effect only if watchdog mode is configured on single channel (parameter WatchdogMode) 190 This parameter can be a value of @ref ADC_channels. */ 191 uint32_t ITMode; /*!< Specifies whether the analog watchdog is configured in interrupt or polling mode. 192 This parameter can be set to ENABLE or DISABLE */ 193 uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value. 194 This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */ 195 uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value. 196 This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */ 197 uint32_t WatchdogNumber; /*!< Reserved for future use, can be set to 0 */ 198 }ADC_AnalogWDGConfTypeDef; 199 200 /** 201 * @brief HAL ADC state machine: ADC states definition (bitfields) 202 */ 203 /* States of ADC global scope */ 204 #define HAL_ADC_STATE_RESET ((uint32_t)0x00000000) /*!< ADC not yet initialized or disabled */ 205 #define HAL_ADC_STATE_READY ((uint32_t)0x00000001) /*!< ADC peripheral ready for use */ 206 #define HAL_ADC_STATE_BUSY_INTERNAL ((uint32_t)0x00000002) /*!< ADC is busy to internal process (initialization, calibration) */ 207 #define HAL_ADC_STATE_TIMEOUT ((uint32_t)0x00000004) /*!< TimeOut occurrence */ 208 209 /* States of ADC errors */ 210 #define HAL_ADC_STATE_ERROR_INTERNAL ((uint32_t)0x00000010) /*!< Internal error occurrence */ 211 #define HAL_ADC_STATE_ERROR_CONFIG ((uint32_t)0x00000020) /*!< Configuration error occurrence */ 212 #define HAL_ADC_STATE_ERROR_DMA ((uint32_t)0x00000040) /*!< DMA error occurrence */ 213 214 /* States of ADC group regular */ 215 #define HAL_ADC_STATE_REG_BUSY ((uint32_t)0x00000100) /*!< A conversion on group regular is ongoing or can occur (either by continuous mode, 216 external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ 217 #define HAL_ADC_STATE_REG_EOC ((uint32_t)0x00000200) /*!< Conversion data available on group regular */ 218 #define HAL_ADC_STATE_REG_OVR ((uint32_t)0x00000400) /*!< Overrun occurrence */ 219 #define HAL_ADC_STATE_REG_EOSMP ((uint32_t)0x00000800) /*!< Not available on STM32L1 device: End Of Sampling flag raised */ 220 221 /* States of ADC group injected */ 222 #define HAL_ADC_STATE_INJ_BUSY ((uint32_t)0x00001000) /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode, 223 external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ 224 #define HAL_ADC_STATE_INJ_EOC ((uint32_t)0x00002000) /*!< Conversion data available on group injected */ 225 #define HAL_ADC_STATE_INJ_JQOVF ((uint32_t)0x00004000) /*!< Not available on STM32L1 device: Injected queue overflow occurrence */ 226 227 /* States of ADC analog watchdogs */ 228 #define HAL_ADC_STATE_AWD1 ((uint32_t)0x00010000) /*!< Out-of-window occurrence of analog watchdog 1 */ 229 #define HAL_ADC_STATE_AWD2 ((uint32_t)0x00020000) /*!< Not available on STM32L1 device: Out-of-window occurrence of analog watchdog 2 */ 230 #define HAL_ADC_STATE_AWD3 ((uint32_t)0x00040000) /*!< Not available on STM32L1 device: Out-of-window occurrence of analog watchdog 3 */ 231 232 /* States of ADC multi-mode */ 233 #define HAL_ADC_STATE_MULTIMODE_SLAVE ((uint32_t)0x00100000) /*!< Not available on STM32L1 device: ADC in multimode slave state, controlled by another ADC master ( */ 234 235 236 /** 237 * @brief ADC handle Structure definition 238 */ 239 typedef struct 240 { 241 ADC_TypeDef *Instance; /*!< Register base address */ 242 243 ADC_InitTypeDef Init; /*!< ADC required parameters */ 244 245 __IO uint32_t NbrOfConversionRank ; /*!< ADC conversion rank counter */ 246 247 DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ 248 249 HAL_LockTypeDef Lock; /*!< ADC locking object */ 250 251 __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */ 252 253 __IO uint32_t ErrorCode; /*!< ADC Error code */ 254 }ADC_HandleTypeDef; 255 /** 256 * @} 257 */ 258 259 260 261 /* Exported constants --------------------------------------------------------*/ 262 263 /** @defgroup ADC_Exported_Constants ADC Exported Constants 264 * @{ 265 */ 266 267 /** @defgroup ADC_Error_Code ADC Error Code 268 * @{ 269 */ 270 #define HAL_ADC_ERROR_NONE ((uint32_t)0x00) /*!< No error */ 271 #define HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01) /*!< ADC IP internal error: if problem of clocking, 272 enable/disable, erroneous state */ 273 #define HAL_ADC_ERROR_OVR ((uint32_t)0x02) /*!< Overrun error */ 274 #define HAL_ADC_ERROR_DMA ((uint32_t)0x04) /*!< DMA transfer error */ 275 /** 276 * @} 277 */ 278 279 /** @defgroup ADC_ClockPrescaler ADC ClockPrescaler 280 * @{ 281 */ 282 #define ADC_CLOCK_ASYNC_DIV1 ((uint32_t)0x00000000) /*!< ADC asynchronous clock derived from ADC dedicated HSI without prescaler */ 283 #define ADC_CLOCK_ASYNC_DIV2 ((uint32_t)ADC_CCR_ADCPRE_0) /*!< ADC asynchronous clock derived from ADC dedicated HSI divided by a prescaler of 2 */ 284 #define ADC_CLOCK_ASYNC_DIV4 ((uint32_t)ADC_CCR_ADCPRE_1) /*!< ADC asynchronous clock derived from ADC dedicated HSI divided by a prescaler of 4 */ 285 /** 286 * @} 287 */ 288 289 /** @defgroup ADC_Resolution ADC Resolution 290 * @{ 291 */ 292 #define ADC_RESOLUTION_12B ((uint32_t)0x00000000) /*!< ADC 12-bit resolution */ 293 #define ADC_RESOLUTION_10B ((uint32_t)ADC_CR1_RES_0) /*!< ADC 10-bit resolution */ 294 #define ADC_RESOLUTION_8B ((uint32_t)ADC_CR1_RES_1) /*!< ADC 8-bit resolution */ 295 #define ADC_RESOLUTION_6B ((uint32_t)ADC_CR1_RES) /*!< ADC 6-bit resolution */ 296 /** 297 * @} 298 */ 299 300 /** @defgroup ADC_Data_align ADC Data_align 301 * @{ 302 */ 303 #define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000) 304 #define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN) 305 /** 306 * @} 307 */ 308 309 /** @defgroup ADC_Scan_mode ADC Scan mode 310 * @{ 311 */ 312 #define ADC_SCAN_DISABLE ((uint32_t)0x00000000) 313 #define ADC_SCAN_ENABLE ((uint32_t)ADC_CR1_SCAN) 314 /** 315 * @} 316 */ 317 318 /** @defgroup ADC_External_trigger_edge_Regular ADC external trigger enable for regular group 319 * @{ 320 */ 321 #define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000) 322 #define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTEN_0) 323 #define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CR2_EXTEN_1) 324 #define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_EXTEN) 325 /** 326 * @} 327 */ 328 329 /** @defgroup ADC_External_trigger_source_Regular ADC External trigger source Regular 330 * @{ 331 */ 332 /* List of external triggers with generic trigger name, sorted by trigger */ 333 /* name: */ 334 335 /* External triggers of regular group for ADC1 */ 336 #define ADC_EXTERNALTRIGCONV_T2_CC3 ADC_EXTERNALTRIG_T2_CC3 337 #define ADC_EXTERNALTRIGCONV_T2_CC2 ADC_EXTERNALTRIG_T2_CC2 338 #define ADC_EXTERNALTRIGCONV_T2_TRGO ADC_EXTERNALTRIG_T2_TRGO 339 #define ADC_EXTERNALTRIGCONV_T3_CC1 ADC_EXTERNALTRIG_T3_CC1 340 #define ADC_EXTERNALTRIGCONV_T3_CC3 ADC_EXTERNALTRIG_T3_CC3 341 #define ADC_EXTERNALTRIGCONV_T3_TRGO ADC_EXTERNALTRIG_T3_TRGO 342 #define ADC_EXTERNALTRIGCONV_T4_CC4 ADC_EXTERNALTRIG_T4_CC4 343 #define ADC_EXTERNALTRIGCONV_T4_TRGO ADC_EXTERNALTRIG_T4_TRGO 344 #define ADC_EXTERNALTRIGCONV_T6_TRGO ADC_EXTERNALTRIG_T6_TRGO 345 #define ADC_EXTERNALTRIGCONV_T9_CC2 ADC_EXTERNALTRIG_T9_CC2 346 #define ADC_EXTERNALTRIGCONV_T9_TRGO ADC_EXTERNALTRIG_T9_TRGO 347 #define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC_EXTERNALTRIG_EXT_IT11 348 #define ADC_SOFTWARE_START ((uint32_t)0x00000010) 349 /** 350 * @} 351 */ 352 353 /** @defgroup ADC_EOCSelection ADC EOCSelection 354 * @{ 355 */ 356 #define ADC_EOC_SEQ_CONV ((uint32_t)0x00000000) 357 #define ADC_EOC_SINGLE_CONV ((uint32_t)ADC_CR2_EOCS) 358 /** 359 * @} 360 */ 361 362 /** @defgroup ADC_LowPowerAutoWait ADC LowPowerAutoWait 363 * @{ 364 */ 365 /*!< Note : For compatibility with other STM32 devices with ADC autowait */ 366 /* feature limited to enable or disable settings: */ 367 /* Setting "ADC_AUTOWAIT_UNTIL_DATA_READ" is equivalent to "ENABLE". */ 368 369 #define ADC_AUTOWAIT_DISABLE ((uint32_t)0x00000000) 370 #define ADC_AUTOWAIT_UNTIL_DATA_READ ((uint32_t)( ADC_CR2_DELS_0)) /*!< Insert a delay between ADC conversions: infinite delay, until the result of previous conversion is read */ 371 #define ADC_AUTOWAIT_7_APBCLOCKCYCLES ((uint32_t)( ADC_CR2_DELS_1 )) /*!< Insert a delay between ADC conversions: 7 APB clock cycles */ 372 #define ADC_AUTOWAIT_15_APBCLOCKCYCLES ((uint32_t)( ADC_CR2_DELS_1 | ADC_CR2_DELS_0)) /*!< Insert a delay between ADC conversions: 15 APB clock cycles */ 373 #define ADC_AUTOWAIT_31_APBCLOCKCYCLES ((uint32_t)(ADC_CR2_DELS_2 )) /*!< Insert a delay between ADC conversions: 31 APB clock cycles */ 374 #define ADC_AUTOWAIT_63_APBCLOCKCYCLES ((uint32_t)(ADC_CR2_DELS_2 | ADC_CR2_DELS_0)) /*!< Insert a delay between ADC conversions: 63 APB clock cycles */ 375 #define ADC_AUTOWAIT_127_APBCLOCKCYCLES ((uint32_t)(ADC_CR2_DELS_2 | ADC_CR2_DELS_1 )) /*!< Insert a delay between ADC conversions: 127 APB clock cycles */ 376 #define ADC_AUTOWAIT_255_APBCLOCKCYCLES ((uint32_t)(ADC_CR2_DELS_2 | ADC_CR2_DELS_1 | ADC_CR2_DELS_0)) /*!< Insert a delay between ADC conversions: 255 APB clock cycles */ 377 378 /** 379 * @} 380 */ 381 382 /** @defgroup ADC_LowPowerAutoPowerOff ADC LowPowerAutoPowerOff 383 * @{ 384 */ 385 #define ADC_AUTOPOWEROFF_DISABLE ((uint32_t)0x00000000) 386 #define ADC_AUTOPOWEROFF_IDLE_PHASE ((uint32_t)ADC_CR1_PDI) /*!< ADC power off when ADC is not converting (idle phase) */ 387 #define ADC_AUTOPOWEROFF_DELAY_PHASE ((uint32_t)ADC_CR1_PDD) /*!< ADC power off when a delay is inserted between conversions (see parameter ADC_LowPowerAutoWait) */ 388 #define ADC_AUTOPOWEROFF_IDLE_DELAY_PHASES ((uint32_t)(ADC_CR1_PDI | ADC_CR1_PDD)) /*!< ADC power off when ADC is not converting (idle phase) and when a delay is inserted between conversions */ 389 /** 390 * @} 391 */ 392 393 394 /** @defgroup ADC_ChannelsBank ADC ChannelsBank 395 * @{ 396 */ 397 #if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) 398 #define ADC_CHANNELS_BANK_A ((uint32_t)0x00000000) 399 #define ADC_CHANNELS_BANK_B ((uint32_t)ADC_CR2_CFG) 400 401 #define IS_ADC_CHANNELSBANK(BANK) (((BANK) == ADC_CHANNELS_BANK_A) || \ 402 ((BANK) == ADC_CHANNELS_BANK_B) ) 403 #else 404 #define ADC_CHANNELS_BANK_A ((uint32_t)0x00000000) 405 406 #define IS_ADC_CHANNELSBANK(BANK) (((BANK) == ADC_CHANNELS_BANK_A)) 407 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 408 /** 409 * @} 410 */ 411 412 /** @defgroup ADC_channels ADC channels 413 * @{ 414 */ 415 /* Note: Depending on devices, some channels may not be available on package */ 416 /* pins. Refer to device datasheet for channels availability. */ 417 #define ADC_CHANNEL_0 ((uint32_t)0x00000000) /* Channel different in bank A and bank B */ 418 #define ADC_CHANNEL_1 ((uint32_t)( ADC_SQR5_SQ1_0)) /* Channel different in bank A and bank B */ 419 #define ADC_CHANNEL_2 ((uint32_t)( ADC_SQR5_SQ1_1 )) /* Channel different in bank A and bank B */ 420 #define ADC_CHANNEL_3 ((uint32_t)( ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0)) /* Channel different in bank A and bank B */ 421 #define ADC_CHANNEL_4 ((uint32_t)( ADC_SQR5_SQ1_2 )) /* Direct (fast) channel */ 422 #define ADC_CHANNEL_5 ((uint32_t)( ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_0)) /* Direct (fast) channel */ 423 #define ADC_CHANNEL_6 ((uint32_t)( ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_1 )) /* Channel different in bank A and bank B */ 424 #define ADC_CHANNEL_7 ((uint32_t)( ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0)) /* Channel different in bank A and bank B */ 425 #define ADC_CHANNEL_8 ((uint32_t)( ADC_SQR5_SQ1_3 )) /* Channel different in bank A and bank B */ 426 #define ADC_CHANNEL_9 ((uint32_t)( ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_0)) /* Channel different in bank A and bank B */ 427 #define ADC_CHANNEL_10 ((uint32_t)( ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_1 )) /* Channel different in bank A and bank B */ 428 #define ADC_CHANNEL_11 ((uint32_t)( ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0)) /* Channel different in bank A and bank B */ 429 #define ADC_CHANNEL_12 ((uint32_t)( ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_2 )) /* Channel different in bank A and bank B */ 430 #define ADC_CHANNEL_13 ((uint32_t)( ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */ 431 #define ADC_CHANNEL_14 ((uint32_t)( ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_1 )) /* Channel common to both bank A and bank B */ 432 #define ADC_CHANNEL_15 ((uint32_t)( ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */ 433 #define ADC_CHANNEL_16 ((uint32_t)(ADC_SQR5_SQ1_4 )) /* Channel common to both bank A and bank B */ 434 #define ADC_CHANNEL_17 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */ 435 #define ADC_CHANNEL_18 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_1 )) /* Channel common to both bank A and bank B */ 436 #define ADC_CHANNEL_19 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */ 437 #define ADC_CHANNEL_20 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_2 )) /* Channel common to both bank A and bank B */ 438 #define ADC_CHANNEL_21 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */ 439 #define ADC_CHANNEL_22 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_1 )) /* Direct (fast) channel */ 440 #define ADC_CHANNEL_23 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0)) /* Direct (fast) channel */ 441 #define ADC_CHANNEL_24 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3 )) /* Direct (fast) channel */ 442 #define ADC_CHANNEL_25 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_0)) /* Direct (fast) channel */ 443 #define ADC_CHANNEL_26 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_1 )) /* Channel common to both bank A and bank B */ 444 #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) 445 #define ADC_CHANNEL_27 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */ 446 #define ADC_CHANNEL_28 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_2 )) /* Channel common to both bank A and bank B */ 447 #define ADC_CHANNEL_29 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */ 448 #define ADC_CHANNEL_30 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_1 )) /* Channel common to both bank A and bank B */ 449 #define ADC_CHANNEL_31 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */ 450 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 451 452 #define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_16 /* ADC internal channel (no connection on device pin). Channel common to both bank A and bank B. */ 453 #define ADC_CHANNEL_VREFINT ADC_CHANNEL_17 /* ADC internal channel (no connection on device pin). Channel common to both bank A and bank B. */ 454 #define ADC_CHANNEL_VCOMP ADC_CHANNEL_26 /* ADC internal channel (no connection on device pin). Channel common to both bank A and bank B. */ 455 456 #if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) 457 #define ADC_CHANNEL_VOPAMP1 ADC_CHANNEL_3 /* Internal connection from OPAMP1 output to ADC switch matrix */ 458 #define ADC_CHANNEL_VOPAMP2 ADC_CHANNEL_8 /* Internal connection from OPAMP2 output to ADC switch matrix */ 459 #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) 460 #define ADC_CHANNEL_VOPAMP3 ADC_CHANNEL_13 /* Internal connection from OPAMP3 output to ADC switch matrix */ 461 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD */ 462 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 463 /** 464 * @} 465 */ 466 467 /** @defgroup ADC_sampling_times ADC sampling times 468 * @{ 469 */ 470 #define ADC_SAMPLETIME_4CYCLES ((uint32_t)0x00000000) /*!< Sampling time 4 ADC clock cycles */ 471 #define ADC_SAMPLETIME_9CYCLES ((uint32_t) ADC_SMPR3_SMP0_0) /*!< Sampling time 9 ADC clock cycles */ 472 #define ADC_SAMPLETIME_16CYCLES ((uint32_t) ADC_SMPR3_SMP0_1) /*!< Sampling time 16 ADC clock cycles */ 473 #define ADC_SAMPLETIME_24CYCLES ((uint32_t)(ADC_SMPR3_SMP0_1 | ADC_SMPR3_SMP0_0)) /*!< Sampling time 24 ADC clock cycles */ 474 #define ADC_SAMPLETIME_48CYCLES ((uint32_t) ADC_SMPR3_SMP0_2) /*!< Sampling time 48 ADC clock cycles */ 475 #define ADC_SAMPLETIME_96CYCLES ((uint32_t)(ADC_SMPR3_SMP0_2 | ADC_SMPR3_SMP0_0)) /*!< Sampling time 96 ADC clock cycles */ 476 #define ADC_SAMPLETIME_192CYCLES ((uint32_t)(ADC_SMPR3_SMP0_2 | ADC_SMPR3_SMP0_1)) /*!< Sampling time 192 ADC clock cycles */ 477 #define ADC_SAMPLETIME_384CYCLES ((uint32_t) ADC_SMPR3_SMP0) /*!< Sampling time 384 ADC clock cycles */ 478 /** 479 * @} 480 */ 481 482 /** @defgroup ADC_sampling_times_all_channels ADC sampling times all channels 483 * @{ 484 */ 485 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR3BIT2 \ 486 (ADC_SMPR3_SMP9_2 | ADC_SMPR3_SMP8_2 | ADC_SMPR3_SMP7_2 | ADC_SMPR3_SMP6_2 | \ 487 ADC_SMPR3_SMP5_2 | ADC_SMPR3_SMP4_2 | ADC_SMPR3_SMP3_2 | ADC_SMPR3_SMP2_2 | \ 488 ADC_SMPR3_SMP1_2 | ADC_SMPR3_SMP0_2) 489 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 \ 490 (ADC_SMPR2_SMP19_2 | ADC_SMPR2_SMP18_2 | ADC_SMPR2_SMP17_2 | ADC_SMPR2_SMP16_2 | \ 491 ADC_SMPR2_SMP15_2 | ADC_SMPR2_SMP14_2 | ADC_SMPR2_SMP13_2 | ADC_SMPR2_SMP12_2 | \ 492 ADC_SMPR2_SMP11_2 | ADC_SMPR2_SMP10_2) 493 #if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) || defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) 494 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 \ 495 (ADC_SMPR1_SMP26_2 | ADC_SMPR1_SMP25_2 | ADC_SMPR1_SMP24_2 | ADC_SMPR1_SMP23_2 | \ 496 ADC_SMPR1_SMP22_2 | ADC_SMPR1_SMP21_2 | ADC_SMPR1_SMP20_2) 497 #endif /* STM32L100xB || STM32L151xB || STM32L152xB || STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC */ 498 #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) 499 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 \ 500 (ADC_SMPR1_SMP29_2 | ADC_SMPR1_SMP28_2 | ADC_SMPR1_SMP27_2 | ADC_SMPR1_SMP26_2 | \ 501 ADC_SMPR1_SMP25_2 | ADC_SMPR1_SMP24_2 | ADC_SMPR1_SMP23_2 | ADC_SMPR1_SMP22_2 | \ 502 ADC_SMPR1_SMP21_2 | ADC_SMPR1_SMP20_2) 503 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR0BIT2 \ 504 (ADC_SMPR0_SMP31_2 | ADC_SMPR0_SMP30_2 ) 505 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 506 507 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR3BIT1 \ 508 (ADC_SMPR3_SMP9_1 | ADC_SMPR3_SMP8_1 | ADC_SMPR3_SMP7_1 | ADC_SMPR3_SMP6_1 | \ 509 ADC_SMPR3_SMP5_1 | ADC_SMPR3_SMP4_1 | ADC_SMPR3_SMP3_1 | ADC_SMPR3_SMP2_1 | \ 510 ADC_SMPR3_SMP1_1 | ADC_SMPR3_SMP0_1) 511 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 \ 512 (ADC_SMPR2_SMP19_1 | ADC_SMPR2_SMP18_1 | ADC_SMPR2_SMP17_1 | ADC_SMPR2_SMP16_1 | \ 513 ADC_SMPR2_SMP15_1 | ADC_SMPR2_SMP14_1 | ADC_SMPR2_SMP13_1 | ADC_SMPR2_SMP12_1 | \ 514 ADC_SMPR2_SMP11_1 | ADC_SMPR2_SMP10_1) 515 #if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) || defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) 516 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 \ 517 (ADC_SMPR1_SMP26_1 | ADC_SMPR1_SMP25_1 | ADC_SMPR1_SMP24_1 | ADC_SMPR1_SMP23_1 | \ 518 ADC_SMPR1_SMP22_1 | ADC_SMPR1_SMP21_1 | ADC_SMPR1_SMP20_1) 519 #endif /* STM32L100xB || STM32L151xB || STM32L152xB || STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC */ 520 #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) 521 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 \ 522 (ADC_SMPR1_SMP29_1 | ADC_SMPR1_SMP28_1 | ADC_SMPR1_SMP27_1 | ADC_SMPR1_SMP26_1 | \ 523 ADC_SMPR1_SMP25_1 | ADC_SMPR1_SMP24_1 | ADC_SMPR1_SMP23_1 | ADC_SMPR1_SMP22_1 | \ 524 ADC_SMPR1_SMP21_1 | ADC_SMPR1_SMP20_1) 525 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR0BIT1 \ 526 (ADC_SMPR0_SMP31_1 | ADC_SMPR0_SMP30_1 ) 527 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 528 529 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR3BIT0 \ 530 (ADC_SMPR3_SMP9_0 | ADC_SMPR3_SMP8_0 | ADC_SMPR3_SMP7_0 | ADC_SMPR3_SMP6_0 | \ 531 ADC_SMPR3_SMP5_0 | ADC_SMPR3_SMP4_0 | ADC_SMPR3_SMP3_0 | ADC_SMPR3_SMP2_0 | \ 532 ADC_SMPR3_SMP1_0 | ADC_SMPR3_SMP0_0) 533 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0 \ 534 (ADC_SMPR2_SMP19_0 | ADC_SMPR2_SMP18_0 | ADC_SMPR2_SMP17_0 | ADC_SMPR2_SMP16_0 | \ 535 ADC_SMPR2_SMP15_0 | ADC_SMPR2_SMP14_0 | ADC_SMPR2_SMP13_0 | ADC_SMPR2_SMP12_0 | \ 536 ADC_SMPR2_SMP11_0 | ADC_SMPR2_SMP10_0) 537 #if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) || defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) 538 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0 \ 539 (ADC_SMPR1_SMP26_0 | ADC_SMPR1_SMP25_0 | ADC_SMPR1_SMP24_0 | ADC_SMPR1_SMP23_0 | \ 540 ADC_SMPR1_SMP22_0 | ADC_SMPR1_SMP21_0 | ADC_SMPR1_SMP20_0) 541 #endif /* STM32L100xB || STM32L151xB || STM32L152xB || STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC */ 542 #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) 543 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0 \ 544 (ADC_SMPR1_SMP29_0 | ADC_SMPR1_SMP28_0 | ADC_SMPR1_SMP27_0 | ADC_SMPR1_SMP26_0 | \ 545 ADC_SMPR1_SMP25_0 | ADC_SMPR1_SMP24_0 | ADC_SMPR1_SMP23_0 | ADC_SMPR1_SMP22_0 | \ 546 ADC_SMPR1_SMP21_0 | ADC_SMPR1_SMP20_0) 547 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR0BIT0 \ 548 (ADC_SMPR0_SMP31_0 | ADC_SMPR0_SMP30_0 ) 549 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 550 /** 551 * @} 552 */ 553 554 /** @defgroup ADC_regular_rank ADC rank into regular group 555 * @{ 556 */ 557 #define ADC_REGULAR_RANK_1 ((uint32_t)0x00000001) 558 #define ADC_REGULAR_RANK_2 ((uint32_t)0x00000002) 559 #define ADC_REGULAR_RANK_3 ((uint32_t)0x00000003) 560 #define ADC_REGULAR_RANK_4 ((uint32_t)0x00000004) 561 #define ADC_REGULAR_RANK_5 ((uint32_t)0x00000005) 562 #define ADC_REGULAR_RANK_6 ((uint32_t)0x00000006) 563 #define ADC_REGULAR_RANK_7 ((uint32_t)0x00000007) 564 #define ADC_REGULAR_RANK_8 ((uint32_t)0x00000008) 565 #define ADC_REGULAR_RANK_9 ((uint32_t)0x00000009) 566 #define ADC_REGULAR_RANK_10 ((uint32_t)0x0000000A) 567 #define ADC_REGULAR_RANK_11 ((uint32_t)0x0000000B) 568 #define ADC_REGULAR_RANK_12 ((uint32_t)0x0000000C) 569 #define ADC_REGULAR_RANK_13 ((uint32_t)0x0000000D) 570 #define ADC_REGULAR_RANK_14 ((uint32_t)0x0000000E) 571 #define ADC_REGULAR_RANK_15 ((uint32_t)0x0000000F) 572 #define ADC_REGULAR_RANK_16 ((uint32_t)0x00000010) 573 #define ADC_REGULAR_RANK_17 ((uint32_t)0x00000011) 574 #define ADC_REGULAR_RANK_18 ((uint32_t)0x00000012) 575 #define ADC_REGULAR_RANK_19 ((uint32_t)0x00000013) 576 #define ADC_REGULAR_RANK_20 ((uint32_t)0x00000014) 577 #define ADC_REGULAR_RANK_21 ((uint32_t)0x00000015) 578 #define ADC_REGULAR_RANK_22 ((uint32_t)0x00000016) 579 #define ADC_REGULAR_RANK_23 ((uint32_t)0x00000017) 580 #define ADC_REGULAR_RANK_24 ((uint32_t)0x00000018) 581 #define ADC_REGULAR_RANK_25 ((uint32_t)0x00000019) 582 #define ADC_REGULAR_RANK_26 ((uint32_t)0x0000001A) 583 #define ADC_REGULAR_RANK_27 ((uint32_t)0x0000001B) 584 #if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) 585 #define ADC_REGULAR_RANK_28 ((uint32_t)0x0000001C) 586 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 587 /** 588 * @} 589 */ 590 591 /** @defgroup ADC_analog_watchdog_mode ADC analog watchdog mode 592 * @{ 593 */ 594 #define ADC_ANALOGWATCHDOG_NONE ((uint32_t)0x00000000) 595 #define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN)) 596 #define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN)) 597 #define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN)) 598 #define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t) ADC_CR1_AWDEN) 599 #define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t) ADC_CR1_JAWDEN) 600 #define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN)) 601 /** 602 * @} 603 */ 604 605 /** @defgroup ADC_conversion_group ADC conversion group 606 * @{ 607 */ 608 #define ADC_REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC)) 609 #define ADC_INJECTED_GROUP ((uint32_t)(ADC_FLAG_JEOC)) 610 #define ADC_REGULAR_INJECTED_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_JEOC)) 611 /** 612 * @} 613 */ 614 615 /** @defgroup ADC_Event_type ADC Event type 616 * @{ 617 */ 618 #define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD) /*!< ADC Analog watchdog event */ 619 #define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR) /*!< ADC overrun event */ 620 /** 621 * @} 622 */ 623 624 /** @defgroup ADC_interrupts_definition ADC interrupts definition 625 * @{ 626 */ 627 #define ADC_IT_EOC ADC_CR1_EOCIE /*!< ADC End of Regular Conversion interrupt source */ 628 #define ADC_IT_JEOC ADC_CR1_JEOCIE /*!< ADC End of Injected Conversion interrupt source */ 629 #define ADC_IT_AWD ADC_CR1_AWDIE /*!< ADC Analog watchdog interrupt source */ 630 #define ADC_IT_OVR ADC_CR1_OVRIE /*!< ADC overrun interrupt source */ 631 /** 632 * @} 633 */ 634 635 /** @defgroup ADC_flags_definition ADC flags definition 636 * @{ 637 */ 638 #define ADC_FLAG_AWD ADC_SR_AWD /*!< ADC Analog watchdog flag */ 639 #define ADC_FLAG_EOC ADC_SR_EOC /*!< ADC End of Regular conversion flag */ 640 #define ADC_FLAG_JEOC ADC_SR_JEOC /*!< ADC End of Injected conversion flag */ 641 #define ADC_FLAG_JSTRT ADC_SR_JSTRT /*!< ADC Injected group start flag */ 642 #define ADC_FLAG_STRT ADC_SR_STRT /*!< ADC Regular group start flag */ 643 #define ADC_FLAG_OVR ADC_SR_OVR /*!< ADC overrun flag */ 644 #define ADC_FLAG_ADONS ADC_SR_ADONS /*!< ADC ready status flag */ 645 #define ADC_FLAG_RCNR ADC_SR_RCNR /*!< ADC Regular group ready status flag */ 646 #define ADC_FLAG_JCNR ADC_SR_JCNR /*!< ADC Injected group ready status flag */ 647 /** 648 * @} 649 */ 650 651 /** 652 * @} 653 */ 654 655 656 /* Private constants ---------------------------------------------------------*/ 657 658 /** @addtogroup ADC_Private_Constants ADC Private Constants 659 * @{ 660 */ 661 662 /* List of external triggers of regular group for ADC1: */ 663 /* (used internally by HAL driver. To not use into HAL structure parameters) */ 664 665 /* External triggers of regular group for ADC1 */ 666 #define ADC_EXTERNALTRIG_T9_CC2 ((uint32_t) 0x00000000) 667 #define ADC_EXTERNALTRIG_T9_TRGO ((uint32_t)( ADC_CR2_EXTSEL_0)) 668 #define ADC_EXTERNALTRIG_T2_CC3 ((uint32_t)( ADC_CR2_EXTSEL_1 )) 669 #define ADC_EXTERNALTRIG_T2_CC2 ((uint32_t)( ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) 670 #define ADC_EXTERNALTRIG_T3_TRGO ((uint32_t)( ADC_CR2_EXTSEL_2 )) 671 #define ADC_EXTERNALTRIG_T4_CC4 ((uint32_t)( ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0)) 672 #define ADC_EXTERNALTRIG_T2_TRGO ((uint32_t)( ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 )) 673 #define ADC_EXTERNALTRIG_T3_CC1 ((uint32_t)( ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) 674 #define ADC_EXTERNALTRIG_T3_CC3 ((uint32_t)(ADC_CR2_EXTSEL_3 )) 675 #define ADC_EXTERNALTRIG_T4_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0)) 676 #define ADC_EXTERNALTRIG_T6_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 )) 677 #define ADC_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) 678 679 /* Combination of all post-conversion flags bits: EOC/EOS, JEOC/JEOS, OVR, AWDx */ 680 #define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_EOC | ADC_FLAG_JEOC | ADC_FLAG_AWD | \ 681 ADC_FLAG_OVR) 682 683 /** 684 * @} 685 */ 686 687 688 /* Exported macro ------------------------------------------------------------*/ 689 690 /** @defgroup ADC_Exported_Macros ADC Exported Macros 691 * @{ 692 */ 693 /* Macro for internal HAL driver usage, and possibly can be used into code of */ 694 /* final user. */ 695 696 /** 697 * @brief Enable the ADC peripheral 698 * @param __HANDLE__: ADC handle 699 * @retval None 700 */ 701 #define __HAL_ADC_ENABLE(__HANDLE__) \ 702 (__HANDLE__)->Instance->CR2 |= ADC_CR2_ADON 703 704 /** 705 * @brief Disable the ADC peripheral 706 * @param __HANDLE__: ADC handle 707 * @retval None 708 */ 709 #define __HAL_ADC_DISABLE(__HANDLE__) \ 710 (__HANDLE__)->Instance->CR2 &= ~ADC_CR2_ADON 711 712 /** 713 * @brief Enable the ADC end of conversion interrupt. 714 * @param __HANDLE__: ADC handle 715 * @param __INTERRUPT__: ADC Interrupt 716 * This parameter can be any combination of the following values: 717 * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source 718 * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source 719 * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source 720 * @arg ADC_IT_OVR: ADC overrun interrupt source 721 * @retval None 722 */ 723 #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ 724 (SET_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__))) 725 726 /** 727 * @brief Disable the ADC end of conversion interrupt. 728 * @param __HANDLE__: ADC handle 729 * @param __INTERRUPT__: ADC Interrupt 730 * This parameter can be any combination of the following values: 731 * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source 732 * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source 733 * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source 734 * @arg ADC_IT_OVR: ADC overrun interrupt source 735 * @retval None 736 */ 737 #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ 738 (CLEAR_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__))) 739 740 /** @brief Checks if the specified ADC interrupt source is enabled or disabled. 741 * @param __HANDLE__: ADC handle 742 * @param __INTERRUPT__: ADC interrupt source to check 743 * This parameter can be any combination of the following values: 744 * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source 745 * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source 746 * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source 747 * @arg ADC_IT_OVR: ADC overrun interrupt source 748 * @retval State of interruption (SET or RESET) 749 */ 750 #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ 751 (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) 752 753 /** 754 * @brief Get the selected ADC's flag status. 755 * @param __HANDLE__: ADC handle 756 * @param __FLAG__: ADC flag 757 * This parameter can be any combination of the following values: 758 * @arg ADC_FLAG_STRT: ADC Regular group start flag 759 * @arg ADC_FLAG_JSTRT: ADC Injected group start flag 760 * @arg ADC_FLAG_EOC: ADC End of Regular conversion flag 761 * @arg ADC_FLAG_JEOC: ADC End of Injected conversion flag 762 * @arg ADC_FLAG_AWD: ADC Analog watchdog flag 763 * @arg ADC_FLAG_OVR: ADC overrun flag 764 * @arg ADC_FLAG_ADONS: ADC ready status flag 765 * @arg ADC_FLAG_RCNR: ADC Regular group ready status flag 766 * @arg ADC_FLAG_JCNR: ADC Injected group ready status flag 767 * @retval None 768 */ 769 #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \ 770 ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) 771 772 /** 773 * @brief Clear the ADC's pending flags 774 * @param __HANDLE__: ADC handle 775 * @param __FLAG__: ADC flag 776 * @arg ADC_FLAG_STRT: ADC Regular group start flag 777 * @arg ADC_FLAG_JSTRT: ADC Injected group start flag 778 * @arg ADC_FLAG_EOC: ADC End of Regular conversion flag 779 * @arg ADC_FLAG_JEOC: ADC End of Injected conversion flag 780 * @arg ADC_FLAG_AWD: ADC Analog watchdog flag 781 * @arg ADC_FLAG_OVR: ADC overrun flag 782 * @arg ADC_FLAG_ADONS: ADC ready status flag 783 * @arg ADC_FLAG_RCNR: ADC Regular group ready status flag 784 * @arg ADC_FLAG_JCNR: ADC Injected group ready status flag 785 * @retval None 786 */ 787 #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \ 788 (((__HANDLE__)->Instance->SR) = ~(__FLAG__)) 789 790 /** @brief Reset ADC handle state 791 * @param __HANDLE__: ADC handle 792 * @retval None 793 */ 794 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ 795 ((__HANDLE__)->State = HAL_ADC_STATE_RESET) 796 797 /** 798 * @} 799 */ 800 801 /* Private macro ------------------------------------------------------------*/ 802 803 /** @defgroup ADC_Private_Macros ADC Private Macros 804 * @{ 805 */ 806 /* Macro reserved for internal HAL driver usage, not intended to be used in */ 807 /* code of final user. */ 808 809 /** 810 * @brief Verification of ADC state: enabled or disabled 811 * @param __HANDLE__: ADC handle 812 * @retval SET (ADC enabled) or RESET (ADC disabled) 813 */ 814 #define ADC_IS_ENABLE(__HANDLE__) \ 815 ((( ((__HANDLE__)->Instance->SR & ADC_SR_ADONS) == ADC_SR_ADONS ) \ 816 ) ? SET : RESET) 817 818 /** 819 * @brief Test if conversion trigger of regular group is software start 820 * or external trigger. 821 * @param __HANDLE__: ADC handle 822 * @retval SET (software start) or RESET (external trigger) 823 */ 824 #define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \ 825 (((__HANDLE__)->Instance->CR2 & ADC_CR2_EXTEN) == RESET) 826 827 /** 828 * @brief Test if conversion trigger of injected group is software start 829 * or external trigger. 830 * @param __HANDLE__: ADC handle 831 * @retval SET (software start) or RESET (external trigger) 832 */ 833 #define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \ 834 (((__HANDLE__)->Instance->CR2 & ADC_CR2_JEXTEN) == RESET) 835 836 /** 837 * @brief Simultaneously clears and sets specific bits of the handle State 838 * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(), 839 * the first parameter is the ADC handle State, the second parameter is the 840 * bit field to clear, the third and last parameter is the bit field to set. 841 * @retval None 842 */ 843 #define ADC_STATE_CLR_SET MODIFY_REG 844 845 /** 846 * @brief Clear ADC error code (set it to error code: "no error") 847 * @param __HANDLE__: ADC handle 848 * @retval None 849 */ 850 #define ADC_CLEAR_ERRORCODE(__HANDLE__) \ 851 ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) 852 853 /** 854 * @brief Set ADC number of ranks into regular channel sequence length. 855 * @param _NbrOfConversion_: Regular channel sequence length 856 * @retval None 857 */ 858 #define ADC_SQR1_L_SHIFT(_NbrOfConversion_) \ 859 (((_NbrOfConversion_) - (uint8_t)1) << POSITION_VAL(ADC_SQR1_L)) 860 861 /** 862 * @brief Set the ADC's sample time for channel numbers between 10 and 18. 863 * @param _SAMPLETIME_: Sample time parameter. 864 * @param _CHANNELNB_: Channel number. 865 * @retval None 866 */ 867 #define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) \ 868 ((_SAMPLETIME_) << (3 * ((_CHANNELNB_) - 10))) 869 870 /** 871 * @brief Set the ADC's sample time for channel numbers between 0 and 9. 872 * @param _SAMPLETIME_: Sample time parameter. 873 * @param _CHANNELNB_: Channel number. 874 * @retval None 875 */ 876 #define ADC_SMPR3(_SAMPLETIME_, _CHANNELNB_) \ 877 ((_SAMPLETIME_) << (3 * (_CHANNELNB_))) 878 879 /** 880 * @brief Set the selected regular channel rank for rank between 1 and 6. 881 * @param _CHANNELNB_: Channel number. 882 * @param _RANKNB_: Rank number. 883 * @retval None 884 */ 885 #define ADC_SQR5_RK(_CHANNELNB_, _RANKNB_) \ 886 ((_CHANNELNB_) << (5 * ((_RANKNB_) - 1))) 887 888 /** 889 * @brief Set the selected regular channel rank for rank between 7 and 12. 890 * @param _CHANNELNB_: Channel number. 891 * @param _RANKNB_: Rank number. 892 * @retval None 893 */ 894 #define ADC_SQR4_RK(_CHANNELNB_, _RANKNB_) \ 895 ((_CHANNELNB_) << (5 * ((_RANKNB_) - 7))) 896 897 /** 898 * @brief Set the selected regular channel rank for rank between 13 and 18. 899 * @param _CHANNELNB_: Channel number. 900 * @param _RANKNB_: Rank number. 901 * @retval None 902 */ 903 #define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) \ 904 ((_CHANNELNB_) << (5 * ((_RANKNB_) - 13))) 905 906 /** 907 * @brief Set the selected regular channel rank for rank between 19 and 24. 908 * @param _CHANNELNB_: Channel number. 909 * @param _RANKNB_: Rank number. 910 * @retval None 911 */ 912 #define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) \ 913 ((_CHANNELNB_) << (5 * ((_RANKNB_) - 19))) 914 915 /** 916 * @brief Set the selected regular channel rank for rank between 25 and 28. 917 * @param _CHANNELNB_: Channel number. 918 * @param _RANKNB_: Rank number. 919 * @retval None 920 */ 921 #define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) \ 922 ((_CHANNELNB_) << (5 * ((_RANKNB_) - 25))) 923 924 /** 925 * @brief Set the injected sequence length. 926 * @param _JSQR_JL_: Sequence length. 927 * @retval None 928 */ 929 #define ADC_JSQR_JL_SHIFT(_JSQR_JL_) (((_JSQR_JL_) -1) << 20) 930 931 /** 932 * @brief Set the selected injected channel rank 933 * Note: on STM32L1 devices, channel rank position in JSQR register 934 * is depending on total number of ranks selected into 935 * injected sequencer (ranks sequence starting from 4-JL) 936 * @param _CHANNELNB_: Channel number. 937 * @param _RANKNB_: Rank number. 938 * @param _JSQR_JL_: Sequence length. 939 * @retval None 940 */ 941 #define ADC_JSQR_RK_JL(_CHANNELNB_, _RANKNB_, _JSQR_JL_) \ 942 ((_CHANNELNB_) << (5 * ((4 - ((_JSQR_JL_) - (_RANKNB_))) - 1))) 943 944 /** 945 * @brief Enable the ADC DMA continuous request. 946 * @param _DMACONTREQ_MODE_: DMA continuous request mode. 947 * @retval None 948 */ 949 #define ADC_CR2_DMACONTREQ(_DMACONTREQ_MODE_) \ 950 ((_DMACONTREQ_MODE_) << POSITION_VAL(ADC_CR2_DDS)) 951 952 /** 953 * @brief Enable ADC continuous conversion mode. 954 * @param _CONTINUOUS_MODE_: Continuous mode. 955 * @retval None 956 */ 957 #define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) \ 958 ((_CONTINUOUS_MODE_) << POSITION_VAL(ADC_CR2_CONT)) 959 960 /** 961 * @brief Configures the number of discontinuous conversions for the regular group channels. 962 * @param _NBR_DISCONTINUOUS_CONV_: Number of discontinuous conversions. 963 * @retval None 964 */ 965 #define ADC_CR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) \ 966 (((_NBR_DISCONTINUOUS_CONV_) - 1) << POSITION_VAL(ADC_CR1_DISCNUM)) 967 968 /** 969 * @brief Enable ADC scan mode to convert multiple ranks with sequencer. 970 * @param _SCAN_MODE_: Scan conversion mode. 971 * @retval None 972 */ 973 /* Note: Scan mode is compared to ENABLE for legacy purpose, this parameter */ 974 /* is equivalent to ADC_SCAN_ENABLE. */ 975 #define ADC_CR1_SCAN_SET(_SCAN_MODE_) \ 976 (( ((_SCAN_MODE_) == ADC_SCAN_ENABLE) || ((_SCAN_MODE_) == ENABLE) \ 977 )? (ADC_SCAN_ENABLE) : (ADC_SCAN_DISABLE) \ 978 ) 979 980 981 #define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1) || \ 982 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV2) || \ 983 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV4) ) 984 985 #define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) || \ 986 ((RESOLUTION) == ADC_RESOLUTION_10B) || \ 987 ((RESOLUTION) == ADC_RESOLUTION_8B) || \ 988 ((RESOLUTION) == ADC_RESOLUTION_6B) ) 989 990 #define IS_ADC_RESOLUTION_8_6_BITS(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_8B) || \ 991 ((RESOLUTION) == ADC_RESOLUTION_6B) ) 992 993 #define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \ 994 ((ALIGN) == ADC_DATAALIGN_LEFT) ) 995 996 #define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DISABLE) || \ 997 ((SCAN_MODE) == ADC_SCAN_ENABLE) ) 998 999 #define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \ 1000 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \ 1001 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \ 1002 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING) ) 1003 1004 #define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3) || \ 1005 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \ 1006 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \ 1007 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1) || \ 1008 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC3) || \ 1009 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \ 1010 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \ 1011 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_TRGO) || \ 1012 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T6_TRGO) || \ 1013 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T9_CC2) || \ 1014 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T9_TRGO) || \ 1015 ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \ 1016 ((REGTRIG) == ADC_SOFTWARE_START) ) 1017 1018 #define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == ADC_EOC_SINGLE_CONV) || \ 1019 ((EOC_SELECTION) == ADC_EOC_SEQ_CONV) ) 1020 1021 #define IS_ADC_AUTOWAIT(AUTOWAIT) (((AUTOWAIT) == ADC_AUTOWAIT_DISABLE) || \ 1022 ((AUTOWAIT) == ADC_AUTOWAIT_UNTIL_DATA_READ) || \ 1023 ((AUTOWAIT) == ADC_AUTOWAIT_7_APBCLOCKCYCLES) || \ 1024 ((AUTOWAIT) == ADC_AUTOWAIT_15_APBCLOCKCYCLES) || \ 1025 ((AUTOWAIT) == ADC_AUTOWAIT_31_APBCLOCKCYCLES) || \ 1026 ((AUTOWAIT) == ADC_AUTOWAIT_63_APBCLOCKCYCLES) || \ 1027 ((AUTOWAIT) == ADC_AUTOWAIT_127_APBCLOCKCYCLES) || \ 1028 ((AUTOWAIT) == ADC_AUTOWAIT_255_APBCLOCKCYCLES) ) 1029 1030 #define IS_ADC_AUTOPOWEROFF(AUTOPOWEROFF) (((AUTOPOWEROFF) == ADC_AUTOPOWEROFF_DISABLE) || \ 1031 ((AUTOPOWEROFF) == ADC_AUTOPOWEROFF_IDLE_PHASE) || \ 1032 ((AUTOPOWEROFF) == ADC_AUTOPOWEROFF_DELAY_PHASE) || \ 1033 ((AUTOPOWEROFF) == ADC_AUTOPOWEROFF_IDLE_DELAY_PHASES) ) 1034 1035 #if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) 1036 1037 #define IS_ADC_CHANNELSBANK(BANK) (((BANK) == ADC_CHANNELS_BANK_A) || \ 1038 ((BANK) == ADC_CHANNELS_BANK_B) ) 1039 #else 1040 1041 #define IS_ADC_CHANNELSBANK(BANK) (((BANK) == ADC_CHANNELS_BANK_A)) 1042 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 1043 1044 #if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) || defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) 1045 #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \ 1046 ((CHANNEL) == ADC_CHANNEL_1) || \ 1047 ((CHANNEL) == ADC_CHANNEL_2) || \ 1048 ((CHANNEL) == ADC_CHANNEL_3) || \ 1049 ((CHANNEL) == ADC_CHANNEL_4) || \ 1050 ((CHANNEL) == ADC_CHANNEL_5) || \ 1051 ((CHANNEL) == ADC_CHANNEL_6) || \ 1052 ((CHANNEL) == ADC_CHANNEL_7) || \ 1053 ((CHANNEL) == ADC_CHANNEL_8) || \ 1054 ((CHANNEL) == ADC_CHANNEL_9) || \ 1055 ((CHANNEL) == ADC_CHANNEL_10) || \ 1056 ((CHANNEL) == ADC_CHANNEL_11) || \ 1057 ((CHANNEL) == ADC_CHANNEL_12) || \ 1058 ((CHANNEL) == ADC_CHANNEL_13) || \ 1059 ((CHANNEL) == ADC_CHANNEL_14) || \ 1060 ((CHANNEL) == ADC_CHANNEL_15) || \ 1061 ((CHANNEL) == ADC_CHANNEL_16) || \ 1062 ((CHANNEL) == ADC_CHANNEL_17) || \ 1063 ((CHANNEL) == ADC_CHANNEL_18) || \ 1064 ((CHANNEL) == ADC_CHANNEL_19) || \ 1065 ((CHANNEL) == ADC_CHANNEL_20) || \ 1066 ((CHANNEL) == ADC_CHANNEL_21) || \ 1067 ((CHANNEL) == ADC_CHANNEL_22) || \ 1068 ((CHANNEL) == ADC_CHANNEL_23) || \ 1069 ((CHANNEL) == ADC_CHANNEL_24) || \ 1070 ((CHANNEL) == ADC_CHANNEL_25) || \ 1071 ((CHANNEL) == ADC_CHANNEL_26) ) 1072 #endif /* STM32L100xB || STM32L151xB || STM32L152xB || STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC */ 1073 #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) 1074 #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \ 1075 ((CHANNEL) == ADC_CHANNEL_1) || \ 1076 ((CHANNEL) == ADC_CHANNEL_2) || \ 1077 ((CHANNEL) == ADC_CHANNEL_3) || \ 1078 ((CHANNEL) == ADC_CHANNEL_4) || \ 1079 ((CHANNEL) == ADC_CHANNEL_5) || \ 1080 ((CHANNEL) == ADC_CHANNEL_6) || \ 1081 ((CHANNEL) == ADC_CHANNEL_7) || \ 1082 ((CHANNEL) == ADC_CHANNEL_8) || \ 1083 ((CHANNEL) == ADC_CHANNEL_9) || \ 1084 ((CHANNEL) == ADC_CHANNEL_10) || \ 1085 ((CHANNEL) == ADC_CHANNEL_11) || \ 1086 ((CHANNEL) == ADC_CHANNEL_12) || \ 1087 ((CHANNEL) == ADC_CHANNEL_13) || \ 1088 ((CHANNEL) == ADC_CHANNEL_14) || \ 1089 ((CHANNEL) == ADC_CHANNEL_15) || \ 1090 ((CHANNEL) == ADC_CHANNEL_16) || \ 1091 ((CHANNEL) == ADC_CHANNEL_17) || \ 1092 ((CHANNEL) == ADC_CHANNEL_18) || \ 1093 ((CHANNEL) == ADC_CHANNEL_19) || \ 1094 ((CHANNEL) == ADC_CHANNEL_20) || \ 1095 ((CHANNEL) == ADC_CHANNEL_21) || \ 1096 ((CHANNEL) == ADC_CHANNEL_22) || \ 1097 ((CHANNEL) == ADC_CHANNEL_23) || \ 1098 ((CHANNEL) == ADC_CHANNEL_24) || \ 1099 ((CHANNEL) == ADC_CHANNEL_25) || \ 1100 ((CHANNEL) == ADC_CHANNEL_26) || \ 1101 ((CHANNEL) == ADC_CHANNEL_27) || \ 1102 ((CHANNEL) == ADC_CHANNEL_28) || \ 1103 ((CHANNEL) == ADC_CHANNEL_29) || \ 1104 ((CHANNEL) == ADC_CHANNEL_30) || \ 1105 ((CHANNEL) == ADC_CHANNEL_31) ) 1106 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 1107 1108 #define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_4CYCLES) || \ 1109 ((TIME) == ADC_SAMPLETIME_9CYCLES) || \ 1110 ((TIME) == ADC_SAMPLETIME_16CYCLES) || \ 1111 ((TIME) == ADC_SAMPLETIME_24CYCLES) || \ 1112 ((TIME) == ADC_SAMPLETIME_48CYCLES) || \ 1113 ((TIME) == ADC_SAMPLETIME_96CYCLES) || \ 1114 ((TIME) == ADC_SAMPLETIME_192CYCLES) || \ 1115 ((TIME) == ADC_SAMPLETIME_384CYCLES) ) 1116 1117 #if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) 1118 1119 #define IS_ADC_REGULAR_RANK(CHANNEL) (((CHANNEL) == ADC_REGULAR_RANK_1 ) || \ 1120 ((CHANNEL) == ADC_REGULAR_RANK_2 ) || \ 1121 ((CHANNEL) == ADC_REGULAR_RANK_3 ) || \ 1122 ((CHANNEL) == ADC_REGULAR_RANK_4 ) || \ 1123 ((CHANNEL) == ADC_REGULAR_RANK_5 ) || \ 1124 ((CHANNEL) == ADC_REGULAR_RANK_6 ) || \ 1125 ((CHANNEL) == ADC_REGULAR_RANK_7 ) || \ 1126 ((CHANNEL) == ADC_REGULAR_RANK_8 ) || \ 1127 ((CHANNEL) == ADC_REGULAR_RANK_9 ) || \ 1128 ((CHANNEL) == ADC_REGULAR_RANK_10) || \ 1129 ((CHANNEL) == ADC_REGULAR_RANK_11) || \ 1130 ((CHANNEL) == ADC_REGULAR_RANK_12) || \ 1131 ((CHANNEL) == ADC_REGULAR_RANK_13) || \ 1132 ((CHANNEL) == ADC_REGULAR_RANK_14) || \ 1133 ((CHANNEL) == ADC_REGULAR_RANK_15) || \ 1134 ((CHANNEL) == ADC_REGULAR_RANK_16) || \ 1135 ((CHANNEL) == ADC_REGULAR_RANK_17) || \ 1136 ((CHANNEL) == ADC_REGULAR_RANK_18) || \ 1137 ((CHANNEL) == ADC_REGULAR_RANK_19) || \ 1138 ((CHANNEL) == ADC_REGULAR_RANK_20) || \ 1139 ((CHANNEL) == ADC_REGULAR_RANK_21) || \ 1140 ((CHANNEL) == ADC_REGULAR_RANK_22) || \ 1141 ((CHANNEL) == ADC_REGULAR_RANK_23) || \ 1142 ((CHANNEL) == ADC_REGULAR_RANK_24) || \ 1143 ((CHANNEL) == ADC_REGULAR_RANK_25) || \ 1144 ((CHANNEL) == ADC_REGULAR_RANK_26) || \ 1145 ((CHANNEL) == ADC_REGULAR_RANK_27) || \ 1146 ((CHANNEL) == ADC_REGULAR_RANK_28) ) 1147 #else 1148 1149 #define IS_ADC_REGULAR_RANK(CHANNEL) (((CHANNEL) == ADC_REGULAR_RANK_1 ) || \ 1150 ((CHANNEL) == ADC_REGULAR_RANK_2 ) || \ 1151 ((CHANNEL) == ADC_REGULAR_RANK_3 ) || \ 1152 ((CHANNEL) == ADC_REGULAR_RANK_4 ) || \ 1153 ((CHANNEL) == ADC_REGULAR_RANK_5 ) || \ 1154 ((CHANNEL) == ADC_REGULAR_RANK_6 ) || \ 1155 ((CHANNEL) == ADC_REGULAR_RANK_7 ) || \ 1156 ((CHANNEL) == ADC_REGULAR_RANK_8 ) || \ 1157 ((CHANNEL) == ADC_REGULAR_RANK_9 ) || \ 1158 ((CHANNEL) == ADC_REGULAR_RANK_10) || \ 1159 ((CHANNEL) == ADC_REGULAR_RANK_11) || \ 1160 ((CHANNEL) == ADC_REGULAR_RANK_12) || \ 1161 ((CHANNEL) == ADC_REGULAR_RANK_13) || \ 1162 ((CHANNEL) == ADC_REGULAR_RANK_14) || \ 1163 ((CHANNEL) == ADC_REGULAR_RANK_15) || \ 1164 ((CHANNEL) == ADC_REGULAR_RANK_16) || \ 1165 ((CHANNEL) == ADC_REGULAR_RANK_17) || \ 1166 ((CHANNEL) == ADC_REGULAR_RANK_18) || \ 1167 ((CHANNEL) == ADC_REGULAR_RANK_19) || \ 1168 ((CHANNEL) == ADC_REGULAR_RANK_20) || \ 1169 ((CHANNEL) == ADC_REGULAR_RANK_21) || \ 1170 ((CHANNEL) == ADC_REGULAR_RANK_22) || \ 1171 ((CHANNEL) == ADC_REGULAR_RANK_23) || \ 1172 ((CHANNEL) == ADC_REGULAR_RANK_24) || \ 1173 ((CHANNEL) == ADC_REGULAR_RANK_25) || \ 1174 ((CHANNEL) == ADC_REGULAR_RANK_26) || \ 1175 ((CHANNEL) == ADC_REGULAR_RANK_27) ) 1176 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 1177 1178 #define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE) || \ 1179 ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \ 1180 ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \ 1181 ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \ 1182 ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) || \ 1183 ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \ 1184 ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) ) 1185 1186 #define IS_ADC_CONVERSION_GROUP(CONVERSION) (((CONVERSION) == ADC_REGULAR_GROUP) || \ 1187 ((CONVERSION) == ADC_INJECTED_GROUP) || \ 1188 ((CONVERSION) == ADC_REGULAR_INJECTED_GROUP) ) 1189 1190 #define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_AWD_EVENT) || \ 1191 ((EVENT) == ADC_FLAG_OVR) ) 1192 1193 /** 1194 * @brief Verify that a ADC data is within range corresponding to 1195 * ADC resolution. 1196 * @param __RESOLUTION__: ADC resolution (12, 10, 8 or 6 bits). 1197 * @param __ADC_DATA__: value checked against the resolution. 1198 * @retval SET: ADC data is within range corresponding to ADC resolution 1199 * RESET: ADC data is not within range corresponding to ADC resolution 1200 * 1201 */ 1202 #define IS_ADC_RANGE(__RESOLUTION__, __ADC_DATA__) \ 1203 ((((__RESOLUTION__) == ADC_RESOLUTION_12B) && ((__ADC_DATA__) <= ((uint32_t)0x0FFF))) || \ 1204 (((__RESOLUTION__) == ADC_RESOLUTION_10B) && ((__ADC_DATA__) <= ((uint32_t)0x03FF))) || \ 1205 (((__RESOLUTION__) == ADC_RESOLUTION_8B) && ((__ADC_DATA__) <= ((uint32_t)0x00FF))) || \ 1206 (((__RESOLUTION__) == ADC_RESOLUTION_6B) && ((__ADC_DATA__) <= ((uint32_t)0x003F))) ) 1207 1208 1209 #if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) 1210 #define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)28))) 1211 #else 1212 #define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)27))) 1213 #endif 1214 1215 #define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= ((uint32_t)1)) && ((NUMBER) <= ((uint32_t)8))) 1216 1217 /** 1218 * @} 1219 */ 1220 1221 1222 /* Include ADC HAL Extension module */ 1223 #include "stm32l1xx_hal_adc_ex.h" 1224 1225 /* Exported functions --------------------------------------------------------*/ 1226 /** @addtogroup ADC_Exported_Functions 1227 * @{ 1228 */ 1229 1230 /** @addtogroup ADC_Exported_Functions_Group1 1231 * @{ 1232 */ 1233 1234 1235 /* Initialization and de-initialization functions **********************************/ 1236 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc); 1237 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc); 1238 void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc); 1239 void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc); 1240 /** 1241 * @} 1242 */ 1243 1244 /* IO operation functions *****************************************************/ 1245 1246 /** @addtogroup ADC_Exported_Functions_Group2 1247 * @{ 1248 */ 1249 1250 1251 /* Blocking mode: Polling */ 1252 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc); 1253 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc); 1254 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout); 1255 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout); 1256 1257 /* Non-blocking mode: Interruption */ 1258 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc); 1259 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc); 1260 1261 /* Non-blocking mode: DMA */ 1262 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length); 1263 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc); 1264 1265 /* ADC retrieve conversion value intended to be used with polling or interruption */ 1266 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc); 1267 1268 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */ 1269 void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc); 1270 void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc); 1271 void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc); 1272 void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc); 1273 void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); 1274 /** 1275 * @} 1276 */ 1277 1278 1279 /* Peripheral Control functions ***********************************************/ 1280 /** @addtogroup ADC_Exported_Functions_Group3 1281 * @{ 1282 */ 1283 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig); 1284 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig); 1285 /** 1286 * @} 1287 */ 1288 1289 1290 /* Peripheral State functions *************************************************/ 1291 /** @addtogroup ADC_Exported_Functions_Group4 1292 * @{ 1293 */ 1294 uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc); 1295 uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); 1296 /** 1297 * @} 1298 */ 1299 1300 1301 /** 1302 * @} 1303 */ 1304 1305 1306 /* Internal HAL driver functions **********************************************/ 1307 /** @addtogroup ADC_Private_Functions 1308 * @{ 1309 */ 1310 1311 HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc); 1312 HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc); 1313 /** 1314 * @} 1315 */ 1316 1317 1318 /** 1319 * @} 1320 */ 1321 1322 /** 1323 * @} 1324 */ 1325 1326 #ifdef __cplusplus 1327 } 1328 #endif 1329 1330 1331 #endif /* __STM32L1xx_HAL_ADC_H */ 1332 1333 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 1334