1 /** 2 ****************************************************************************** 3 * @file stm32l1xx_hal_adc_ex.h 4 * @author MCD Application Team 5 * @version V1.2.0 6 * @date 01-July-2016 7 * @brief Header file of ADC HAL Extension module. 8 ****************************************************************************** 9 * @attention 10 * 11 * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> 12 * 13 * Redistribution and use in source and binary forms, with or without modification, 14 * are permitted provided that the following conditions are met: 15 * 1. Redistributions of source code must retain the above copyright notice, 16 * this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright notice, 18 * this list of conditions and the following disclaimer in the documentation 19 * and/or other materials provided with the distribution. 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 ****************************************************************************** 36 */ 37 38 /* Define to prevent recursive inclusion -------------------------------------*/ 39 #ifndef __STM32L1xx_HAL_ADC_EX_H 40 #define __STM32L1xx_HAL_ADC_EX_H 41 42 #ifdef __cplusplus 43 extern "C" { 44 #endif 45 46 /* Includes ------------------------------------------------------------------*/ 47 #include "stm32l1xx_hal_def.h" 48 49 /** @addtogroup STM32L1xx_HAL_Driver 50 * @{ 51 */ 52 53 /** @addtogroup ADCEx 54 * @{ 55 */ 56 57 /* Exported types ------------------------------------------------------------*/ 58 /** @defgroup ADCEx_Exported_Types ADCEx Exported Types 59 * @{ 60 */ 61 62 /** 63 * @brief ADC Configuration injected Channel structure definition 64 * @note Parameters of this structure are shared within 2 scopes: 65 * - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime, InjectedOffset 66 * - Scope injected group (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode, 67 * AutoInjectedConv, ExternalTrigInjecConvEdge, ExternalTrigInjecConv. 68 * @note The setting of these parameters with function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state. 69 * ADC state can be either: 70 * - For all parameters: ADC disabled 71 * - For all except parameters 'InjectedDiscontinuousConvMode' and 'AutoInjectedConv': ADC enabled without conversion on going on injected group. 72 * - For parameters 'ExternalTrigInjecConv' and 'ExternalTrigInjecConvEdge': ADC enabled, even with conversion on going on injected group. 73 */ 74 typedef struct 75 { 76 uint32_t InjectedChannel; /*!< Selection of ADC channel to configure 77 This parameter can be a value of @ref ADC_channels 78 Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */ 79 uint32_t InjectedRank; /*!< Rank in the injected group sequencer 80 This parameter must be a value of @ref ADCEx_injected_rank 81 Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */ 82 uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel. 83 Unit: ADC clock cycles 84 Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits). 85 This parameter can be a value of @ref ADC_sampling_times 86 Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups. 87 If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting. 88 Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), 89 sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) 90 Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */ 91 uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data (for channels set on injected group only). 92 Offset value must be a positive number. 93 Depending of ADC resolution selected (12, 10, 8 or 6 bits), 94 this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */ 95 uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the injected group sequencer. 96 To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. 97 This parameter must be a number between Min_Data = 1 and Max_Data = 4. 98 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 99 configure a channel on injected group can impact the configuration of other channels previously set. */ 100 uint32_t InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). 101 Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. 102 Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. 103 This parameter can be set to ENABLE or DISABLE. 104 Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one. 105 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 106 configure a channel on injected group can impact the configuration of other channels previously set. */ 107 uint32_t AutoInjectedConv; /*!< Enables or disables the selected ADC automatic injected group conversion after regular one 108 This parameter can be set to ENABLE or DISABLE. 109 Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE) 110 Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_SOFTWARE_START) 111 Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete. 112 To maintain JAUTO always enabled, DMA must be configured in circular mode. 113 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 114 configure a channel on injected group can impact the configuration of other channels previously set. */ 115 uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group. 116 If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled. 117 If set to external trigger source, triggering is on event rising edge. 118 This parameter can be a value of @ref ADCEx_External_trigger_source_Injected 119 Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). 120 If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly) 121 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 122 configure a channel on injected group can impact the configuration of other channels previously set. */ 123 uint32_t ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of injected group. 124 This parameter can be a value of @ref ADCEx_External_trigger_edge_Injected. 125 If trigger is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded. 126 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 127 configure a channel on injected group can impact the configuration of other channels previously set. */ 128 }ADC_InjectionConfTypeDef; 129 /** 130 * @} 131 */ 132 133 134 /* Exported constants --------------------------------------------------------*/ 135 136 /** @defgroup ADCEx_Exported_Constants ADCEx Exported Constants 137 * @{ 138 */ 139 140 /** @defgroup ADCEx_injected_rank ADCEx rank into injected group 141 * @{ 142 */ 143 #define ADC_INJECTED_RANK_1 ((uint32_t)0x00000001) 144 #define ADC_INJECTED_RANK_2 ((uint32_t)0x00000002) 145 #define ADC_INJECTED_RANK_3 ((uint32_t)0x00000003) 146 #define ADC_INJECTED_RANK_4 ((uint32_t)0x00000004) 147 /** 148 * @} 149 */ 150 151 /** @defgroup ADCEx_External_trigger_edge_Injected ADCEx external trigger enable for injected group 152 * @{ 153 */ 154 #define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE ((uint32_t)0x00000000) 155 #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING ((uint32_t)ADC_CR2_JEXTEN_0) 156 #define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING ((uint32_t)ADC_CR2_JEXTEN_1) 157 #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING ((uint32_t)ADC_CR2_JEXTEN) 158 /** 159 * @} 160 */ 161 162 /** @defgroup ADCEx_External_trigger_source_Injected ADCEx External trigger source Injected 163 * @{ 164 */ 165 /* External triggers for injected groups of ADC1 */ 166 #define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ADC_EXTERNALTRIGINJEC_T2_CC1 167 #define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ADC_EXTERNALTRIGINJEC_T2_TRGO 168 #define ADC_EXTERNALTRIGINJECCONV_T3_CC4 ADC_EXTERNALTRIGINJEC_T3_CC4 169 #define ADC_EXTERNALTRIGINJECCONV_T4_TRGO ADC_EXTERNALTRIGINJEC_T4_TRGO 170 #define ADC_EXTERNALTRIGINJECCONV_T4_CC1 ADC_EXTERNALTRIGINJEC_T4_CC1 171 #define ADC_EXTERNALTRIGINJECCONV_T4_CC2 ADC_EXTERNALTRIGINJEC_T4_CC2 172 #define ADC_EXTERNALTRIGINJECCONV_T4_CC3 ADC_EXTERNALTRIGINJEC_T4_CC3 173 #define ADC_EXTERNALTRIGINJECCONV_T7_TRGO ADC_EXTERNALTRIGINJEC_T7_TRGO 174 #define ADC_EXTERNALTRIGINJECCONV_T9_CC1 ADC_EXTERNALTRIGINJEC_T9_CC1 175 #define ADC_EXTERNALTRIGINJECCONV_T9_TRGO ADC_EXTERNALTRIGINJEC_T9_TRGO 176 #define ADC_EXTERNALTRIGINJECCONV_T10_CC1 ADC_EXTERNALTRIGINJEC_T10_CC1 177 #define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ADC_EXTERNALTRIGINJEC_EXT_IT15 178 #define ADC_INJECTED_SOFTWARE_START ((uint32_t)0x00000010) 179 /** 180 * @} 181 */ 182 183 /** 184 * @} 185 */ 186 187 188 /* Private constants ---------------------------------------------------------*/ 189 190 /** @addtogroup ADCEx_Private_Constants ADCEx Private Constants 191 * @{ 192 */ 193 194 /** @defgroup ADCEx_Internal_HAL_driver_Ext_trig_src_Injected ADCEx Internal HAL driver Ext trig src Injected 195 * @{ 196 */ 197 198 /* List of external triggers of injected group for ADC1: */ 199 /* (used internally by HAL driver. To not use into HAL structure parameters) */ 200 #define ADC_EXTERNALTRIGINJEC_T9_CC1 ((uint32_t) 0x00000000) 201 #define ADC_EXTERNALTRIGINJEC_T9_TRGO ((uint32_t)( ADC_CR2_JEXTSEL_0)) 202 #define ADC_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)( ADC_CR2_JEXTSEL_1 )) 203 #define ADC_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)( ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0)) 204 #define ADC_EXTERNALTRIGINJEC_T3_CC4 ((uint32_t)( ADC_CR2_JEXTSEL_2 )) 205 #define ADC_EXTERNALTRIGINJEC_T4_TRGO ((uint32_t)( ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0)) 206 #define ADC_EXTERNALTRIGINJEC_T4_CC1 ((uint32_t)( ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 )) 207 #define ADC_EXTERNALTRIGINJEC_T4_CC2 ((uint32_t)( ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0)) 208 #define ADC_EXTERNALTRIGINJEC_T4_CC3 ((uint32_t)(ADC_CR2_JEXTSEL_3 )) 209 #define ADC_EXTERNALTRIGINJEC_T10_CC1 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_0)) 210 #define ADC_EXTERNALTRIGINJEC_T7_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 )) 211 #define ADC_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0)) 212 /** 213 * @} 214 */ 215 216 /** 217 * @} 218 */ 219 220 221 /* Exported macro ------------------------------------------------------------*/ 222 223 /** @defgroup ADCEx_Exported_Macros ADCEx Exported Macros 224 * @{ 225 */ 226 /* Macro for internal HAL driver usage, and possibly can be used into code of */ 227 /* final user. */ 228 229 /** 230 * @brief Selection of channels bank. 231 * Note: Banks availability depends on devices categories. 232 * This macro is intended to change bank selection quickly on the fly, 233 * without going through ADC init structure update and execution of function 234 * 'HAL_ADC_Init()'. 235 * @param __HANDLE__: ADC handle 236 * @param __BANK__: Bank selection. This parameter can be a value of @ref ADC_ChannelsBank. 237 * @retval None 238 */ 239 #define __HAL_ADC_CHANNELS_BANK(__HANDLE__, __BANK__) \ 240 MODIFY_REG((__HANDLE__)->Instance->CR2, ADC_CR2_CFG, (__BANK__)) 241 242 #if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) 243 /** 244 * @brief Configures the ADC channels speed. 245 * Limited to channels 3, 8, 13 and to devices category Cat.3, Cat.4, Cat.5. 246 * - For ADC_CHANNEL_3: Used as ADC direct channel (fast channel) if OPAMP1 is 247 * in power down mode. 248 * - For ADC_CHANNEL_8: Used as ADC direct channel (fast channel) if OPAMP2 is 249 * in power down mode. 250 * - For ADC_CHANNEL_13: Used as ADC re-routed channel if OPAMP3 is in 251 * power down mode. Otherwise, channel 13 is connected to OPAMP3 output and 252 * routed through switches COMP1_SW1 and VCOMP to ADC switch matrix. 253 * (Note: OPAMP3 is available on STM32L1 Cat.4 only). 254 * @param __CHANNEL__: ADC channel 255 * This parameter can be one of the following values: 256 * @arg ADC_CHANNEL_3: Channel 3 is selected. 257 * @arg ADC_CHANNEL_8: Channel 8 is selected. 258 * @arg ADC_CHANNEL_13: Channel 13 is selected. 259 * @retval None 260 */ 261 #define __HAL_ADC_CHANNEL_SPEED_FAST(__CHANNEL__) \ 262 ( ( ((__CHANNEL__) == ADC_CHANNEL_3) \ 263 )? \ 264 (SET_BIT(COMP->CSR, COMP_CSR_FCH3)) \ 265 : \ 266 ( ( ((__CHANNEL__) == ADC_CHANNEL_8) \ 267 )? \ 268 (SET_BIT(COMP->CSR, COMP_CSR_FCH8)) \ 269 : \ 270 ( ( ((__CHANNEL__) == ADC_CHANNEL_13) \ 271 )? \ 272 (SET_BIT(COMP->CSR, COMP_CSR_RCH13)) \ 273 : \ 274 (SET_BIT(COMP->CSR, 0x00000000)) \ 275 ) \ 276 ) \ 277 ) 278 279 #define __HAL_ADC_CHANNEL_SPEED_SLOW(__CHANNEL__) \ 280 ( ( ((__CHANNEL__) == ADC_CHANNEL_3) \ 281 )? \ 282 (CLEAR_BIT(COMP->CSR, COMP_CSR_FCH3)) \ 283 : \ 284 ( ( ((__CHANNEL__) == ADC_CHANNEL_8) \ 285 )? \ 286 (CLEAR_BIT(COMP->CSR, COMP_CSR_FCH8)) \ 287 : \ 288 ( ( ((__CHANNEL__) == ADC_CHANNEL_13) \ 289 )? \ 290 (CLEAR_BIT(COMP->CSR, COMP_CSR_RCH13)) \ 291 : \ 292 (SET_BIT(COMP->CSR, 0x00000000)) \ 293 ) \ 294 ) \ 295 ) 296 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 297 298 /** 299 * @} 300 */ 301 302 /* Private macro ------------------------------------------------------------*/ 303 304 /** @defgroup ADCEx_Private_Macro ADCEx Private Macro 305 * @{ 306 */ 307 /* Macro reserved for internal HAL driver usage, not intended to be used in */ 308 /* code of final user. */ 309 310 /** 311 * @brief Set ADC ranks available in register SQR1. 312 * Register SQR1 bits availability depends on device category. 313 * @param _NbrOfConversion_: Regular channel sequence length 314 * @retval None 315 */ 316 #if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) 317 #define __ADC_SQR1_SQXX (ADC_SQR1_SQ28 | ADC_SQR1_SQ27 | ADC_SQR1_SQ26 | ADC_SQR1_SQ25) 318 #else 319 #define __ADC_SQR1_SQXX (ADC_SQR1_SQ27 | ADC_SQR1_SQ26 | ADC_SQR1_SQ25) 320 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 321 322 /** 323 * @brief Set the ADC's sample time for channel numbers between 30 and 31. 324 * Register SMPR0 availability depends on device category. If register is not 325 * available on the current device, this macro does nothing. 326 * @retval None 327 * @param _SAMPLETIME_: Sample time parameter. 328 * @param _CHANNELNB_: Channel number. 329 * @retval None 330 */ 331 #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) 332 #define ADC_SMPR0(_SAMPLETIME_, _CHANNELNB_) \ 333 ((_SAMPLETIME_) << (3 * ((_CHANNELNB_) - 30))) 334 #else 335 #define ADC_SMPR0(_SAMPLETIME_, _CHANNELNB_) \ 336 ((uint32_t)0x00000000) 337 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 338 339 #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) 340 /** 341 * @brief Set the ADC's sample time for channel numbers between 20 and 29. 342 * @param _SAMPLETIME_: Sample time parameter. 343 * @param _CHANNELNB_: Channel number. 344 * @retval None 345 */ 346 #define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) \ 347 ((_SAMPLETIME_) << (3 * ((_CHANNELNB_) - 20))) 348 #else 349 /** 350 * @brief Set the ADC's sample time for channel numbers between 20 and 26. 351 * @param _SAMPLETIME_: Sample time parameter. 352 * @param _CHANNELNB_: Channel number. 353 * @retval None 354 */ 355 #define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) \ 356 ((_SAMPLETIME_) << (3 * ((_CHANNELNB_) - 20))) 357 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 358 359 /** 360 * @brief Defines the highest channel available in register SMPR1. Channels 361 * availability depends on device category: 362 * Highest channel in register SMPR1 is channel 26 for devices Cat.1, Cat.2, Cat.3 363 * Highest channel in register SMPR1 is channel 29 for devices Cat.4, Cat.5 364 * @param None 365 * @retval None 366 */ 367 #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) 368 #define ADC_SMPR1_CHANNEL_MAX ADC_CHANNEL_29 369 #else 370 #define ADC_SMPR1_CHANNEL_MAX ADC_CHANNEL_26 371 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 372 373 374 /** 375 * @brief Define mask of configuration bits of ADC and regular group in 376 * register CR2 (bits of ADC enable, conversion start and injected group are 377 * excluded of this mask). 378 * @retval None 379 */ 380 #if defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) 381 #define ADC_CR2_MASK_ADCINIT() \ 382 (ADC_CR2_EXTEN | ADC_CR2_EXTSEL | ADC_CR2_ALIGN | ADC_CR2_EOCS | ADC_CR2_DDS | ADC_CR2_DELS | ADC_CR2_CFG | ADC_CR2_CONT) 383 #else 384 #define ADC_CR2_MASK_ADCINIT() \ 385 (ADC_CR2_EXTEN | ADC_CR2_EXTSEL | ADC_CR2_ALIGN | ADC_CR2_EOCS | ADC_CR2_DDS | ADC_CR2_DELS | ADC_CR2_CONT) 386 #endif 387 388 389 /** 390 * @brief Get the maximum ADC conversion cycles on all channels. 391 * Returns the selected sampling time + conversion time (12.5 ADC clock cycles) 392 * Approximation of sampling time within 2 ranges, returns the highest value: 393 * below 24 cycles {4 cycles; 9 cycles; 16 cycles; 24 cycles} 394 * between 48 cycles and 384 cycles {48 cycles; 96 cycles; 192 cycles; 384 cycles} 395 * Unit: ADC clock cycles 396 * @param __HANDLE__: ADC handle 397 * @retval ADC conversion cycles on all channels 398 */ 399 #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) 400 #define ADC_CONVCYCLES_MAX_RANGE(__HANDLE__) \ 401 (( (((__HANDLE__)->Instance->SMPR3 & ADC_SAMPLETIME_ALLCHANNELS_SMPR3BIT2) == RESET) && \ 402 (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2) == RESET) && \ 403 (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2) == RESET) && \ 404 (((__HANDLE__)->Instance->SMPR0 & ADC_SAMPLETIME_ALLCHANNELS_SMPR0BIT2) == RESET) ) ? \ 405 \ 406 ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_24CYCLES : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_384CYCLES \ 407 ) 408 #else 409 #define ADC_CONVCYCLES_MAX_RANGE(__HANDLE__) \ 410 (( (((__HANDLE__)->Instance->SMPR3 & ADC_SAMPLETIME_ALLCHANNELS_SMPR3BIT2) == RESET) && \ 411 (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2) == RESET) && \ 412 (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2) == RESET) ) ? \ 413 \ 414 ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_24CYCLES : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_384CYCLES \ 415 ) 416 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 417 418 /** 419 * @brief Get the ADC clock prescaler from ADC common control register 420 * and convert it to its decimal number setting (refer to reference manual) 421 * @retval None 422 */ 423 #define ADC_GET_CLOCK_PRESCALER_DECIMAL(__HANDLE__) \ 424 ((0x01) << ((ADC->CCR & ADC_CCR_ADCPRE) >> POSITION_VAL(ADC_CCR_ADCPRE))) 425 426 /** 427 * @brief Clear register SMPR0. 428 * Register SMPR0 availability depends on device category. If register is not 429 * available on the current device, this macro performs no action. 430 * @param __HANDLE__: ADC handle 431 * @retval None 432 */ 433 #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) 434 #define ADC_SMPR1_CLEAR(__HANDLE__) \ 435 CLEAR_BIT((__HANDLE__)->Instance->SMPR1, (ADC_SMPR1_SMP29 | ADC_SMPR1_SMP28 | ADC_SMPR1_SMP27 | \ 436 ADC_SMPR1_SMP26 | ADC_SMPR1_SMP25 | ADC_SMPR1_SMP24 | \ 437 ADC_SMPR1_SMP23 | ADC_SMPR1_SMP22 | ADC_SMPR1_SMP21 | \ 438 ADC_SMPR1_SMP20 )) 439 440 #define ADC_SMPR0_CLEAR(__HANDLE__) \ 441 (CLEAR_BIT((__HANDLE__)->Instance->SMPR0, (ADC_SMPR0_SMP31 | ADC_SMPR0_SMP30))) 442 #else 443 #define ADC_SMPR1_CLEAR(__HANDLE__) \ 444 CLEAR_BIT((__HANDLE__)->Instance->SMPR1, (ADC_SMPR1_SMP26 | ADC_SMPR1_SMP25 | ADC_SMPR1_SMP24 | \ 445 ADC_SMPR1_SMP23 | ADC_SMPR1_SMP22 | ADC_SMPR1_SMP21 | \ 446 ADC_SMPR1_SMP20 )) 447 448 #define ADC_SMPR0_CLEAR(__HANDLE__) __NOP() 449 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 450 451 /** 452 * @brief Clear register CR2. 453 * @param __HANDLE__: ADC handle 454 * @retval None 455 */ 456 #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) 457 #define ADC_CR2_CLEAR(__HANDLE__) \ 458 (CLEAR_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTEN | ADC_CR2_EXTSEL | \ 459 ADC_CR2_JSWSTART | ADC_CR2_JEXTEN | ADC_CR2_JEXTSEL | \ 460 ADC_CR2_ALIGN | ADC_CR2_EOCS | ADC_CR2_DDS | \ 461 ADC_CR2_DMA | ADC_CR2_DELS | ADC_CR2_CFG | \ 462 ADC_CR2_CONT | ADC_CR2_ADON )) \ 463 ) 464 #else 465 #define ADC_CR2_CLEAR(__HANDLE__) \ 466 (CLEAR_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTEN | ADC_CR2_EXTSEL | \ 467 ADC_CR2_JSWSTART | ADC_CR2_JEXTEN | ADC_CR2_JEXTSEL | \ 468 ADC_CR2_ALIGN | ADC_CR2_EOCS | ADC_CR2_DDS | \ 469 ADC_CR2_DMA | ADC_CR2_DELS | \ 470 ADC_CR2_CONT | ADC_CR2_ADON )) \ 471 ) 472 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 473 474 /** 475 * @brief Set the sampling time of selected channel on register SMPR0 476 * Register SMPR0 availability depends on device category. If register is not 477 * available on the current device, this macro performs no action. 478 * @param __HANDLE__: ADC handle 479 * @param _SAMPLETIME_: Sample time parameter. 480 * @param __CHANNEL__: Channel number. 481 * @retval None 482 */ 483 #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) 484 #define ADC_SMPR0_CHANNEL_SET(__HANDLE__, _SAMPLETIME_, __CHANNEL__) \ 485 MODIFY_REG((__HANDLE__)->Instance->SMPR0, \ 486 ADC_SMPR0(ADC_SMPR0_SMP30, (__CHANNEL__)), \ 487 ADC_SMPR0((_SAMPLETIME_), (__CHANNEL__)) ) 488 #else 489 #define ADC_SMPR0_CHANNEL_SET(__HANDLE__, _SAMPLETIME_, __CHANNEL__) __NOP() 490 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 491 492 493 #define IS_ADC_INJECTED_RANK(CHANNEL) (((CHANNEL) == ADC_INJECTED_RANK_1) || \ 494 ((CHANNEL) == ADC_INJECTED_RANK_2) || \ 495 ((CHANNEL) == ADC_INJECTED_RANK_3) || \ 496 ((CHANNEL) == ADC_INJECTED_RANK_4) ) 497 498 #define IS_ADC_EXTTRIGINJEC_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \ 499 ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING) || \ 500 ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING) || \ 501 ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) ) 502 503 #define IS_ADC_EXTTRIGINJEC(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \ 504 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \ 505 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \ 506 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \ 507 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC1) || \ 508 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC2) || \ 509 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3) || \ 510 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T7_TRGO) || \ 511 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T9_CC1) || \ 512 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T9_TRGO) || \ 513 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T10_CC1) || \ 514 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \ 515 ((REGTRIG) == ADC_SOFTWARE_START) ) 516 517 /** @defgroup ADCEx_injected_nb_conv_verification ADCEx injected nb conv verification 518 * @{ 519 */ 520 #define IS_ADC_INJECTED_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)4))) 521 /** 522 * @} 523 */ 524 525 /** 526 * @} 527 */ 528 529 530 /* Exported functions --------------------------------------------------------*/ 531 /** @addtogroup ADCEx_Exported_Functions 532 * @{ 533 */ 534 535 /* IO operation functions *****************************************************/ 536 /** @addtogroup ADCEx_Exported_Functions_Group1 537 * @{ 538 */ 539 540 /* Blocking mode: Polling */ 541 HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc); 542 HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc); 543 HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout); 544 545 /* Non-blocking mode: Interruption */ 546 HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc); 547 HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc); 548 549 /* ADC retrieve conversion value intended to be used with polling or interruption */ 550 uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank); 551 552 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */ 553 void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc); 554 /** 555 * @} 556 */ 557 558 559 /* Peripheral Control functions ***********************************************/ 560 /** @addtogroup ADCEx_Exported_Functions_Group2 561 * @{ 562 */ 563 564 HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected); 565 /** 566 * @} 567 */ 568 569 570 /** 571 * @} 572 */ 573 574 575 /** 576 * @} 577 */ 578 579 /** 580 * @} 581 */ 582 583 #ifdef __cplusplus 584 } 585 #endif 586 587 #endif /* __STM32L1xx_HAL_ADC_EX_H */ 588 589 590 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 591