1 /**
2 ******************************************************************************
3 * @file stm32l1xx_ll_cortex.h
4 * @author MCD Application Team
5 * @version V1.2.0
6 * @date 01-July-2016
7 * @brief Header file of CORTEX LL module.
8 @verbatim
9 ==============================================================================
10 ##### How to use this driver #####
11 ==============================================================================
12 [..]
13 The LL CORTEX driver contains a set of generic APIs that can be
14 used by user:
15 (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick
16 functions
17 (+) Low power mode configuration (SCB register of Cortex-MCU)
18 (+) MPU API to configure and enable regions
19 (+) API to access to MCU info (CPUID register)
20 (+) API to enable fault handler (SHCSR accesses)
21
22 @endverbatim
23 ******************************************************************************
24 * @attention
25 *
26 * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
27 *
28 * Redistribution and use in source and binary forms, with or without modification,
29 * are permitted provided that the following conditions are met:
30 * 1. Redistributions of source code must retain the above copyright notice,
31 * this list of conditions and the following disclaimer.
32 * 2. Redistributions in binary form must reproduce the above copyright notice,
33 * this list of conditions and the following disclaimer in the documentation
34 * and/or other materials provided with the distribution.
35 * 3. Neither the name of STMicroelectronics nor the names of its contributors
36 * may be used to endorse or promote products derived from this software
37 * without specific prior written permission.
38 *
39 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
40 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
41 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
42 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
43 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
44 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
45 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
46 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
47 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
48 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
49 *
50 ******************************************************************************
51 */
52
53 /* Define to prevent recursive inclusion -------------------------------------*/
54 #ifndef __STM32L1xx_LL_CORTEX_H
55 #define __STM32L1xx_LL_CORTEX_H
56
57 #ifdef __cplusplus
58 extern "C" {
59 #endif
60
61 /* Includes ------------------------------------------------------------------*/
62 #include "stm32l1xx.h"
63
64 /** @addtogroup STM32L1xx_LL_Driver
65 * @{
66 */
67
68 /** @defgroup CORTEX_LL CORTEX
69 * @{
70 */
71
72 /* Private types -------------------------------------------------------------*/
73 /* Private variables ---------------------------------------------------------*/
74
75 /* Private constants ---------------------------------------------------------*/
76
77 /* Private macros ------------------------------------------------------------*/
78
79 /* Exported types ------------------------------------------------------------*/
80 /* Exported constants --------------------------------------------------------*/
81 /** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
82 * @{
83 */
84
85 /** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
86 * @{
87 */
88 #define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000U) /*!< AHB clock divided by 8 selected as SysTick clock source.*/
89 #define LL_SYSTICK_CLKSOURCE_HCLK ((uint32_t)SysTick_CTRL_CLKSOURCE_Msk) /*!< AHB clock selected as SysTick clock source. */
90 /**
91 * @}
92 */
93
94 /** @defgroup CORTEX_LL_EC_FAULT Handler Fault type
95 * @{
96 */
97 #define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */
98 #define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */
99 #define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */
100 /**
101 * @}
102 */
103
104 #if __MPU_PRESENT
105
106 /** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control
107 * @{
108 */
109 #define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000U) /*!< Disable NMI and privileged SW access */
110 #define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
111 #define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */
112 #define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
113 /**
114 * @}
115 */
116
117 /** @defgroup CORTEX_LL_EC_REGION MPU Region Number
118 * @{
119 */
120 #define LL_MPU_REGION_NUMBER0 ((uint32_t)0x00U) /*!< REGION Number 0 */
121 #define LL_MPU_REGION_NUMBER1 ((uint32_t)0x01U) /*!< REGION Number 1 */
122 #define LL_MPU_REGION_NUMBER2 ((uint32_t)0x02U) /*!< REGION Number 2 */
123 #define LL_MPU_REGION_NUMBER3 ((uint32_t)0x03U) /*!< REGION Number 3 */
124 #define LL_MPU_REGION_NUMBER4 ((uint32_t)0x04U) /*!< REGION Number 4 */
125 #define LL_MPU_REGION_NUMBER5 ((uint32_t)0x05U) /*!< REGION Number 5 */
126 #define LL_MPU_REGION_NUMBER6 ((uint32_t)0x06U) /*!< REGION Number 6 */
127 #define LL_MPU_REGION_NUMBER7 ((uint32_t)0x07U) /*!< REGION Number 7 */
128 /**
129 * @}
130 */
131
132 /** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size
133 * @{
134 */
135 #define LL_MPU_REGION_SIZE_32B ((uint32_t)(0x04U << MPU_RASR_SIZE_Pos)) /*!< 32B Size of the MPU protection region */
136 #define LL_MPU_REGION_SIZE_64B ((uint32_t)(0x05U << MPU_RASR_SIZE_Pos)) /*!< 64B Size of the MPU protection region */
137 #define LL_MPU_REGION_SIZE_128B ((uint32_t)(0x06U << MPU_RASR_SIZE_Pos)) /*!< 128B Size of the MPU protection region */
138 #define LL_MPU_REGION_SIZE_256B ((uint32_t)(0x07U << MPU_RASR_SIZE_Pos)) /*!< 256B Size of the MPU protection region */
139 #define LL_MPU_REGION_SIZE_512B ((uint32_t)(0x08U << MPU_RASR_SIZE_Pos)) /*!< 512B Size of the MPU protection region */
140 #define LL_MPU_REGION_SIZE_1KB ((uint32_t)(0x09U << MPU_RASR_SIZE_Pos)) /*!< 1KB Size of the MPU protection region */
141 #define LL_MPU_REGION_SIZE_2KB ((uint32_t)(0x0AU << MPU_RASR_SIZE_Pos)) /*!< 2KB Size of the MPU protection region */
142 #define LL_MPU_REGION_SIZE_4KB ((uint32_t)(0x0BU << MPU_RASR_SIZE_Pos)) /*!< 4KB Size of the MPU protection region */
143 #define LL_MPU_REGION_SIZE_8KB ((uint32_t)(0x0CU << MPU_RASR_SIZE_Pos)) /*!< 8KB Size of the MPU protection region */
144 #define LL_MPU_REGION_SIZE_16KB ((uint32_t)(0x0DU << MPU_RASR_SIZE_Pos)) /*!< 16KB Size of the MPU protection region */
145 #define LL_MPU_REGION_SIZE_32KB ((uint32_t)(0x0EU << MPU_RASR_SIZE_Pos)) /*!< 32KB Size of the MPU protection region */
146 #define LL_MPU_REGION_SIZE_64KB ((uint32_t)(0x0FU << MPU_RASR_SIZE_Pos)) /*!< 64KB Size of the MPU protection region */
147 #define LL_MPU_REGION_SIZE_128KB ((uint32_t)(0x10U << MPU_RASR_SIZE_Pos)) /*!< 128KB Size of the MPU protection region */
148 #define LL_MPU_REGION_SIZE_256KB ((uint32_t)(0x11U << MPU_RASR_SIZE_Pos)) /*!< 256KB Size of the MPU protection region */
149 #define LL_MPU_REGION_SIZE_512KB ((uint32_t)(0x12U << MPU_RASR_SIZE_Pos)) /*!< 512KB Size of the MPU protection region */
150 #define LL_MPU_REGION_SIZE_1MB ((uint32_t)(0x13U << MPU_RASR_SIZE_Pos)) /*!< 1MB Size of the MPU protection region */
151 #define LL_MPU_REGION_SIZE_2MB ((uint32_t)(0x14U << MPU_RASR_SIZE_Pos)) /*!< 2MB Size of the MPU protection region */
152 #define LL_MPU_REGION_SIZE_4MB ((uint32_t)(0x15U << MPU_RASR_SIZE_Pos)) /*!< 4MB Size of the MPU protection region */
153 #define LL_MPU_REGION_SIZE_8MB ((uint32_t)(0x16U << MPU_RASR_SIZE_Pos)) /*!< 8MB Size of the MPU protection region */
154 #define LL_MPU_REGION_SIZE_16MB ((uint32_t)(0x17U << MPU_RASR_SIZE_Pos)) /*!< 16MB Size of the MPU protection region */
155 #define LL_MPU_REGION_SIZE_32MB ((uint32_t)(0x18U << MPU_RASR_SIZE_Pos)) /*!< 32MB Size of the MPU protection region */
156 #define LL_MPU_REGION_SIZE_64MB ((uint32_t)(0x19U << MPU_RASR_SIZE_Pos)) /*!< 64MB Size of the MPU protection region */
157 #define LL_MPU_REGION_SIZE_128MB ((uint32_t)(0x1AU << MPU_RASR_SIZE_Pos)) /*!< 128MB Size of the MPU protection region */
158 #define LL_MPU_REGION_SIZE_256MB ((uint32_t)(0x1BU << MPU_RASR_SIZE_Pos)) /*!< 256MB Size of the MPU protection region */
159 #define LL_MPU_REGION_SIZE_512MB ((uint32_t)(0x1CU << MPU_RASR_SIZE_Pos)) /*!< 512MB Size of the MPU protection region */
160 #define LL_MPU_REGION_SIZE_1GB ((uint32_t)(0x1DU << MPU_RASR_SIZE_Pos)) /*!< 1GB Size of the MPU protection region */
161 #define LL_MPU_REGION_SIZE_2GB ((uint32_t)(0x1EU << MPU_RASR_SIZE_Pos)) /*!< 2GB Size of the MPU protection region */
162 #define LL_MPU_REGION_SIZE_4GB ((uint32_t)(0x1FU << MPU_RASR_SIZE_Pos)) /*!< 4GB Size of the MPU protection region */
163 /**
164 * @}
165 */
166
167 /** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges
168 * @{
169 */
170 #define LL_MPU_REGION_NO_ACCESS ((uint32_t)(0x00U << MPU_RASR_AP_Pos)) /*!< No access*/
171 #define LL_MPU_REGION_PRIV_RW ((uint32_t)(0x01U << MPU_RASR_AP_Pos)) /*!< RW privileged (privileged access only)*/
172 #define LL_MPU_REGION_PRIV_RW_URO ((uint32_t)(0x02U << MPU_RASR_AP_Pos)) /*!< RW privileged - RO user (Write in a user program generates a fault) */
173 #define LL_MPU_REGION_FULL_ACCESS ((uint32_t)(0x03U << MPU_RASR_AP_Pos)) /*!< RW privileged & user (Full access) */
174 #define LL_MPU_REGION_PRIV_RO ((uint32_t)(0x05U << MPU_RASR_AP_Pos)) /*!< RO privileged (privileged read only)*/
175 #define LL_MPU_REGION_PRIV_RO_URO ((uint32_t)(0x06U << MPU_RASR_AP_Pos)) /*!< RO privileged & user (read only) */
176 /**
177 * @}
178 */
179
180 /** @defgroup CORTEX_LL_EC_TEX MPU TEX Level
181 * @{
182 */
183 #define LL_MPU_TEX_LEVEL0 ((uint32_t)(0x00U << MPU_RASR_TEX_Pos)) /*!< b000 for TEX bits */
184 #define LL_MPU_TEX_LEVEL1 ((uint32_t)(0x01U << MPU_RASR_TEX_Pos)) /*!< b001 for TEX bits */
185 #define LL_MPU_TEX_LEVEL2 ((uint32_t)(0x02U << MPU_RASR_TEX_Pos)) /*!< b010 for TEX bits */
186 #define LL_MPU_TEX_LEVEL4 ((uint32_t)(0x04U << MPU_RASR_TEX_Pos)) /*!< b100 for TEX bits */
187 /**
188 * @}
189 */
190
191 /** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access
192 * @{
193 */
194 #define LL_MPU_INSTRUCTION_ACCESS_ENABLE ((uint32_t)0x00U) /*!< Instruction fetches enabled */
195 #define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/
196 /**
197 * @}
198 */
199
200 /** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access
201 * @{
202 */
203 #define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */
204 #define LL_MPU_ACCESS_NOT_SHAREABLE ((uint32_t)0x00U) /*!< Not Shareable memory attribute */
205 /**
206 * @}
207 */
208
209 /** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access
210 * @{
211 */
212 #define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */
213 #define LL_MPU_ACCESS_NOT_CACHEABLE ((uint32_t)0x00U) /*!< Not Cacheable memory attribute */
214 /**
215 * @}
216 */
217
218 /** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access
219 * @{
220 */
221 #define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */
222 #define LL_MPU_ACCESS_NOT_BUFFERABLE ((uint32_t)0x00U) /*!< Not Bufferable memory attribute */
223 /**
224 * @}
225 */
226 #endif /* __MPU_PRESENT */
227 /**
228 * @}
229 */
230
231 /* Exported macro ------------------------------------------------------------*/
232
233 /* Exported functions --------------------------------------------------------*/
234 /** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
235 * @{
236 */
237
238 /** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
239 * @{
240 */
241
242 /**
243 * @brief This function checks if the Systick counter flag is active or not.
244 * @note It can be used in timeout function on application side.
245 * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag
246 * @retval State of bit (1 or 0).
247 */
LL_SYSTICK_IsActiveCounterFlag(void)248 __STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
249 {
250 return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk));
251 }
252
253 /**
254 * @brief Configures the SysTick clock source
255 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource
256 * @param Source This parameter can be one of the following values:
257 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
258 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
259 * @retval None
260 */
LL_SYSTICK_SetClkSource(uint32_t Source)261 __STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
262 {
263 if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
264 {
265 SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
266 }
267 else
268 {
269 CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
270 }
271 }
272
273 /**
274 * @brief Get the SysTick clock source
275 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource
276 * @retval Returned value can be one of the following values:
277 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
278 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
279 */
LL_SYSTICK_GetClkSource(void)280 __STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
281 {
282 return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
283 }
284
285 /**
286 * @brief Enable SysTick exception request
287 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT
288 * @retval None
289 */
LL_SYSTICK_EnableIT(void)290 __STATIC_INLINE void LL_SYSTICK_EnableIT(void)
291 {
292 SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
293 }
294
295 /**
296 * @brief Disable SysTick exception request
297 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT
298 * @retval None
299 */
LL_SYSTICK_DisableIT(void)300 __STATIC_INLINE void LL_SYSTICK_DisableIT(void)
301 {
302 CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
303 }
304
305 /**
306 * @brief Checks if the SYSTICK interrupt is enabled or disabled.
307 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT
308 * @retval State of bit (1 or 0).
309 */
LL_SYSTICK_IsEnabledIT(void)310 __STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
311 {
312 return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk));
313 }
314
315 /**
316 * @}
317 */
318
319 /** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
320 * @{
321 */
322
323 /**
324 * @brief Processor uses sleep as its low power mode
325 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
326 * @retval None
327 */
LL_LPM_EnableSleep(void)328 __STATIC_INLINE void LL_LPM_EnableSleep(void)
329 {
330 /* Clear SLEEPDEEP bit of Cortex System Control Register */
331 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
332 }
333
334 /**
335 * @brief Processor uses deep sleep as its low power mode
336 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep
337 * @retval None
338 */
LL_LPM_EnableDeepSleep(void)339 __STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
340 {
341 /* Set SLEEPDEEP bit of Cortex System Control Register */
342 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
343 }
344
345 /**
346 * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode.
347 * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
348 * empty main application.
349 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit
350 * @retval None
351 */
LL_LPM_EnableSleepOnExit(void)352 __STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
353 {
354 /* Set SLEEPONEXIT bit of Cortex System Control Register */
355 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
356 }
357
358 /**
359 * @brief Do not sleep when returning to Thread mode.
360 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit
361 * @retval None
362 */
LL_LPM_DisableSleepOnExit(void)363 __STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
364 {
365 /* Clear SLEEPONEXIT bit of Cortex System Control Register */
366 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
367 }
368
369 /**
370 * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the
371 * processor.
372 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend
373 * @retval None
374 */
LL_LPM_EnableEventOnPend(void)375 __STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
376 {
377 /* Set SEVEONPEND bit of Cortex System Control Register */
378 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
379 }
380
381 /**
382 * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are
383 * excluded
384 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend
385 * @retval None
386 */
LL_LPM_DisableEventOnPend(void)387 __STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
388 {
389 /* Clear SEVEONPEND bit of Cortex System Control Register */
390 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
391 }
392
393 /**
394 * @}
395 */
396
397 /** @defgroup CORTEX_LL_EF_HANDLER HANDLER
398 * @{
399 */
400
401 /**
402 * @brief Enable a fault in System handler control register (SHCSR)
403 * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault
404 * @param Fault This parameter can be a combination of the following values:
405 * @arg @ref LL_HANDLER_FAULT_USG
406 * @arg @ref LL_HANDLER_FAULT_BUS
407 * @arg @ref LL_HANDLER_FAULT_MEM
408 * @retval None
409 */
LL_HANDLER_EnableFault(uint32_t Fault)410 __STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
411 {
412 /* Enable the system handler fault */
413 SET_BIT(SCB->SHCSR, Fault);
414 }
415
416 /**
417 * @brief Disable a fault in System handler control register (SHCSR)
418 * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault
419 * @param Fault This parameter can be a combination of the following values:
420 * @arg @ref LL_HANDLER_FAULT_USG
421 * @arg @ref LL_HANDLER_FAULT_BUS
422 * @arg @ref LL_HANDLER_FAULT_MEM
423 * @retval None
424 */
LL_HANDLER_DisableFault(uint32_t Fault)425 __STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
426 {
427 /* Disable the system handler fault */
428 CLEAR_BIT(SCB->SHCSR, Fault);
429 }
430
431 /**
432 * @}
433 */
434
435 /** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
436 * @{
437 */
438
439 /**
440 * @brief Get Implementer code
441 * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer
442 * @retval Value should be equal to 0x41 for ARM
443 */
LL_CPUID_GetImplementer(void)444 __STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
445 {
446 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
447 }
448
449 /**
450 * @brief Get Variant number (The r value in the rnpn product revision identifier)
451 * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant
452 * @retval Value between 0 and 255 (0x1: revision 1, 0x2: revision 2)
453 */
LL_CPUID_GetVariant(void)454 __STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
455 {
456 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
457 }
458
459 /**
460 * @brief Get Constant number
461 * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant
462 * @retval Value should be equal to 0xF for Cortex-M3 devices
463 */
LL_CPUID_GetConstant(void)464 __STATIC_INLINE uint32_t LL_CPUID_GetConstant(void)
465 {
466 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
467 }
468
469 /**
470 * @brief Get Part number
471 * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo
472 * @retval Value should be equal to 0xC23 for Cortex-M3
473 */
LL_CPUID_GetParNo(void)474 __STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
475 {
476 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
477 }
478
479 /**
480 * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
481 * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision
482 * @retval Value between 0 and 255 (0x0: patch 0, 0x1: patch 1)
483 */
LL_CPUID_GetRevision(void)484 __STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
485 {
486 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
487 }
488
489 /**
490 * @}
491 */
492
493 #if __MPU_PRESENT
494 /** @defgroup CORTEX_LL_EF_MPU MPU
495 * @{
496 */
497
498 /**
499 * @brief Enable MPU with input options
500 * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable
501 * @param Options This parameter can be one of the following values:
502 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
503 * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
504 * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
505 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
506 * @retval None
507 */
LL_MPU_Enable(uint32_t Options)508 __STATIC_INLINE void LL_MPU_Enable(uint32_t Options)
509 {
510 /* Enable the MPU*/
511 WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));
512 /* Ensure MPU settings take effects */
513 __DSB();
514 /* Sequence instruction fetches using update settings */
515 __ISB();
516 }
517
518 /**
519 * @brief Disable MPU
520 * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable
521 * @retval None
522 */
LL_MPU_Disable(void)523 __STATIC_INLINE void LL_MPU_Disable(void)
524 {
525 /* Make sure outstanding transfers are done */
526 __DMB();
527 /* Disable MPU*/
528 WRITE_REG(MPU->CTRL, 0U);
529 }
530
531 /**
532 * @brief Check if MPU is enabled or not
533 * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled
534 * @retval State of bit (1 or 0).
535 */
LL_MPU_IsEnabled(void)536 __STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
537 {
538 return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk));
539 }
540
541 /**
542 * @brief Enable a MPU region
543 * @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion
544 * @param Region This parameter can be one of the following values:
545 * @arg @ref LL_MPU_REGION_NUMBER0
546 * @arg @ref LL_MPU_REGION_NUMBER1
547 * @arg @ref LL_MPU_REGION_NUMBER2
548 * @arg @ref LL_MPU_REGION_NUMBER3
549 * @arg @ref LL_MPU_REGION_NUMBER4
550 * @arg @ref LL_MPU_REGION_NUMBER5
551 * @arg @ref LL_MPU_REGION_NUMBER6
552 * @arg @ref LL_MPU_REGION_NUMBER7
553 * @retval None
554 */
LL_MPU_EnableRegion(uint32_t Region)555 __STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
556 {
557 /* Set Region number */
558 WRITE_REG(MPU->RNR, Region);
559 /* Enable the MPU region */
560 SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
561 }
562
563 /**
564 * @brief Configure and enable a region
565 * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n
566 * MPU_RBAR REGION LL_MPU_ConfigRegion\n
567 * MPU_RBAR ADDR LL_MPU_ConfigRegion\n
568 * MPU_RASR XN LL_MPU_ConfigRegion\n
569 * MPU_RASR AP LL_MPU_ConfigRegion\n
570 * MPU_RASR S LL_MPU_ConfigRegion\n
571 * MPU_RASR C LL_MPU_ConfigRegion\n
572 * MPU_RASR B LL_MPU_ConfigRegion\n
573 * MPU_RASR SIZE LL_MPU_ConfigRegion
574 * @param Region This parameter can be one of the following values:
575 * @arg @ref LL_MPU_REGION_NUMBER0
576 * @arg @ref LL_MPU_REGION_NUMBER1
577 * @arg @ref LL_MPU_REGION_NUMBER2
578 * @arg @ref LL_MPU_REGION_NUMBER3
579 * @arg @ref LL_MPU_REGION_NUMBER4
580 * @arg @ref LL_MPU_REGION_NUMBER5
581 * @arg @ref LL_MPU_REGION_NUMBER6
582 * @arg @ref LL_MPU_REGION_NUMBER7
583 * @param Address Value of region base address
584 * @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
585 * @param Attributes This parameter can be a combination of the following values:
586 * @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B
587 * or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB
588 * or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB
589 * or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB
590 * or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB
591 * or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
592 * @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS
593 * or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
594 * @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4
595 * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
596 * @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
597 * @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
598 * @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE
599 * @retval None
600 */
LL_MPU_ConfigRegion(uint32_t Region,uint32_t SubRegionDisable,uint32_t Address,uint32_t Attributes)601 __STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
602 {
603 /* Set Region number */
604 WRITE_REG(MPU->RNR, Region);
605 /* Set base address */
606 WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
607 /* Configure MPU */
608 WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos));
609 }
610
611 /**
612 * @brief Disable a region
613 * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n
614 * MPU_RASR ENABLE LL_MPU_DisableRegion
615 * @param Region This parameter can be one of the following values:
616 * @arg @ref LL_MPU_REGION_NUMBER0
617 * @arg @ref LL_MPU_REGION_NUMBER1
618 * @arg @ref LL_MPU_REGION_NUMBER2
619 * @arg @ref LL_MPU_REGION_NUMBER3
620 * @arg @ref LL_MPU_REGION_NUMBER4
621 * @arg @ref LL_MPU_REGION_NUMBER5
622 * @arg @ref LL_MPU_REGION_NUMBER6
623 * @arg @ref LL_MPU_REGION_NUMBER7
624 * @retval None
625 */
LL_MPU_DisableRegion(uint32_t Region)626 __STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
627 {
628 /* Set Region number */
629 WRITE_REG(MPU->RNR, Region);
630 /* Disable the MPU region */
631 CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
632 }
633
634 /**
635 * @}
636 */
637
638 #endif /* __MPU_PRESENT */
639 /**
640 * @}
641 */
642
643 /**
644 * @}
645 */
646
647 /**
648 * @}
649 */
650
651 #ifdef __cplusplus
652 }
653 #endif
654
655 #endif /* __STM32L1xx_LL_CORTEX_H */
656
657 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
658