1 /** 2 ****************************************************************************** 3 * @file stm32l1xx_ll_sdmmc.h 4 * @author MCD Application Team 5 * @version V1.2.0 6 * @date 01-July-2016 7 * @brief Header file of SDMMC HAL module. 8 ****************************************************************************** 9 * @attention 10 * 11 * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> 12 * 13 * Redistribution and use in source and binary forms, with or without modification, 14 * are permitted provided that the following conditions are met: 15 * 1. Redistributions of source code must retain the above copyright notice, 16 * this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright notice, 18 * this list of conditions and the following disclaimer in the documentation 19 * and/or other materials provided with the distribution. 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 ****************************************************************************** 36 */ 37 38 /* Define to prevent recursive inclusion -------------------------------------*/ 39 #ifndef __STM32L1xx_LL_SD_H 40 #define __STM32L1xx_LL_SD_H 41 42 #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD) 43 44 #ifdef __cplusplus 45 extern "C" { 46 #endif 47 48 /* Includes ------------------------------------------------------------------*/ 49 #include "stm32l1xx_hal_def.h" 50 51 /** @addtogroup STM32L1xx_HAL_Driver 52 * @{ 53 */ 54 55 /** @addtogroup SDMMC_LL 56 * @{ 57 */ 58 59 /* Exported types ------------------------------------------------------------*/ 60 /** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types 61 * @{ 62 */ 63 64 /** 65 * @brief SDMMC Configuration Structure definition 66 */ 67 typedef struct 68 { 69 uint32_t ClockEdge; /*!< Specifies the clock transition on which the bit capture is made. 70 This parameter can be a value of @ref SDIO_Clock_Edge */ 71 72 uint32_t ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is 73 enabled or disabled. 74 This parameter can be a value of @ref SDIO_Clock_Bypass */ 75 76 uint32_t ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or 77 disabled when the bus is idle. 78 This parameter can be a value of @ref SDIO_Clock_Power_Save */ 79 80 uint32_t BusWide; /*!< Specifies the SDIO bus width. 81 This parameter can be a value of @ref SDIO_Bus_Wide */ 82 83 uint32_t HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled. 84 This parameter can be a value of @ref SDIO_Hardware_Flow_Control */ 85 86 uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDIO controller. 87 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ 88 89 }SDIO_InitTypeDef; 90 91 92 /** 93 * @brief SDIO Command Control structure 94 */ 95 typedef struct 96 { 97 uint32_t Argument; /*!< Specifies the SDIO command argument which is sent 98 to a card as part of a command message. If a command 99 contains an argument, it must be loaded into this register 100 before writing the command to the command register. */ 101 102 uint32_t CmdIndex; /*!< Specifies the SDIO command index. It must be Min_Data = 0 and 103 Max_Data = 64 */ 104 105 uint32_t Response; /*!< Specifies the SDIO response type. 106 This parameter can be a value of @ref SDIO_Response_Type */ 107 108 uint32_t WaitForInterrupt; /*!< Specifies whether SDIO wait for interrupt request is 109 enabled or disabled. 110 This parameter can be a value of @ref SDIO_Wait_Interrupt_State */ 111 112 uint32_t CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM) 113 is enabled or disabled. 114 This parameter can be a value of @ref SDIO_CPSM_State */ 115 }SDIO_CmdInitTypeDef; 116 117 118 /** 119 * @brief SDIO Data Control structure 120 */ 121 typedef struct 122 { 123 uint32_t DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */ 124 125 uint32_t DataLength; /*!< Specifies the number of data bytes to be transferred. */ 126 127 uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer. 128 This parameter can be a value of @ref SDIO_Data_Block_Size */ 129 130 uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer 131 is a read or write. 132 This parameter can be a value of @ref SDIO_Transfer_Direction */ 133 134 uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode. 135 This parameter can be a value of @ref SDIO_Transfer_Type */ 136 137 uint32_t DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM) 138 is enabled or disabled. 139 This parameter can be a value of @ref SDIO_DPSM_State */ 140 }SDIO_DataInitTypeDef; 141 142 /** 143 * @} 144 */ 145 146 /* Exported constants --------------------------------------------------------*/ 147 /** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants 148 * @{ 149 */ 150 151 /** @defgroup SDIO_Clock_Edge Clock Edge 152 * @{ 153 */ 154 #define SDIO_CLOCK_EDGE_RISING ((uint32_t)0x00000000) 155 #define SDIO_CLOCK_EDGE_FALLING SDIO_CLKCR_NEGEDGE 156 157 #define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_CLOCK_EDGE_RISING) || \ 158 ((EDGE) == SDIO_CLOCK_EDGE_FALLING)) 159 /** 160 * @} 161 */ 162 163 /** @defgroup SDIO_Clock_Bypass Clock Bypass 164 * @{ 165 */ 166 #define SDIO_CLOCK_BYPASS_DISABLE ((uint32_t)0x00000000) 167 #define SDIO_CLOCK_BYPASS_ENABLE SDIO_CLKCR_BYPASS 168 169 #define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_CLOCK_BYPASS_DISABLE) || \ 170 ((BYPASS) == SDIO_CLOCK_BYPASS_ENABLE)) 171 /** 172 * @} 173 */ 174 175 /** @defgroup SDIO_Clock_Power_Save Clock Power Saving 176 * @{ 177 */ 178 #define SDIO_CLOCK_POWER_SAVE_DISABLE ((uint32_t)0x00000000) 179 #define SDIO_CLOCK_POWER_SAVE_ENABLE SDIO_CLKCR_PWRSAV 180 181 #define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_CLOCK_POWER_SAVE_DISABLE) || \ 182 ((SAVE) == SDIO_CLOCK_POWER_SAVE_ENABLE)) 183 /** 184 * @} 185 */ 186 187 /** @defgroup SDIO_Bus_Wide Bus Width 188 * @{ 189 */ 190 #define SDIO_BUS_WIDE_1B ((uint32_t)0x00000000) 191 #define SDIO_BUS_WIDE_4B SDIO_CLKCR_WIDBUS_0 192 #define SDIO_BUS_WIDE_8B SDIO_CLKCR_WIDBUS_1 193 194 #define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BUS_WIDE_1B) || \ 195 ((WIDE) == SDIO_BUS_WIDE_4B) || \ 196 ((WIDE) == SDIO_BUS_WIDE_8B)) 197 /** 198 * @} 199 */ 200 201 /** @defgroup SDIO_Hardware_Flow_Control Hardware Flow Control 202 * @{ 203 */ 204 #define SDIO_HARDWARE_FLOW_CONTROL_DISABLE ((uint32_t)0x00000000) 205 #define SDIO_HARDWARE_FLOW_CONTROL_ENABLE SDIO_CLKCR_HWFC_EN 206 207 #define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_DISABLE) || \ 208 ((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_ENABLE)) 209 /** 210 * @} 211 */ 212 213 /** @defgroup SDIO_Clock_Division Clock Division 214 * @{ 215 */ 216 #define IS_SDIO_CLKDIV(DIV) ((DIV) <= 0xFF) 217 /** 218 * @} 219 */ 220 221 /** @defgroup SDIO_Command_Index Command Index 222 * @{ 223 */ 224 #define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40) 225 /** 226 * @} 227 */ 228 229 /** @defgroup SDIO_Response_Type Response Type 230 * @{ 231 */ 232 #define SDIO_RESPONSE_NO ((uint32_t)0x00000000) 233 #define SDIO_RESPONSE_SHORT SDIO_CMD_WAITRESP_0 234 #define SDIO_RESPONSE_LONG SDIO_CMD_WAITRESP 235 236 #define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_RESPONSE_NO) || \ 237 ((RESPONSE) == SDIO_RESPONSE_SHORT) || \ 238 ((RESPONSE) == SDIO_RESPONSE_LONG)) 239 /** 240 * @} 241 */ 242 243 /** @defgroup SDIO_Wait_Interrupt_State Wait Interrupt 244 * @{ 245 */ 246 #define SDIO_WAIT_NO ((uint32_t)0x00000000) 247 #define SDIO_WAIT_IT SDIO_CMD_WAITINT 248 #define SDIO_WAIT_PEND SDIO_CMD_WAITPEND 249 250 #define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_WAIT_NO) || \ 251 ((WAIT) == SDIO_WAIT_IT) || \ 252 ((WAIT) == SDIO_WAIT_PEND)) 253 /** 254 * @} 255 */ 256 257 /** @defgroup SDIO_CPSM_State CPSM State 258 * @{ 259 */ 260 #define SDIO_CPSM_DISABLE ((uint32_t)0x00000000) 261 #define SDIO_CPSM_ENABLE SDIO_CMD_CPSMEN 262 263 #define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_DISABLE) || \ 264 ((CPSM) == SDIO_CPSM_ENABLE)) 265 /** 266 * @} 267 */ 268 269 /** @defgroup SDIO_Response_Registers Response Register 270 * @{ 271 */ 272 #define SDIO_RESP1 ((uint32_t)0x00000000) 273 #define SDIO_RESP2 ((uint32_t)0x00000004) 274 #define SDIO_RESP3 ((uint32_t)0x00000008) 275 #define SDIO_RESP4 ((uint32_t)0x0000000C) 276 277 #define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || \ 278 ((RESP) == SDIO_RESP2) || \ 279 ((RESP) == SDIO_RESP3) || \ 280 ((RESP) == SDIO_RESP4)) 281 /** 282 * @} 283 */ 284 285 /** @defgroup SDIO_Data_Length Data Lenght 286 * @{ 287 */ 288 #define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF) 289 /** 290 * @} 291 */ 292 293 /** @defgroup SDIO_Data_Block_Size Data Block Size 294 * @{ 295 */ 296 #define SDIO_DATABLOCK_SIZE_1B ((uint32_t)0x00000000) 297 #define SDIO_DATABLOCK_SIZE_2B SDIO_DCTRL_DBLOCKSIZE_0 298 #define SDIO_DATABLOCK_SIZE_4B SDIO_DCTRL_DBLOCKSIZE_1 299 #define SDIO_DATABLOCK_SIZE_8B ((uint32_t)0x00000030) 300 #define SDIO_DATABLOCK_SIZE_16B SDIO_DCTRL_DBLOCKSIZE_2 301 #define SDIO_DATABLOCK_SIZE_32B ((uint32_t)0x00000050) 302 #define SDIO_DATABLOCK_SIZE_64B ((uint32_t)0x00000060) 303 #define SDIO_DATABLOCK_SIZE_128B ((uint32_t)0x00000070) 304 #define SDIO_DATABLOCK_SIZE_256B SDIO_DCTRL_DBLOCKSIZE_3 305 #define SDIO_DATABLOCK_SIZE_512B ((uint32_t)0x00000090) 306 #define SDIO_DATABLOCK_SIZE_1024B ((uint32_t)0x000000A0) 307 #define SDIO_DATABLOCK_SIZE_2048B ((uint32_t)0x000000B0) 308 #define SDIO_DATABLOCK_SIZE_4096B ((uint32_t)0x000000C0) 309 #define SDIO_DATABLOCK_SIZE_8192B ((uint32_t)0x000000D0) 310 #define SDIO_DATABLOCK_SIZE_16384B ((uint32_t)0x000000E0) 311 312 #define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DATABLOCK_SIZE_1B) || \ 313 ((SIZE) == SDIO_DATABLOCK_SIZE_2B) || \ 314 ((SIZE) == SDIO_DATABLOCK_SIZE_4B) || \ 315 ((SIZE) == SDIO_DATABLOCK_SIZE_8B) || \ 316 ((SIZE) == SDIO_DATABLOCK_SIZE_16B) || \ 317 ((SIZE) == SDIO_DATABLOCK_SIZE_32B) || \ 318 ((SIZE) == SDIO_DATABLOCK_SIZE_64B) || \ 319 ((SIZE) == SDIO_DATABLOCK_SIZE_128B) || \ 320 ((SIZE) == SDIO_DATABLOCK_SIZE_256B) || \ 321 ((SIZE) == SDIO_DATABLOCK_SIZE_512B) || \ 322 ((SIZE) == SDIO_DATABLOCK_SIZE_1024B) || \ 323 ((SIZE) == SDIO_DATABLOCK_SIZE_2048B) || \ 324 ((SIZE) == SDIO_DATABLOCK_SIZE_4096B) || \ 325 ((SIZE) == SDIO_DATABLOCK_SIZE_8192B) || \ 326 ((SIZE) == SDIO_DATABLOCK_SIZE_16384B)) 327 /** 328 * @} 329 */ 330 331 /** @defgroup SDIO_Transfer_Direction Transfer Direction 332 * @{ 333 */ 334 #define SDIO_TRANSFER_DIR_TO_CARD ((uint32_t)0x00000000) 335 #define SDIO_TRANSFER_DIR_TO_SDIO SDIO_DCTRL_DTDIR 336 337 #define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TRANSFER_DIR_TO_CARD) || \ 338 ((DIR) == SDIO_TRANSFER_DIR_TO_SDIO)) 339 /** 340 * @} 341 */ 342 343 /** @defgroup SDIO_Transfer_Type Transfer Type 344 * @{ 345 */ 346 #define SDIO_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000) 347 #define SDIO_TRANSFER_MODE_STREAM SDIO_DCTRL_DTMODE 348 349 #define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TRANSFER_MODE_BLOCK) || \ 350 ((MODE) == SDIO_TRANSFER_MODE_STREAM)) 351 /** 352 * @} 353 */ 354 355 /** @defgroup SDIO_DPSM_State DPSM State 356 * @{ 357 */ 358 #define SDIO_DPSM_DISABLE ((uint32_t)0x00000000) 359 #define SDIO_DPSM_ENABLE SDIO_DCTRL_DTEN 360 361 #define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_DISABLE) ||\ 362 ((DPSM) == SDIO_DPSM_ENABLE)) 363 /** 364 * @} 365 */ 366 367 /** @defgroup SDIO_Read_Wait_Mode Read Wait Mode 368 * @{ 369 */ 370 #define SDIO_READ_WAIT_MODE_DATA2 ((uint32_t)0x00000000) 371 #define SDIO_READ_WAIT_MODE_CLK ((uint32_t)0x00000001) 372 373 #define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_READ_WAIT_MODE_CLK) || \ 374 ((MODE) == SDIO_READ_WAIT_MODE_DATA2)) 375 /** 376 * @} 377 */ 378 379 /** @defgroup SDIO_Interrupt_sources Interrupt Sources 380 * @{ 381 */ 382 #define SDIO_IT_CCRCFAIL SDIO_STA_CCRCFAIL 383 #define SDIO_IT_DCRCFAIL SDIO_STA_DCRCFAIL 384 #define SDIO_IT_CTIMEOUT SDIO_STA_CTIMEOUT 385 #define SDIO_IT_DTIMEOUT SDIO_STA_DTIMEOUT 386 #define SDIO_IT_TXUNDERR SDIO_STA_TXUNDERR 387 #define SDIO_IT_RXOVERR SDIO_STA_RXOVERR 388 #define SDIO_IT_CMDREND SDIO_STA_CMDREND 389 #define SDIO_IT_CMDSENT SDIO_STA_CMDSENT 390 #define SDIO_IT_DATAEND SDIO_STA_DATAEND 391 #define SDIO_IT_STBITERR SDIO_STA_STBITERR 392 #define SDIO_IT_DBCKEND SDIO_STA_DBCKEND 393 #define SDIO_IT_CMDACT SDIO_STA_CMDACT 394 #define SDIO_IT_TXACT SDIO_STA_TXACT 395 #define SDIO_IT_RXACT SDIO_STA_RXACT 396 #define SDIO_IT_TXFIFOHE SDIO_STA_TXFIFOHE 397 #define SDIO_IT_RXFIFOHF SDIO_STA_RXFIFOHF 398 #define SDIO_IT_TXFIFOF SDIO_STA_TXFIFOF 399 #define SDIO_IT_RXFIFOF SDIO_STA_RXFIFOF 400 #define SDIO_IT_TXFIFOE SDIO_STA_TXFIFOE 401 #define SDIO_IT_RXFIFOE SDIO_STA_RXFIFOE 402 #define SDIO_IT_TXDAVL SDIO_STA_TXDAVL 403 #define SDIO_IT_RXDAVL SDIO_STA_RXDAVL 404 #define SDIO_IT_SDIOIT SDIO_STA_SDIOIT 405 #define SDIO_IT_CEATAEND SDIO_STA_CEATAEND 406 /** 407 * @} 408 */ 409 410 /** @defgroup SDIO_Flags Flags 411 * @{ 412 */ 413 #define SDIO_FLAG_CCRCFAIL SDIO_STA_CCRCFAIL 414 #define SDIO_FLAG_DCRCFAIL SDIO_STA_DCRCFAIL 415 #define SDIO_FLAG_CTIMEOUT SDIO_STA_CTIMEOUT 416 #define SDIO_FLAG_DTIMEOUT SDIO_STA_DTIMEOUT 417 #define SDIO_FLAG_TXUNDERR SDIO_STA_TXUNDERR 418 #define SDIO_FLAG_RXOVERR SDIO_STA_RXOVERR 419 #define SDIO_FLAG_CMDREND SDIO_STA_CMDREND 420 #define SDIO_FLAG_CMDSENT SDIO_STA_CMDSENT 421 #define SDIO_FLAG_DATAEND SDIO_STA_DATAEND 422 #define SDIO_FLAG_STBITERR SDIO_STA_STBITERR 423 #define SDIO_FLAG_DBCKEND SDIO_STA_DBCKEND 424 #define SDIO_FLAG_CMDACT SDIO_STA_CMDACT 425 #define SDIO_FLAG_TXACT SDIO_STA_TXACT 426 #define SDIO_FLAG_RXACT SDIO_STA_RXACT 427 #define SDIO_FLAG_TXFIFOHE SDIO_STA_TXFIFOHE 428 #define SDIO_FLAG_RXFIFOHF SDIO_STA_RXFIFOHF 429 #define SDIO_FLAG_TXFIFOF SDIO_STA_TXFIFOF 430 #define SDIO_FLAG_RXFIFOF SDIO_STA_RXFIFOF 431 #define SDIO_FLAG_TXFIFOE SDIO_STA_TXFIFOE 432 #define SDIO_FLAG_RXFIFOE SDIO_STA_RXFIFOE 433 #define SDIO_FLAG_TXDAVL SDIO_STA_TXDAVL 434 #define SDIO_FLAG_RXDAVL SDIO_STA_RXDAVL 435 #define SDIO_FLAG_SDIOIT SDIO_STA_SDIOIT 436 #define SDIO_FLAG_CEATAEND SDIO_STA_CEATAEND 437 /** 438 * @} 439 */ 440 441 /** 442 * @} 443 */ 444 /* Exported macro ------------------------------------------------------------*/ 445 /** @defgroup SDMMC_LL_Exported_macros SDMMC_LL Exported Macros 446 * @{ 447 */ 448 449 /** @defgroup SDMMC_LL_Alias_Region Bit Address in the alias region 450 * @{ 451 */ 452 /* ------------ SDIO registers bit address in the alias region -------------- */ 453 #define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE) 454 455 /* --- CLKCR Register ---*/ 456 /* Alias word address of CLKEN bit */ 457 #define CLKCR_OFFSET (SDIO_OFFSET + 0x04) 458 #define CLKEN_BITNUMBER 0x08 459 #define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BITNUMBER * 4)) 460 461 /* --- CMD Register ---*/ 462 /* Alias word address of SDIOSUSPEND bit */ 463 #define CMD_OFFSET (SDIO_OFFSET + 0x0C) 464 #define SDIOSUSPEND_BITNUMBER 0x0B 465 #define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BITNUMBER * 4)) 466 467 /* Alias word address of ENCMDCOMPL bit */ 468 #define ENCMDCOMPL_BITNUMBER 0x0C 469 #define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BITNUMBER * 4)) 470 471 /* Alias word address of NIEN bit */ 472 #define NIEN_BITNUMBER 0x0D 473 #define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BITNUMBER * 4)) 474 475 /* Alias word address of ATACMD bit */ 476 #define ATACMD_BITNUMBER 0x0E 477 #define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BITNUMBER * 4)) 478 479 /* --- DCTRL Register ---*/ 480 /* Alias word address of DMAEN bit */ 481 #define DCTRL_OFFSET (SDIO_OFFSET + 0x2C) 482 #define DMAEN_BITNUMBER 0x03 483 #define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BITNUMBER * 4)) 484 485 /* Alias word address of RWSTART bit */ 486 #define RWSTART_BITNUMBER 0x08 487 #define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BITNUMBER * 4)) 488 489 /* Alias word address of RWSTOP bit */ 490 #define RWSTOP_BITNUMBER 0x09 491 #define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BITNUMBER * 4)) 492 493 /* Alias word address of RWMOD bit */ 494 #define RWMOD_BITNUMBER 0x0A 495 #define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BITNUMBER * 4)) 496 497 /* Alias word address of SDIOEN bit */ 498 #define SDIOEN_BITNUMBER 0x0B 499 #define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BITNUMBER * 4)) 500 /** 501 * @} 502 */ 503 504 /** @defgroup SDMMC_LL_Register Bits And Addresses Definitions 505 * @brief SDMMC_LL registers bit address in the alias region 506 * @{ 507 */ 508 509 /* ---------------------- SDIO registers bit mask --------------------------- */ 510 /* --- CLKCR Register ---*/ 511 /* CLKCR register clear mask */ 512 #define CLKCR_CLEAR_MASK ((uint32_t)(SDIO_CLKCR_CLKDIV | SDIO_CLKCR_PWRSAV |\ 513 SDIO_CLKCR_BYPASS | SDIO_CLKCR_WIDBUS |\ 514 SDIO_CLKCR_NEGEDGE | SDIO_CLKCR_HWFC_EN)) 515 516 /* --- PWRCTRL Register ---*/ 517 /* --- DCTRL Register ---*/ 518 /* SDIO DCTRL Clear Mask */ 519 #define DCTRL_CLEAR_MASK ((uint32_t)(SDIO_DCTRL_DTEN | SDIO_DCTRL_DTDIR |\ 520 SDIO_DCTRL_DTMODE | SDIO_DCTRL_DBLOCKSIZE)) 521 522 /* --- CMD Register ---*/ 523 /* CMD Register clear mask */ 524 #define CMD_CLEAR_MASK ((uint32_t)(SDIO_CMD_CMDINDEX | SDIO_CMD_WAITRESP |\ 525 SDIO_CMD_WAITINT | SDIO_CMD_WAITPEND |\ 526 SDIO_CMD_CPSMEN | SDIO_CMD_SDIOSUSPEND)) 527 528 /* SDIO RESP Registers Address */ 529 #define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14)) 530 531 /* SDIO Initialization Frequency (400KHz max) */ 532 #define SDIO_INIT_CLK_DIV ((uint8_t)0x76) 533 534 /* SDIO Data Transfer Frequency */ 535 #define SDIO_TRANSFER_CLK_DIV ((uint8_t)0x4) 536 537 /** 538 * @} 539 */ 540 541 /** @defgroup SDMMC_LL_Interrupt_Clock Interrupt And Clock Configuration 542 * @brief macros to handle interrupts and specific clock configurations 543 * @{ 544 */ 545 546 /** 547 * @brief Enable the SDIO device. 548 * @retval None 549 */ 550 #define __SDIO_ENABLE() (*(__IO uint32_t *)CLKCR_CLKEN_BB = ENABLE) 551 552 /** 553 * @brief Disable the SDIO device. 554 * @retval None 555 */ 556 #define __SDIO_DISABLE() (*(__IO uint32_t *)CLKCR_CLKEN_BB = DISABLE) 557 558 /** 559 * @brief Enable the SDIO DMA transfer. 560 * @retval None 561 */ 562 #define __SDIO_DMA_ENABLE() (*(__IO uint32_t *)DCTRL_DMAEN_BB = ENABLE) 563 564 /** 565 * @brief Disable the SDIO DMA transfer. 566 * @retval None 567 */ 568 #define __SDIO_DMA_DISABLE() (*(__IO uint32_t *)DCTRL_DMAEN_BB = DISABLE) 569 570 /** 571 * @brief Enable the SDIO device interrupt. 572 * @param __INSTANCE__ : Pointer to SDIO register base 573 * @param __INTERRUPT__ : specifies the SDIO interrupt sources to be enabled. 574 * This parameter can be one or a combination of the following values: 575 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt 576 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt 577 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt 578 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt 579 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt 580 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt 581 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt 582 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt 583 * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt 584 * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide 585 * bus mode interrupt 586 * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt 587 * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt 588 * @arg SDIO_IT_TXACT: Data transmit in progress interrupt 589 * @arg SDIO_IT_RXACT: Data receive in progress interrupt 590 * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt 591 * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt 592 * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt 593 * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt 594 * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt 595 * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt 596 * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt 597 * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt 598 * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt 599 * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt 600 * @retval None 601 */ 602 #define __SDIO_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK |= (__INTERRUPT__)) 603 604 /** 605 * @brief Disable the SDIO device interrupt. 606 * @param __INSTANCE__ : Pointer to SDIO register base 607 * @param __INTERRUPT__ : specifies the SDIO interrupt sources to be disabled. 608 * This parameter can be one or a combination of the following values: 609 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt 610 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt 611 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt 612 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt 613 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt 614 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt 615 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt 616 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt 617 * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt 618 * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide 619 * bus mode interrupt 620 * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt 621 * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt 622 * @arg SDIO_IT_TXACT: Data transmit in progress interrupt 623 * @arg SDIO_IT_RXACT: Data receive in progress interrupt 624 * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt 625 * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt 626 * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt 627 * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt 628 * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt 629 * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt 630 * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt 631 * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt 632 * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt 633 * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt 634 * @retval None 635 */ 636 #define __SDIO_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__)) 637 638 /** 639 * @brief Checks whether the specified SDIO flag is set or not. 640 * @param __INSTANCE__ : Pointer to SDIO register base 641 * @param __FLAG__: specifies the flag to check. 642 * This parameter can be one of the following values: 643 * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) 644 * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) 645 * @arg SDIO_FLAG_CTIMEOUT: Command response timeout 646 * @arg SDIO_FLAG_DTIMEOUT: Data timeout 647 * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error 648 * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error 649 * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) 650 * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) 651 * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) 652 * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode. 653 * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) 654 * @arg SDIO_FLAG_CMDACT: Command transfer in progress 655 * @arg SDIO_FLAG_TXACT: Data transmit in progress 656 * @arg SDIO_FLAG_RXACT: Data receive in progress 657 * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty 658 * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full 659 * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full 660 * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full 661 * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty 662 * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty 663 * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO 664 * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO 665 * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received 666 * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61 667 * @retval The new state of SDIO_FLAG (SET or RESET). 668 */ 669 #define __SDIO_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != RESET) 670 671 672 /** 673 * @brief Clears the SDIO pending flags. 674 * @param __INSTANCE__ : Pointer to SDIO register base 675 * @param __FLAG__: specifies the flag to clear. 676 * This parameter can be one or a combination of the following values: 677 * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) 678 * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) 679 * @arg SDIO_FLAG_CTIMEOUT: Command response timeout 680 * @arg SDIO_FLAG_DTIMEOUT: Data timeout 681 * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error 682 * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error 683 * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) 684 * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) 685 * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) 686 * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode 687 * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) 688 * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received 689 * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61 690 * @retval None 691 */ 692 #define __SDIO_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__)) 693 694 /** 695 * @brief Checks whether the specified SDIO interrupt has occurred or not. 696 * @param __INSTANCE__ : Pointer to SDIO register base 697 * @param __INTERRUPT__: specifies the SDIO interrupt source to check. 698 * This parameter can be one of the following values: 699 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt 700 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt 701 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt 702 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt 703 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt 704 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt 705 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt 706 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt 707 * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt 708 * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide 709 * bus mode interrupt 710 * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt 711 * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt 712 * @arg SDIO_IT_TXACT: Data transmit in progress interrupt 713 * @arg SDIO_IT_RXACT: Data receive in progress interrupt 714 * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt 715 * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt 716 * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt 717 * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt 718 * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt 719 * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt 720 * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt 721 * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt 722 * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt 723 * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt 724 * @retval The new state of SDIO_IT (SET or RESET). 725 */ 726 #define __SDIO_GET_IT (__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__)) 727 728 /** 729 * @brief Clears the SDIO's interrupt pending bits. 730 * @param __INSTANCE__ : Pointer to SDIO register base 731 * @param __INTERRUPT__: specifies the interrupt pending bit to clear. 732 * This parameter can be one or a combination of the following values: 733 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt 734 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt 735 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt 736 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt 737 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt 738 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt 739 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt 740 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt 741 * @arg SDIO_IT_DATAEND: Data end (data counter, SDIO_DCOUNT, is zero) interrupt 742 * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide 743 * bus mode interrupt 744 * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt 745 * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 746 * @retval None 747 */ 748 #define __SDIO_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__)) 749 750 /** 751 * @brief Enable Start the SD I/O Read Wait operation. 752 * @retval None 753 */ 754 #define __SDIO_START_READWAIT_ENABLE() (*(__IO uint32_t *) DCTRL_RWSTART_BB = ENABLE) 755 756 /** 757 * @brief Disable Start the SD I/O Read Wait operations. 758 * @retval None 759 */ 760 #define __SDIO_START_READWAIT_DISABLE() (*(__IO uint32_t *) DCTRL_RWSTART_BB = DISABLE) 761 762 /** 763 * @brief Enable Start the SD I/O Read Wait operation. 764 * @retval None 765 */ 766 #define __SDIO_STOP_READWAIT_ENABLE() (*(__IO uint32_t *) DCTRL_RWSTOP_BB = ENABLE) 767 768 /** 769 * @brief Disable Stop the SD I/O Read Wait operations. 770 * @retval None 771 */ 772 #define __SDIO_STOP_READWAIT_DISABLE() (*(__IO uint32_t *) DCTRL_RWSTOP_BB = DISABLE) 773 774 /** 775 * @brief Enable the SD I/O Mode Operation. 776 * @retval None 777 */ 778 #define __SDIO_OPERATION_ENABLE() (*(__IO uint32_t *) DCTRL_SDIOEN_BB = ENABLE) 779 780 /** 781 * @brief Disable the SD I/O Mode Operation. 782 * @retval None 783 */ 784 #define __SDIO_OPERATION_DISABLE() (*(__IO uint32_t *) DCTRL_SDIOEN_BB = DISABLE) 785 786 /** 787 * @brief Enable the SD I/O Suspend command sending. 788 * @retval None 789 */ 790 #define __SDIO_SUSPEND_CMD_ENABLE() (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = ENABLE) 791 792 /** 793 * @brief Disable the SD I/O Suspend command sending. 794 * @retval None 795 */ 796 #define __SDIO_SUSPEND_CMD_DISABLE() (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = DISABLE) 797 798 /** 799 * @brief Enable the command completion signal. 800 * @retval None 801 */ 802 #define __SDIO_CEATA_CMD_COMPLETION_ENABLE() (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = ENABLE) 803 804 /** 805 * @brief Disable the command completion signal. 806 * @retval None 807 */ 808 #define __SDIO_CEATA_CMD_COMPLETION_DISABLE() (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = DISABLE) 809 810 /** 811 * @brief Enable the CE-ATA interrupt. 812 * @retval None 813 */ 814 #define __SDIO_CEATA_ENABLE_IT() (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)0) 815 816 /** 817 * @brief Disable the CE-ATA interrupt. 818 * @retval None 819 */ 820 #define __SDIO_CEATA_DISABLE_IT() (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)1) 821 822 /** 823 * @brief Enable send CE-ATA command (CMD61). 824 * @retval None 825 */ 826 #define __SDIO_CEATA_SENDCMD_ENABLE() (*(__IO uint32_t *) CMD_ATACMD_BB = ENABLE) 827 828 /** 829 * @brief Disable send CE-ATA command (CMD61). 830 * @retval None 831 */ 832 #define __SDIO_CEATA_SENDCMD_DISABLE() (*(__IO uint32_t *) CMD_ATACMD_BB = DISABLE) 833 834 /** 835 * @} 836 */ 837 838 /** 839 * @} 840 */ 841 842 /* Exported functions --------------------------------------------------------*/ 843 /** @addtogroup SDMMC_LL_Exported_Functions 844 * @{ 845 */ 846 847 /* Initialization/de-initialization functions **********************************/ 848 /** @addtogroup HAL_SDMMC_LL_Group1 849 * @{ 850 */ 851 HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init); 852 /** 853 * @} 854 */ 855 856 /* I/O operation functions *****************************************************/ 857 /** @addtogroup HAL_SDMMC_LL_Group2 858 * @{ 859 */ 860 /* Blocking mode: Polling */ 861 uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx); 862 HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData); 863 /** 864 * @} 865 */ 866 867 /* Peripheral Control functions ************************************************/ 868 /** @addtogroup HAL_SDMMC_LL_Group3 869 * @{ 870 */ 871 HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx); 872 HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx); 873 uint32_t SDIO_GetPowerState(SDIO_TypeDef *SDIOx); 874 875 /* Command path state machine (CPSM) management functions */ 876 HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *SDIO_CmdInitStruct); 877 uint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx); 878 uint32_t SDIO_GetResponse(uint32_t SDIO_RESP); 879 880 /* Data path state machine (DPSM) management functions */ 881 HAL_StatusTypeDef SDIO_DataConfig(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* SDIO_DataInitStruct); 882 uint32_t SDIO_GetDataCounter(SDIO_TypeDef *SDIOx); 883 uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx); 884 885 /* SDIO IO Cards mode management functions */ 886 HAL_StatusTypeDef SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode); 887 888 /** 889 * @} 890 */ 891 892 /** 893 * @} 894 */ 895 896 /** 897 * @} 898 */ 899 900 /** 901 * @} 902 */ 903 904 #ifdef __cplusplus 905 } 906 #endif 907 908 #endif /* STM32L151xD || STM32L152xD || STM32L162xD */ 909 910 #endif /* __STM32L1xx_LL_SD_H */ 911 912 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 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