1 use crate::common::Register; 2 3 macro_rules! registers { 4 ($struct_name:ident, { $($name:ident = ($val:expr, $disp:expr)),+ $(,)? } 5 $(, aliases { $($alias_name:ident = ($alias_val:expr, $alias_disp:expr)),+ $(,)? })?) => { 6 #[allow(missing_docs)] 7 impl $struct_name { 8 $( 9 pub const $name: Register = Register($val); 10 )+ 11 $( 12 $(pub const $alias_name: Register = Register($alias_val);)+ 13 )* 14 } 15 16 impl $struct_name { 17 /// The name of a register, or `None` if the register number is unknown. 18 /// 19 /// Only returns the primary name for registers that alias with others. 20 pub fn register_name(register: Register) -> Option<&'static str> { 21 match register { 22 $( 23 Self::$name => Some($disp), 24 )+ 25 _ => return None, 26 } 27 } 28 29 /// Converts a register name into a register number. 30 pub fn name_to_register(value: &str) -> Option<Register> { 31 match value { 32 $( 33 $disp => Some(Self::$name), 34 )+ 35 $( 36 $($alias_disp => Some(Self::$alias_name),)+ 37 )* 38 _ => return None, 39 } 40 } 41 } 42 }; 43 } 44 45 /// ARM architecture specific definitions. 46 /// 47 /// See [DWARF for the ARM Architecture](https://developer.arm.com/documentation/ihi0040/c/). 48 #[derive(Debug, Clone, Copy)] 49 pub struct Arm; 50 51 registers!(Arm, { 52 R0 = (0, "R0"), 53 R1 = (1, "R1"), 54 R2 = (2, "R2"), 55 R3 = (3, "R3"), 56 R4 = (4, "R4"), 57 R5 = (5, "R5"), 58 R6 = (6, "R6"), 59 R7 = (7, "R7"), 60 R8 = (8, "R8"), 61 R9 = (9, "R9"), 62 R10 = (10, "R10"), 63 R11 = (11, "R11"), 64 R12 = (12, "R12"), 65 R13 = (13, "R13"), 66 R14 = (14, "R14"), 67 R15 = (15, "R15"), 68 69 WCGR0 = (104, "wCGR0"), 70 WCGR1 = (105, "wCGR1"), 71 WCGR2 = (106, "wCGR2"), 72 WCGR3 = (107, "wCGR3"), 73 WCGR4 = (108, "wCGR4"), 74 WCGR5 = (109, "wCGR5"), 75 WCGR6 = (110, "wCGR6"), 76 WCGR7 = (111, "wCGR7"), 77 78 WR0 = (112, "wR0"), 79 WR1 = (113, "wR1"), 80 WR2 = (114, "wR2"), 81 WR3 = (115, "wR3"), 82 WR4 = (116, "wR4"), 83 WR5 = (117, "wR5"), 84 WR6 = (118, "wR6"), 85 WR7 = (119, "wR7"), 86 WR8 = (120, "wR8"), 87 WR9 = (121, "wR9"), 88 WR10 = (122, "wR10"), 89 WR11 = (123, "wR11"), 90 WR12 = (124, "wR12"), 91 WR13 = (125, "wR13"), 92 WR14 = (126, "wR14"), 93 WR15 = (127, "wR15"), 94 95 SPSR = (128, "SPSR"), 96 SPSR_FIQ = (129, "SPSR_FIQ"), 97 SPSR_IRQ = (130, "SPSR_IRQ"), 98 SPSR_ABT = (131, "SPSR_ABT"), 99 SPSR_UND = (132, "SPSR_UND"), 100 SPSR_SVC = (133, "SPSR_SVC"), 101 102 R8_USR = (144, "R8_USR"), 103 R9_USR = (145, "R9_USR"), 104 R10_USR = (146, "R10_USR"), 105 R11_USR = (147, "R11_USR"), 106 R12_USR = (148, "R12_USR"), 107 R13_USR = (149, "R13_USR"), 108 R14_USR = (150, "R14_USR"), 109 110 R8_FIQ = (151, "R8_FIQ"), 111 R9_FIQ = (152, "R9_FIQ"), 112 R10_FIQ = (153, "R10_FIQ"), 113 R11_FIQ = (154, "R11_FIQ"), 114 R12_FIQ = (155, "R12_FIQ"), 115 R13_FIQ = (156, "R13_FIQ"), 116 R14_FIQ = (157, "R14_FIQ"), 117 118 R13_IRQ = (158, "R13_IRQ"), 119 R14_IRQ = (159, "R14_IRQ"), 120 121 R13_ABT = (160, "R13_ABT"), 122 R14_ABT = (161, "R14_ABT"), 123 124 R13_UND = (162, "R13_UND"), 125 R14_UND = (163, "R14_UND"), 126 127 R13_SVC = (164, "R13_SVC"), 128 R14_SVC = (165, "R14_SVC"), 129 130 WC0 = (192, "wC0"), 131 WC1 = (193, "wC1"), 132 WC2 = (194, "wC2"), 133 WC3 = (195, "wC3"), 134 WC4 = (196, "wC4"), 135 WC5 = (197, "wC5"), 136 WC6 = (198, "wC6"), 137 WC7 = (199, "wC7"), 138 139 D0 = (256, "D0"), 140 D1 = (257, "D1"), 141 D2 = (258, "D2"), 142 D3 = (259, "D3"), 143 D4 = (260, "D4"), 144 D5 = (261, "D5"), 145 D6 = (262, "D6"), 146 D7 = (263, "D7"), 147 D8 = (264, "D8"), 148 D9 = (265, "D9"), 149 D10 = (266, "D10"), 150 D11 = (267, "D11"), 151 D12 = (268, "D12"), 152 D13 = (269, "D13"), 153 D14 = (270, "D14"), 154 D15 = (271, "D15"), 155 D16 = (272, "D16"), 156 D17 = (273, "D17"), 157 D18 = (274, "D18"), 158 D19 = (275, "D19"), 159 D20 = (276, "D20"), 160 D21 = (277, "D21"), 161 D22 = (278, "D22"), 162 D23 = (279, "D23"), 163 D24 = (280, "D24"), 164 D25 = (281, "D25"), 165 D26 = (282, "D26"), 166 D27 = (283, "D27"), 167 D28 = (284, "D28"), 168 D29 = (285, "D29"), 169 D30 = (286, "D30"), 170 D31 = (287, "D31"), 171 }, 172 aliases { 173 SP = (13, "SP"), 174 LR = (14, "LR"), 175 PC = (15, "PC"), 176 177 ACC0 = (104, "ACC0"), 178 ACC1 = (105, "ACC1"), 179 ACC2 = (106, "ACC2"), 180 ACC3 = (107, "ACC3"), 181 ACC4 = (108, "ACC4"), 182 ACC5 = (109, "ACC5"), 183 ACC6 = (110, "ACC6"), 184 ACC7 = (111, "ACC7"), 185 186 S0 = (256, "S0"), 187 S1 = (256, "S1"), 188 S2 = (257, "S2"), 189 S3 = (257, "S3"), 190 S4 = (258, "S4"), 191 S5 = (258, "S5"), 192 S6 = (259, "S6"), 193 S7 = (259, "S7"), 194 S8 = (260, "S8"), 195 S9 = (260, "S9"), 196 S10 = (261, "S10"), 197 S11 = (261, "S11"), 198 S12 = (262, "S12"), 199 S13 = (262, "S13"), 200 S14 = (263, "S14"), 201 S15 = (263, "S15"), 202 S16 = (264, "S16"), 203 S17 = (264, "S17"), 204 S18 = (265, "S18"), 205 S19 = (265, "S19"), 206 S20 = (266, "S20"), 207 S21 = (266, "S21"), 208 S22 = (267, "S22"), 209 S23 = (267, "S23"), 210 S24 = (268, "S24"), 211 S25 = (268, "S25"), 212 S26 = (269, "S26"), 213 S27 = (269, "S27"), 214 S28 = (270, "S28"), 215 S29 = (270, "S29"), 216 S30 = (271, "S30"), 217 S31 = (271, "S31"), 218 }); 219 220 /// ARM 64-bit (AArch64) architecture specific definitions. 221 /// 222 /// See [DWARF for the ARM 64-bit Architecture](https://developer.arm.com/documentation/ihi0057/b/). 223 #[derive(Debug, Clone, Copy)] 224 pub struct AArch64; 225 226 registers!(AArch64, { 227 X0 = (0, "X0"), 228 X1 = (1, "X1"), 229 X2 = (2, "X2"), 230 X3 = (3, "X3"), 231 X4 = (4, "X4"), 232 X5 = (5, "X5"), 233 X6 = (6, "X6"), 234 X7 = (7, "X7"), 235 X8 = (8, "X8"), 236 X9 = (9, "X9"), 237 X10 = (10, "X10"), 238 X11 = (11, "X11"), 239 X12 = (12, "X12"), 240 X13 = (13, "X13"), 241 X14 = (14, "X14"), 242 X15 = (15, "X15"), 243 X16 = (16, "X16"), 244 X17 = (17, "X17"), 245 X18 = (18, "X18"), 246 X19 = (19, "X19"), 247 X20 = (20, "X20"), 248 X21 = (21, "X21"), 249 X22 = (22, "X22"), 250 X23 = (23, "X23"), 251 X24 = (24, "X24"), 252 X25 = (25, "X25"), 253 X26 = (26, "X26"), 254 X27 = (27, "X27"), 255 X28 = (28, "X28"), 256 X29 = (29, "X29"), 257 X30 = (30, "X30"), 258 SP = (31, "SP"), 259 260 V0 = (64, "V0"), 261 V1 = (65, "V1"), 262 V2 = (66, "V2"), 263 V3 = (67, "V3"), 264 V4 = (68, "V4"), 265 V5 = (69, "V5"), 266 V6 = (70, "V6"), 267 V7 = (71, "V7"), 268 V8 = (72, "V8"), 269 V9 = (73, "V9"), 270 V10 = (74, "V10"), 271 V11 = (75, "V11"), 272 V12 = (76, "V12"), 273 V13 = (77, "V13"), 274 V14 = (78, "V14"), 275 V15 = (79, "V15"), 276 V16 = (80, "V16"), 277 V17 = (81, "V17"), 278 V18 = (82, "V18"), 279 V19 = (83, "V19"), 280 V20 = (84, "V20"), 281 V21 = (85, "V21"), 282 V22 = (86, "V22"), 283 V23 = (87, "V23"), 284 V24 = (88, "V24"), 285 V25 = (89, "V25"), 286 V26 = (90, "V26"), 287 V27 = (91, "V27"), 288 V28 = (92, "V28"), 289 V29 = (93, "V29"), 290 V30 = (94, "V30"), 291 V31 = (95, "V31"), 292 }); 293 294 /// RISC-V architecture specific definitions. 295 /// 296 /// See [RISC-V ELF psABI specification](https://github.com/riscv/riscv-elf-psabi-doc). 297 #[derive(Debug, Clone, Copy)] 298 pub struct RiscV; 299 300 registers!(RiscV, { 301 X0 = (0, "x0"), 302 X1 = (1, "x1"), 303 X2 = (2, "x2"), 304 X3 = (3, "x3"), 305 X4 = (4, "x4"), 306 X5 = (5, "x5"), 307 X6 = (6, "x6"), 308 X7 = (7, "x7"), 309 X8 = (8, "x8"), 310 X9 = (9, "x9"), 311 X10 = (10, "x10"), 312 X11 = (11, "x11"), 313 X12 = (12, "x12"), 314 X13 = (13, "x13"), 315 X14 = (14, "x14"), 316 X15 = (15, "x15"), 317 X16 = (16, "x16"), 318 X17 = (17, "x17"), 319 X18 = (18, "x18"), 320 X19 = (19, "x19"), 321 X20 = (20, "x20"), 322 X21 = (21, "x21"), 323 X22 = (22, "x22"), 324 X23 = (23, "x23"), 325 X24 = (24, "x24"), 326 X25 = (25, "x25"), 327 X26 = (26, "x26"), 328 X27 = (27, "x27"), 329 X28 = (28, "x28"), 330 X29 = (29, "x29"), 331 X30 = (30, "x30"), 332 X31 = (31, "x31"), 333 334 F0 = (32, "f0"), 335 F1 = (33, "f1"), 336 F2 = (34, "f2"), 337 F3 = (35, "f3"), 338 F4 = (36, "f4"), 339 F5 = (37, "f5"), 340 F6 = (38, "f6"), 341 F7 = (39, "f7"), 342 F8 = (40, "f8"), 343 F9 = (41, "f9"), 344 F10 = (42, "f10"), 345 F11 = (43, "f11"), 346 F12 = (44, "f12"), 347 F13 = (45, "f13"), 348 F14 = (46, "f14"), 349 F15 = (47, "f15"), 350 F16 = (48, "f16"), 351 F17 = (49, "f17"), 352 F18 = (50, "f18"), 353 F19 = (51, "f19"), 354 F20 = (52, "f20"), 355 F21 = (53, "f21"), 356 F22 = (54, "f22"), 357 F23 = (55, "f23"), 358 F24 = (56, "f24"), 359 F25 = (57, "f25"), 360 F26 = (58, "f26"), 361 F27 = (59, "f27"), 362 F28 = (60, "f28"), 363 F29 = (61, "f29"), 364 F30 = (62, "f30"), 365 F31 = (63, "f31"), 366 }, 367 aliases { 368 ZERO = (0, "zero"), 369 RA = (1, "ra"), 370 SP = (2, "sp"), 371 GP = (3, "gp"), 372 TP = (4, "tp"), 373 T0 = (5, "t0"), 374 T1 = (6, "t1"), 375 T2 = (7, "t2"), 376 S0 = (8, "s0"), 377 S1 = (9, "s1"), 378 A0 = (10, "a0"), 379 A1 = (11, "a1"), 380 A2 = (12, "a2"), 381 A3 = (13, "a3"), 382 A4 = (14, "a4"), 383 A5 = (15, "a5"), 384 A6 = (16, "a6"), 385 A7 = (17, "a7"), 386 S2 = (18, "s2"), 387 S3 = (19, "s3"), 388 S4 = (20, "s4"), 389 S5 = (21, "s5"), 390 S6 = (22, "s6"), 391 S7 = (23, "s7"), 392 S8 = (24, "s8"), 393 S9 = (25, "s9"), 394 S10 = (26, "s10"), 395 S11 = (27, "s11"), 396 T3 = (28, "t3"), 397 T4 = (29, "t4"), 398 T5 = (30, "t5"), 399 T6 = (31, "t6"), 400 401 FT0 = (32, "ft0"), 402 FT1 = (33, "ft1"), 403 FT2 = (34, "ft2"), 404 FT3 = (35, "ft3"), 405 FT4 = (36, "ft4"), 406 FT5 = (37, "ft5"), 407 FT6 = (38, "ft6"), 408 FT7 = (39, "ft7"), 409 FS0 = (40, "fs0"), 410 FS1 = (41, "fs1"), 411 FA0 = (42, "fa0"), 412 FA1 = (43, "fa1"), 413 FA2 = (44, "fa2"), 414 FA3 = (45, "fa3"), 415 FA4 = (46, "fa4"), 416 FA5 = (47, "fa5"), 417 FA6 = (48, "fa6"), 418 FA7 = (49, "fa7"), 419 FS2 = (50, "fs2"), 420 FS3 = (51, "fs3"), 421 FS4 = (52, "fs4"), 422 FS5 = (53, "fs5"), 423 FS6 = (54, "fs6"), 424 FS7 = (55, "fs7"), 425 FS8 = (56, "fs8"), 426 FS9 = (57, "fs9"), 427 FS10 = (58, "fs10"), 428 FS11 = (59, "fs11"), 429 FT8 = (60, "ft8"), 430 FT9 = (61, "ft9"), 431 FT10 = (62, "ft10"), 432 FT11 = (63, "ft11"), 433 }); 434 435 /// Intel i386 architecture specific definitions. 436 /// 437 /// See Intel386 psABi version 1.1 at the [X86 psABI wiki](https://github.com/hjl-tools/x86-psABI/wiki/X86-psABI). 438 #[derive(Debug, Clone, Copy)] 439 pub struct X86; 440 441 registers!(X86, { 442 EAX = (0, "eax"), 443 ECX = (1, "ecx"), 444 EDX = (2, "edx"), 445 EBX = (3, "ebx"), 446 ESP = (4, "esp"), 447 EBP = (5, "ebp"), 448 ESI = (6, "esi"), 449 EDI = (7, "edi"), 450 451 // Return Address register. This is stored in `0(%esp, "")` and is not a physical register. 452 RA = (8, "RA"), 453 454 ST0 = (11, "st0"), 455 ST1 = (12, "st1"), 456 ST2 = (13, "st2"), 457 ST3 = (14, "st3"), 458 ST4 = (15, "st4"), 459 ST5 = (16, "st5"), 460 ST6 = (17, "st6"), 461 ST7 = (18, "st7"), 462 463 XMM0 = (21, "xmm0"), 464 XMM1 = (22, "xmm1"), 465 XMM2 = (23, "xmm2"), 466 XMM3 = (24, "xmm3"), 467 XMM4 = (25, "xmm4"), 468 XMM5 = (26, "xmm5"), 469 XMM6 = (27, "xmm6"), 470 XMM7 = (28, "xmm7"), 471 472 MM0 = (29, "mm0"), 473 MM1 = (30, "mm1"), 474 MM2 = (31, "mm2"), 475 MM3 = (32, "mm3"), 476 MM4 = (33, "mm4"), 477 MM5 = (34, "mm5"), 478 MM6 = (35, "mm6"), 479 MM7 = (36, "mm7"), 480 481 MXCSR = (39, "mxcsr"), 482 483 ES = (40, "es"), 484 CS = (41, "cs"), 485 SS = (42, "ss"), 486 DS = (43, "ds"), 487 FS = (44, "fs"), 488 GS = (45, "gs"), 489 490 TR = (48, "tr"), 491 LDTR = (49, "ldtr"), 492 493 FS_BASE = (93, "fs.base"), 494 GS_BASE = (94, "gs.base"), 495 }); 496 497 /// AMD64 architecture specific definitions. 498 /// 499 /// See x86-64 psABI version 1.0 at the [X86 psABI wiki](https://github.com/hjl-tools/x86-psABI/wiki/X86-psABI). 500 #[derive(Debug, Clone, Copy)] 501 pub struct X86_64; 502 503 registers!(X86_64, { 504 RAX = (0, "rax"), 505 RDX = (1, "rdx"), 506 RCX = (2, "rcx"), 507 RBX = (3, "rbx"), 508 RSI = (4, "rsi"), 509 RDI = (5, "rdi"), 510 RBP = (6, "rbp"), 511 RSP = (7, "rsp"), 512 513 R8 = (8, "r8"), 514 R9 = (9, "r9"), 515 R10 = (10, "r10"), 516 R11 = (11, "r11"), 517 R12 = (12, "r12"), 518 R13 = (13, "r13"), 519 R14 = (14, "r14"), 520 R15 = (15, "r15"), 521 522 // Return Address register. This is stored in `0(%rsp, "")` and is not a physical register. 523 RA = (16, "RA"), 524 525 XMM0 = (17, "xmm0"), 526 XMM1 = (18, "xmm1"), 527 XMM2 = (19, "xmm2"), 528 XMM3 = (20, "xmm3"), 529 XMM4 = (21, "xmm4"), 530 XMM5 = (22, "xmm5"), 531 XMM6 = (23, "xmm6"), 532 XMM7 = (24, "xmm7"), 533 534 XMM8 = (25, "xmm8"), 535 XMM9 = (26, "xmm9"), 536 XMM10 = (27, "xmm10"), 537 XMM11 = (28, "xmm11"), 538 XMM12 = (29, "xmm12"), 539 XMM13 = (30, "xmm13"), 540 XMM14 = (31, "xmm14"), 541 XMM15 = (32, "xmm15"), 542 543 ST0 = (33, "st0"), 544 ST1 = (34, "st1"), 545 ST2 = (35, "st2"), 546 ST3 = (36, "st3"), 547 ST4 = (37, "st4"), 548 ST5 = (38, "st5"), 549 ST6 = (39, "st6"), 550 ST7 = (40, "st7"), 551 552 MM0 = (41, "mm0"), 553 MM1 = (42, "mm1"), 554 MM2 = (43, "mm2"), 555 MM3 = (44, "mm3"), 556 MM4 = (45, "mm4"), 557 MM5 = (46, "mm5"), 558 MM6 = (47, "mm6"), 559 MM7 = (48, "mm7"), 560 561 RFLAGS = (49, "rFLAGS"), 562 ES = (50, "es"), 563 CS = (51, "cs"), 564 SS = (52, "ss"), 565 DS = (53, "ds"), 566 FS = (54, "fs"), 567 GS = (55, "gs"), 568 569 FS_BASE = (58, "fs.base"), 570 GS_BASE = (59, "gs.base"), 571 572 TR = (62, "tr"), 573 LDTR = (63, "ldtr"), 574 MXCSR = (64, "mxcsr"), 575 FCW = (65, "fcw"), 576 FSW = (66, "fsw"), 577 578 XMM16 = (67, "xmm16"), 579 XMM17 = (68, "xmm17"), 580 XMM18 = (69, "xmm18"), 581 XMM19 = (70, "xmm19"), 582 XMM20 = (71, "xmm20"), 583 XMM21 = (72, "xmm21"), 584 XMM22 = (73, "xmm22"), 585 XMM23 = (74, "xmm23"), 586 XMM24 = (75, "xmm24"), 587 XMM25 = (76, "xmm25"), 588 XMM26 = (77, "xmm26"), 589 XMM27 = (78, "xmm27"), 590 XMM28 = (79, "xmm28"), 591 XMM29 = (80, "xmm29"), 592 XMM30 = (81, "xmm30"), 593 XMM31 = (82, "xmm31"), 594 595 K0 = (118, "k0"), 596 K1 = (119, "k1"), 597 K2 = (120, "k2"), 598 K3 = (121, "k3"), 599 K4 = (122, "k4"), 600 K5 = (123, "k5"), 601 K6 = (124, "k6"), 602 K7 = (125, "k7"), 603 }); 604