1 /* 2 * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <arch.h> 11 #include <lib/utils_def.h> 12 13 #include "../gxl_def.h" 14 15 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 16 #define PLATFORM_LINKER_ARCH aarch64 17 18 #define PLATFORM_STACK_SIZE UL(0x1000) 19 20 #define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) 21 #define PLATFORM_CLUSTER_COUNT U(1) 22 #define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER 23 #define PLATFORM_CORE_COUNT PLATFORM_CLUSTER0_CORE_COUNT 24 25 #define AML_PRIMARY_CPU U(0) 26 27 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1 28 #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \ 29 PLATFORM_CORE_COUNT) 30 31 #define PLAT_MAX_RET_STATE U(1) 32 #define PLAT_MAX_OFF_STATE U(2) 33 34 /* Local power state for power domains in Run state. */ 35 #define PLAT_LOCAL_STATE_RUN U(0) 36 /* Local power state for retention. Valid only for CPU power domains */ 37 #define PLAT_LOCAL_STATE_RET U(1) 38 /* Local power state for power-down. Valid for CPU and cluster power domains. */ 39 #define PLAT_LOCAL_STATE_OFF U(2) 40 41 /* 42 * Macros used to parse state information from State-ID if it is using the 43 * recommended encoding for State-ID. 44 */ 45 #define PLAT_LOCAL_PSTATE_WIDTH U(4) 46 #define PLAT_LOCAL_PSTATE_MASK ((U(1) << PLAT_LOCAL_PSTATE_WIDTH) - 1) 47 48 /* 49 * Some data must be aligned on the biggest cache line size in the platform. 50 * This is known only to the platform as it might have a combination of 51 * integrated and external caches. 52 */ 53 #define CACHE_WRITEBACK_SHIFT U(6) 54 #define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT) 55 56 /* Memory-related defines */ 57 #define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 32) 58 #define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 32) 59 60 #define MAX_MMAP_REGIONS 12 61 #define MAX_XLAT_TABLES 6 62 63 #endif /* PLATFORM_DEF_H */ 64