1 /*
2 * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <string.h>
9
10 #include <platform_def.h>
11
12 #include <arch_helpers.h>
13 #include <common/bl_common.h>
14 #include <common/debug.h>
15 #include <context.h>
16 #include <drivers/arm/gicv2.h>
17 #include <drivers/arm/tzc400.h>
18 #include <drivers/generic_delay_timer.h>
19 #include <drivers/st/bsec.h>
20 #include <drivers/st/etzpc.h>
21 #include <drivers/st/stm32_console.h>
22 #include <drivers/st/stm32_gpio.h>
23 #include <drivers/st/stm32_iwdg.h>
24 #include <drivers/st/stm32mp1_clk.h>
25 #include <dt-bindings/clock/stm32mp1-clks.h>
26 #include <lib/el3_runtime/context_mgmt.h>
27 #include <lib/mmio.h>
28 #include <lib/xlat_tables/xlat_tables_v2.h>
29 #include <plat/common/platform.h>
30
31 #include <platform_sp_min.h>
32
33 /******************************************************************************
34 * Placeholder variables for copying the arguments that have been passed to
35 * BL32 from BL2.
36 ******************************************************************************/
37 static entry_point_info_t bl33_image_ep_info;
38
39 static console_t console;
40
41 /*******************************************************************************
42 * Interrupt handler for FIQ (secure IRQ)
43 ******************************************************************************/
sp_min_plat_fiq_handler(uint32_t id)44 void sp_min_plat_fiq_handler(uint32_t id)
45 {
46 switch (id & INT_ID_MASK) {
47 case STM32MP1_IRQ_TZC400:
48 (void)tzc400_it_handler();
49 panic();
50 break;
51 case STM32MP1_IRQ_AXIERRIRQ:
52 ERROR("STM32MP1_IRQ_AXIERRIRQ generated\n");
53 panic();
54 break;
55 default:
56 ERROR("SECURE IT handler not define for it : %u", id);
57 break;
58 }
59 }
60
61 /*******************************************************************************
62 * Return a pointer to the 'entry_point_info' structure of the next image for
63 * the security state specified. BL33 corresponds to the non-secure image type
64 * while BL32 corresponds to the secure image type. A NULL pointer is returned
65 * if the image does not exist.
66 ******************************************************************************/
sp_min_plat_get_bl33_ep_info(void)67 entry_point_info_t *sp_min_plat_get_bl33_ep_info(void)
68 {
69 entry_point_info_t *next_image_info;
70
71 next_image_info = &bl33_image_ep_info;
72
73 if (next_image_info->pc == 0U) {
74 return NULL;
75 }
76
77 return next_image_info;
78 }
79
80 CASSERT((STM32MP_SEC_SYSRAM_BASE == STM32MP_SYSRAM_BASE) &&
81 ((STM32MP_SEC_SYSRAM_BASE + STM32MP_SEC_SYSRAM_SIZE) <=
82 (STM32MP_SYSRAM_BASE + STM32MP_SYSRAM_SIZE)),
83 assert_secure_sysram_fits_at_begining_of_sysram);
84
85 #ifdef STM32MP_NS_SYSRAM_BASE
86 CASSERT((STM32MP_NS_SYSRAM_BASE >= STM32MP_SEC_SYSRAM_BASE) &&
87 ((STM32MP_NS_SYSRAM_BASE + STM32MP_NS_SYSRAM_SIZE) ==
88 (STM32MP_SYSRAM_BASE + STM32MP_SYSRAM_SIZE)),
89 assert_non_secure_sysram_fits_at_end_of_sysram);
90
91 CASSERT((STM32MP_NS_SYSRAM_BASE & (PAGE_SIZE_4KB - U(1))) == 0U,
92 assert_non_secure_sysram_base_is_4kbyte_aligned);
93
94 #define TZMA1_SECURE_RANGE \
95 (((STM32MP_NS_SYSRAM_BASE - STM32MP_SYSRAM_BASE) >> FOUR_KB_SHIFT) - 1U)
96 #else
97 #define TZMA1_SECURE_RANGE STM32MP1_ETZPC_TZMA_ALL_SECURE
98 #endif /* STM32MP_NS_SYSRAM_BASE */
99 #define TZMA0_SECURE_RANGE STM32MP1_ETZPC_TZMA_ALL_SECURE
100
stm32mp1_etzpc_early_setup(void)101 static void stm32mp1_etzpc_early_setup(void)
102 {
103 if (etzpc_init() != 0) {
104 panic();
105 }
106
107 etzpc_configure_tzma(STM32MP1_ETZPC_TZMA_ROM, TZMA0_SECURE_RANGE);
108 etzpc_configure_tzma(STM32MP1_ETZPC_TZMA_SYSRAM, TZMA1_SECURE_RANGE);
109 }
110
111 /*******************************************************************************
112 * Perform any BL32 specific platform actions.
113 ******************************************************************************/
sp_min_early_platform_setup2(u_register_t arg0,u_register_t arg1,u_register_t arg2,u_register_t arg3)114 void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1,
115 u_register_t arg2, u_register_t arg3)
116 {
117 struct dt_node_info dt_uart_info;
118 int result;
119 bl_params_t *params_from_bl2 = (bl_params_t *)arg0;
120
121 /* Imprecise aborts can be masked in NonSecure */
122 write_scr(read_scr() | SCR_AW_BIT);
123
124 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE,
125 BL_CODE_END - BL_CODE_BASE,
126 MT_CODE | MT_SECURE);
127
128 configure_mmu();
129
130 assert(params_from_bl2 != NULL);
131 assert(params_from_bl2->h.type == PARAM_BL_PARAMS);
132 assert(params_from_bl2->h.version >= VERSION_2);
133
134 bl_params_node_t *bl_params = params_from_bl2->head;
135
136 /*
137 * Copy BL33 entry point information.
138 * They are stored in Secure RAM, in BL2's address space.
139 */
140 while (bl_params != NULL) {
141 if (bl_params->image_id == BL33_IMAGE_ID) {
142 bl33_image_ep_info = *bl_params->ep_info;
143 break;
144 }
145
146 bl_params = bl_params->next_params_info;
147 }
148
149 if (dt_open_and_check() < 0) {
150 panic();
151 }
152
153 if (bsec_probe() != 0) {
154 panic();
155 }
156
157 if (stm32mp1_clk_probe() < 0) {
158 panic();
159 }
160
161 result = dt_get_stdout_uart_info(&dt_uart_info);
162
163 if ((result > 0) && (dt_uart_info.status != 0U)) {
164 unsigned int console_flags;
165
166 if (console_stm32_register(dt_uart_info.base, 0,
167 STM32MP_UART_BAUDRATE, &console) ==
168 0) {
169 panic();
170 }
171
172 console_flags = CONSOLE_FLAG_BOOT | CONSOLE_FLAG_CRASH |
173 CONSOLE_FLAG_TRANSLATE_CRLF;
174 #ifdef DEBUG
175 console_flags |= CONSOLE_FLAG_RUNTIME;
176 #endif
177 console_set_scope(&console, console_flags);
178 }
179
180 stm32mp1_etzpc_early_setup();
181 }
182
183 /*******************************************************************************
184 * Initialize the MMU, security and the GIC.
185 ******************************************************************************/
sp_min_platform_setup(void)186 void sp_min_platform_setup(void)
187 {
188 /* Initialize tzc400 after DDR initialization */
189 stm32mp1_security_setup();
190
191 generic_delay_timer_init();
192
193 stm32mp1_gic_init();
194
195 if (stm32_iwdg_init() < 0) {
196 panic();
197 }
198
199 stm32mp_lock_periph_registering();
200
201 stm32mp1_init_scmi_server();
202 }
203
sp_min_plat_arch_setup(void)204 void sp_min_plat_arch_setup(void)
205 {
206 }
207